Circuit board, image sensor, and method for manufacturing the image sensor

Abstract

Each of the circuit boards functioning as the substrates (10a to 10h) includes a switch (107) including four or more selection pins, a logic circuit (108) that outputs an ON signal from one output terminal selected from four or more independent output terminals when an ON signal is input from only one predetermined selection pin among the selection pins and an OFF signal is input from all the other selection pins, and an electrical component that switches between enabled and disabled based on the output of the logic circuit (108).

Description

[Technical field]

[0001] The present disclosure relates to a circuit board, an image sensor, and a method for manufacturing an image sensor. [Background technology]

[0002] Image sensors read images using sensor ICs (Integrated Circuits) arranged in the longitudinal direction, and as the sensor section becomes longer and faster, the signal processing section includes many signal processing ICs such as FPGAs (Field Programmable Gate Arrays) and AFEs (Analog Front Ends). Since the number of signal processing ICs that can be mounted on one circuit board is limited, they are mounted on multiple circuit boards. The multiple circuit boards are synchronized with each other and process the image signals read from each sensor IC.

[0003] The multiple circuit boards that make up the signal processing unit may differ from one another in the types of mounted parts and the length of the boards depending on the function, arrangement order, etc. In such cases, part management and mounting become complicated, leading to increased costs or mounting errors. In response to this, a method is used in which a switch is used to switch between enabled and disabled parts or to switch wiring in order to reduce the number of board types (for example, Patent Document 1).

[0004] The semiconductor integrated circuit described in Patent Document 1 includes a keeper circuit that holds the output logic of three logic operation circuits and three inverters connected to the output terminals of the logic operation circuits, so that when the output of any one of the first logic operation circuits is at a low level, the output of the other first logic operation circuits is forcibly set to a high level, thereby making it possible to set only one of the output terminals to a high level. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2001-244808 A Summary of the Invention [Problem to be solved by the invention]

[0006] The image sensor needs to read out one line of an image using a single synchronous signal, and multiple boards synchronize to acquire the sensor signal and output the image signal. For this reason, at least two types of boards are required: one that outputs the source clock and synchronous signal, and one that receives it. Also, in order to make the length in the longitudinal direction that the image is read at one time conform to the specifications of the image reading device, multiple types of boards with different numbers of longitudinal pixels capable of signal processing are required.

[0007] The semiconductor integrated circuit described in Patent Document 1 includes a logic circuit that selects one of three terminals and outputs the selected terminal based on eight input signals Q1 to Q8. In contrast, in an image sensor, when components or wiring are selected using a common substrate and multiple types of substrates with different functions are manufactured, the logic circuit exemplified in Patent Document 1 is insufficient because the number of outputs is small relative to the number of inputs.

[0008] The present disclosure has been made in consideration of the above-mentioned circumstances, and aims to provide a circuit board, an image sensor, and a method for manufacturing an image sensor that can function as multiple types of substrates with different components or wiring. [Means for solving the problem]

[0009] In order to achieve the above object, the circuit board of the present disclosure includes a physical switch including eight selection pins from a first pin to an eighth pin, and a circuit board that is capable of controlling a power supply voltage from only one predetermined selection pin among the selection pins. Low level When the ON signal is input, all other selection pins High level The device is provided with a logic circuit that outputs an ON signal from one output terminal selected from eight mutually independent output terminals when an OFF signal is input, and an electrical component that switches between enabled and disabled based on the output of the logic circuit. do.The logic circuit includes a first logic circuit that outputs an ON signal when an ON signal is input from at least one of the combinations of the first pin and the fifth pin, the second pin and the sixth pin, the third pin and the seventh pin, and the fourth pin and the eighth pin, which are separated from each other; For each combination of pins 1 and 5, pins 2 and 6, pins 3 and 7, and pins 4 and 8, Input from one selection pin and input from the other selection pin Denial By calculating the exclusive OR, Both one select pin and the other select pin An ON signal is input to Outputs an OFF signal from the combination A second logic circuit, an output of the first logic circuit and an output of the second logic circuit Each A third logic circuit that ORs the output and the inputs from each of the eight selection pins. 、 Output of the third logic circuit The outputs corresponding to each selection pin are and a fourth logic circuit for determining the logical sum of The output signal of the fourth logic circuit is output from eight independent output terminals. . Effect of the Invention

[0010] According to the present disclosure, electrical components are enabled or disabled by the output of a logic circuit based on the input from a selection pin of a switch, thereby enabling a circuit board to function as multiple types of boards with different components or wiring. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing inter-substrate wiring of an image sensor according to a first embodiment of the present disclosure. [Diagram 2] Top view of a series of substrates for image processing of image sensors [Diagram 3] Top view of the image processing circuit board of the image sensor [Figure 4] Overall circuit diagram of logic circuit [Diagram 5] Circuit diagram of the first logic circuit [Figure 6] A diagram showing the truth table of the first logic circuit. [Figure 7A] A diagram showing the truth table for pins 1 and 5 of the second logic circuit [Figure 7B] A diagram showing the truth table for pins 2 and 6 of the second logic circuit [Figure 7C] A diagram showing the truth table for pins 3 and 7 of the second logic circuit. [Figure 7D] A diagram showing the truth table for pins 4 and 8 of the second logic circuit. [Figure 8] A diagram showing the truth table of the third logic circuit. [Figure 9] A diagram showing the truth table of the fourth logic circuit. [Figure 10] Diagram showing input and output of logic circuit [Figure 11] Circuit diagram of a logic circuit according to a second embodiment [Figure 12] FIG. 11 is a cross-sectional view showing inter-substrate wiring of another example of an image sensor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Embodiment 1) Hereinafter, an image sensor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The image sensor 1 is any line sensor in which sensor ICs are arranged in a straight line, for example, a contact image sensor (CIS) in which a sensor IC, a light source, and a lens array are integrated.

[0013] 1 is a cross-sectional view illustrating inter-substrate wiring of an image sensor 1 according to the present embodiment. The longitudinal direction of the image sensor 1 is indicated as the X-axis direction, the lateral direction as the Y-axis direction, and the height direction perpendicular to the longitudinal and lateral directions as the Z-axis direction. The longitudinal direction and lateral direction in the image sensor 1 according to the present embodiment correspond to the main scanning direction and sub-scanning direction in the image sensor 1, respectively.

[0014] 1, the image sensor 1 includes a frame 70 that holds optical components and signal processing boards 21, 22, and a cover 80 that covers the entire frame 70. To the cover 80, for example, various connectors including a connector 51 that supplies power to each board and a connector 52 that outputs a signal to control lighting, a cooling fan 53, and boards 40, 41 that control the image sensor 1 are fixed. The frame 70 and the cover 80 are made of, for example, aluminum.

[0015] The boards 21 and 22 fixed to the frame 70 are boards having an A / D (Analog to Digital) conversion circuit that converts an analog signal output by a sensor IC into a digital signal. One or more boards 21 and one or more boards 22 are arranged in the main scanning direction. In order to set the length of the image sensor 1 in the main scanning direction to a predetermined length, the lengths of the boards 21 and 22 in the main scanning direction are different from each other, and the length of the board 22 is longer than the length of the board 21.

[0016] Each of the substrates 21 and 22 is provided with a spacer. 25 Boards 10a to 10h (hereinafter, sometimes collectively referred to as board 10) are fixed via boards 21 and 22. Boards 10a to 10h are boards that add necessary image processing to the digital signals output by boards 21 and 22, and each of boards 10a to 10h inputs and outputs a source clock, a synchronous signal, or a control signal.

[0017] The boards 10a to 10h have the same size, components, and wiring, and switch functions by physical switches. The number of boards 10 is arbitrary, but there must be at least two boards, one for transmitting a synchronization signal based on a source clock and one for receiving it. In addition, in order to set the length in the main scanning direction in which an image is read at one time to a predetermined length, two or more types of boards with different numbers of pixels in the main scanning direction capable of signal processing are arranged. In this embodiment, a case will be described in which the physical switch is an 8-channel DIP switch, and there are eight boards 10, the boards 10a to 10h. Details of the boards 10a to 10h will be described later.

[0018] A substrate 30 is fixed to each of the substrates 10a to 10h via a spacer 31. The substrate 30 supplies power to each of the substrates 10a to 10h and transmits and receives communication signals thereto.

[0019] A light source for irradiating light onto an object to be read and a control board for the light source may be further provided on the frame 70 of the image sensor 1. The light source is, for example, an LED (Light Emitting Diode).

[0020] The board 40 fixed to the cover 80 is connected to the boards 10a to 10h by wiring, and converts the image signals processed by the boards 10a to 10h into a predetermined standard and outputs the converted signal to the outside. The standard of the signal output to the outside is arbitrary, and may be, for example, CameraLink (registered trademark), CoaXPress (registered trademark), GigE Vision (registered trademark), or USB3 Vision (registered trademark).

[0021] Further, the board 41 fixed to the cover 80 is a board having a microcomputer that centrally manages the entire image sensor 1, is connected to the board 30 by wiring, and transmits and receives control signals between the boards 10 and 30 and the outside.

[0022] The operation of the image sensor 1 is as follows. First, the sensor IC receives light irradiated from a light source that is transmitted through or reflected by a reading target, and outputs an analog signal. The A / D conversion circuits of the boards 21 and 22 convert the analog signal input from the sensor IC into a digital signal. The converted digital signal undergoes signal processing including rearrangement of image data on the boards 10a to 10h, and is transmitted to the board 40 via wiring. The board 40 converts the received image signal into a predetermined standard and outputs it to the outside.

[0023] Furthermore, substrate 40 receives a control signal input from the outside and outputs it to the microcomputer of substrate 41. Based on the received control signal, the microcomputer of substrate 41 transmits a control signal to substrates 10a-10h through wiring and substrate 30, thereby controlling substrates 10a-10h. The substrates 10a-10h of image sensor 1 according to this embodiment are characterized in that they are one type of circuit substrate.

[0024] Fig. 2 is a top view of a series of image processing boards 10a-10h arranged in the main scanning direction with adjacent boards connected to each other, and Fig. 3 is a top view of one board 10. Boards 10a-10h are one type of circuit board mounted with the same components and having the same wiring, and components are enabled and disabled by switching switch 107.

[0025] 2 and 3, for example, the board 10 is equipped with a main clock 101, a buffer 102 that conditions the source clock signal output from the main clock 101, a connector 103 for a cable that electrically connects the boards, a buffer 104 that conditions the signal input from the previous board, a buffer 105 that conditions the signal to be sent to the previous board, and a signal processing IC. The signal processing IC is, for example, an FPGA (Field Programmable Gate Array). 106 It is.

[0026] Further mounted on the board 10 are a switch 107 for selecting a state including enable / disable of the electrical components on the board 10, and a logic circuit 108 for performing a logical operation on the output of the switch 107 and outputting the result. As shown in Fig. 3, four or more output terminals of the logic circuit 108 are connected to the main clock 101 and enable terminals of the buffers 102, 104, and 105 via wiring 109. The connector 103 of the board 10 is connected to the connector 103 of the adjacent board 10 by a cable 110.

[0027] The switch 107 and the logic circuit 108 will be described in detail with reference to Figs. 4 to 10. The switch 107 is a physical switch having four or more channels, for example an eight-channel DIP switch (referred to as DIP-SW in the drawings). One terminal of the switch 107 is connected to GND, and the other terminal, which is a selection pin, is pulled up. The first pin P1 to the eighth pin P8, which are selection pins, are at a low level when the switch 107 is ON (shorted), and are at a high level when the switch 107 is OFF (open).

[0028] The logic circuit 108 is a circuit that outputs an ON signal from one output terminal selected from four or more independent output terminals by a logical operation when an ON signal is input from only one pin of the four or more selection pins of the switch 107 and an OFF signal is input from all the other pins. In this embodiment, a case where the switch 107 has eight channels will be described. That is, when a Low-level ON signal is input from only one pin of the first pin P1 to the eighth pin P8 of the switch 107 and a High-level OFF signal is input from all the other pins, the logic circuit 108 outputs a Low-level ON signal from one output terminal selected from the mutually independent output terminals S1 to S8 by a logical operation. The Low or High output of the logic circuit 108 is input as an enable signal to the enable terminals of the buffers 102, 104, and 105 to control whether the buffers are enabled or disabled.

[0029] For example, when the first pin P1 of the switch 107 is set to low, the logic circuit 108 performs a logical operation in which only the output terminal S1 of the logic circuit 108 goes low. In this case, by turning on only the first channel of the switch 107, an ON signal output from the output terminal S1 of the logic circuit 108 is input to the buffer 102, which enables the buffer 102 and outputs the clock signal of the main clock 101 into the circuit.

[0030] On the other hand, when at least one of the second to eighth channels of the switch 107 of the first substrate 10a is turned ON, the output terminal S1 of the logic circuit 108 goes High, so that the buffer 102 is disabled and the clock signal is not output to the circuit. This allows the substrate that outputs the clock signal to be reliably selected using the switch 107. Also, when multiple channels of the switch 107 are turned ON by mistake, the output of the logic circuit 108 goes High, so it is possible to avoid the problem of signal collision due to erroneous operation.

[0031] Similarly, the output of logic circuit 108 may be input to the enable terminal of main clock 101 to control the oscillation or stopping of the clock. Also, the output of logic circuit 108 can be input to the enable terminals of buffers 104 and 105 to control the transmission of signals between the boards.

[0032] An example of the configuration of the logic circuit 108 will be described with reference to Figs. 4 to 10. Fig. 4 is a diagram showing the overall configuration of the logic circuit 108, and Fig. 5 is a diagram showing the configuration of a first logic circuit 1081 which is a part of the logic circuit 108. As shown in Fig. 4, the logic circuit 108 includes a first logic circuit 1081, a second logic circuit 1082, a third logic circuit 1083, and a fourth logic circuit 1084. Fig. 6 is a truth table of the first logic circuit 1081, Figs. 7A to 7D are truth tables of the second logic circuit 1082, Fig. 8 is a truth table of the third logic circuit 1083, and Fig. 9 is a truth table of the fourth logic circuit 1084. Fig. 10 is a diagram showing inputs and outputs of the logic circuit 108.

[0033] The first pin P1 to the eighth pin P8, which are selection pins for each channel of the switch 107, are connected to the inputs of the first logic circuit 1081. As shown in Fig. 5, the first pin P1 and the fifth pin P5, the second pin P2 and the sixth pin P6, the third pin P3 and the seventh pin P7, and the fourth pin P4 and the eighth pin P8, which are separated from each other, are connected to four AND circuits 1101 in the first stage of the first logic circuit 1081.

[0034] The output of AND circuit 1101 is inverted by NOT circuit 1102 and input to AND circuit 1103 and NOR circuit 1104. The output of AND circuit 1103 is input to NOR circuit 1105, and the output of NOR circuit 1105 is inverted by NOT circuit 1106 and input to NOR circuit 1108.

[0035] The output of the NOR circuit 1104 is input to an AND circuit 1107, the output of which is input to a NOR circuit 1108. The output of the NOR circuit 1108 is inverted by a NOT circuit 1109 and then input to a NOR circuit 1110, the output of which is inverted by a NOT circuit 1111 and output to an output terminal S of the first logic circuit 1081.L1 is output from

[0036] A truth table of the first logic circuit 1081 having such a configuration is shown in Fig. 6. In the truth table of Fig. 6, the four digits on the vertical axis correspond to the values ​​of the third pin P3, the seventh pin P7, the fourth pin P4, and the eighth pin P8 of the switch 107, respectively. Also, the four digits on the horizontal axis correspond to the values ​​of the first pin P1, the fifth pin P5, the second pin P2, and the sixth pin P6 of the switch 107, respectively. Here, a value of 0 is a low value, and a value of 1 is a high value.

[0037] As shown in FIG. 6, when at least one of the first pin P1 and the fifth pin P5 is low, when at least one of the second pin P2 and the sixth pin P6 is low, when at least one of the third pin P3 and the seventh pin P7 is low, and when at least one of the fourth pin P4 and the eighth pin P8 is low, the output terminal S of the first logic circuit L1 The value of the first logic circuit's output terminal S L1 The value will be High.

[0038] 4, the second logic circuit 1082 includes four exclusive OR (XOR) circuits 1201, and the first pin P1 and the fifth pin P5, the second pin P2 and the sixth pin P6, the third pin P3 and the seventh pin P7, and the fourth pin P4 and the eighth pin P8 are connected to the inputs of the exclusive OR circuits 1201. The output of the exclusive OR circuits 1201 is inverted by a NOT circuit 1202 and output to the third logic circuit 1083.

[0039] As is clear from the truth tables of Figures 7A to 7D, the output of the second logic circuit 1082 is High when the values ​​of the first pin P1 and the fifth pin P5, the second pin P2 and the sixth pin P6, the third pin P3 and the seventh pin P7, and the fourth pin P4 and the eighth pin P8 are the same, and is Low when they are different.

[0040] 4, the third logic circuit 1083 includes four NOR circuits 1301, and the output of the first logic circuit 1081 and the output of the second logic circuit 1082 are input to the inputs of each NOR circuit 1301. The output of the NOR circuit 1301 is inverted by a NOT circuit 1302 and output to a fourth logic circuit 1084.

[0041] As is clear from the truth table of FIG. 8, when the outputs of the first logic circuit 1081 and the second logic circuit 1082 are both Low, the output of the third logic circuit 1083 is Low, and when at least one of the outputs of the first logic circuit 1081 and the second logic circuit 1082 is High, the output of the third logic circuit 1083 is High.

[0042] 4, the fourth logic circuit 1084 includes eight NOR circuits 1401, and the output of the third logic circuit 1083 and the first pin P1 to the eighth pin P8 are connected to the inputs of each NOR circuit 1401. The output of the NOR circuit 1401 is inverted by a NOT circuit 1402 and then output.

[0043] As is clear from the truth table of FIG. 9, when the output of the third logic circuit 1083 and the value of each selection pin of the switch 107 are both Low, the output of the fourth logic circuit 1084, i.e., the output of the logic circuit 108, is Low, and when at least one of the output of the third logic circuit 1083 and the value of each selection pin of the switch 107 is High, the output of the fourth logic circuit 1084 is High.

[0044] 10 shows inputs and outputs of the logic circuit 108 having the above-described configuration. In the logic circuit 108, when a low-level ON signal is input only from the first pin P1 by turning on only the first channel of the switch 107, a low-level ON signal is output from the output terminal S1. Similarly, when a low-level ON signal is input only from the fifth pin P5, only from the second pin P2, only from the sixth pin P6, only from the third pin P3, only from the seventh pin P7, only from the fourth pin P4, and only from the eighth pin P8, a low-level ON signal is output from the output terminals S5, S2, S6, S3, S7, S4, and S8, respectively. On the other hand, when two or more channels of the switch 107 are ON or when all channels are OFF, a high-level OFF signal is output from each output terminal. In other words, when only one of the first to eighth channels of the switch 107 is turned ON, the logic circuit 108 outputs an ON signal from one of the output terminals S1 to S8, which are independent of each other.

[0045] The output of logic circuit 108 operating in this manner can control the enable / disable of electrical components including main clock 101 of boards 10a to 10h. Furthermore, if logic circuit 108 was not provided and switch 107 was directly connected to the enable terminals of the electrical components, malfunctions could occur by accidentally turning on multiple channels out of the eight channels of switch 107, but using logic circuit 108 can prevent such malfunctions.

[0046] 4 to 9 are merely examples, and may be replaced. For example, a combination of a NOR circuit and a NOT circuit may be replaced with an OR circuit. A combination of an AND circuit and a NOT circuit may be replaced with a NAND circuit. A combination of an XOR circuit and a NOT circuit may be replaced with an exclusive NOR circuit.

[0047] A method for manufacturing the image sensor 1 configured as above will be described with reference to FIGS.

[0048] First, substrates 21 and 22 having A / D conversion circuits are fixed along the arrangement direction of the sensor ICs, that is, the main scanning direction, to frame 70 to which the sensor ICs shown in Fig. 1 are fixed. Next, substrates 10a to 10h are fixed to each of substrates 21 and 22 via spacers 25 (substrate fixing step).

[0049] Then, the switches 107 of the boards 10a to 10h shown in Fig. 2 are operated. Specifically, only one predetermined selection pin of the switches 107 of each of the boards 10a to 10h is turned ON, and the other selection pins are turned OFF. This causes an ON signal to be output from one output selected from eight independent outputs of the logic circuit 108, and the corresponding electric component is switched to an enabled state (switch setting step).

[0050] Next, the board 30 is fixed to the boards 10a to 10h via the spacer 31. Thereafter, the boards 40, 41, the connectors 51, 52, and the FAN 53 fixed to the cover are connected by wiring to the boards 10, 30 fixed to the frame 70. Thereafter, the cover 80 is fixed to the frame 70.

[0051] As described above, the image sensor 1 according to the present embodiment uses the substrate 10 having the same components and wiring as a substrate for processing an image signal acquired from a sensor IC. The substrate 10 is mounted with a switch 107 and a logic circuit 108 that performs a logical operation on an input signal from the switch 107 and outputs the result. The logic circuit 108 performs a logical operation to output a low level from one output terminal selected from the mutually independent output terminals S1 to S8 when only one pin of the first pin P1 to the eighth pin P8 of the switch 107 becomes low. The output of the logic circuit 108 is input to the enable terminals of the buffers 102, 104, and 105 to control whether the buffers are enabled or disabled. This makes it possible to realize a long image sensor by using one type of circuit board instead of multiple types of circuit boards for image processing. In addition, since one type of circuit board is used, the manufacturing process can be simplified.

[0052] In addition, when a microcomputer or FPGA is used to select the board function, a start-up time of several milliseconds to several seconds is required after power-on, but in this embodiment, the board function is selected by a combination of logic elements, so the start-up time can be significantly shortened. Also, since the board function is selected by a simple configuration of switch 107 and logic circuit 108, costs can be reduced.

[0053] (Embodiment 2) Image sensor 1 according to embodiment 2 of the present disclosure is a line sensor in which sensor ICs are linearly arranged, having a similar configuration to image sensor 1 according to embodiment 1. The configuration of logic circuit 128 mounted on substrate 10 is different from that of embodiment 1. Image sensor 1 according to embodiment 2 will be described in detail with reference to the drawings.

[0054] 11 is a diagram showing a partial configuration of logic circuit 128 according to the second embodiment. In addition to logic circuit 108 of the first embodiment, logic circuit 128 includes a total AND circuit 1281, which is a multi-stage AND circuit, between logic circuit 108 and a specific electric component. That is, as shown in FIG. 11, logic circuit 128 includes a total AND circuit 1281 that outputs the logical product of output signals from all output terminals other than one output terminal selected from output terminals S1 to S8 of fourth logic circuit 1084. In FIG. 11, the total AND circuit 1281 outputs the logical product of output signals from output terminals S2 to S8 other than output terminal S1. Logical AND As a result, when any of the values ​​of the output terminals S2 to S8 is Low, the logic circuit 128 outputs A When the values ​​of output terminals S2 to S8 are all High, the output terminal S A Outputs High from.

[0055] Output S of logic circuit 128 A The specific electrical component can be controlled to be enabled or disabled by being input as an enable signal to an enable terminal of the specific electrical component. A Based on this, the clock oscillation or stopping is controlled.

[0056] Incidentally, one output terminal selected from the output terminals S1 to S8 of the fourth logic circuit 1084 is directly connected to the buffers 102, 104, and 105, which are other electric components, and is controlled to be valid or invalid.

[0057] In this way, by providing switch 107 and logic circuit 128, it is possible to realize long image sensor 1 using one type of circuit board, without the need to use multiple types of circuit boards for image processing. Also, since one type of circuit board is used, the manufacturing process can be simplified.

[0058] As described above, in the image sensor 1 according to the present embodiment, the logic circuit 128 that outputs the enable signal includes a full AND circuit 1281 that outputs the logical product of the output signals from all output terminals other than one output terminal selected from the output terminals S1 to S8 of the fourth logic circuit 1084. A Since the signal from is also used as an enable signal, the electrical components can be reliably switched between enabled and disabled.

[0059] In the above first and second embodiments, the case where switch 107 has eight channels and logic circuit 108 has eight outputs has been described, but the case where switch 107 has four to seven channels and logic circuit 108 has four to seven outputs can also be implemented in the same manner.

[0060] For example, when the switch 107 has four channels, this can be achieved by fixing the fifth pin P5, sixth pin P6, seventh pin P7, and eighth pin P8 of the first logic circuit 1081 all to High (pull-up). Similarly, when the switch 107 has five channels, this can be achieved by fixing the sixth pin P6, seventh pin P7, and eighth pin P8 of the first logic circuit 1081 to High, when the switch 107 has six channels, this can be achieved by fixing the seventh pin P7 and eighth pin P8 of the first logic circuit 1081 to High, and when the switch 107 has seven channels, this can be achieved by fixing the eighth pin P8 of the first logic circuit 1081 to High.

[0061] When the switch 107 has 4 to 7 channels, the output terminals S5, S6, S7, and S8 of the fourth logic circuit 1084 corresponding to the pins fixed to High among the fifth pin P5, the sixth pin P6, the seventh pin P7, and the eighth pin P8 of the first logic circuit 1081 become High, and therefore these output terminals are fixed to High (pulled up).

[0062] In addition, in the above first and second embodiments, the configuration of logic circuit 108 has been described as an example of a logic circuit that outputs an enable signal, but any other logic circuit may be used as long as it is a logic circuit that performs a logical operation to output an ON or OFF signal from one output terminal selected from four or more output terminals that are independent of each other in response to four or more ON or OFF input signals.

[0063] In the above first and second embodiments, the boards 10a to 10h are configured from one type of circuit board, and the function of the board 10 is switched by the switch 107 and the logic circuits 108, 128, but this is not limited to the above. For example, the board 10 may include the function of the board 30. That is, as shown in FIG. 12, the boards 11 (11a to h) including the functions of the boards 10 and 30 may be configured from one type of circuit board, and the function of the board 11 may be switched by the switch 107 and the logic circuits 108, 128. FIG. 12 is a diagram showing another example of the image sensor 2. This makes it possible to further reduce the number of types of boards.

[0064] Various aspects of the present disclosure are summarized below as appendices.

[0065] (Appendix 1) A switch including four or more selection pins; a logic circuit that outputs an ON signal from one output terminal selected from four or more output terminals that are independent of each other when an ON signal is input from only one of the selection pins that is predetermined among the selection pins and an OFF signal is input from all of the other selection pins; an electrical component that switches between enabled and disabled based on an output of the logic circuit; A circuit board comprising:

[0066] (Appendix 2) The switch is a physical switch including eight select pins, the logic circuit includes a first logic circuit that outputs an ON signal when an ON signal is input from at least one of a predetermined one of the selection pins and another selection pin separated from the predetermined one selection pin; 2. The circuit board of claim 1.

[0067] (Appendix 3) the logic circuit further includes a second logic circuit that calculates an exclusive OR of an input from the one selection pin and an input from the other selection pin, a third logic circuit that calculates an OR of an output from the first logic circuit and an output from the second logic circuit, and a fourth logic circuit that calculates an OR of an input from each of the eight selection pins and an output from the third logic circuit. 3. The circuit board according to claim 2.

[0068] (Appendix 4) the logic circuit includes a full AND circuit that outputs a logical product of outputs from all output terminals other than the one selected output terminal, At least one of the electrical components is switched between enabled and disabled based on an output of the full AND circuit. 4. The circuit board according to claim 1.

[0069] (Appendix 5) the electrical component is a clock or a buffer; 5. The circuit board of claim 1.

[0070] (Appendix 6) An image sensor including a plurality of circuit boards according to any one of claims 1 to 5, performing image processing on the output signal of the sensor IC using the electrical components enabled by selecting the selection pin of the switch of each circuit board; Image sensor.

[0071] (Appendix 7) a substrate fixing step of fixing a plurality of substrates for image processing, each substrate having a switch including four or more selection pins, a logic circuit that performs a logical operation on an input from the selection pins, and an electrical component that switches between enabled and disabled based on an output from the logic circuit, along an arrangement direction of the sensor ICs, to a frame on which the sensor ICs are fixed; a switch setting step of setting only one of the selection pins to ON and setting all the other selection pins to OFF, thereby outputting a signal for enabling the electrical component from one output terminal selected from four or more output terminals independent of each other of the logic circuit. A method for manufacturing an image sensor.

[0072] Various embodiments and modifications of the present disclosure are possible without departing from the broad spirit and scope of the present disclosure. The above-described embodiments are for explaining the present disclosure and do not limit the scope of the present disclosure. That is, the scope of the present disclosure is indicated by the claims, not the embodiments. Various modifications made within the scope of the claims and the scope of the disclosure equivalent thereto are considered to be within the scope of the present disclosure. [Explanation of symbols]

[0074] 1,2 Image sensor, 10,10a~10h,11,11a~11h,21,22,30 Board, 25,31 Spacer, 40,41 Board, 51,52 Connector, 53 FAN, 70 Frame, 80 Cover, 101 Main clock, 102,104,105 Buffer, 103 Connector, 106 FPGA, 107 Switch, 108,128 Logic circuit, 109 Wiring, 110 Cable, 1081 First logic circuit, 1082 Second logic circuit, 1083 Third logic circuit, 1084 Fourth logic circuit, 1101,1103,1107 Logical AND circuit, 1102,1106,1109,1111 NOT circuit, 1104,1105,1108,1110 NOR circuit, 1201 exclusive OR circuit, 1202,1302,1402 NOR circuit, 1301,1401 NOR circuit, 1501 AND circuit.

Claims

1. A physical switch including eight selection pins from pin 1 to pin 8; a logic circuit that outputs an ON signal from one output terminal selected from eight mutually independent output terminals when an ON signal is input from only one predetermined selection pin among the selection pins and OFF signals are input from all other selection pins; an electrical component that switches between enabled and disabled based on the output of the logic circuit; Equipped with The logic circuits include a first logic circuit that outputs an ON signal when an ON signal is input from at least one of the combinations of the first pin and the fifth pin, the second pin and the sixth pin, the third pin and the seventh pin, or the fourth pin and the eighth pin that are spaced apart from each other; a second logic circuit that invalidates an ON signal when it is input to two or more of the selection pins by calculating an exclusive OR between an input from one of the selection pins and an input from the other selection pin; a third logic circuit that calculates an OR between the output of the first logic circuit and the output of the second logic circuit; and a fourth logic circuit that calculates an OR between an input from each of the eight selection pins and the output of the third logic circuit. Circuit board.

2. the logic circuit includes a full AND circuit that outputs a logical product of outputs from all output terminals other than the selected one output terminal, at least one of the electrical components is switched between enabled and disabled based on the output of the full AND circuit; The circuit board according to claim 1 .

3. the electrical component is a clock or a buffer; The circuit board according to claim 1 .

4. An image sensor comprising a plurality of circuit boards according to any one of claims 1 to 3, performing image processing on the output signal of the sensor IC using the electrical components enabled by selecting the selection pin of the switch on each circuit board; Image sensor.

5. a substrate fixing step of fixing a plurality of substrates for image processing, each substrate having a physical switch including eight selection pins (1st pin to 8th pin), a logic circuit that performs logical operations on inputs from the selection pins, and an electrical component that switches between enabled and disabled based on an output from the logic circuit, to a frame on which the sensor ICs are fixed, along the arrangement direction of the sensor ICs; a switch setting step of setting only one predetermined selection pin among the selection pins to ON and setting all other selection pins to OFF, thereby outputting a signal that enables the electrical component from one output terminal selected from eight independent output terminals of the logic circuit, The logic circuits include a first logic circuit that outputs an ON signal when an ON signal is input from at least one of the combinations of the first pin and the fifth pin, the second pin and the sixth pin, the third pin and the seventh pin, or the fourth pin and the eighth pin that are spaced apart from each other; a second logic circuit that invalidates an ON signal when it is input to two or more of the selection pins by calculating an exclusive OR between an input from one of the selection pins and an input from the other selection pin; a third logic circuit that calculates an OR between the output of the first logic circuit and the output of the second logic circuit; and a fourth logic circuit that calculates an OR between an input from each of the eight selection pins and the output of the third logic circuit. Image sensor manufacturing method.

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