Semiconductor device

Abstract

Provided is a semiconductor device which achieves high insulation and low inductance. The semiconductor device includes a semiconductor element, a first electrode, a second electrode, and a sealing material. The first electrode is electrically connected to the semiconductor element. The second electrode is provided adjacent to the first electrode and is electrically connected to the semiconductor element. The sealing material seals the semiconductor element, parts other than the upper surface in the first electrode, and parts other than the upper surface in the second electrode. The first electrode includes a first side surface and a first upper surface. The first side surface projects from the outer peripheral upper surface constituting the outer peripheral part of the sealing material and faces the second electrode. The first upper surface is exposed from the sealing material. The second electrode includes a second side surface and a second upper surface. The second side surface projects from the outer peripheral upper surface constituting the outer peripheral part of the sealing material and faces the first electrode. The second upper surface is exposed from the sealing material. The first side surface and the second side surface are covered with the sealing material. The sealing material has, between the first electrode and the second electrode, at least one of a recess and a protrusion.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Semiconductor devices are required to have high heat dissipation properties. In the semiconductor device described in Patent Document 1, in order to improve heat dissipation properties, the main terminals and the control terminals are exposed from the upper flush surface of the sealing resin body.

[0003] JP 2014-157927 A

[0004] Semiconductor devices are required to have not only high heat dissipation but also low inductance to reduce losses. Reducing the distance between electrodes is an effective way to reduce inductance, but when the distance between electrodes is reduced, problems arise in ensuring insulation between the electrodes.

[0005] The present disclosure has been made to solve the above problems, and aims to provide a semiconductor device that achieves high insulation and low inductance.

[0006] The semiconductor device according to the present disclosure includes a semiconductor element, a first electrode, a second electrode, and a sealing material. The first electrode is electrically connected to the semiconductor element. The second electrode is disposed adjacent to the first electrode and is electrically connected to the semiconductor element. The sealing material seals the semiconductor element, all except for the top surface of the first electrode, and all except for the top surface of the second electrode. The first electrode includes a first side surface and a first top surface. The first side surface protrudes from the outer peripheral top surface that forms the outer periphery of the sealing material and faces the second electrode. The first top surface is exposed from the sealing material. The second electrode includes a second side surface and a second top surface. The second side surface protrudes from the outer peripheral top surface that forms the outer periphery of the sealing material and faces the first electrode. The second top surface is exposed from the sealing material. The first side surface and the second side surface are covered with the sealing material. The sealing material includes at least one of a recess and a protrusion between the first electrode and the second electrode.

[0007] According to the present disclosure, a semiconductor device that achieves high insulation and low inductance is provided.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] 1 is a cross-sectional view showing the configuration of a semiconductor device in a first embodiment; 2 is a cross-sectional view showing the configuration of a semiconductor device in a second embodiment; 3 is a cross-sectional view showing the configuration of a semiconductor device in a third embodiment; 4 is a cross-sectional view showing the configuration of a semiconductor device in a fourth embodiment; 5 is a cross-sectional view showing the configuration of a semiconductor device in a fifth embodiment; 6 is a plan view showing the configuration of a semiconductor device in a sixth embodiment; 7 is a plan view showing the configuration of a semiconductor device in a seventh embodiment; 8 is a cross-sectional view showing the configuration of a semiconductor device in a seventh embodiment.

[0010] First Preferred Embodiment FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 101 according to a first preferred embodiment.

[0011] The semiconductor device 101 includes a heat dissipation substrate 1 , an insulating substrate 2 , a semiconductor element 3 , a first electrode 4 , a second electrode 5 , and a sealing material 6 .

[0012] The heat dissipation substrate 1 is a plate made of metal such as copper, aluminum, etc. The heat dissipation substrate 1 has the function of transferring heat generated by electronic components such as semiconductor elements 3 to the outside.

[0013] The insulating substrate 2 is provided on the heat dissipation substrate 1. The insulating substrate 2 includes an insulating layer 2A, a front circuit pattern 2B, and a back circuit pattern 2C. The insulating layer 2A is formed of, for example, ceramic. The front circuit pattern 2B is provided on the upper surface of the insulating layer 2A. The back circuit pattern 2C is provided on the lower surface of the insulating layer 2A. The front circuit pattern 2B and the back circuit pattern 2C are formed of a conductive material such as metal. The back circuit pattern 2C is bonded to the heat dissipation substrate 1 via a bonding material 7A. The bonding material 7A is, for example, solder, brazing material, or sintered material.

[0014] The semiconductor element 3 is held by the insulating substrate 2. The semiconductor element 3 in the first embodiment is a vertical semiconductor element in which current flows between its upper and lower surfaces, and includes a front electrode (not shown) and a back electrode (not shown). The back electrode of the semiconductor element 3 is bonded to the front circuit pattern 2B of the insulating substrate 2 via a bonding material 7B. The bonding material 7B is a conductive material such as solder. The semiconductor element 3 is formed of a semiconductor such as Si. The semiconductor element 3 may be made of SiC, GaN, Ga ２ O ３ Preferably, the semiconductor element 3 is formed of a so-called wide bandgap semiconductor such as diamond. The semiconductor element 3 is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, or the like. The semiconductor element 3 includes, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a Schottky barrier diode, or the like. Alternatively, the semiconductor element 3 may include a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a free wheel diode are formed within a single semiconductor substrate.

[0015] The first electrode 4 is disposed adjacent to the second electrode 5. The first electrode 4 is electrically connected to the semiconductor element 3 inside the encapsulant 6. In the first embodiment, the lower surface of the first electrode 4 is bonded to the surface electrode of the semiconductor element 3 via a bonding material 7C. The surface electrode of the semiconductor element 3 is, for example, an emitter electrode. The first electrode 4 protrudes above a peripheral upper surface 6A that constitutes the outer periphery of the encapsulant 6. The first electrode 4 includes a first side surface 4A and a first upper surface 4B. The first side surface 4A protrudes from the peripheral upper surface 6A of the encapsulant 6 and faces the second electrode 5. The first side surface 4A is covered with the encapsulant 6. In the first embodiment, the entire first side surface 4A is covered with the encapsulant 6. The first upper surface 4B is not covered with the encapsulant 6 and is exposed through an opening provided in the encapsulant 6. The shape of the first electrode 4 is not important. The first electrode 4 has, for example, a block shape. The block shape may be, for example, a square pillar, a cylinder, or a U-shape.

[0016] The second electrode 5 is disposed adjacent to the first electrode 4. The second electrode 5 is electrically connected to the semiconductor element 3 inside the encapsulant 6. In the first embodiment, the lower surface of the second electrode 5 is bonded to the front circuit pattern 2B via a bonding material 7D. The front circuit pattern 2B is electrically connected to, for example, a collector electrode, which is a back electrode of the semiconductor element 3. The front circuit pattern 2B may be electrically connected to a control electrode, such as a gate electrode or a sensing electrode, of the semiconductor element 3. The second electrode 5 protrudes above a peripheral upper surface 6A that constitutes the outer periphery of the encapsulant 6. The second electrode 5 includes a second side surface 5A and a second upper surface 5B. The second side surface 5A protrudes from the peripheral upper surface 6A of the encapsulant 6 and faces the first electrode 4. The second side surface 5A is covered with the encapsulant 6. In the first embodiment, the entire second side surface 5A is covered with the encapsulant 6. The second upper surface 5B is not covered by the encapsulant 6 and is exposed through an opening provided in the encapsulant 6. There is no particular limitation on the shape of the second electrode 5. The second electrode 5 may have, for example, a block shape. The block shape may be, for example, a square pillar, a cylinder, or a U-shape.

[0017] The sealing material 6 seals the insulating substrate 2, the semiconductor element 3, and all parts except the top surface of the first electrode 4 and all parts except the top surface of the second electrode 5. The sealing material 6 in the first embodiment includes a recess 6B between the first electrode 4 and the second electrode 5. The bottom surface of the recess 6B is located lower than the first top surface 4B of the first electrode 4 and the second top surface 5B of the second electrode 5. The sealing material 6 is made of an insulating resin. The sealing material 6 is, for example, a silicone resin or an epoxy resin.

[0018] In summary, the semiconductor device 101 in the first embodiment includes a semiconductor element 3, a first electrode 4, a second electrode 5, and an encapsulant 6. The first electrode 4 is electrically connected to the semiconductor element 3. The second electrode 5 is disposed adjacent to the first electrode 4 and is electrically connected to the semiconductor element 3. The encapsulant 6 encapsulates the semiconductor element 3, all except for the top surfaces of the first electrode 4 and the second electrode 5. The first electrode 4 includes a first side surface 4A and a first top surface 4B. The first side surface 4A protrudes from a peripheral top surface 6A that constitutes the outer periphery of the encapsulant 6 and faces the second electrode 5. The first top surface 4B is exposed from the encapsulant 6. The second electrode 5 includes a second side surface 5A and a second top surface 5B. The second side surface 5A protrudes from a peripheral top surface 6A that constitutes the outer periphery of the encapsulant 6 and faces the first electrode 4. The second top surface 5B is exposed from the encapsulant 6. The first side surface 4A and the second side surface 5A are covered with a sealing material 6. The sealing material 6 includes at least one of a recessed portion 6B and a protruding portion 6C (see FIGS. 2 and 3 ) between the first electrode 4 and the second electrode 5.

[0019] In this semiconductor device 101, the creepage distance between the first electrode 4 and the second electrode 5 is longer than the spatial distance between the first electrode 4 and the second electrode 5. The creepage distance corresponds, for example, to the distance from the edge of the first upper surface 4B to the edge of the second upper surface 5B via the surface of the sealing material 6. The spatial distance corresponds, for example, to the linear distance from the edge of the first upper surface 4B to the edge of the second upper surface 5B. Because the creepage distance is longer than the spatial distance, insulation is ensured even if the spatial distance is reduced. As the spatial distance is reduced, the inductances cancel each other out, thereby reducing the inductance of the semiconductor device 101. As described above, the semiconductor device 101 achieves high insulation and low inductance. The semiconductor device 101 is applicable to various products such as power supplies and power sources, power systems, and the like.

[0020] Instead of the insulating substrate 2 in the first embodiment, a single component (not shown) in which the insulating layer 2A and the heat dissipation substrate 1 are integrated may be used. In this case, the heat dissipation substrate 1 includes an insulating layer 2A formed on the upper surface of the heat dissipation substrate 1 and a front circuit pattern 2B formed on the insulating layer 2A. In this case, no bonding material exists between the insulating layer 2A and the heat dissipation substrate 1. The insulating layer 2A is formed of, for example, resin.

[0021] Second Embodiment In a second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0022] 2 is a cross-sectional view showing the configuration of a semiconductor device 102 according to the second embodiment. The sealing material 6 includes a protrusion 6C between the first electrode 4 and the second electrode 5. The protrusion 6C in the second embodiment is formed by the sealing material 6 between the first electrode 4 and the second electrode 5 protruding upward. The upper surface of the protrusion 6C is located higher than the first upper surface 4B of the first electrode 4 and the second upper surface 5B of the second electrode 5.

[0023] Such a semiconductor device 102 achieves low inductance by reducing the spatial distance between the first electrode 4 and the second electrode 5, and improves insulation by increasing the creepage distance.

[0024] Third Embodiment In a third embodiment, the same components as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0025] FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device 103 according to the third embodiment. The encapsulant 6 includes a recess 6B and a protrusion 6C between the first electrode 4 and the second electrode 5. The protrusion 6C of the encapsulant 6 includes a first protrusion 16C and a second protrusion 26C. The first protrusion 16C covers the first side surface 4A and protrudes above the first upper surface 4B. The second protrusion 26C covers the second side surface 5A and protrudes above the second upper surface 5B. In the third embodiment, only the first protrusion 16C and the second protrusion 26C protrude above the first electrode 4 and the second electrode 5. The recess 6B of the encapsulant 6 is provided between the first protrusion 16C and the second protrusion 26C. The bottom surface of the recess 6B is located lower than the first upper surface 4B of the first electrode 4 and the second upper surface 5B of the second electrode 5.

[0026] Such a semiconductor device 103 achieves low inductance by reducing the spatial distance between the first electrode 4 and the second electrode 5, and improves insulation by increasing the creepage distance.

[0027] Fourth Embodiment In a fourth embodiment, the same components as those in any of the first to third embodiments are given the same reference numerals, and detailed description thereof will be omitted.

[0028] FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device 104 according to a fourth embodiment. The first electrode 4 and the second electrode 5 are formed of a plate material having multiple bent portions within the encapsulant 6. The inter-electrode distance H between the first electrode 4 and the second electrode 5 within the encapsulant 6 is shorter than the distance G between the end of the first upper surface 4B and the end of the second upper surface 5B. The inter-electrode distance H in the fourth embodiment is the shortest distance between the first electrode 4 and the second electrode 5 within the encapsulant 6. Similarly, the distance G in the fourth embodiment is the shortest distance between the end of the first upper surface 4B and the end of the second upper surface 5B. The encapsulant 6 includes a recess 6B between the first electrode 4 and the second electrode 5. The bottom surface of the recess 6B is located lower than the first upper surface 4B and the second upper surface 5B.

[0029] Such a semiconductor device 104 achieves low inductance by reducing the spatial distance between the first electrode 4 and the second electrode 5, and improves insulation by increasing the creepage distance.

[0030] Fifth Embodiment In a fifth embodiment, the same components as those in any of the first to fourth embodiments are given the same reference numerals, and detailed description thereof will be omitted.

[0031] 5 is a cross-sectional view showing the configuration of a semiconductor device 105 according to the fifth embodiment. The sealing material 6 includes a first sealing material 16 and a second sealing material 26. The first sealing material 16 seals the insulating substrate 2, the semiconductor element 3, the lower part of the first electrode 4, and the lower part of the second electrode 5. The second sealing material 26 covers the first side surface 4A of the first electrode 4 and the second side surface 5A of the second electrode 5. The second sealing material 26 is an insulating resin. The second sealing material 26 is, for example, an epoxy resin.

[0032] Such a semiconductor device 105 achieves low inductance by reducing the spatial distance between the first electrode 4 and the second electrode 5, and improves insulation by increasing the creepage distance.

[0033] Sixth Embodiment In a sixth embodiment, the same components as those in any of the first to fifth embodiments are given the same reference numerals, and detailed description thereof will be omitted.

[0034] Fig. 6 is a plan view showing the configuration of semiconductor device 106 according to embodiment 6. Fig. 7 is a cross-sectional view showing the configuration of semiconductor device 106 according to embodiment 6. Semiconductor device 106 includes heat dissipation substrate 1, insulating substrate 2, semiconductor element 3, first electrode 4, second electrode 5, and sealing material 6, as well as first bus bar 8 and second bus bar 9.

[0035] The height of the first upper surface 4B from the outer peripheral upper surface 6A of the sealing material 6 is different from the height of the second upper surface 5B from the outer peripheral upper surface 6A of the sealing material 6. The first upper surface 4B in the sixth embodiment is located at a higher position than the second upper surface 5B. The first side surface 4A and the second side surface 5A are covered with the sealing material 6. The sealing material 6 includes a recess 6B between the first electrode 4 and the second electrode 5.

[0036] The first bus bar 8 has a flat plate shape. The first bus bar 8 is joined to the first top surface 4B of the first electrode 4 via a bonding material 7E. The second bus bar 9 has a flat plate shape. The second bus bar 9 is joined to the second top surface 5B of the second electrode 5 via a bonding material 7F. The first bus bar 8 and the second bus bar 9 are arranged parallel to each other and overlap with a gap therebetween. The first bus bar 8 and the second bus bar 9 in the sixth embodiment are parallel flat plates. The first bus bar 8 and the second bus bar 9 are connected to a power system external to the semiconductor device 106.

[0037] In such semiconductor device 106, there is no need to prepare first and second bus bars having bent portions. Because first bus bar 8 and second bus bar 9 can be parallel plates, it is possible to design the clearance between first bus bar 8 and second bus bar 9 with high precision. Because first bus bar 8 and second bus bar 9 are parallel plates, the inductance of the entire power system including semiconductor device 106 is reduced.

[0038] As the current density of semiconductor device 106 increases, the thickness of first bus bar 8 and second bus bar 9 increases. When first bus bar 8 and second bus bar 9 have bent portions, it is difficult to control the distance between them. The first bus bar 8 and second bus bar 9 that are parallel flat plates as described above are effective.

[0039] The sealing material 6 shown in Fig. 7 may have a protrusion in addition to the recess 6B. For example, the protrusion is provided inside the recess 6B. The height of the protrusion is such that it does not come into contact with the first bus bar 8 and the second bus bar 9. Unlike what is shown in Fig. 7, if the region between the first electrode 4 and the second electrode 5 is not covered by the first bus bar 8 and the second bus bar 9, the height of the protrusion may be higher than at least one of the first upper surface 4B and the second upper surface 5B.

[0040] Seventh Embodiment In the seventh embodiment, the same components as those in any of the first to sixth embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0041] FIG. 8 is a plan view showing the configuration of a semiconductor device 107 according to the seventh embodiment. FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device 107 according to the seventh embodiment. The basic configuration of the semiconductor device 107 is similar to that of the semiconductor device 106 shown in the sixth embodiment. In the semiconductor device 107, the first bus bar 8 has a welding mark 8A. The welding mark 8A is formed at the joint between the first bus bar 8 and the first upper surface 4B of the first electrode 4. Similarly, the second bus bar 9 has a welding mark 8B. The welding mark 8B is formed at the joint between the second bus bar 9 and the second upper surface 5B of the second electrode 5.

[0042] When solder or other bonding materials 7E and 7F are used to bond the electrodes and bus bars, the volume of the bonding material differs before and after hardening, making it difficult to control the clearance between the first bus bar 8 and the second bus bar 9. However, by using welding to bond the electrodes and bus bars, the clearance between the first bus bar 8 and the second bus bar 9 can be controlled with high precision.

[0043] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0044] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0045] REFERENCE SIGNS LIST 1 heat dissipation substrate, 2 insulating substrate, 2A insulating layer, 2B front circuit pattern, 2C back circuit pattern, 3 semiconductor element, 4 first electrode, 4A first side surface, 4B first upper surface, 5 second electrode, 5A second side surface, 5B second upper surface, 6 sealing material, 6A outer peripheral upper surface, 6B recess, 6C protrusion, 7A to 7F bonding material, 8 first bus bar, 8A welding mark, 8B welding mark, 9 second bus bar, 16 first sealing material, 16C first protrusion, 26 second sealing material, 26C second protrusion, 101 to 107 semiconductor device, G distance, H inter-electrode distance.

Claims

1. A semiconductor element, a first electrode electrically connected to the semiconductor element, a second electrode provided adjacent to the first electrode and electrically connected to the semiconductor element, and a sealing material that seals the semiconductor element, the upper surface other than the upper surface of the first electrode, and the upper surface other than the upper surface of the second electrode, wherein the first electrode includes a first side surface that protrudes from an outer peripheral upper surface constituting an outer peripheral portion of the sealing material and faces the second electrode, and a first upper surface that is the upper surface exposed from the sealing material, the second electrode includes a second side surface that protrudes from the outer peripheral upper surface of the sealing material and faces the first electrode, and a second upper surface that is the upper surface exposed from the sealing material, the first side surface and the second side surface are covered with the sealing material, and the sealing material includes at least one of a concave portion and a convex portion between the first electrode and the second electrode, a semiconductor device.

2. The semiconductor device according to claim 1, wherein a bottom surface of the concave portion of the sealing material is provided at a position lower than the first upper surface and the second upper surface.

3. The semiconductor device according to claim 1 or claim 2, wherein an upper surface of the convex portion of the sealing material is provided at a position higher than the first upper surface and the second upper surface.

4. The convex portion of the sealing material, includes a first protruding portion that covers the first side surface and protrudes above the first upper surface, and a second protruding portion that covers the second side surface and protrudes above the second upper surface, The semiconductor device according to claim 1 or claim 2, wherein the concave portion of the sealing material is provided between the first protruding portion and the second protruding portion.

5. The semiconductor device according to claim 1 or claim 2, wherein an interelectrode distance between the first electrode and the second electrode inside the sealing material is shorter than a distance between an end portion of the first upper surface and an end portion of the second upper surface.

6. The sealing material, includes a first sealing material that seals the semiconductor element, and a second sealing material that covers the first side surface of the first electrode and the second side surface of the second electrode, The semiconductor device according to claim 1 or claim 2, wherein the second sealing material is a resin having insulating properties.

7. The semiconductor device according to claim 1 or claim 2, wherein a height of the first upper surface of the first electrode from the outer peripheral upper surface of the sealing material is different from a height of the second upper surface of the second electrode from the outer peripheral upper surface of the sealing material.

8. a first bus bar having a flat plate shape and joined to the first upper surface of the first electrode; a second bus bar having a flat plate shape and joined to the second upper surface of the second electrode, the semiconductor device according to claim 7, further comprising: the first bus bar and the second bus bar are provided so as to overlap each other in parallel with a space therebetween.

9. the first bus bar has a welding mark at a joint between the first bus bar and the first upper surface; the second bus bar has a welding mark at a joint between the second bus bar and the second upper surface, the semiconductor device according to claim 8.

10. the encapsulant covers the entire first side surface of the first electrode and the entire second side surface of the second electrode, the semiconductor device according to claim 1 or claim 2.