Microphone signal conversion module and microphone module

Abstract

The microphone signal conversion module (1) includes a buffer circuit (2) that outputs a second analog signal (Sa2) obtained by performing level conversion with a first gain (G1) on a first analog signal (Sa1) input from a transducer, an analog-to-digital conversion circuit (3) that converts the level of the second analog signal (Sa2) into a digital value with a second gain (G2), and a control circuit (4) that controls the first gain (G1) and the second gain (G2). The second analog signal (Sa2) is input to the control circuit (4), and the control circuit (4) is configured to control the magnitudes of the first gain (G1) and the second gain (G2) in opposite directions based on the level of the second analog signal (Sa2).

Description

[Technical field]

[0001] The present invention relates to a microphone signal conversion module and a microphone module. [Background technology]

[0002] Conventionally, transducers that convert various types of energy into different types of energy have been widely used in industrial and consumer applications. One form of such transducers is a microphone. With the development of interactive devices due to the recent dramatic progress in natural language processing technology and voice recognition technology, the usefulness of microphone devices and the demand for microphones have increased. A transducer that functions as a microphone detects sound and converts it into an analog electrical signal. Therefore, in many applications, the electrical signal generated by the microphone is converted into a digital signal and input to a signal processing device such as a microcomputer, as in the microphone device shown in Patent Document 1, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-120310 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a device such as that disclosed in Patent Document 1, which converts analog electrical signals such as audio signals into digital signals, the electrical signal input from a microphone or the like is amplified to a level suitable for an analog-to-digital converter (AD converter) before the conversion. Such an electronic module that converts the level, form, etc. of an analog signal is required to ensure a sufficient signal-to-noise ratio (SN ratio) so that the signal detected by the microphone is not buried in noise such as conversion errors.

[0005] On the other hand, electronic modules that amplify and convert signals from small transducers, such as MEMS (Micro Electro Mechanical Systems) microphones, are often required to operate at low voltages and low current consumption. In addition, in order to meet the continuous demand for miniaturization of various devices equipped with microphones, there is also a constant demand for miniaturization of microphone electronic modules themselves. In theory, it may be difficult to ensure a sufficient signal-to-noise ratio in low-voltage, low-current, and small-sized electronic modules that amplify and convert signals from such microphones.

[0006] One way to improve the SNR is to increase the gain of amplifier (preamplifier) ​​901 in the stage preceding AD converter 910 in microphone amplifier 900 as shown in Fig. 8A. AD converter 910 is a typical delta-sigma AD converter, and includes subtractor 902, integrator 903, quantizer 904, and 1-bit DA converter 905.

[0007] By increasing the gain of the preamplifier 901, the signal input to the AD converter 910 can be increased, and the apparent S / N ratio can be increased. However, when the gain of the preamplifier 901 is increased in this way, when the amplitude of the input signal Vi is large, the output signal Vo may become saturated like the signal Voa shown in Fig. 8B. Note that the signal Voa shown in Fig. 8B is an analog signal obtained by passing the output signal Vo of the AD converter 910 through an appropriate low-pass filter (the output signals So and Voa shown in Figs. 6A, 9, and 10, which will be referred to in turn below, are also output signals after passing through a low-pass filter in the same manner).

[0008] That is, in Fig. 8B, the signal Via input to the AD converter 910 is saturated near the extreme value of the amplitude of the input signal Vi (within part P in Fig. 8B). As a result, the delta-sigma AD converter 910 does not perform an appropriate conversion operation, and the signal Voa cannot reproduce the input signal Vi. In this way, simply increasing the gain of the amplifier in the front stage of the AD converter to improve the SNR can reduce the dynamic range. Therefore, there is a problem that it is difficult for an electronic module that handles microphone signals to fully provide the required performance in both SNR and dynamic range.

[0009] In view of the above problems, an object of the present invention is to enable conversion of an analog signal from a transducer into a digital value without sacrificing the dynamic range and with a good signal-to-noise ratio. [Means for solving the problem]

[0010] A microphone signal conversion module according to an embodiment of the present invention includes a buffer circuit that performs level conversion with a first gain on a first analog signal input from a transducer and outputs a second analog signal obtained by the level conversion, an analog-to-digital conversion circuit that converts the level of the second analog signal into a digital value with a second gain, and a control circuit that controls the first gain and the second gain. The second analog signal is input to the control circuit, and the control circuit is configured to control the magnitudes of the first gain and the second gain in opposite directions to each other based on the level of the second analog signal.

[0011] A microphone module according to an embodiment of the present invention includes the above microphone signal conversion module and a MEMS transducer that generates the first analog signal. Effect of the Invention

[0012] According to the microphone signal conversion module and microphone module of the present invention, an analog signal from a transducer can be converted into a digital value with a good signal-to-noise ratio without sacrificing the dynamic range. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a block diagram illustrating an example of a microphone signal conversion module and a microphone module according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a circuit diagram illustrating an example of a buffer circuit according to an embodiment of the present invention. [Figure 2B] FIG. 2B is a circuit diagram showing a more specific example of the configuration of the example in FIG. 2A. [Figure 3A] FIG. 4 is a circuit diagram showing another example of a buffer circuit in an embodiment of the present invention. [Figure 3B] FIG. 3B is a circuit diagram showing a more specific example of the configuration of the example in FIG. 3A. [Figure 4] FIG. 2 is a block diagram showing an example of a control circuit according to an embodiment of the present invention. [Figure 5A] 1 is a block diagram showing an example of an AD conversion circuit according to an embodiment of the present invention. [Figure 5B] FIG. 5B is a block diagram showing a more specific example of the configuration of the example in FIG. 5A. [Figure 6A] 3A to 3C are diagrams illustrating examples of signal waveforms in a microphone signal conversion module according to an embodiment of the present invention. [Figure 6B] 6B is an enlarged view of part VIB in FIG. 6A together with changes in gain and count value. FIG. [Figure 7] FIG. 4 is a block diagram showing another example of an AD conversion circuit in one embodiment of the present invention. [Figure 8A] FIG. 1 is a circuit diagram showing an example of a conventional microphone amplifier. [Figure 8B] 8B is a diagram showing signal waveforms at various parts in the conventional microphone amplifier of FIG. 8A. [Figure 9]1A to 1C are diagrams illustrating an example of signal waveforms at various parts when an increase or decrease in the gain of a preamplifier is compensated for by digital processing in a conventional microphone amplifier. [Figure 10] 11A to 11C are diagrams showing other examples of signal waveforms at various parts when an increase or decrease in the gain of a preamplifier is compensated for by digital processing in a conventional microphone amplifier. [Figure 11A] 1 is a circuit diagram showing a comparative example for the buffer circuit of the microphone signal conversion module of the embodiment. [Figure 11B] 11B is a diagram showing an example of a signal waveform by the buffer circuit of FIG. 11A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] With reference to the drawings, the embodiments of the microphone signal conversion module and microphone module of the present invention will be described. Note that the embodiments described below merely show some of the possible aspects of the microphone signal conversion module and microphone module of the present invention. The microphone signal conversion module and microphone module of the present invention are not limited to the embodiments described below.

[0015] <Overall structure and function> 1 shows a microphone signal conversion module 1, which is an example of a microphone signal conversion module of an embodiment, and a microphone module 10, which is an example of a microphone module of an embodiment and includes the microphone signal conversion module 1. Note that the microphone signal conversion module of the embodiment described below is also simply referred to as a "microphone signal module."

[0016] 1, a microphone signal module 1 of this embodiment includes a buffer circuit 2 that performs level conversion on an analog signal and outputs the converted signal, an analog-to-digital conversion circuit (AD conversion circuit) 3 that converts the level of the analog signal into a digital value, and a control circuit 4. In the example of FIG. 1, a microphone module 10 of this embodiment includes the microphone signal module 1 and a microphone 11.

[0017] The microphone signal module 1 in FIG. 1 further includes a constant voltage source 5 and an output buffer 6. The constant voltage source 5 generates a constant voltage Vc as a bias voltage for operating the microphone 11 and provides it to the microphone 11. The constant voltage source 5 is composed of, for example, a linear regulator such as a low dropout (LDO) regulator, a switching regulator, or the like. The output buffer 6 receives a digital signal Sd1 from the AD conversion circuit 3. The output buffer 6 outputs the digital signal Sd1 with an output impedance and driving capability required for an external device (not shown) connected to the output terminal Sout of the microphone signal module 1. The output buffer 6 is composed of, for example, a non-inverting inverter or a composite circuit of transistors.

[0018] The buffer circuit 2 performs level conversion on the first analog signal Sa1 input from the microphone 11 at a first gain G1, and outputs a second analog signal Sa2 obtained by the level conversion. The AD conversion circuit 3 converts the level of the second analog signal Sa2 into a digital value at a second gain G2, and outputs a digital signal Sd1, which is the converted signal. The second analog signal Sa2 is input from the buffer circuit 2 to the control circuit 4. The control circuit 4 controls the first gain G1 of the buffer circuit 2 and the second gain G2 of the AD conversion circuit 3 by outputting control signals Sc1 and Sc2 based on the level of the second analog signal Sa2. That is, the buffer circuit 2 is configured so that the first gain G1 can be controlled, i.e., adjusted, from outside the buffer circuit 2. And the AD conversion circuit 3 is configured so that the second gain G2 can be controlled, i.e., adjusted, from outside the AD conversion circuit 3.

[0019] As generally used, the first gain G1 of the buffer circuit 2 is the ratio of the level (absolute value) of the output signal output based on the input signal to the level (absolute value) of the input signal. Meanwhile, the second gain G2 of the AD conversion circuit 3 indicates the amount of change in the output digital value applied to a unit amount of change in the level of the input analog signal. For example, when the second gain G2 is 0 dB, an analog signal having a voltage amplitude one time that of the analog signal input to the AD conversion circuit 3 is obtained by converting the output signal of the AD conversion circuit 3 into an analog signal. In another example, when the second gain G2 is 20 dB, an analog signal having a voltage amplitude ten times that of the input analog signal is obtained by similarly converting the output signal of the AD conversion circuit 3 into an analog signal.

[0020] Specifically, the control circuit 4 is configured to control the magnitudes of the first gain G1 and the second gain G2 in opposite directions based on the level of the second analog signal Sa2. That is, when the control circuit 4 increases the first gain G1 based on the level of the second analog signal Sa2, it decreases the second gain G2, and when the control circuit 4 decreases the first gain G1, it increases the second gain G2. By controlling the first gain G1 and the second gain G2 in this way, it is possible to keep the linearity of the output signal relative to the input signal of the microphone signal module 1 constant.

[0021] In the microphone signal module 1 of the embodiment including the control circuit 4 configured as described above, as an example, the first gain G1 in the default state (basic state, initial state, or factory-shipped state) is set to a relatively large value. By doing so, even when the amplitude of the input signal (first analog signal Sa1) is small, the amplitude of the second analog signal Sa2 can be increased. Therefore, the S / N ratio can be improved. The second gain G2 is set to a relatively small value according to the relatively large first gain G1. Therefore, a digital signal Sd1 having a magnitude according to the level of the first analog signal Sa1 is obtained as the output of the AD conversion circuit 3.

[0022] On the other hand, when the amplitude of the first analog signal Sa1 is large to a certain extent, causing signal saturation in the microphone signal module 1, the control circuit 4 reduces the first gain G1 to reduce (compress) the amplitude of the second analog signal Sa2. By doing so, it is possible to prevent signal saturation in the microphone signal module 1. Therefore, it is possible to avoid a decrease in the dynamic range.

[0023] When the control circuit 4 reduces the first gain G1 in this way, it increases the second gain G2. That is, the signal is expanded in the conversion from the second analog signal Sa2 to the digital signal Sd1. Therefore, it is possible to compensate for the attenuation of the output signal (digital signal Sd1) caused by reducing the first gain G1. Therefore, it is possible to obtain an output signal (digital signal Sd1) that can faithfully reproduce the relatively large amplitude of the input signal (first analog signal Sa1). That is, it is possible to prevent or at least suppress a decrease in the dynamic range.

[0024] In addition, the gain (sensitivity) of the entire microphone signal module 1 can be kept constant from small to large amplitudes of the input signal. Moreover, even when the amplitude of the input signal is small, a good S / N ratio can be ensured. Therefore, according to this embodiment, an analog signal from a transducer such as the microphone 11 can be converted into a digital value with a good S / N ratio without sacrificing the dynamic range.

[0025] The microphone signal module 1 of this embodiment can receive an input signal (first analog signal Sa1) from a transducer of any type and structure capable of converting sound into an electric signal, not limited to the microphone 11. In other words, the transducer that inputs the input signal to the microphone signal module 1 does not have to be intended for use as a microphone. The microphone signal module 1 can receive, as the first analog signal Sa1, a signal from any transducer capable of converting air vibrations at any frequency, not limited to the audible range, into an electric signal.

[0026] In particular, a signal generated by a MEMS transducer using MEMS technology as a mechanism for detecting vibrations in the air may be input to the microphone signal module 1 as the first analog signal Sa1. Thus, the microphone 11 in the example of FIG. 1 may be a MEMS microphone. Similarly, the microphone module 10 of the embodiment may include the microphone signal module 1 and a MEMS transducer that generates the first analog signal Sa1. The microphone 11 included in the microphone module 10 in the example of FIG. 1 may be a MEMS microphone. It is believed that the inclusion of a MEMS microphone makes it possible to obtain a microphone module 10 having good performance, such as small size and high heat resistance.

[0027] The following describes an example and some modified examples of the buffer circuit 2, the control circuit 4, and the AD conversion circuit 3. Note that the configurations of the circuits described below are merely examples of the circuits, and the configurations of the circuits are not limited to the configurations described below.

[0028] <An example of a buffer circuit (inverting type)> FIG. 2A shows an example of a configuration that the buffer circuit 2 of the microphone signal module of this embodiment can take. As shown in FIG. 2A, the buffer circuit 2 includes an operational amplifier 21 and a plurality of capacitors (capacitor 22 and capacitor 23). The operational amplifier 21 has an inverting input terminal that receives a first analog signal Sa1 from a transducer such as the microphone 11, and a non-inverting input terminal to which a reference potential Vref is applied. The capacitors 22 and 23 are arranged in parallel with each other between the output terminal and the inverting input terminal of the operational amplifier 21. In FIG. 2A, the capacitance of the capacitor 22 is fixed, while the capacitor 23 is a variable capacitor whose capacitance can be adjusted.

[0029] The reference potential Vref is generated independently of the constant voltage Vc, for example, by a voltage source (not shown) separate from the constant voltage source 5 in Fig. 1. The reference potential Vref can be, for example, a midpoint potential of the maximum amplitude of the first analog signal Sa1, or a midpoint potential between the positive and negative power supplies of the operational amplifier 21 (between the power supply and ground in the case of a single power supply).

[0030] If the microphone 11 is a capacitive transducer such as a capacitive MEMS microphone, it has an inherent capacitance. Therefore, the first gain G1 of the buffer circuit 2 with respect to the AC component of the first analog signal Sa1 is expressed by the following (Equation 1). G1=C11 / (C22+C23) (Formula 1) Here, C11, C22, and C23 are the capacitances of the microphone 11, the capacitor 22, and the capacitor 23, respectively. Therefore, the control circuit 4 (see FIG. 1) can adjust the first gain G1 by adjusting the capacitance of the capacitor 23.

[0031] Fig. 2B shows a more specific example of the configuration of the buffer circuit 2 of Fig. 2A. Fig. 2B shows a more specific example of the capacitor 23 whose capacitance is adjustable. As shown in Fig. 2B, the capacitor 23 is composed of a plurality of capacitors for adjusting the first gain G1, namely, capacitors 231, 232, 233, ... 23n. In this way, the buffer circuit 2 includes a plurality of capacitors arranged between the output terminal and the inverting input terminal of the operational amplifier 21.

[0032] Further, the buffer circuit 2 includes a plurality of switches 24 and a plurality of switches 25. Each switch 25 is disposed between one end of any one of the capacitors 231-23n, which are a part of the plurality of capacitors between the output terminal and the inverting input terminal of the operational amplifier 21, and the inverting input terminal of the operational amplifier 21. Each switch 25 connects or disconnects any one of the capacitors 231-23n to which the switch 25 is connected and the inverting input terminal of the operational amplifier 21. Meanwhile, each switch 24 is connected in parallel with any one of the capacitors 231-23n. When each switch 24 is closed, the capacitor of the capacitors 231-23n that is connected in parallel to the closed switch 24 is discharged.

[0033] In the buffer circuit 2 configured as shown in FIG. 2B, the combined capacitance of the capacitor 22 and the capacitor 23 can be adjusted by closing a desired number of switches 25. That is, the first gain G1 can be adjusted. According to the above (Equation 1), by closing the switch 25, the capacitances 231 to 23n connected to the operational amplifier 21 via the switch 25 can be increased to reduce the first gain G1. Therefore, the control circuit 4 may be configured to control the first gain G1 by opening and closing the switch 25. For example, when the amplitude of the first analog signal Sa1 is large, the control circuit 4 (see FIG. 1) can attenuate the second analog signal Sa2 by closing the switch 25.

[0034] 2B, by closing switch 24, it is possible to discharge those of capacitors 231-23n that do not contribute to the adjustment of first gain G1, i.e., those that are not connected to operational amplifier 21 via switch 25. Control circuit 4 is configured to discharge those of capacitors 23 that do not contribute to setting first gain G1, by closing switch 24.

[0035] The capacitors 231 to 23n are preferably configured to be discharged when they are separated from the inverting input terminal of the operational amplifier 21 by the switch 25, as described above. By discharging the capacitors 231 to 23n in this manner, when these separated capacitors are connected to the operational amplifier 21 and the first gain G1 is switched, the amount of charge stored between the input and output terminals of the operational amplifier 21 is correctly maintained. Therefore, theoretically, no DC offset is generated in the second analog signal Sa2 due to the switching of the first gain G1. Therefore, the first gain G1 can be switched even when the first analog signal Sa1 is not at a zero cross (or a midpoint potential cross).

[0036] As described above, when the second analog signal Sa2 is to be attenuated, the switch 25 is closed. On the other hand, a state in which all the switches 25 are open and all the switches 24 are closed may be the default state of the microphone signal module. In such a state in which all the switches 25 are open, as is clear from the above (Equation 1), the first gain G1 is determined by the ratio between the capacitance of the capacitor 22 and the capacitance of the microphone 11. Not limited to this default state, the first gain G1 depends on the capacitance of a transducer such as the microphone 11, as shown in (Equation 1).

[0037] However, the amount of change in the first gain G1 caused by closing the switch 25 (for example, the amount of attenuation of the second analog signal Sa2 caused by closing one switch 25) is determined by the ratio of C22 to C23 in the denominator of the above (Equation 1). In other words, the attenuation rate ∂G1 of the first gain G1 caused by adjusting the capacitance of the capacitor 23 is expressed by the following (Equation 2). ∂G1=1+(C22 / C23) (Equation 2) As an example, when the microphone signal module of the embodiment is configured on a semiconductor substrate, the capacitor 22 and the capacitor 23 are formed on the semiconductor substrate. In such a case, it is relatively easy to accurately fabricate the ratio between the capacitance of the capacitor 22 and the capacitance of each of the capacitors 231 to 23n. Therefore, it may be relatively easy to correctly configure the amount of change in the first gain G1 caused by closing the switch 25.

[0038] Therefore, by configuring the element that determines the second gain G2 on a semiconductor substrate in the same manner as the capacitors 22 and 23, good linearity of the microphone signal module can be easily ensured even if the capacitance of the microphone 11 varies. Thus, in the inverting buffer circuit 2 illustrated in Figs. 2A and 2B, the first gain G1 depends on the variation in capacitance of the transducer such as the microphone 11. However, it is considered relatively easy to ensure linearity in the signal conversion of the microphone signal module involving control of each gain. Incidentally, the variation in the first gain G1 due to the variation in the capacitance of the transducer can be compensated for by a conventional adjustment method.

[0039] <Another example of a buffer circuit (non-inverting type)> FIG. 3A shows another example of a configuration that the buffer circuit 2 of the microphone signal module of this embodiment can take. In the example shown in FIG. 3A, the buffer circuit 2 includes a non-inverting buffer 26 and a capacitor 27. The non-inverting buffer 26 has an input terminal that receives the first analog signal Sa1 sent from the microphone 11. The non-inverting buffer 26 is, for example, an operational amplifier whose inverting input terminal and output terminal are connected to form a voltage follower. The non-inverting input terminal of the operational amplifier may be the input terminal of the non-inverting buffer 26 in FIG. 3A. In the example of FIG. 3A, the microphone 11 is a capacitive transducer such as a capacitive MEMS microphone. The capacitor 27 is disposed between the input terminal of the non-inverting buffer 26 and a reference potential Vref, which is a predetermined constant potential. The capacitor 27 is a variable capacitance capacitor whose capacitance can be adjusted.

[0040] The reference potential Vref is generated independently of the constant voltage Vc, for example, by a voltage source (not shown) separate from the constant voltage source 5 in Fig. 1. The reference potential Vref can be, for example, a midpoint potential of the maximum amplitude of the first analog signal Sa1, or a midpoint potential between the positive and negative power supplies of the operational amplifier 21 (between the power supply and ground in the case of a single power supply).

[0041] The microphone 11, which is a capacitive transducer, has an inherent capacitance. Therefore, the first gain G1 of the buffer circuit 2 with respect to the AC component of the first analog signal Sa1 is expressed by the following (Equation 3). G1=C11 / (C11+C27) (Formula 3) Here, C11 and C27 are the capacitances of the microphone 11 and the capacitor 27, respectively. Therefore, the control circuit 4 (see FIG. 1) can adjust the capacitance of the capacitor 27 to adjust the first gain G1.

[0042] Fig. 3B shows a more specific configuration example of one example of the buffer circuit 2 in Fig. 3A. Fig. 3B shows a more specific example of the capacitor 27 whose capacitance is adjustable. As shown in Fig. 3B, the capacitor 27 is composed of a plurality of capacitors for adjusting the first gain G1, namely, capacitors 271, 272, 273, ... 27n. That is, the buffer circuit 2 includes a plurality of capacitors each arranged between the input terminal of the non-inverting buffer 26 and a reference potential Vref, which is a predetermined constant potential.

[0043] Further, the buffer circuit 2 includes a plurality of switches 28 and a plurality of switches 29. Each switch 29 is disposed between the input terminal of the non-inverting buffer 26 and one end of any one of the capacitors 271 to 27n. The switch 29 connects or disconnects the plurality of capacitors 271 to 27n and the input terminal of the non-inverting buffer 26. Meanwhile, each switch 28 is connected in parallel to any one of the capacitors 271 to 27n. When each switch 28 is closed, the capacitor among the capacitors 271 to 27n that is connected in parallel to the closed switch 28 is discharged.

[0044] In the buffer circuit 2 configured as shown in FIG. 3B, the capacitance of the capacitor 27 can be adjusted to adjust the first gain G1 by closing a desired number of switches 29. According to the above (Equation 3), by closing the switch 29, the capacitances 271 to 27n connected to the non-inverting buffer 26 can be increased to reduce the first gain G1. Therefore, the control circuit 4 may be configured to control the first gain G1 by opening and closing the switch 29. For example, when the amplitude of the first analog signal Sa1 is large, the control circuit 4 (see FIG. 1) can attenuate the second analog signal Sa2 by closing the switch 29.

[0045] 3B, among the capacitors 271 to 27n, those that are not connected to the non-inverting buffer 26 via the switch 29 can be discharged by closing the switch 28. The control circuit 4 is configured to discharge, by closing the switch 28, those of the capacitors constituting the capacitor 27 that do not contribute to setting the first gain G1.

[0046] The capacitors 271 to 27n are preferably configured to be discharged when they are separated from the input terminal of the non-inverting buffer 26 by the switch 29 as described above. By discharging the capacitors 271 to 27n in this manner, when the separated capacitors are connected to the non-inverting buffer 26 and the first gain G1 is switched by connecting the separated capacitors to the non-inverting buffer 26, the amount of charge stored in the capacitor connected to the non-inverting buffer 26 is correctly maintained. Therefore, theoretically, no DC offset is generated in the second analog signal Sa2 due to the switching of the first gain G1. Therefore, the first gain G1 can be switched even when the first analog signal Sa1 is not at a zero cross (or a midpoint potential cross).

[0047] As described above, when the second analog signal Sa2 is to be attenuated, the switch 29 is closed. On the other hand, a state in which all the switches 29 are open and all the switches 28 are closed may be the default state of the microphone signal module. In such a state in which all the switches 29 are open, as is clear from the above (Equation 3), the first gain G1 is 1x (0 dB). Therefore, in the example of FIG. 3B, it is considered that the variation in the first gain G1 in the default state is small.

[0048] On the other hand, the amount of change in the first gain G1 caused by closing the switch 29 (for example, the amount of attenuation of the second analog signal Sa2 caused by closing one switch 29) is determined by the ratio of C11 and C27 in the denominator of the above (Equation 3). That is, the attenuation rate ∂G1 of the first gain G1 caused by adjusting the capacitance of the capacitor 27 is expressed by the following (Equation 4). ∂G1=1+(C11 / C27) (Equation 4) Therefore, the amount of change in the first gain G1 depends on the variation in the capacitance C11 of the capacitive transducer.

[0049] Since the capacitance C11 varies independently of the capacitance C27 of the capacitor 27, the amount of change in the first gain G1 relative to the amount of adjustment of the capacitance C27 varies according to the variation in the capacitance C11. Therefore, in an operating region where one of the switches 29 is closed to attenuate the second analog signal Sa2, the linearity between the input of the buffer circuit 2 and the output of the AD conversion circuit 3 (see FIG. 1) is not maintained depending on the variation in the capacitance of the transducer. For example, in a plot diagram in which the horizontal and vertical axes represent the input and output, the relationship between the two is shown as a straight line in the region of small input values, but is shown as a curve whose slope gradually increases or decreases in the region of input values ​​above a certain value. Therefore, in order to correct the variation in the capacitance of the transducer, preferably, the amount of feedback in the AD conversion circuit 3 (see FIG. 1) is adjusted. This adjustment will be described in detail later with reference to FIG. 7.

[0050] The capacitors 231-23n in Fig. 2B and the capacitors 271-27n in Fig. 3B are arranged in a number corresponding to the number of set values ​​required for the first gain G1. The same number of switches 24 and switches 25 as the number of capacitors 231-23n are provided. Similarly, the same number of switches 28 and switches 29 as the number of capacitors 271-27n are provided. By providing n capacitors 231-23n or n capacitors 271-27n, the first gain G1 can be set to n values ​​other than the value in the default state.

[0051] <Control circuit> FIG. 4 is a block diagram showing an example of a configuration that the control circuit 4 of the microphone signal module of this embodiment can take. The control circuit 4 shown in FIG. 4 includes a comparison circuit 40, an OR gate 43, a counter 44, a detector 45, an edge detection circuit 46, a pulse generation circuit 47, and an OR gate 48. The pulse generation circuit 47 includes a timer 471 and a pulse generator 472. The comparison circuit 40 compares the level of the second analog signal Sa2 with a predetermined upper threshold Vth+ and a predetermined lower threshold Vth-. In the example of FIG. 4, the comparison circuit 40 includes a comparator 41 and a comparator 42.

[0052] The upper threshold Vth+ is input to the inverting input terminal of the comparator 41, and the lower threshold Vth- is input to the non-inverting input terminal of the comparator 42. The non-inverting input terminal of the comparator 41 and the inverting input terminal of the comparator 42 are connected to the output terminal of the buffer circuit 2 (see FIG. 1). Therefore, the second analog signal Sa2 is input to the non-inverting input terminal of the comparator 41 and the inverting input terminal of the comparator 42. The comparator 41 compares the second analog signal Sa2 with a predetermined upper threshold Vth+. The comparator 42 compares the second analog signal Sa2 with a predetermined lower threshold Vth-. The output voltages of the comparators 41 and 42 are input to the input terminals of the OR gate 43. The comparators 41 and 42 form a window comparator having a range from the lower threshold Vth- to the upper threshold Vth+ as a comparison target.

[0053] The counter 44 has an increment input terminal 441, a decrement terminal 442, and an output terminal 443. The counter 44 increments the count value by one in response to a rising edge or a falling edge input to the increment input terminal, and decrements the count value by one in response to a rising edge or a falling edge input to the decrement input terminal. The counter 44 outputs the count value held therein in serial or parallel from one or more output terminals 443.

[0054] The OR gate 43 outputs a logical sum of the logical value of the output voltage of the comparator 41 and the logical value of the output voltage of the comparator 42 to an increment input terminal 441 of the counter 44. Therefore, the count value of the counter 44 is incremented every time the second analog signal Sa2 exceeds the upper threshold Vth+, and is further incremented every time the second analog signal Sa2 falls below the lower threshold Vth-.

[0055] The detector 45 is composed of a comparator. The inverting input terminal of the detector 45 is connected to the output terminal of the buffer circuit 2. The second analog signal Sa2 is input to the inverting input terminal of the detector 45, and the midpoint potential Vcom of the maximum amplitude of the second analog signal Sa2 is input to the non-inverting input terminal. Therefore, the detector 45 detects an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom (a crossing between the second analog signal Sa2 and the midpoint potential Vcom on a time series basis, and a zero crossing when the midpoint potential Vcom is 0V). Each time the inversion is detected, the logic of the output voltage of the detector 45 changes from "positive ("1")" (high level potential) to "negative ("0")" (low level potential) or from "negative" to "positive".

[0056] Specifically, in the example of Fig. 4, when the level of the second analog signal Sa2 reaches the midpoint potential Vcom from a side lower than the midpoint potential Vcom or exceeds the midpoint potential Vcom, the logic of the output voltage of the detector 45 changes from "positive" to "negative". On the other hand, when the level of the second analog signal Sa2 reaches the midpoint potential Vcom from a side higher than the midpoint potential Vcom or falls below the midpoint potential Vcom, the logic of the output voltage of the detector 45 changes from "negative" to "positive". Note that, unlike Fig. 4, the second analog signal Sa2 may be input to the non-inverting input terminal of the detector 45, and the midpoint potential Vcom may be input to the inverting input terminal.

[0057] The edge detection circuit 46 detects the rising edge of the output voltage of the detector 45 and detects the falling edge of the output voltage of the detector 45. The edge detection circuit 46 outputs a pulse to the OR gate 48 every time it detects either of these two edges. One of the two input terminals of the OR gate 48 is connected to the output terminal of the edge detection circuit 46, and the other is connected to the output terminal of the pulse generator 472. The output terminal of the OR gate 48 is connected to the decrement input terminal 442 of the counter 44. In a state in which a low level is input from the pulse generator 472, the OR gate 48 outputs a pulse that is substantially the same as the input pulse to the decrement input terminal 442 of the counter 44 every time a pulse is input from the edge detection circuit 46. Therefore, the count value of the counter 44 is decremented every time an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is detected.

[0058] That is, the counter 44 is incremented when the comparator circuit 40 detects that the level of the second analog signal Sa2 is outside the range from the lower threshold Vth- to the upper threshold Vth+, and is decremented when the detector 45 detects an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom. As an example, the upper threshold Vth+ and the lower threshold Vth- are selected according to the maximum and minimum values ​​of the maximum input voltage range of the AD conversion circuit 3, respectively. As an example, the upper threshold Vth+ is a voltage value that is lower by a predetermined voltage width than the maximum value of the maximum input voltage range of the AD conversion circuit 3. Similarly, the lower threshold Vth- may be a voltage value that is higher by a predetermined voltage width than the minimum value of the maximum input voltage range of the AD conversion circuit 3.

[0059] Since the count value is increased and decreased as described above, if the level of the second analog signal Sa2 continues to approach or exceed the maximum or minimum value of the maximum input voltage range of the AD conversion circuit 3, for example, the count value of the counter 44 gradually increases. On the other hand, if the level of the second analog signal Sa2 repeatedly crosses the midpoint potential Vcom without reaching a value near the maximum or minimum value of the maximum input voltage range of the AD conversion circuit 3, the count value of the counter 44 gradually decreases.

[0060] Therefore, by adjusting the first gain G1 according to the count value of the counter 44, it is possible to suppress the generation of the second analog signal Sa2 that exceeds the maximum input voltage range of the AD conversion circuit 3, for example. That is, it is possible to prevent signal saturation in the microphone signal module. Furthermore, by adjusting the second gain G2 according to the count value of the counter 44 in the same manner as the first gain G1, it is possible to compensate for the attenuation of the output signal of the AD conversion circuit 3 (see FIG. 1) caused by reducing the first gain G1. Therefore, the control circuit 4 configured as in the example of FIG. 4 may be configured to control the first gain G1 and the second gain G2 according to the count value of the counter 44.

[0061] The count value outputted in serial or parallel from the output terminal 443 of the counter 44 may be outputted to the buffer circuit 2 as a control signal Sc1 for controlling the first gain G1, and may be outputted to the AD conversion circuit 3 as a control signal Sc2 for controlling the second gain G2. Alternatively, the control circuit 4 may perform necessary signal processing such as processing and distribution on the output signal from the counter 44 including information on the count value in an appropriate signal processing circuit (not shown). Then, the control circuit 4 may output the processed signals as control signals Sc1 and Sc2 to the buffer circuit 2 and the AD conversion circuit 3, respectively.

[0062] In the control circuit 4 of the example of FIG. 4, when an inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is detected, a reset signal Rst is input from the edge detection circuit 46 to the timer 471. Each time the reset signal Rst is input, the timer 471 resets the time counting state up to that point and measures the elapsed time thereafter. Then, when a predetermined time has elapsed, the timer 471 outputs an enable signal En to the pulse generator 472, resets the internal time counting state, and repeats the time counting. When the enable signal En is input, the pulse generator 472 outputs a pulse Pr at every predetermined time.

[0063] In this way, the pulse generating circuit 47 outputs a pulse Pr to the counter 44 when a predetermined time has elapsed from the detection of the inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom by the detector 45 to the detection of the next inversion. Specifically, the pulse generating circuit 47 in the example of FIG. 4 outputs a pulse Pr to the OR gate 48. In a state in which a low level is input from the edge detection circuit 46, the OR gate 48 outputs a pulse Pr to the decrement input terminal 442 of the counter 44 every time a pulse Pr is input from the pulse generating circuit 47. That is, the counter 44 is configured to decrement the count value every time a pulse Pr is output. Therefore, the count value of the counter 44 is decremented every time a predetermined time set in the timer 471 has elapsed from the detection of the inversion of the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom to the detection of the next inversion.

[0064] In the control circuit 4 of FIG. 4 including the pulse generation circuit 47, the count value of the counter 44 can be forcibly decremented by operating the pulse generator 472 based on the elapse of a predetermined time. With such a configuration, when the second analog signal Sa2 is a small signal or no signal that cannot be detected by the detector 45, the count value of the counter 44 can be decremented. Alternatively, when the second analog signal Sa2 with a small amplitude does not change across the midpoint potential Vcom due to an offset from the midpoint potential Vcom, the count value of the counter 44 can be decremented. By forcibly decrementing the count value in such a manner, the first gain G1 and the second gain G2 may be controllable to appropriate values.

[0065] The predetermined time set in the timer 471 is, for example, 50 msec or more. When such a time is set in the timer 471, it is possible to return to the initial state even when a small signal or no signal is present. Note that even if the magnitude relationship between the level of the second analog signal Sa2 and the midpoint potential Vcom is inverted when the count value is 0, the pulse Pr input to the decrement input terminal 442 of the counter 44 is ignored. Therefore, the count value does not change.

[0066] <AD conversion circuit> FIG. 5A shows, in block diagram form, an example of a configuration that the AD conversion circuit 3 of the microphone signal module of the present embodiment can adopt. The AD conversion circuit 3 illustrated in FIG. 5A is a delta-sigma type AD conversion circuit that performs delta-sigma modulation on an input signal (the “delta-sigma type AD conversion circuit” is also referred to as the “sigma-delta type AD conversion circuit”). Therefore, the AD conversion circuit 3 includes a subtractor 31, an integrator 32, a quantizer 33, and a 1-bit digital-to-analog converter (DA converter) 34. A feedback circuit FB is mainly configured by the DA converter 34 to feedback the output value of the AD conversion circuit 3 from the output terminal Vado to the input terminal Vadi of the AD conversion circuit 3.

[0067] The subtractor 31 subtracts a positive or negative reference voltage (+Vr or -Vr) output by the DA converter 34 from the second analog signal Sa2 and outputs the result to the integrator 32. The integrator 32 accumulates the output of the subtractor 31 and outputs the result to the quantizer 33. The quantizer 33 outputs a digital value of "positive ("1")" (high level potential) if the voltage input from the integrator 32 is equal to or greater than a reference value, and outputs a digital value of "negative ("0")" (low level potential) if the voltage is equal to or less than the reference value. The DA converter 34 outputs a positive reference voltage +Vr to the subtractor 31 if the output of the quantizer 33 is "positive", and outputs a negative reference voltage (-Vr) to the subtractor 31 if the output of the quantizer 33 is "negative". By performing such delta-sigma modulation on the second analog signal Sa2, a digital output value in a PDM (pulse density modulation) format according to the magnitude of the second analog signal Sa2 can be obtained. The AD conversion circuit 3 that operates in this manner is suitable for combination with the inverting buffer circuit 2 exemplified in FIGS. 2A and 2B.

[0068] The AD conversion circuit 3 shown in FIG. 5A is configured so that the feedback amount of the feedback circuit FB is adjustable. The "feedback amount" means the magnitude of the voltage given to the input side of the AD conversion circuit 3 based on the output of the quantizer 33. More specifically, in the example of FIG. 5A, the "feedback amount" means the magnitude of the positive or negative reference voltage Vr input to the subtractor 31 based on the positive and negative outputs of the quantizer 33. When the feedback amount increases, the amount of change in the subtraction result for each subtraction process by the subtractor 31 increases, so that the digital value output from the quantizer 33 for the input second analog signal Sa2 decreases, and the second gain G2 decreases. Conversely, when the feedback amount decreases, the digital value output for the input second analog signal Sa2 increases, and the second gain G2 increases. That is, the second gain G2 of the AD conversion circuit 3 can be controlled by increasing or decreasing the feedback amount of the feedback circuit FB. Therefore, the control circuit 4 (see FIG. 1) may be configured to control the second gain G2 by increasing or decreasing the feedback amount of the feedback circuit FB. Such a configuration is believed to facilitate control of the second gain G2.

[0069] FIG. 5B shows a more specific configuration example of one example of the AD conversion circuit 3 of FIG. 5A. FIG. 5B shows a more specific feedback circuit FB capable of adjusting the feedback amount. As shown in FIG. 5B, the feedback circuit FB is composed of a plurality of feedback circuits, namely, feedback circuits FB0, FB1, FB2, FB3, . . . FBn. The feedback circuit FB0 is mainly composed of a DA converter 340. Similarly, the feedback circuits FB1, FB2, FB3, . . . FBn are mainly composed of DA converters 341, 342, 343, . . . FBn, respectively. In this way, the AD conversion circuit 3 may have any number of feedback circuits, each of which is composed of a DA converter.

[0070] 5B further includes a plurality of switches 35. Each switch 35 is provided in each of the feedback circuits FB1 to FBn. Each switch 35 is disposed between the output of each of the DA converters 341 to 34n and the subtractor 31, and connects or disconnects the output of each of the DA converters 341 to 34n and the subtractor 31.

[0071] As described above, each of the DA converters 340, 341 to 34n outputs a positive or negative reference voltage Vr according to the logic of the output of the quantizer 33. Therefore, the more DA converters among the DA converters 341 to 34n that are connected to the subtractor 31 by the switches 35, the greater the feedback amount of the entire feedback circuit FB. Conversely, the fewer the number of DA converters that are connected, the smaller the feedback amount. That is, by controlling the opening and closing of each switch 35, the feedback amount of the feedback circuit FB can be adjusted. Therefore, the control circuit 4 (see FIG. 1) may be configured to control the second gain G2 by opening and closing the switches 35.

[0072] As an example, a state in which all the switches 35 are closed may be the default state of the microphone signal module 1. In this state, the DA converters 340 to 340n form a feedback circuit FB. Then, each time one of the switches 35 is opened, the feedback amount of the feedback circuit FB is reduced by the reference voltage Vr output by one of the DA converters 341 to 34n connected to the opened switch 35. The second gain G2 increases in response to the reduction in the feedback amount. Note that the reference voltages Vr output by the DA converters 340, 341 to 34n may all be the same or different.

[0073] The feedback circuits FB1 to FBn are provided in a number corresponding to the number of set values ​​required for the second gain G2. The same number of switches 35 as the number of feedback circuits FB1 to FBn are provided. By providing n feedback circuits FB1 to FBn, the second gain G2 can be set to n values ​​other than the value in the default state.

[0074] The AD conversion circuit 3 is preferably configured so that the rate of change of the second gain G2 by closing one of the switches 35 is approximately the same as the rate of change of the first gain G1 by closing one of the switches 25 in the buffer circuit 2 of the example of FIG. 2B. The rate of change of the second gain G2 by closing one of the switches 35 may be approximately the same as the rate of change of the first gain G1 by closing one of the switches 29 in the buffer circuit 2 of the example of FIG. 3B, and is preferably approximately the same. Furthermore, the first gain G1 and the second gain G2 may be mutually inverse numbers (numbers with approximately the same absolute value and opposite positive and negative) in decibel notation. When the AD conversion circuit 3 and the buffer circuit 2 are configured in this way, it may be easy to maintain the linearity of the microphone signal module in the control of the first gain G1 and the second gain G2.

[0075] As an example, the control circuit 4 (see FIG. 1) may output a plurality of control signals including a control signal for each of the plurality of switches 24 and the plurality of switches 25 in FIG. 2B. As another example, the control circuit 4 may output a plurality of control signals including a control signal for each of the plurality of switches 28 and the plurality of switches 29 in the example of FIG. 3B. Furthermore, the control circuit 4 may output a plurality of control signals including a control signal for each of the plurality of switches 35 in the example of FIG. 5B. Each of the plurality of control signals may be input to a control terminal of each of the switches 24 and 25, the switches 28 and 29, or the switch 35 that controls opening and closing thereof. Alternatively, the control signal output from the control circuit 4 may be distributed to the control terminals of each of the switches 24 and 25, or each of the switches 28 and 29, and also to the control terminal of each of the switches 35, via an appropriate multiplexer (not shown).

[0076] <Examples of waveforms for each signal> FIG. 6A shows an example of the waveforms of the first analog signal Sa1 and the second analog signal Sa2 generated by inputting the first analog signal Sa1 in the microphone signal module 1 (see FIG. 1) of this embodiment. FIG. 6A also shows an example of the waveform of the output signal So obtained from the AD conversion circuit 3 (see FIG. 1) for the first analog signal Sa1 in FIG. 6A. Note that the output signal So in FIG. 6A is a waveform of a signal obtained by passing the digital signal Sd1 (see FIG. 1) output from the AD conversion circuit 3 through a low-pass filter, as described above with reference to FIG. 8B. The first analog signal Sa1 and the second analog signal Sa2 in the VIB section in FIG. 6A are enlarged and shown in FIG. 6B. FIG. 6B also shows an example of changes in the count value Nc, the first gain G1, and the second gain G2 of the counter 44 (see FIG. 4) included in the control circuit 4.

[0077] As shown in Fig. 6A, in the time domain before time T1, the amplitude of the first analog signal Sa1 is relatively small, so that the first analog signal Sa1 is amplified by the first gain G1 to generate a second analog signal Sa2 having an amplitude larger than that of the first analog signal Sa1. It is considered that the signal-to-noise ratio is improved by generating the second analog signal Sa2 having a large amplitude. The first gain G1 at this time may be, for example, C11 / C22 based on the above (Equation 1) described above with reference to Fig. 2A. Here, C11 is the capacitance of a transducer such as the microphone 11 (see Fig. 2A), and C22 is the capacitance between the input and output of the buffer circuit 2 in Fig. 2A.

[0078] In the time domain up to time T1, the AD conversion circuit 3 (see FIG. 5B) converts the level of the second analog signal Sa2 into a digital value with a second gain G2 corresponding to the first gain G1. As a result, the first analog signal Sa1 is reproduced almost faithfully in the output signal So.

[0079] After time T1, the amplitude of the first analog signal Sa1 increases, so the first gain G1 is made smaller than the value in the time domain before time T1. That is, as shown in FIG. 6B, the second analog signal Sa2 reaches the lower threshold Vth- at time T11, so the count value Nc is incremented. Therefore, the first gain G1 is made smaller than the value up to time T11. As a result, the amplitude of the second analog signal Sa2 decreases by an amount corresponding to the decrease in the first gain G1, so that the signal does not become saturated in the AD conversion circuit 3. In addition, the second gain G2 is increased in response to the increment in the count value Nc, so that the second analog signal Sa2 is converted into a digital value of an appropriate magnitude.

[0080] Since the level of the first analog signal Sa1 continues to increase even after time point T11, the second analog signal Sa2 reaches the lower threshold value Vth- again at time point T12. Therefore, the count value Nc is further incremented, the first gain G1 is decreased, and the second gain G2 is increased. Accordingly, the second analog signal Sa2 is continuously converted into a digital value of an appropriate magnitude without saturation. After time point T12, each time the second analog signal Sa2 reaches the lower threshold value Vth-, the count value Nc is incremented, and accordingly, the first gain G1 is decreased and the second gain G2 is increased.

[0081] Thereafter, when the second analog signal Sa2 reaches the midpoint potential Vcom at time point T2, the count value Nc is decremented, and accordingly, the first gain G1 is increased and the second gain G2 is decreased. Thereafter, when the second analog signal Sa2 reaches the upper threshold value Vth+ at time point T3, again, the count value Nc is incremented, and accordingly, the first gain G1 is decreased and the second gain G2 is increased.

[0082] In this way, since the first gain G1 and the second gain G2 are controlled, as shown in FIG. 6A, even after time point T1, the first analog signal Sa1 is reproduced substantially faithfully in the output signal So. As described above, according to this embodiment, it is possible to secure a sufficient dynamic range with good linearity and also secure a sufficient SN ratio at the time of a small amplitude of the input signal (the first analog signal Sa1).

[0083] <Another example of the AD conversion circuit> FIG. 7 shows an AD conversion circuit 3x which is another example of the AD conversion circuit in the microphone signal module of the present embodiment. The AD conversion circuit 3x has a second feedback circuit FBx in addition to the AD conversion circuit 3 of FIG. 5A. The second feedback circuit FBx is mainly added to correct the capacitance variation of a transducer such as the microphone 11 connected to the input terminal of the buffer circuit 2 (see FIGS. 3A and 3B). The AD conversion circuit 3x is suitable for combination with the forward buffer circuit 2 illustrated in FIGS. 3A and 3B.

[0084] When the buffer circuit 2 is of the non-inverting type, unlike the inverting type, the second analog signal Sa2 having the same polarity as that of the first analog signal Sa1 (see FIG. 3A) with respect to the reference potential Vref (see FIG. 3A) is output from the buffer circuit 2 to the AD conversion circuit 3x. Therefore, the DA converter 34 in the AD conversion circuit 3x in FIG. 7 outputs a negative reference voltage −Vr to the subtractor 31 if the output of the quantizer 33 is “positive”, and outputs a positive reference voltage (+Vr) to the subtractor 31 if the output of the quantizer 33 is “negative”. Therefore, in the subtractor 31, the absolute value Vr is substantially added when the output of the quantizer 33 is “positive”, and the absolute value Vr is subtracted when the output of the quantizer 33 is “negative”. By the DA converter 34 operating in this way, an appropriate delta-sigma modulation operation for the second analog signal Sa2 from the non-inverting buffer circuit 2 is realized. 7, the DA converter 34 may operate in the same manner as in the example of FIG. 5A, and in that case, the subtractor 31 may have a function as an adder for the output from the DA converter 34.

[0085] On the other hand, the second feedback circuit FBx is mainly composed of a DA converter 34x that operates in the same manner as the DA converter 34 in Fig. 5A. That is, if the output of the quantizer 33 is "positive", the DA converter 34x outputs a positive reference voltage +Vrx to the subtractor 31, and if the output of the quantizer 33 is "negative", the DA converter 34x outputs a negative reference voltage -Vrx to the subtractor 31. The positive or negative reference voltage (+Vrx or -Vrx) output by the DA converter 34x is subtracted from the second analog signal Sa2 by the subtractor 31 together with the reference voltage (+Vr or -Vr) output from the DA converter 34.

[0086] The second feedback circuit FBx is configured to be able to adjust the amount of feedback, similar to the feedback circuit FB. Therefore, the second feedback circuit FBx may be configured by a plurality of feedback circuits, each including a switch and a DA converter, similar to the feedback circuit FB in FIG. 5B. The amount of feedback of the second feedback circuit FBx can be adjusted by opening and closing the switch. The amount of feedback of the second feedback circuit FBx is set according to the ratio between the capacitance of a transducer such as the microphone 11 connected to the buffer circuit 2 (see FIGS. 3A and 3B) and the input capacitance of the buffer circuit 2. The "input capacitance of the buffer circuit 2" is the capacitance of a capacitive element (such as the capacitor 27 in FIGS. 3A and 3B) other than a transducer such as the microphone 11, which is connected to the input terminal of the buffer circuit 2.

[0087] As described above, the amount of change in the first gain G1 caused by closing the switch 29 in the buffer circuit 2 of Figures 3A and 3B is determined by the ratio between C27 and C11 according to the above (Equation 4). C11 is the capacitance of a transducer such as the microphone 11 connected to the buffer circuit 2. C27 is the capacitance of the capacitor 27 in Figures 3A and 3B, and is the input capacitance of the buffer circuit 2. Therefore, in order to convert the second analog signal Sa2 into a digital signal with high accuracy, it is necessary to correct the variation in the ratio between the capacitance of the transducer connected to the buffer circuit 2 and the input capacitance of the buffer circuit 2.

[0088] 7, as described above, the second feedback circuit FBx has a feedback amount that is set according to the ratio between the capacitance of the transducer connected to the buffer circuit 2 and the input capacitance of the buffer circuit 2. Therefore, the second feedback circuit FBx can correct the variation in the first gain G1. Therefore, it is considered that the input analog signal can be accurately converted into a digital signal.

[0089] For example, when the second feedback circuit FBx includes a plurality of sets of switches and DA converters such as the switch 35 and DA converters 341 to 34n of the feedback circuit FB in FIG. 5B, the feedback amount of the second feedback circuit FBx can be adjusted by controlling the opening and closing of the switches. That is, the variation of the first gain G1 can be corrected. For example, the feedback amount of the second feedback circuit FBx is determined by measuring the capacitance of the transducer connected to the buffer circuit 2 and the input impedance of the buffer circuit 2 using a known analog signal. Then, for example, the opening and closing of a switch that functions like the switch 35 in FIG. 5B for the DA converter 34x of the second feedback circuit FBx is controlled so that the determined feedback amount is realized. Note that the feedback amount of the second feedback circuit FBx may be adjusted by adjusting the reference voltage Vrx by a means other than adjusting the capacitance in the second feedback circuit FBx.

[0090] The second gain G2 of the AD conversion circuit 3x also depends on the feedback amount of the second feedback circuit FBx. Therefore, in the example of Fig. 7, the first gain G1 and the second gain G2 do not have to be mutual inverses in decibel representation. For example, the first gain G1 and the second gain G2 may differ from each other in a ratio substantially the same as the ratio between the capacitance of the transducer connected to the buffer circuit 2 and the input capacitance of the buffer circuit 2 in magnification representation.

[0091] <Comparison with configurations other than the embodiment> 1 to 7, in the microphone signal module of this embodiment, the second gain G2 of the AD conversion circuit 3 is controlled to maintain linearity by compensating for the increase or decrease in the first gain G1 of the buffer circuit 2 due to control. For the configuration of this embodiment, it is also possible to maintain linearity by performing processing such as expansion / compression on the digital signal after AD conversion using a DSP (digital signal processor) or the like.

[0092] However, in signal processing in the digital domain after AD conversion using a DSP or the like, the gain is switched at the zero crossing of the input analog signal in order to avoid noise due to DC offset or to secure signal processing time in the DSP. Therefore, as in the output signal Voa of the P1 section shown in FIG. 9, the first wave immediately after the amplitude of the input signal increases may be clipped (missing). Note that FIG. 9 shows the waveforms of each signal in the conventional microphone amplifier 900 of FIG. 8A when the gain of the preamplifier 901 is controlled and the increase or decrease in the gain of the preamplifier 901 due to the control is compensated for by digital processing of the output signal of the AD converter 910. In FIG. 9, the signals Vi, Via, and Voa are, as in FIG. 8B, an observation example of the input signal of the preamplifier 901, the input signal of the AD converter 910, and the output signal of the AD converter 910 (analog signal after passing through an appropriate low-pass filter) of FIG. 8A, respectively. In FIG. 9, a DC offset Vof is also generated in the output signal Voa after the gain of the preamplifier is switched.

[0093] Further, in FIG. 10, similar to FIG. 9, another observation example of the input signal Vi and the output signal Voa when digital processing is performed in the microphone amplifier 900 of FIG. 8A to compensate for the increase or decrease in the gain of the preamplifier 901 is shown. In the example of FIG. 10, the first wave of the output signal Voa is clipped as shown in part P2. In the time domain after part P2, the output signal Voa is clipped as shown in part P3 due to the input voltage range of the AD converter 910 being exceeded by the DC offset. Furthermore, a delay td occurs between the input signal Vi and the output signal Voa. The defects shown in FIG. 9 and FIG. 10 can be avoided by providing a cancellation circuit such as a DC offset, but adding such a circuit will increase the size of the microphone amplifier 900 of FIG. 8A.

[0094] On the other hand, in this embodiment, the increase or decrease in the first gain G1 of the buffer circuit 2 due to the control is compensated for in the analog domain by the control of the second gain G2 of the AD conversion circuit 3. Since both the first gain G1 and the second gain G2 are controlled in the analog domain, it is possible to control the first gain G1 and the second gain G2 almost in real time or at a very high frequency of several MHz for the audio signal. Therefore, signal delay is unlikely to occur, and therefore waveform distortion such as clipping due to signal delay is unlikely to occur. Furthermore, since a DSP is not used, the circuit scale can be reduced and the current consumption during operation can be saved. While having these advantages, it may be possible to obtain performance equal to or better than that when a DSP is used.

[0095] <Comparison with other buffer circuit configurations> FIG. 11A shows a buffer circuit 92 having a different configuration from the buffer circuit 2 illustrated in FIG. 2B and FIG. 3B as a comparative example. FIG. 11B shows an example of a first analog signal Sa1 and a second analog signal Sa2 when the buffer circuit 92 is used in the microphone signal module of the embodiment instead of the buffer circuit 2 of FIG. 2B. The buffer circuit 92 includes an operational amplifier 921, capacitors 922 and 923, a plurality of switches 924, and a plurality of switches 925. The operational amplifier 921, the capacitors 922 and 923 (capacitors 9231 to 923n), and the switch 925 function in the same manner as the operational amplifier 21, the capacitors 22 and 23, and the switch 25 of the buffer circuit 2 of FIG. 2B, respectively. Meanwhile, each switch 924 connects or disconnects any one of the capacitors 9231 to 923n and the non-inverting input terminal of the operational amplifier 921 to which the reference potential Vref is applied. In the buffer circuit 92 as well, the gain of the buffer circuit 92 can be controlled by switching between opening and closing the respective switches 925 .

[0096] In the buffer circuit 92, among the capacitors 9231 to 923n, the capacitor separated from the inverting input terminal of the operational amplifier 921 by the switch 925 is charged by closing the switch 924. This suppresses abrupt fluctuations in the output signal of the buffer circuit 92 when the gain is switched, so that so-called pop noise can be reduced. However, since the amount of charge stored between the output terminal and the inverting input terminal of the operational amplifier 921 changes when the gain is switched, a DC offset Vof occurs in the second analog signal Sa2 as shown in FIG. 11B. Note that the noticeable attenuation of the amplitude after the occurrence of the DC offset in the second analog signal Sa2 in FIG. 11B is due to the second analog signal Sa2 having the DC offset being mistaken for a large amplitude signal by the control circuit 4 (see FIG. 1). Such a DC offset can be prevented, for example, by switching the gain at the zero crossing of the second analog signal Sa2. However, if there is such a restriction on the timing of the gain switching, the signal clipping as described above may occur due to a delay in switching.

[0097] In contrast, in the buffer circuit 2 shown in FIG. 2B or FIG. 3B, the switching timing of the first gain G1 is not restricted by the DC offset suppression, so that it is possible to suppress switching delays and the accompanying signal clipping. [Explanation of symbols]

[0098] 1 Microphone signal conversion module (microphone signal module) 10 Microphone Module 11 Microphone 2. Buffer circuit 21 Operational Amplifier 22 Capacitor 23 Variable Capacitor 24, 25 Switch 26 Non-inverting buffer 27 Variable Capacitor 28, 29 Switch 3. 3x AD conversion circuit 34, 34x, 340, 341~34n DA converters 4 Control circuit 40 Comparison circuit 44 Counter 45 Detector (comparator) 47 Pulse Generator Circuit 471 Timer 472 Pulse Generator FB Feedback circuit FBx Secondary Feedback Circuit G1 First gain G2 2nd Gain Sa1 First analog signal Sa2 Second analog signal Pr Pulse Vcom midpoint potential Vth+ Upper threshold Vth- Lower threshold

Claims

1. a buffer circuit that performs level conversion with a first gain on a first analog signal input from a transducer and outputs a second analog signal obtained by the level conversion; an analog-to-digital conversion circuit that converts the level of the second analog signal into a digital value with a second gain; a control circuit for controlling the first gain and the second gain; A microphone signal conversion module comprising: The second analog signal is input to the control circuit; the control circuit is configured to control the magnitudes of the first gain and the second gain in opposite directions based on a level of the second analog signal; The control circuit includes: a comparison circuit for comparing the level of the second analog signal with a predetermined upper threshold and a predetermined lower threshold; a detector for detecting an inversion of a magnitude relationship between a level of the second analog signal and a midpoint potential of a maximum amplitude of the second analog signal; a counter that is incremented when the comparator detects that the level of the second analog signal is outside the range between the lower threshold and the upper threshold, and that is decremented when the detector detects the inversion; Including, The control circuit is configured to control the first gain and the second gain according to a count value of the counter.

2. The buffer circuit includes: an operational amplifier having an inverting input terminal for receiving the first analog signal; a plurality of capacitors disposed between the output terminal and the inverting input terminal of the operational amplifier; a switch that connects or disconnects a portion of the plurality of capacitors to the inverting input terminal; Including, The microphone signal conversion module of claim 1 , wherein the control circuit is configured to control the first gain by opening and closing the switch.

3. The microphone signal conversion module of claim 2 , wherein the portion of the plurality of capacitors is configured to discharge when isolated from the inverting input terminal by the switch.

4. The buffer circuit includes: a non-inverting buffer having an input terminal for receiving the first analog signal sent from a capacitive transducer; A plurality of capacitors each disposed between the input terminal and a predetermined constant potential; a switch for connecting or disconnecting each of the plurality of capacitors to or from the input terminal; Including, The microphone signal conversion module of claim 1 , wherein the control circuit is configured to control the first gain by opening and closing the switch.

5. The microphone signal conversion module of claim 4 , wherein the plurality of capacitors are configured to discharge when isolated from the input terminal by the switch.

6. the control circuit further includes a pulse generating circuit that outputs a pulse when a predetermined time has elapsed since the detector detected the inversion; 2. The microphone signal conversion module of claim 1, wherein the counter is configured to decrement the count value each time the pulse is output.

7. a buffer circuit that performs level conversion with a first gain on a first analog signal input from a transducer and outputs a second analog signal obtained by the level conversion; an analog-to-digital conversion circuit that converts the level of the second analog signal into a digital value with a second gain; a control circuit for controlling the first gain and the second gain; A microphone signal conversion module comprising: The second analog signal is input to the control circuit; the control circuit is configured to control the magnitudes of the first gain and the second gain in opposite directions based on a level of the second analog signal; the analog-to-digital conversion circuit is a delta-sigma type analog-to-digital conversion circuit having a feedback circuit formed by a digital-to-analog converter; the control circuit is configured to control the second gain by increasing or decreasing a feedback amount of the feedback circuit; The microphone signal conversion module, wherein the analog-to-digital conversion circuit further includes a second feedback circuit having a feedback amount set according to a ratio between a capacitance of a transducer connected to the buffer circuit and an input capacitance of the buffer circuit.

8. A microphone signal conversion module according to any one of claims 1 to 7; a MEMS transducer that generates the first analog signal; 2. A microphone module comprising: