Multilevel inverter

Abstract

The present invention reduces switching loss. A control unit (60) of this multilevel inverter (100) has the function of performing an initial charge control for initially charging a first capacitor (C17), a second capacitor (C27) and a third capacitor (C37) at startup. During the initial charge control, the control unit (60) performs a first control for turning on only a third switching element (Q3) and a fourth switching element (Q4) after turning on only the fourth switching element (Q4), or a second control for turning on only the third switching element (Q3) and the fourth switching element (Q4), and thereafter, alternatingly repeats a third control for turning on only the second switching element (Q2) and the third switching element (Q3), and a fourth control for turning on only the third switching element (Q3) and the fourth switching element (Q4).

Description

Multilevel Inverter

[0001] The present disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter with a bootstrap circuit.

[0002] Japanese Patent Application Laid-Open No. 2006-129999 (Patent Document 1) discloses a switching element drive circuit for a three-level neutral point clamped inverter, which includes first, second, third, and fourth switching elements connected in series between the positive and negative terminals of a DC power supply. The switching element drive circuit includes an element drive power supply with the negative terminal as a potential reference, a fourth element drive unit (fourth gate driver), a third diode, a third element drive unit (third gate driver), a third capacitor, a second diode, a second element drive unit (second gate driver), a second capacitor, a first diode, a first element drive unit (first gate driver), and a first capacitor. The fourth element drive unit is connected between the positive and negative terminals of the element drive power supply and drives the fourth switching element. The third diode has an anode connected to the positive terminal of the element drive power supply. The third element drive unit is connected between the cathode of the third diode and a common connection point of the third and fourth switching elements and drives the third switching element. The third capacitor is connected in parallel to the third element driving unit. The second diode has an anode connected to the cathode of the third diode. The second element driving unit is connected between the cathode of the second diode and a common connection point of the second and third switching elements, and drives the second switching element. The second capacitor is connected in parallel to the second element driving unit. The first diode has an anode connected to the cathode of the second diode. The first element driving unit is connected between the cathode of the first diode and a common connection point of the first and second switching elements, and drives the first switching element. The first capacitor is connected in parallel to the first element driving unit.

[0003] Japanese Patent Application Laid-Open No. 2018-133876

[0004] In the multilevel inverter having a configuration including a three-level neutral point clamped inverter and a switching element drive circuit as disclosed in Patent Document 1, the switching loss in each of the first switching element, the second switching element, and the third switching element may become large.

[0005] An object of the present disclosure is to provide a multilevel inverter capable of reducing switching loss.

[0006] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, an inverter circuit, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The inverter circuit is connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the inverter circuit. The inverter circuit includes a switching circuit, a first clamp diode, and a second clamp diode. The switching circuit includes a first switching element, a second switching element, a third switching element, and a fourth switching element. In the switching circuit, the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element. The first clamp diode is connected between a first connection point between the first switching element and the second switching element and the intermediate potential point. The second clamp diode is connected between a second connection point between the third switching element and the fourth switching element and the intermediate potential point. The control device includes a first gate driver, a second gate driver, a third gate driver, a fourth gate driver, a first bootstrap circuit, a second bootstrap circuit, a third bootstrap circuit, a power supply unit, and a control unit. The first gate driver drives the first switching element. The second gate driver drives the second switching element. The third gate driver drives the third switching element. The fourth gate driver drives the fourth switching element. The first bootstrap circuit includes a first capacitor connected in parallel to the first gate driver and a first diode connected in series to the first capacitor. The second bootstrap circuit includes a second capacitor connected in parallel to the second gate driver and a second diode connected in series to the second capacitor. The third bootstrap circuit includes a third capacitor connected in parallel to the third gate driver and a third diode connected in series to the third capacitor.The power supply unit is connected in parallel to the fourth gate driver. The control unit controls the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver. The power supply unit is connected to the third capacitor via the third diode, to the second capacitor via the third diode and the second diode, and to the first capacitor via the third diode, the second diode, and the first diode. The control unit has a function of performing initial charge control to initially charge the first capacitor, the second capacitor, and the third capacitor at startup. In the initial charge control, the control unit performs a first control in which only the fourth switching element is turned on and then only the third switching element and the fourth switching element are turned on, or a second control in which only the third switching element and the fourth switching element are turned on, and then alternately repeats a third control in which only the second switching element and the third switching element are turned on, and a fourth control in which only the third switching element and the fourth switching element are turned on.

[0007] The multilevel inverter of the present disclosure has the effect of making it possible to reduce switching loss.

[0008] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to an embodiment. FIG. 2 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the embodiment is in a first switching state. FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the embodiment is in a first switching state. FIG. 4 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the embodiment is in a second switching state. FIG. 5 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the embodiment is in a second switching state. FIG. 6 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter according to the embodiment is in a third switching state. FIG. 7 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter according to the embodiment is in a third switching state. FIG. 8 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter according to the embodiment. FIG. 9 is an explanatory diagram of a group of voltage vectors related to the multilevel inverter according to the embodiment. FIG. 10 is a more detailed explanatory diagram of a group of voltage vectors related to the multilevel inverter according to the embodiment. FIG. 11 is a vector diagram for explaining the operation of a control unit in the multilevel inverter according to the embodiment. FIG. 12 is a diagram illustrating a time chart of the switching states of each phase of the multilevel inverter of the embodiment. FIG. 13 is a diagram illustrating a time chart of the on / off states of the first to fourth switching elements of the multilevel inverter of the embodiment. FIG. 14 is an explanatory diagram of a charging path of the third capacitor when the control unit turns on only the fourth switching element during initial charging control in the multilevel inverter of the embodiment. FIG. 15 is an explanatory diagram of a charging path of the second capacitor and a charging path of the third capacitor when the control unit turns on only the third and fourth switching elements during initial charging control in the multilevel inverter of the embodiment. FIG. 16 is an explanatory diagram of a charging path of the first capacitor and a charging path of the second capacitor when the control unit turns on only the second and third switching elements during initial charging control in the multilevel inverter of the embodiment.FIG. 17 is an operational waveform diagram when the control unit performs an initial charging operation in the multilevel inverter of the embodiment.

[0009] Embodiment A multilevel inverter 100 according to an embodiment will be described below with reference to FIGS.

[0010] (1) Overall Configuration of Multilevel Inverter FIG. 1 is a circuit diagram of a system including a multilevel inverter 100 according to an embodiment. For example, as shown in FIG. 1 , the multilevel inverter 100 includes a DC power supply unit 3, a plurality of (three in the example of FIG. 1 ) inverter circuits 1, and a control device 6. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0011] The multilevel inverter 100 is a diode-clamped three-level, three-phase inverter. In the multilevel inverter 100, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the multiple (three in the example of FIG. 1 ) output terminals 41.

[0012] The AC load RA1 is, for example, a three-phase servo motor. In the multilevel inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0013] Each of the inverter circuits 1 includes a switching circuit 10, a first clamp diode D5, and a second clamp diode D6. In the multilevel inverter 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0014] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0015] Each switching circuit 10 further includes four diodes D1 to D4. Diode D1 is connected in anti-parallel to the first switching element Q1. Diode D2 is connected in anti-parallel to the second switching element Q2. Diode D3 is connected in anti-parallel to the third switching element Q3. Diode D4 is connected in anti-parallel to the fourth switching element Q4. A first clamp diode D5 is connected between a first connection point 11 between the first switching element Q1 and the second switching element Q2 and an intermediate potential point M1. A second clamp diode D6 is connected between a second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1.

[0016] The control device 6 has a plurality of (three in the example of FIG. 1 ) first gate drivers 61, a plurality of (three in the example of FIG. 1 ) second gate drivers 62, a plurality of (three in the example of FIG. 1 ) third gate drivers 63, and a plurality of (three in the example of FIG. 1 ) fourth gate drivers 64. The control device 6 also has a plurality of (three in the example of FIG. 1 ) first bootstrap circuits 71, a plurality of (three in the example of FIG. 1 ) second bootstrap circuits 72, a plurality of (three in the example of FIG. 1 ) third bootstrap circuits 73, a power supply unit 9, and a control unit 60.

[0017] The plurality of first gate drivers 61 drive the first switching element Q1 of each of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching element Q2 of each of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching element Q3 of each of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching element Q4 of each of the plurality of inverter circuits 1.

[0018] The multiple first bootstrap circuits 71 correspond one-to-one to the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 includes a first capacitor C17 connected in parallel to the corresponding first gate driver 61 and a first diode D17 connected in series to the first capacitor C17. The multiple second bootstrap circuits 72 correspond one-to-one to the multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 includes a second capacitor C27 connected in parallel to the corresponding second gate driver 62 and a second diode D27 connected in series to the second capacitor C27. The multiple third bootstrap circuits 73 correspond one-to-one to the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a third capacitor C37 connected in parallel to the corresponding third gate driver 63 and a third diode D37 connected in series to the third capacitor C37.

[0019] The power supply unit 9 is connected in parallel to the fourth gate driver 64. The power supply unit 9 is also connected to the third capacitor C37 via the third diode D37. The power supply unit 9 is also connected to the second capacitor C27 via the third diode D37 and the second diode D27. The power supply unit 9 is also connected to the first capacitor C17 via the third diode D37, the second diode D27, and the first diode D17.

[0020] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0021] (2) Details of the Multilevel Inverter The DC power supply unit 3 includes a fourth capacitor C1 and a fifth capacitor C2. In the DC power supply unit 3, the fourth capacitor C1 and the fifth capacitor C2 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the fourth capacitor C1 is connected to the first DC terminal 31, a second end of the fourth capacitor C1 is connected to a first end of the fifth capacitor C2, and a second end of the fifth capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the fourth capacitor C1 and the fifth capacitor C2 is an intermediate potential point M1. For example, a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the fifth capacitor C2 is the same as the capacitance of the fourth capacitor C1. The phrase "the capacitance of the fifth capacitor C2 is the same as the capacitance of the fourth capacitor C1" does not necessarily mean that the capacitance of the fifth capacitor C2 exactly matches the capacitance of the fourth capacitor C1, but may mean that the capacitance of the fifth capacitor C2 is within a range of 95% to 105% of the capacitance of the fourth capacitor C1.

[0022] Hereinafter, for convenience of explanation, with regard to the multiple switching circuits 10, the switching circuit 10 included in inverter circuit 1U may be referred to as switching circuit 10U, the switching circuit 10 included in inverter circuit 1V may be referred to as switching circuit 10V, and the switching circuit 10 included in inverter circuit 1W may be referred to as switching circuit 10W. Furthermore, of the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W may be referred to as output terminal 41W.

[0023] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, respectively, a gate terminal, a collector terminal, and an emitter terminal.

[0024] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0025] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply 3.

[0026] In the inverter circuit 1U, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W. The third connection point 13 of the inverter circuit 1U is connected to, for example, the U-phase of the AC load RA1 via the output terminal 41U. The third connection point 13 of the inverter circuit 1V is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41V. The third connection point 13 of the inverter circuit 1W is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41W.

[0027] In each switching circuit 10, the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each switching circuit 10, the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each switching circuit 10, the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each switching circuit 10, the anode of the diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0028] In each switching circuit 10, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each switching circuit 10, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each switching circuit 10, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each switching circuit 10, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0029] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3. In this embodiment, the intermediate potential point M1 is connected to ground, and therefore the potential of the intermediate potential point M1 is 0 V. In this case, if the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is −Vdc / 2.

[0030] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1, and the anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0031] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (see FIG. 2 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0032] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 2 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0033] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 2 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0034] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 2 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0035] Each of the multiple first bootstrap circuits 71 supplies a voltage to a corresponding one of the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 includes a first resistor R17 in addition to a first capacitor C17 and a first diode D17.

[0036] In each first bootstrap circuit 71, the anode of the first diode D17 is connected to the positive terminal of the power supply unit 9 via the second diode D27 and the third diode D37. In each first bootstrap circuit 71, the cathode of the first diode D17 is connected to the first end of the first capacitor C17 via the first resistor R17. The first end of the first capacitor C17 is connected to the high-potential power supply terminal 61H (see FIG. 3 ) of the first gate driver 61. The second end of the first capacitor C17 is connected to the low-potential power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage (a voltage greater than the threshold voltage of the first switching element Q1) required to turn on the first switching element Q1 in the first gate driver 61. Each of the multiple first bootstrap circuits 71 further includes a first Zener diode Z17 connected in parallel to the first capacitor C17. In each of the multiple first bootstrap circuits 71, the cathode of the first Zener diode Z17 is connected to a first end of the first capacitor C17, and the anode of the first Zener diode Z17 is connected to a second end of the first capacitor C17.

[0037] Each of the second bootstrap circuits 72 supplies a voltage to a corresponding one of the second gate drivers 62. Each of the second bootstrap circuits 72 includes a second resistor R27 in addition to a second capacitor C27 and a second diode D27. In each second bootstrap circuit 72, the anode of the second diode D27 is connected to the positive terminal of the power supply unit 9 via a third diode D37. In each second bootstrap circuit 72, the cathode of the second diode D27 is connected to a first end of the second capacitor C27 via the second resistor R27. The first end of the second capacitor C27 is connected to the high-potential power supply terminal 62H (see FIG. 3 ) of the second gate driver 62. The second end of the second capacitor C27 is connected to the low-potential power supply terminal 62L (see FIG. 3 ) of the second gate driver 62. The second bootstrap circuit 72 supplies a voltage (a voltage greater than the threshold voltage of the second switching element Q2) required to turn on the second gate driver 62 in the second gate driver 62. Each of the second bootstrap circuits 72 further includes a second Zener diode Z27 connected in parallel to the second capacitor C27. In each of the second bootstrap circuits 72, the cathode of the second Zener diode Z27 is connected to a first end of the second capacitor C27, and the anode of the second Zener diode Z27 is connected to a second end of the second capacitor C27.

[0038] Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding one of the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a third resistor R37 in addition to a third capacitor C37 and a third diode D37. In each third bootstrap circuit 73, the anode of the third diode D37 is connected to the positive terminal of the power supply unit 9. In each third bootstrap circuit 73, the cathode of the third diode D37 is connected to a first end of a third capacitor C37 via the third resistor R37. The first end of the third capacitor C37 is connected to a high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63. The second end of the third capacitor C37 is connected to a low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63. The third bootstrap circuit 73 supplies a voltage (a voltage greater than the threshold voltage of the third switching element Q3) required to turn on the third gate driver 63 in the third gate driver 63. Each of the multiple third bootstrap circuits 73 further includes a third Zener diode Z37 connected in parallel to the third capacitor C37. In each of the multiple third bootstrap circuits 73, the cathode of the third Zener diode Z37 is connected to a first end of the third capacitor C37, and the anode of the third Zener diode Z37 is connected to a second end of the third capacitor C37.

[0039] The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. The positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 64H (see FIG. 3) of each of the plurality of fourth gate drivers 64. The positive terminal of the power supply unit 9 is also connected to a first end of a third capacitor C37 via a third diode D37 and a third resistor R37. The positive terminal of the power supply unit 9 is also connected to a first end of a second capacitor C27 via a third diode D37, a second diode D27, and a second resistor R27. The positive terminal of the power supply unit 9 is also connected to a first end of a first capacitor C17 via a third diode D37, a second diode D27, a first diode D17, and a first resistor R17. The negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 64L (see FIG. 3) of each of the plurality of fourth gate drivers 64. The negative terminal of the power supply unit 9 is also connected to the negative pole N1 of the DC power supply unit 3.

[0040] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0041] The control unit 60 outputs a plurality (three) of first control signals S1 (see FIG. 2) for controlling a plurality (three) of first switching elements Q1. The control unit 60 also outputs a plurality (three) of second control signals S2 (see FIG. 2) for controlling a plurality (three) of second switching elements Q2. The control unit 60 also outputs a plurality (three) of third control signals S3 (see FIG. 2) for controlling a plurality of third switching elements Q3. The control unit 60 also outputs a plurality (three) of fourth control signals S4 for controlling a plurality (three) of fourth switching elements Q4. Note that FIG. 2 illustrates only one of the three inverter circuits 1 (see FIG. 1), and the remaining two inverter circuits 1 are not shown. 2 omits the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the power supply unit 9 shown in FIG. 1 . Also, in FIG. 3 , only one inverter circuit 1 of the three inverter circuits 1 (see FIG. 1 ) is shown, and the illustration of the remaining two inverter circuits 1 is omitted. Also, in FIG. 3 , the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, and the two third bootstrap circuits 73 shown in FIG. 1 is omitted.

[0042] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0043] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0044] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0045] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0046] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3 and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.

[0047] The first potential level is, for example, 0 V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.

[0048] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0049] (3) Operation of the Multilevel Inverter The control unit 60 performs a charge control operation to charge the multiple first capacitors C17, the multiple second capacitors C27, and the multiple third capacitors C37 as a startup operation of the multilevel inverter 100, and an inverter control operation to cause an output current to flow to each of the multiple output terminals 41 as a steady-state operation of the multilevel inverter 100.

[0050] In the following, the operation of the multilevel inverter 100 when the control unit 60 performs the inverter control operation will be described first, and then the operation of the multilevel inverter 100 when the control unit 60 performs the charge control operation will be described.

[0051] (3.1) Operation of the Multilevel Inverter When the Control Unit Performs Inverter Control Operation In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0052] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the third connection point 13 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0053] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state and both the second switching element Q2 and the third switching element Q3 are in the on state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0054] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0055] 2 is an explanatory diagram of a current path when the switching circuit 10 is in a first switching state in the multilevel inverter 100 of the embodiment. When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in Fig. 2, a current I1 flows through a path from the positive electrode P1 of the DC power supply unit 3 to the first switching element Q1, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see Fig. 1) becomes approximately Vdc / 2.

[0056] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from the first capacitor C17 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, the charge in the first capacitor C17 of the first bootstrap circuit 71 is discharged via a first discharge path Ru1 shown in FIG. 3 . The first discharge path Ru1 is a path from the first capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61 to the low-potential power supply terminal 61L of the first gate driver 61 to the first capacitor C17. As the charge in the first capacitor C17 is discharged, the voltage Vo1 across the first capacitor C17 in the first bootstrap circuit 71 decreases over time.

[0057] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the second capacitor C27 of the second bootstrap circuit 72 supplies to the second gate driver 62 a voltage required for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge in the second capacitor C27 is discharged via the second discharge path Ru2 shown in FIG. 3 . The second discharge path Ru2 is a path from the second capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62, to the low-potential power supply terminal 62L of the second gate driver 62, and back to the second capacitor C27. As the charge in the first capacitor C17 is discharged, the voltage Vo2 across the second capacitor C27 in the second bootstrap circuit 72 decreases over time.

[0058] 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit 10 in the multilevel inverter 100 according to the embodiment is in the first switching state. When the switching circuit 10 of the inverter circuit 1 is in the first switching state, the first capacitor C17 is charged by the second capacitor C27 if a first condition is met. As shown in FIG. 3 , if the voltage across the first diode D17 is Vd1, the voltage across the first resistor R17 is VR1, and the voltage across the second switching element Q2 is Vf2, the first condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). The charge path Ru21 along which the first capacitor C17 is charged by the second capacitor C27 is the path from the second capacitor C27 to the second resistor R27, the first diode D17, the first resistor R17, the first capacitor C17, the first node 11, the second switching element Q2, and the second capacitor C27.

[0059] 4 is an explanatory diagram of a current path when the switching circuit 10 is in the second switching state in the multilevel inverter 100 according to the embodiment. When the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is positive, as shown in FIG. 4, a current I1 flows through a path (indicated by a thick solid arrow) from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, a current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5 of the inverter circuit 1U, the second switching element Q2 of the switching circuit 10U, the third connection point 13, and the output terminal 41.

[0060] 4, when the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is negative, a current I1 flows through a path (indicated by a thick dashed arrow) of the output terminal 41-the third node 13-the third switching element Q3-the second node 12-the second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, in the inverter circuit 1U, a current I1 flows through a path of the output terminal 41-the third node 13-the third switching element Q3-the second node 12-the second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes 0.

[0061] FIG. 5 is an explanatory diagram of the discharge path and charge path when the switching circuit 10 in the multilevel inverter 100 according to the embodiment is in the second switching state. When the switching circuit 10 in the inverter circuit 1 is in the second switching state, the second capacitor C27 in the second bootstrap circuit 72 supplies the second gate driver 62 with a voltage required for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge in the second capacitor C27 is discharged via the second discharge path Ru2 shown in FIG. 5 . The second discharge path Ru2 is a path from the second capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62, to the low-potential power supply terminal 62L of the second gate driver 62, and then to the second capacitor C27. As the charge in the second capacitor C27 is discharged, the voltage Vo2 across the second capacitor C27 in the second bootstrap circuit 72 decreases over time.

[0062] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for the third gate driver 63 to turn on the third switching element Q3 is supplied from the third capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, the charge in the third capacitor C37 is discharged via the third discharge path Ru3 shown in FIG. 5 . The third discharge path Ru3 is a path from the third capacitor C37 to the high-potential power supply terminal 63H of the third gate driver 63, to the low-potential power supply terminal 63L of the third gate driver 63, and back to the third capacitor C37. As the charge in the third capacitor C37 is discharged, the voltage Vo3 across the third capacitor C37 in the third bootstrap circuit 73 decreases over time.

[0063] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the second capacitor C27 is charged by the third capacitor C37 when the second condition is met, and the first capacitor C17 is charged by the second capacitor C27 when the third condition is met. As shown in Fig. 5, if the voltages across the first diode D17 and the second diode D27 are Vd1 and Vd2, the voltages across the first resistor R17 and the second resistor R27 are VR1 and VR2, and the voltages across the second switching element Q2 and the third switching element Q3 are Vf2 and Vf3, respectively, the second condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The third condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). A charging path Ru32 through which the second capacitor C27 is charged by the third capacitor C37 is a path from the third capacitor C37 to the third resistor R37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, and the third capacitor C37. A charging path Ru21 through which the first capacitor C17 is charged by the second capacitor C27 is a path from the second capacitor C27 to the second resistor R27, the first diode D17, the first resistor R17, the first capacitor C17, the first connection point 11, the second switching element Q2, and the second capacitor C27.

[0064] 6 is an explanatory diagram of a current path when the switching circuit 10 is in the third switching state in the multilevel inverter 100 of the embodiment. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, as shown in FIG. 6, a current I1 flows through a path from the output terminal 41 to the third connection point 13, the third switching element Q3, the fourth switching element Q4, and the negative electrode N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 becomes −Vdc / 2.

[0065] 7 is an explanatory diagram of the discharge path and charge path when the switching circuit 10 in the multilevel inverter 100 according to the embodiment is in the third switching state. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C37 charges the second capacitor C27 of the second bootstrap circuit 72 (see FIG. 1). Therefore, the voltage Vo2 across the second capacitor C27 increases over time, and the second capacitor C27 is fully charged. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C37 of the third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3. Therefore, the charge in the third capacitor C37 is discharged via the discharge path Ru3 shown in FIG. 7. The discharge path Ru3 is a path from the third capacitor C37 to the high-side power supply terminal 63H of the third gate driver 63 to the low-side power supply terminal 63L of the third gate driver 63 to the third capacitor C37. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C37 is charged by the power supply unit 9 when a fourth condition is met, and the second capacitor C27 is charged by the third capacitor C37 when a fifth condition is met. As shown in FIG. 7 , if the voltage across the power supply unit 9 is Voo, the voltages across the second diode D27 and the third diode D37 are Vd2 and Vd3, respectively, the voltages across the second resistor R27 and the third resistor R37 are VR2 and VR3, respectively, and the voltages across the third switching element Q3 and the fourth switching element Q4 are Vf3 and Vf4, respectively, the fourth condition is Voo > (Voo3 + Vd3 + VR3 + Vf4). The fifth condition is Vo3>(Vo2+Vd2+VR2+Vf3). A charging path Ru93 along which the third capacitor C37 is charged by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 to the third diode D37, the third resistor R37, the third capacitor C37, the second connection point 12, the fourth switching element Q4, and the negative terminal of the power supply unit 9.The charging path Ru32 that charges the second capacitor C27 by the third capacitor C37 is a path from the third capacitor C37 to the third resistor R37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, and the third capacitor C37.

[0066] The control unit 60 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U based on a voltage command Vu (see FIG. 8) related to the output voltage of the inverter circuit 1U. The control unit 60 also generates first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V based on a voltage command Vv (see FIG. 8) related to the output voltage of the inverter circuit 1V. The control unit 60 also generates first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W based on a voltage command Vw (see FIG. 8) related to the output voltage of the inverter circuit 1W.

[0067] FIG. 8 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter 100 according to the embodiment. As shown in FIG. 8 , the voltage command Vu and the voltage command Vv are sinusoidal signals, for example, with a phase difference of 120° from each other, and their values ​​(voltage command values) change over time. The voltage command Vu, the voltage command Vv, and the voltage command Vw have the same duration per cycle. The control unit 60 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 8 that detects the state of the AC load RA1. When the AC load RA1 is a three-phase servo motor, the information output from the detection unit 8 includes, for example, at least one of information on the detection results of a plurality of current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1, and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0068] Below, we will explain the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U). The operation of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W is similar to the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0069] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.

[0070] The voltage vector control by the control unit 60 will be described in more detail below.

[0071] The control unit 60 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of potential levels at a connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 33 = 27.

[0072] 9 is an explanatory diagram of a group of voltage vectors related to the multilevel inverter 100 of the embodiment. As shown in FIG. 9 , the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. The group of voltage vectors also includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which has a magnitude of (2 / 3)½·2 Vdc and is oriented in different directions. The group of voltage vectors also includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3)½·Vdc. The group of voltage vectors includes six voltage vectors V13, V14, V15, V16, V17, and V18, each having a magnitude of (2 / 3)1 / 2·31 / 2·Vdc and pointing in different directions. In Figure 9, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. The angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is also 60 degrees. Figure 9 is a vector diagram illustrating the group of voltage vectors on an orthogonal d-q coordinate system.

[0073] A group of voltage vectors can be expressed as shown in FIG. 10 by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating the U phase, V phase, and W phase in that order.

[0074] FIG. 10 is a more detailed explanatory diagram of a group of voltage vectors related to the multilevel inverter 100 of the embodiment. As shown in FIG. 10 , three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P," the switching state of the V-phase switching circuit 10V is "P," and the switching state of the W-phase switching circuit 10W is "P." For example, a voltage vector with a "p" appended, such as V10p, includes "P" but does not include "N." This applies hereinafter. Furthermore, a voltage vector with a "n" appended, such as V10n, includes the switching state "N" but does not include the switching state "P." This applies hereinafter. Furthermore, voltage vectors with "o" appended, such as V10o, include "0" but do not include "P" or "N." When the switching state of the switching circuit 10 is "P," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0075] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0076] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0077] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0078] 11 is a vector diagram for explaining the operation of the control unit 60 in the multilevel inverter 100 of the embodiment. The control unit 60 converts the instantaneous value of the command voltage related to the output voltage of each of the multiple inverter circuits 1 into a command voltage vector V* (see FIG. 11). If the d-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vd and the q-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vq, the command voltage vector V* can be calculated using equation (1).

[0079]

[0080] The control unit 60 selects a plurality of (e.g., five) voltage vectors that are adjacent to the command voltage vector V* from the group of voltage vectors. In the example of Fig. 11, the plurality of voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0081] The angle formed between the voltage vector closest to the command voltage vector V* (hereinafter also referred to as voltage vector VV1) and the command voltage vector V* is smaller than 30 degrees.

[0082] The control unit 60 causes the composite vector of the vectors at the vertices of an equilateral triangle surrounding the command voltage vector V* to coincide with the command voltage vector V* within a predetermined control period Ts. That is, the control unit 60 causes the composite vector of the voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 11 ), the voltage vector V13[P0N], and the voltage vectors V7p[P00] and V7n[0NN] to coincide with the command voltage vector V*. The control period Ts is one period of the carrier signal. In the control period Ts, the control unit 60 changes the switching state of only one of the U, V, and W phases in two voltage vectors arranged in time series between "P" and "0" or between "0" and "N," and outputs the same voltage vector twice.

[0083] FIG. 12 is a timing chart showing the switching states of each phase of the multilevel inverter 100 according to the embodiment. FIG. 13 is a timing chart showing the on / off states of the first to fourth switching elements (Q1 to Q4) of the multilevel inverter 100 according to the embodiment. In FIG. 12, the voltage vectors are output in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. FIG. 12 illustrates a case where, with respect to a control period Ts, the allocation time of the voltage vectors V8p and V8n is T0, the allocation time of the voltage vector V13 is T1, and the allocation time of the voltage vectors V7p and V7n is T2. Regarding T0, T1, and T2, when the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector V* are Va, Vb, and Vc, and the magnitude and angle of the command voltage vector V* are V and θ, respectively, T0, T1, and T2 are determined so as to satisfy equations (2) and (3). "j" in equation (2) is an imaginary unit. In the example of FIG. 11 , for example, the voltage vector Va is the voltage vector V8p[PP0] and V8n[00N], the voltage vector Vb is the voltage vector V13[P0N], and the voltage vector Vc is the voltage vector V7p[P00] and V7n[0NN].

[0084]

[0085]

[0086] In the example of FIG. 12, the on / off states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are as shown in FIG. 13 within the control period Ts.

[0087] Even if the command voltage vector V* is the same as that in FIG. 11, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0088] (3.2) Operation of the Multilevel Inverter When the Control Unit Performs Initial Charging Control as Startup Operation The control unit 60 has a function of performing initial charging control to initially charge the plurality of first capacitors C17, the plurality of second capacitors C27, and the plurality of third capacitors C37 at the start up of the multilevel inverter 100. The operation when the control unit 60 performs initial charging control will be described below with reference to FIGS.

[0089] When the multilevel inverter 100 is started, the DC voltage source E1 is connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3, and the potential of the intermediate potential point M1 of the DC power supply unit 3 transiently rises to Vdc / 2. "Connecting the DC voltage source E1 between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3" means that the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3, i.e., the power supply is turned on. For example, after the DC voltage source E1 is connected to the multilevel inverter 100, the control unit 60 starts operation of the DC-DC converter 91 included in the power supply unit 9. For example, the control unit 60 performs a charge control operation after a time has passed since the DC voltage source E1 was connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3, during which the potential of the intermediate potential point M1 rises to Vdc / 2. The control unit 60 may be configured to monitor the potential of the intermediate potential point M1 of the DC power supply unit 3 and perform the charge control operation after the potential of the intermediate potential point M1 has risen to Vdc / 2.

[0090] In the initial charging control, the control unit 60 charges the plurality of third capacitors C37 and the plurality of second capacitors C27, and then charges the plurality of first capacitors C17. Therefore, in the initial charging control, the control unit 60 turns on only the fourth switching element Q4 in each of the plurality of switching circuits 10, and then performs a control (first control) to turn on only the third switching element Q3 and the fourth switching element Q4. Thereafter, the control unit 60 alternately repeats a control (third control) to turn on only the second switching element Q2 and the third switching element Q3 and a control (fourth control) to turn on only the third switching element Q3 and the fourth switching element Q4. "Turning on only the fourth switching element Q4" means turning off the first switching element Q1, turning off the second switching element Q2, turning off the third switching element Q3, and turning on the fourth switching element Q4. "Turning on only the third switching element Q3 and the fourth switching element Q4" means turning off the first switching element Q1, turning off the second switching element Q2, turning on the third switching element Q3, and turning on the fourth switching element Q4. Therefore, "turning on only the third switching element Q3 and the fourth switching element Q4" means controlling the inverter circuit 1 to the third switching state ("N"). "Turning on only the second switching element Q2 and the third switching element Q3" means turning off the first switching element Q1, turning on the second switching element Q2, turning on the third switching element Q3, and turning off the fourth switching element Q4. Therefore, "turning on only the second switching element Q2 and the third switching element Q3" means controlling the inverter circuit 1 to the second switching state ("0").

[0091] 14 is an explanatory diagram of a charging path of the third capacitor C37 when the control unit 60 turns on only the fourth switching element Q4 during initial charging control in the multilevel inverter 10 of this embodiment. In the first control, the control unit 60 charges the third capacitor C37 from the power supply unit 9 by turning on only the fourth switching element Q4 among the first to fourth switching elements Q1 to Q4 in each of the multiple switching circuits 10. At this time, the charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the third resistor R37, the third capacitor C37, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG.

[0092] In the first control, the control unit 60 sets the on-period time T1 (see FIG. 17 ) of the fourth switching element Q4 when turning on only the fourth switching element Q4 in each of the plurality of inverter circuits 1 to, for example, a time equal to or greater than the CR time constant determined by the capacitance of the third capacitor C37 and the resistance value of the third resistor R37 of the third bootstrap circuit 73 corresponding to the fourth switching element Q4. The on-period time T1 of the fourth switching element Q4 is, for example, 1 ms.

[0093] 15 is an explanatory diagram of the charging path of the second capacitor C27 and the charging path of the third capacitor C37 when the control unit turns on only the third switching element Q3 and the fourth switching element Q4 during initial charging control in the multilevel inverter 100 of this embodiment. In the first control, the control unit 60 turns on only the fourth switching element Q4 as described above, and then turns on only the third switching element Q3 and the fourth switching element Q4 among the first to fourth switching elements Q1 to Q4, thereby charging the third capacitor C37 and the second capacitor C27 from the power supply unit 9. At this time, the charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the third resistor R37, the third capacitor C37, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. In addition, the charging path Ru92 that charges the second capacitor C27 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. 15.

[0094] In the first control, the control unit 60 sets the time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on to, for example, a time equal to or longer than the CR time constant determined by the capacitance of the second capacitor C27 and the resistance value of the second resistor R27 of the second bootstrap circuit 72. The time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on is, for example, 1.1 ms.

[0095] 16 is an explanatory diagram of the charging path of the first capacitor C17 and the charging path of the second capacitor C27 when the control unit 60 turns on only the second switching element Q2 and the third switching element Q3 in the initial charging control in the multilevel inverter 100 of this embodiment. In the third control, the control unit 60 turns on only the second switching element Q2 and the third switching element Q3, thereby charging the first capacitor C17 from the third capacitor C37 and the second capacitor C27. As shown in FIG. 16, the charging path R31 that charges the first capacitor C17 from the third capacitor C37 is a path from the third capacitor C37 to the third resistor R37, the second diode D27, the first diode D17, the first resistor R17, the first capacitor C17, the first node 11, the second switching element Q2, the third node 13, the third switching element Q3, and the third capacitor C37. In addition, the charging path R21 that charges the first capacitor C17 from the second capacitor C27 is a path from the second capacitor C27 to the second resistor R27, the first diode D17, the first resistor R17, the first capacitor C17, the first connection point 11, the second switching element Q2, and the second capacitor C27.

[0096] Furthermore, in the fourth control, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4 in each of the multiple inverter circuits 1. By turning on only the third switching element Q3 and the fourth switching element Q4 among the first to fourth switching elements Q1 to Q4, the third capacitor C37 and the second capacitor C27 are charged from the power supply unit 9. At this time, a charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the third resistor R37, the third capacitor C37, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. In addition, the charging path Ru92 that charges the second capacitor C27 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. 15.

[0097] The voltage charged to the first capacitor C17 during one third control and one fourth control is determined by the amount of charge stored in the first capacitor C17, the amount of charge discharged from the third capacitor C37, and the amount of charge discharged from the second capacitor C27. By alternately repeating the third control and the fourth control, it is possible to increase the voltage Vo1 across the first capacitor C17. During the initial charging control, the control unit 60 sets the time T3 (see FIG. 17 ) during which the third control and the fourth control are repeated to be equal to or longer than the CR time constant determined by the capacitance of the first capacitor C17 and the resistance value of the first resistor R17 of the multiple first bootstrap circuits 71. The time T3 during which the third control and the fourth control are repeated is, for example, 2 ms.

[0098] FIG. 17 is a diagram showing the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 when the control unit 60 starts the charging control operation at time t1, and the waveforms of the voltage Vo1 across the first capacitor C17, the voltage Vo2 across the second capacitor C27, and the voltage Vo3 across the third capacitor C37.

[0099] 17, the control unit 60 starts the first control at time t1, so that only the fourth switching element Q4 is turned on at time t1. When only the fourth switching element Q4 is turned on, charging of the third capacitor C37 from the power supply unit 9 begins, and the voltage Vo3 across the third capacitor C37 increases to the fully charged voltage.

[0100] After that, at time t2, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4. When only the third switching element Q3 and the fourth switching element Q4 are turned on, charging of the second capacitor C27 from the power supply unit 9 begins, and the voltage Vo2 across the second capacitor C27 increases to the fully charged voltage. The control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.

[0101] After that, at time t3, the control unit 60 turns on only the second switching element Q2 and the third switching element Q3. The control unit 60 selects the zero vector V0o

[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.

[0102] After that, at time t4, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4. The control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector and turns on only the third switching element Q3 and the fourth switching element Q4.

[0103] After that, at time t5, the control unit 60 turns on only the second switching element Q2 and the third switching element Q3. The control unit 60 selects the zero vector V0o

[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.

[0104] Thereafter, at time t6, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4. The control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector and turns on only the third switching element Q3 and the fourth switching element Q4. The voltage Vo2 across the second capacitor C27 between time t5 and time t6 is greater than the voltage Vo2 across the second capacitor C27 between time t3 and time t4. The voltage Vo3 across the third capacitor C37 between time t5 and time t6 is greater than the voltage Vo3 across the third capacitor C37 between time t3 and time t4.

[0105] Thereafter, at time t7, the control unit 60 turns on only the second switching element Q2 and the third switching element Q3. The control unit 60 selects the zero vector V0o

[000] (V0o in FIG. 17) as the voltage vector and turns on only the second switching element Q2 and the third switching element Q3. The voltage Vo1 across the first capacitor C17 from time t5 to time t7 is greater than the voltage Vo1 across the first capacitor C17 from time t3 to time t5.

[0106] Thereafter, at time t8, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4. The control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector and turns on only the third switching element Q3 and the fourth switching element Q4. The voltage Vo2 across the second capacitor C27 between time t7 and time t8 is greater than the voltage Vo2 across the second capacitor C27 between time t5 and time t6. The voltage Vo3 across the third capacitor C37 between time t7 and time t8 is greater than the voltage Vo3 across the third capacitor C37 between time t5 and time t6.

[0107] Thereafter, at time t9, the control unit 60 turns on only the second switching element Q2 and the third switching element Q3. The control unit 60 selects the zero vector V0o

[000] (V0o in FIG. 17) as the voltage vector and turns on only the second switching element Q2 and the third switching element Q3. The voltage Vo1 across the first capacitor C17 from time t7 to time t9 is greater than the voltage Vo1 across the first capacitor C17 from time t5 to time t7.

[0108] Thereafter, at time t10, the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4. The control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector and turns on only the third switching element Q3 and the fourth switching element Q4. The voltage Vo2 across the second capacitor C27 between time t9 and time t10 is greater than the voltage Vo2 across the second capacitor C27 between time t7 and time t8. The voltage Vo3 across the third capacitor C37 between time t9 and time t10 is greater than the voltage Vo3 across the third capacitor C37 between time t7 and time t8.

[0109] (4) Summary In the multilevel inverter 100 according to the embodiment, the control unit 60 has a function of performing initial charge control to initially charge each of the first capacitors C17, each of the second capacitors C27, and each of the third capacitors C37 at startup. In the initial charge control, the control unit 60 performs a first control in which only the fourth switching element Q4 is turned on in each inverter circuit 1, and then turns on only the third switching element Q3 and the fourth switching element Q4, or a second control in which only the third switching element Q3 and the fourth switching element Q4 are turned on, and then alternately repeats a third control in which only the second switching element Q2 and the third switching element Q3 are turned on, and a fourth control in which only the third switching element Q3 and the fourth switching element Q4 are turned on.

[0110] In the multilevel inverter 100 according to the embodiment, the control unit 60 performs the above-described initial charge control at startup, and therefore, it is possible to reduce switching loss. More specifically, in the multilevel inverter 100 according to the embodiment, it is possible to reduce switching loss in each of the first switching elements Q1, the second switching elements Q2, and the third switching elements Q3, compared to when the control unit 60 does not perform the above-described initial charge control at startup.

[0111] In the multilevel inverter 100 according to the embodiment, the control unit 60 performs initial charge control before performing inverter control. This allows the voltage Vo1 across each first capacitor C17 to be larger when inverter control starts (for example, the voltage Vo1 across each first capacitor C17 can be set to the fully charged voltage of each first capacitor C17). Therefore, in the multilevel inverter 100 according to the embodiment, the difference between the gate voltage (gate-emitter voltage) applied to the first switching element Q1 in each inverter circuit 1 and the threshold voltage (for example, 5.8 V) of the first switching element Q1 can be larger, thereby reducing the switching loss of the first switching element Q1. Furthermore, in the multilevel inverter 100 according to the embodiment, the voltage Vo2 across each second capacitor C27 when inverter control starts can be larger (for example, the voltage Vo2 across each second capacitor C27 can be set to the fully charged voltage of each second capacitor C27). Therefore, in the multilevel inverter 100 according to the embodiment, the difference between the gate voltage (gate-emitter voltage) applied to the second switching element Q2 in each inverter circuit 1 and the threshold voltage (e.g., 5.8 V) of the second switching element Q2 can be increased, thereby reducing the switching loss of the second switching element Q2. Furthermore, in the multilevel inverter 100 according to the embodiment, the voltage Vo3 across each third capacitor C37 when inverter control starts can be increased (e.g., the voltage Vo3 across each third capacitor C37 can be set to the fully charged voltage of each third capacitor C37). Therefore, in the multilevel inverter 100 according to the embodiment, the difference between the gate voltage (gate-emitter voltage) applied to the third switching element Q3 in each inverter circuit 1 and the threshold voltage (e.g., 5.8 V) of the third switching element Q3 can be increased, thereby reducing the switching loss of the third switching element Q3.

[0112] (Modifications) The above embodiment is merely one of various embodiments of the present disclosure. The above embodiment can be modified in various ways depending on the design and the like as long as the object of the present disclosure can be achieved.

[0113] For example, instead of the first control, the control unit 60 may perform a control (second control) in which only the third switching element Q3 and the fourth switching element Q4 are turned on, and then the third control and the fourth control may be repeated alternately. When the control unit 60 performs the second control, the duration of the on-period of the third switching element Q3 is the same as the duration of the on-period of the fourth switching element Q4.

[0114] Furthermore, the time T1 during which the control unit 60 turns on only the fourth switching element Q4 in the first control is not limited to a time equal to or greater than the CR time constant of the third bootstrap circuit 73, but may be, for example, a time equal to or greater than 90% but less than 100% of the CR time constant.

[0115] Furthermore, the time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on when the control unit 60 is in the first control or second control is not limited to a time equal to or greater than the CR time constant determined by the capacitance of the second capacitor C27 and the resistance value of the second resistor R27 of the second bootstrap circuit 72, but may be, for example, a time equal to or greater than 90% but less than 100% of the CR time constant.

[0116] Furthermore, the time T3 (see FIG. 17) during which the control unit 60 repeats the third control and the fourth control is not limited to a time equal to or greater than the CR time constant determined by the capacitance of the first capacitor C17 and the resistance value of the first resistor R17 of the plurality of first bootstrap circuits 71, but may be, for example, a time equal to or greater than 90% but less than 100% of the CR time constant.

[0117] Furthermore, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are a gate terminal, a drain terminal, and a source terminal, respectively. In each switching circuit 10, the MOSFETs constituting each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are, for example, normally-off n-channel MOSFETs. Note that although the MOSFETs are Si-based MOSFETs, they are not limited to Si-based MOSFETs and may be, for example, SiC-based MOSFETs.

[0118] Furthermore, each of the plurality of first bootstrap circuits 71 may include the first Zener diode Z17 but may not include the first Zener diode Z17. Furthermore, each of the plurality of second bootstrap circuits 72 may include the second Zener diode Z27 but may not include the second Zener diode Z27. Furthermore, each of the plurality of third bootstrap circuits 73 may include the third Zener diode Z37 but may not include the third Zener diode Z37.

[0119] Each of the plurality of first bootstrap circuits 71 includes a first resistor R17, and the CR time constant is determined by the capacitance of the first capacitor C17 and the resistance value of the first resistor R17, but the CR time constant may be determined by the capacitance of the first capacitor C17 and the equivalent series resistance (ESR) of the first capacitor C17 without including the first resistor R17. Each of the plurality of second bootstrap circuits 72 includes a second resistor R27, and the CR time constant is determined by the capacitance of the second capacitor C27 and the resistance value of the second resistor R27, but the CR time constant may be determined by the capacitance of the second capacitor C27 and the ESR of the second capacitor C27 without including the second resistor R27. Furthermore, each of the plurality of third bootstrap circuits 73 includes a third resistor R37, and the CR time constant is determined by the capacitance of the third capacitor C37 and the resistance value of the third resistor R37. However, the configuration may be such that the CR time constant is determined by the capacitance of the third capacitor C37 and the ESR of the third capacitor C37 without including the third resistor R37.

[0120] Furthermore, the multilevel inverter 100 may be configured such that the power supply unit 9 includes a plurality (three) of DC-DC converters 91. The plurality of DC-DC converters 91 correspond to a plurality (three) of fourth gate drivers 64 and are connected in parallel to the corresponding fourth gate drivers 64.

[0121] Furthermore, the multilevel inverter 100 is not limited to a configuration including a plurality of switching circuits 10, and may be a configuration including one switching circuit 10. When the multilevel inverter 100 is a configuration including one switching circuit 10 instead of a plurality of switching circuits 10, there is also one each of the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64, and there is also one each of the first bootstrap circuit 71, the second bootstrap circuit 72, and the third bootstrap circuit 73.

[0122] Furthermore, the control unit 60 is not limited to being configured to perform voltage vector control, but may also be configured to perform PWM control.

[0123] The multilevel inverter 100 may be any multilevel inverter having three or more levels, and may be, for example, a five-level inverter.

[0124] (Aspects) The following aspects are disclosed in this specification.

[0125] A multilevel inverter (100) according to a first aspect includes a DC power supply unit (3), an inverter circuit (1), and a control device (6). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The inverter circuit (1) is connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control device (6) controls the inverter circuit (1). The inverter circuit (1) includes a switching circuit (10), a first clamp diode (D5), and a second clamp diode (D6). The switching circuit (10) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4). In the switching circuit (10), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side in the order of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4). A first clamp diode (D5) is connected between a first connection point (11) between the first switching element (Q1) and the second switching element (Q2) and an intermediate potential point (M1). A second clamp diode (D6) is connected between a second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4) and the intermediate potential point (M1). The control device (6) has a first gate driver (61), a second gate driver (62), a third gate driver (63), a fourth gate driver (64), a first bootstrap circuit (71), a second bootstrap circuit (72), a third bootstrap circuit (73), a power supply unit (9), and a control unit (60). The first gate driver (61) drives a first switching element (Q1). The second gate driver (62) drives a second switching element (Q2). The third gate driver (63) drives a third switching element (Q3). The fourth gate driver (64) drives a fourth switching element (Q4).The first bootstrap circuit (71) includes a first capacitor (C17) connected in parallel to the first gate driver (61) and a first diode (D17) connected in series to the first capacitor (C17). The second bootstrap circuit (72) includes a second capacitor (C27) connected in parallel to the second gate driver (62) and a second diode (D27) connected in series to the second capacitor (C27). The third bootstrap circuit (73) includes a third capacitor (C37) connected in parallel to the third gate driver (63) and a third diode (D37) connected in series to the third capacitor (C37). The power supply unit (9) is connected in parallel to the fourth gate driver (64). The control unit (60) controls the first gate driver (61), the second gate driver (62), the third gate driver (63), and the fourth gate driver (64). The power supply unit (9) is connected to the third capacitor (C37) via a third diode (D37), to the second capacitor (C27) via the third diode (D37) and the second diode (D27), and to the first capacitor (C17) via the third diode (D37), the second diode (D27), and the first diode (D17). The control unit (60) has a function of performing initial charge control to initially charge the first capacitor (C17), the second capacitor (C27), and the third capacitor (C37) at startup. In the initial charging control, the control unit (60) performs a first control in which only the fourth switching element (Q4) is turned on and then only the third switching element (Q3) and the fourth switching element (Q4) are turned on, or a second control in which only the third switching element (Q3) and the fourth switching element (Q4) are turned on, and then alternately repeats a third control in which only the second switching element (Q2) and the third switching element (Q3) are turned on, and a fourth control in which only the third switching element (Q3) and the fourth switching element (Q4) are turned on.

[0126] According to this aspect, switching loss can be reduced.

[0127] In the multilevel inverter (100) according to the second aspect, in the first aspect, the first bootstrap circuit (71) further includes a first resistor (R17). The first resistor (R17) is connected between the first diode (D17) and the first capacitor (C17). The second bootstrap circuit (72) further includes a second resistor (R27). The second resistor (R27) is connected between the second diode (D27) and the second capacitor (C27). The third bootstrap circuit (73) further includes a third resistor (R37). The third resistor (R37) is connected between the third diode (D37) and the third capacitor (C37).

[0128] In the multilevel inverter (100) according to the third aspect, in the second aspect, the control unit (60) sets the time (T1) of the on-period of the fourth switching element (Q4) to a time equal to or greater than a CR time constant determined by the capacitance of the third capacitor (C37) and the resistance value of the third resistor (R37) of the third bootstrap circuit (73) in the first control or the second control.

[0129] According to this aspect, it is possible to reduce the switching loss of the third switching element (Q3) after the initial charge control.

[0130] In the multilevel inverter (100) according to the fourth aspect, in the second aspect, the control unit (60) performs a first control in the initial charge control in which only the fourth switching element (Q4) is turned on and then only the third switching element (Q3) and the fourth switching element (Q4) are turned on. In the first control, the control unit (60) sets a time (T1) of a period in which only the fourth switching element (Q4) is turned on to a time equal to or longer than a CR time constant determined by the capacitance of the third capacitor (C37) and the resistance value of the third resistor (R37) of the third bootstrap circuit (73), and sets a time (T2) of a period in which only the third switching element (Q3) and the fourth switching element (Q4) are turned on to a time equal to or longer than a CR time constant determined by the capacitance of the second capacitor (C27) and the resistance value of the second resistor (R27) of the second bootstrap circuit (72).

[0131] According to this aspect, it is possible to reduce the switching loss of each of the second switching element (Q2) and the third switching element (Q3) after the initial charging control.

[0132] In the multilevel inverter (100) according to the fifth aspect, in any one of the second to fourth aspects, the control unit (60) sets the time of the period during which the third control and the fourth control are repeated in the initial charge control to a time equal to or greater than a CR time constant determined by the capacitance of the first capacitors (C17) and the resistance values ​​of the first resistors (R17) of the plurality of first bootstrap circuits (71).

[0133] According to this aspect, it is possible to reduce the switching loss of the first switching element (Q1) after the initial charge control.

[0134] A multilevel inverter (100) according to a sixth aspect is any one of the first to fifth aspects, and includes three inverter circuits (1), three first gate drivers (61), three second gate drivers (62), three third gate drivers (63), three fourth gate drivers (64), three first bootstrap circuits (71), three second bootstrap circuits (72), and three third bootstrap circuits (73).

[0135] According to this aspect, it is possible to reduce the switching loss in each of the three inverter circuits (1).

[0136] In a multilevel inverter (100) according to a seventh aspect, in the sixth aspect, three first bootstrap circuits (71) and three second bootstrap circuits (72) are in one-to-one correspondence. Three first bootstrap circuits (71) and three third bootstrap circuits (73) are in one-to-one correspondence. Three second bootstrap circuits (72) and three third bootstrap circuits (73) are in one-to-one correspondence. A power supply unit (9) is connected in parallel to three fourth gate drivers (64). The power supply unit (9) is connected to a third capacitor (C37) via a third diode (D37) in each of the three third bootstrap circuits (73). The power supply unit (9) is connected to a second capacitor (C27) in each of the three second bootstrap circuits (72) via a third diode (D37) and a second diode (D27) in a corresponding one of the three third bootstrap circuits (73). The power supply unit (9) is connected to the first capacitor (C17) in each of the three first bootstrap circuits (71) via the third diode (D37) of the corresponding third bootstrap circuit (73) among the three third bootstrap circuits (73), and the second diode (D27) and first diode (D17) of the corresponding second bootstrap circuit (72) among the three second bootstrap circuits (72).

[0137] According to this aspect, it is possible to achieve miniaturization.

[0138] In the multilevel inverter (100) according to an eighth aspect, in any one of the first to seventh aspects, the power supply unit (9) includes a DC-DC converter (91).

[0139] The multilevel inverter of the present disclosure can reduce switching loss, and is thus industrially useful.

[0140] REFERENCE SIGNS LIST 1 inverter circuit 3 DC power supply unit 6 control device 60 control unit 61 first gate driver 62 second gate driver 63 third gate driver 64 fourth gate driver 9 power supply unit 91 DC-DC converter 10 switching circuit 11 first connection point 12 second connection point 13 third connection point 71 first bootstrap circuit 72 second bootstrap circuit 73 third bootstrap circuit 100 multilevel inverter C17 first capacitor C27 second capacitor C37 third capacitor D5 first clamp diode D6 second clamp diode D17 first diode D27 second diode D37 third diode P1 positive pole Q1 first switching element Q2 second switching element Q3 third switching element Q4 fourth switching element M1 intermediate potential point N1 negative pole R17 first resistor R27 second resistor R37 third resistor

Claims

1. A DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point, An inverter circuit connected between the positive and negative electrodes of the DC power supply unit, The system comprises a control device for controlling the inverter circuit, The aforementioned inverter circuit is A switching circuit having a first switching element, a second switching element, a third switching element, and a fourth switching element, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series in the order of first switching element, second switching element, third switching element, and fourth switching element from the positive side to the negative side, A first clamp diode is connected between the first connection point between the first switching element and the second switching element and the intermediate potential point, The device comprises a second connection point between the third switching element and the fourth switching element, and a second clamp diode connected between the intermediate potential point, The control device is A first gate driver that drives the first switching element, A second gate driver that drives the second switching element, A third gate driver that drives the third switching element, A fourth gate driver that drives the fourth switching element, A first bootstrap circuit including a first capacitor connected in parallel to the first gate driver and a first diode connected in series with the first capacitor, A second bootstrap circuit including a second capacitor connected in parallel to the second gate driver and a second diode connected in series with the second capacitor, A third bootstrap circuit including a third capacitor connected in parallel to the third gate driver and a third diode connected in series with the third capacitor, A power supply unit connected in parallel to the fourth gate driver, It comprises a control unit that controls the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver, The power supply unit is connected to the third capacitor via the third diode, to the second capacitor via the third diode and the second diode, and to the first capacitor via the third diode, the second diode and the first diode. The control unit has a function to perform initial charge control to initially charge the first capacitor, the second capacitor, and the third capacitor at startup. In the initial charge control, the control unit, A first control is performed in which only the fourth switching element is turned on, and then only the third and fourth switching elements are turned on, or a second control is performed in which only the third and fourth switching elements are turned on. Subsequently, a third control that turns on only the second and third switching elements, and a fourth control that turns on only the third and fourth switching elements are alternately repeated. Multilevel inverter.

2. The first bootstrap circuit further includes a first resistor connected between the first diode and the first capacitor, The second bootstrap circuit further includes a second resistor connected between the second diode and the second capacitor, The third bootstrap circuit further includes a third resistor connected between the third diode and the third capacitor. The multilevel inverter according to claim 1.

3. In the first control or the second control, the control unit sets the on-period time of the fourth switching element to a time that is greater than or equal to the CR time constant determined by the capacitance of the third capacitor and the resistance of the third resistor in the third bootstrap circuit. The multilevel inverter according to claim 2.

4. In the initial charge control, the control unit, A first control is performed in which only the fourth switching element is turned on, and then only the third switching element and the fourth switching element are turned on. The control unit, In the first control, the on-time of only the fourth switching element is set to be longer than or equal to the CR time constant determined by the capacitance of the third capacitor and the resistance of the third resistor in the third bootstrap circuit, and the on-time of only the third switching element and the fourth switching element is set to be longer than or equal to the CR time constant determined by the capacitance of the second capacitor and the resistance of the second resistor in the second bootstrap circuit. The multilevel inverter according to claim 2.

5. In the initial charge control, the control unit sets the time for repeating the third control and the fourth control to be longer than or equal to the CR time constant determined by the capacitance of the first capacitor and the resistance value of the first resistor of the plurality of first bootstrap circuits. A multilevel inverter according to any one of claims 2 to 4.

6. The inverter circuit comprises three of the above-mentioned circuits. The system comprises three of the aforementioned first gate drivers, The system comprises three of the aforementioned second gate drivers, The system comprises three of the aforementioned third gate drivers, The system comprises three of the aforementioned fourth gate drivers, The system comprises three of the aforementioned first bootstrap circuits, The system comprises three of the aforementioned second bootstrap circuits, The system comprises three of the aforementioned third bootstrap circuits. A multilevel inverter according to any one of claims 1 to 4.

7. The three first bootstrap circuits and the three second bootstrap circuits correspond one-to-one. The three first bootstrap circuits and the three third bootstrap circuits correspond one-to-one. The three second bootstrap circuits and the three third bootstrap circuits correspond one-to-one. The aforementioned power supply unit is It is connected in parallel to the three fourth gate drivers mentioned above. In each of the three third bootstrap circuits, the third capacitor is connected via the third diode. In each of the three second bootstrap circuits, the second capacitor is connected via the third diode and the second diode of the corresponding third bootstrap circuit among the three third bootstrap circuits. In each of the three first bootstrap circuits, the first capacitor is connected via the third diode of the corresponding third bootstrap circuit among the three third bootstrap circuits, the second diode of the corresponding second bootstrap circuit among the three second bootstrap circuits, and the first diode. The multilevel inverter according to claim 6.

8. The aforementioned power supply unit is Including a DC-DC converter, A multilevel inverter according to any one of claims 1 to 4.