Storage circuit, processing device, and electronic equipment

Abstract

Provided is a storage circuit comprising: a volatile memory which performs writing and reading quickly; and a non-volatile memory which is capable of backing up data. The storage circuit has a first layer and a second layer that is positioned above the first layer. The first layer has a semiconductor substrate that has silicon and a first circuit and a second circuit that are formed on the semiconductor substrate. Furthermore, the second layer has a first ferroelectric capacitor and a second ferroelectric capacitor. Furthermore, the first ferroelectric capacitor and the second ferroelectric capacitor each have a dielectric. The first circuit functions as a flip-flop circuit which holds first digital data, and the second circuit functions to write the first digital data to be paired with each of the first ferroelectric capacitor and the second ferroelectric capacitor. The dielectric has an oxide that contains hafnium and zirconium.

Description

Memory circuit, processing device and electronic device

[0001] One embodiment of the present invention relates to a memory circuit, a processing device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, development of FeRAMs (Ferroelectric Random Access Memories) including ferroelectric capacitors has been progressing. A ferroelectric capacitor is a capacitor in which a ferroelectric dielectric is sandwiched between a pair of electrodes. The direction of dielectric polarization (also called dielectric polarization moment, polarization moment, or polarization) can be determined by applying an external voltage, and the direction of dielectric polarization within the dielectric is maintained even when the external voltage is subsequently set to 0 V (residual polarization occurs). By utilizing this characteristic, it is possible to fabricate a memory (nonvolatile memory) capable of retaining data even without the application of a voltage. In particular, Patent Documents 1 and 2 disclose circuit configurations that retain data in a ferroelectric capacitor even when the power supply potential to a flip-flop circuit is interrupted. This circuit configuration allows data retained in the flip-flop circuit to be backed up to the ferroelectric capacitor, thereby shutting down the flip-flop circuit.

[0004] Republished Patent Publication No. 03-044953 Japanese Patent Application Laid-Open No. 2013-124290

[0005] When fabricating a ferroelectric capacitor, a high-temperature heat treatment may be required to impart ferroelectricity to a dielectric sandwiched between a pair of electrodes. For example, when hafnium oxide is used as the dielectric, a heat treatment at a temperature of 650° C. to 1000° C. is required.

[0006] When forming the above-mentioned flip-flop circuit and ferroelectric capacitor, a transistor included in the flip-flop circuit is formed on a semiconductor substrate, and then the ferroelectric capacitor is formed on the transistor. Here, when a heat treatment is performed on the dielectric of the ferroelectric capacitor, the heat treatment may affect the transistor included in the flip-flop circuit, and the characteristics of the transistor may deteriorate.

[0007] An object of one embodiment of the present invention is to provide a memory circuit that can back up data when power is turned off. Another object of one embodiment of the present invention is to provide a memory circuit with a small circuit area. Another object of one embodiment of the present invention is to provide a memory circuit with a high yield. Another object of one embodiment of the present invention is to provide a processing device including the above-described memory circuit. Another object of one embodiment of the present invention is to provide an electronic device including the above-described processing device. Another object of one embodiment of the present invention is to provide a novel memory circuit, a novel processing device, or a novel electronic device.

[0008] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0009] In view of the above-mentioned problems, one aspect of the present invention is a memory circuit in which a ferroelectric capacitor having an oxide containing hafnium and zirconium as a dielectric is stacked on a layer including a circuit, the circuit layer including a holding circuit functioning as a flip-flop circuit, a circuit for writing data to the ferroelectric capacitor, and a circuit for reading data from the ferroelectric capacitor.

[0010] In particular, oxides containing hafnium and zirconium used as dielectrics for ferroelectric capacitors can be made ferroelectric by heat treatment preferably at 400°C or higher and 700°C or lower, more preferably at 400°C or higher and 650°C or lower, and even more preferably at 400°C or higher and 500°C or lower.

[0011] A typical example of the configuration of a processing apparatus according to one embodiment of the present invention will be described below.

[0012] (1) One aspect of the present invention is a memory circuit having a first layer and a second layer located above the first layer. The first layer has a semiconductor substrate having silicon and a first circuit and a second circuit formed on the semiconductor substrate. The second layer has a first ferroelectric capacitor and a second ferroelectric capacitor. The first circuit functions as a flip-flop circuit that holds first digital data, and the second circuit functions to write first digital data that are logically paired with each other to the first ferroelectric capacitor and the second ferroelectric capacitor. The dielectric includes an oxide containing hafnium and zirconium.

[0013] (2) Alternatively, according to one aspect of the present invention, in the above-mentioned (1), the first circuit may have a selector. Furthermore, the second circuit may have a function of reading out first digital data from the first ferroelectric capacitor and the second ferroelectric capacitor. Furthermore, it is preferable that the selector has a first input terminal and a second input terminal. Furthermore, it is preferable that the selector has a function of selecting one of the first digital data read out from the first ferroelectric capacitor and the second ferroelectric capacitor and input to the first input terminal, and the second digital data input to the second input terminal. Furthermore, it is preferable that the first circuit holds the digital data selected by the selector.

[0014] (3) Alternatively, one embodiment of the present invention may have a structure in (2) above that includes a third layer located above the second layer. In particular, the third layer preferably includes a first transistor, a second transistor, and a capacitor. Furthermore, the first transistor and the second transistor preferably include an oxide semiconductor in their channel formation regions. Furthermore, it is preferable that one of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and one of a pair of electrodes of the capacitor.

[0015] It is preferable that the other of the source and drain of the first transistor receives first digital data read from the first circuit, and that the first digital data be held in one of a pair of electrodes of the capacitor. It is also preferable that the other of the source and drain of the second transistor outputs a potential corresponding to the first digital data read from the capacitor to the selector. The selector has a function of selecting one of the first digital data read from the first ferroelectric capacitor and the second ferroelectric capacitor, the first digital data read from the capacitor, and second digital data input from outside.

[0016] (4) Alternatively, in one embodiment of the present invention, in the above-described (3), the oxide semiconductor may contain one or more elements selected from indium, zinc, and an element M.

[0017] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0018] (5) In one embodiment of the present invention, in any one of (1) to (4), the dielectric may contain yttrium. In particular, the yttrium content in the oxide is preferably 0.1 atomic % to 3 atomic %.

[0019] (6) Another embodiment of the present invention is a processing device including the memory circuit of (5), a register controller, and an arithmetic circuit, wherein the register controller has a function of causing the memory circuit to write first digital data stored in a first circuit to a second circuit in accordance with an instruction from the arithmetic circuit.

[0020] (7) Another embodiment of the present invention is an electronic device including the processing device according to (6) above and a housing.

[0021] As described above, an oxide containing hafnium and zirconium used as a dielectric for a ferroelectric capacitor can obtain ferroelectricity by heat treatment, preferably at 400°C or higher and 700°C or lower, more preferably at 400°C or higher and 650°C or lower. The temperature of this heat treatment is lower than the heat treatment temperature for hafnium oxide, for example (approximately 650°C or higher and 1000°C or lower). Therefore, when a dielectric made of an oxide containing hafnium and zirconium is formed on a layer including a circuit, the influence of the heat treatment on the circuit can be reduced. This makes it possible to realize a memory circuit capable of backing up, and also to increase the yield of the memory circuit.

[0022] According to one embodiment of the present invention, a memory circuit capable of backing up data when power is cut off can be provided. Alternatively, according to one embodiment of the present invention, a memory circuit with a small circuit area can be provided. Alternatively, according to one embodiment of the present invention, a memory circuit with a high yield can be provided. Alternatively, according to one embodiment of the present invention, a processing device including the above-described memory circuit can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described processing device can be provided. Alternatively, according to one embodiment of the present invention, a novel memory circuit, a novel processing device, or a novel electronic device can be provided.

[0023] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

[0024] FIG. 1 is a circuit diagram showing an example of the configuration of a memory circuit. FIG. 2 is a circuit diagram showing an example of the configuration of a circuit included in the memory circuit. FIG. 3 is a circuit diagram showing an example of the configuration of a circuit included in the memory circuit. FIG. 4 is a timing chart showing an example of the operation of the memory circuit. FIGS. 5A and 5B are schematic perspective views showing an example of the configuration of a memory circuit. FIGS. 6A and 6B are schematic cross-sectional views showing an example of the configuration of a memory circuit. FIG. 7 is a schematic cross-sectional view showing an example of the configuration of a memory circuit. FIG. 8 is a circuit diagram showing an example of the configuration of a memory circuit. FIG. 9 is a circuit diagram showing an example of the configuration of a circuit included in the memory circuit. FIG. 10 is a timing chart showing an example of the operation of the memory circuit. FIGS. 11A and 11B are schematic perspective views showing an example of the configuration of a memory circuit. FIG. 12 is a schematic cross-sectional view showing an example of the configuration of a memory circuit. FIG. 13 is a schematic perspective view showing an example of the configuration of a processing device. FIGS. 14A and 14B are diagrams showing various memory devices by layer. FIGS. 15A to 15D are diagrams showing examples of electronic components. 16A and 16B are diagrams showing an example of electronic equipment, and FIG. 16C is a diagram showing an example of a mainframe computer. FIG. 17 is a diagram showing an example of space equipment. FIG. 18 is a diagram showing an example of a storage system applicable to a data center. FIG. 19 is a diagram showing the configuration of a ferroelectric capacitor according to an example. FIGS. 20A and 20B are diagrams showing the dielectric polarization-voltage characteristics of the ferroelectric capacitor according to the example, and FIGS. 20C and 20D are diagrams showing measurement results of an endurance test of the ferroelectric capacitor according to the example.

[0025] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component in which a chip is housed in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0026] In addition, in this specification, "connection" includes "electrical connection" and "functional connection."

[0027] In this specification, the phrase "A is electrically connected to B" refers to a state in which, when replaced with an equivalent circuit, a path through which current can flow is formed between A and B. A state in which a path through which current can flow between A and B includes a case in which A is connected to B (direct connection) without a circuit element (such as a transistor or a resistor) and a case in which A is connected to B (indirect connection) via a circuit element. Circuit elements do not include wiring. For example, when A is connected to B via the source and drain of a transistor, a path through which current can flow is formed between A and B via the source and drain of the transistor. Therefore, regardless of whether the transistor is in an on or off state, it can be said that "A is electrically connected to B." On the other hand, when an insulator (e.g., a dielectric of a capacitor element or a gate insulating film of a transistor) is included in the path from A to B, a path through which current can flow from A to B is not formed. Furthermore, when a power supply potential or a potential from a signal source (e.g., a clock signal potential) is supplied in the path from A to B, a path through which current can flow from A to B is not formed. Therefore, in these cases, it cannot be said that "A is electrically connected to B."

[0028] In this specification, the phrase "A is functionally connected to B" refers to a state in which, when replaced with an equivalent circuit, they are connected in a manner that allows a signal to be transmitted, or in a manner in which an output signal can be determined in response to an input signal. For example, the phrase "A is functionally connected to B" refers to a state in which A is connected to B via a circuit (e.g., a logic circuit, a signal conversion circuit, an amplifier circuit, etc.) that enables functional connection, or a circuit element that enables functional connection. For example, if A is connected to the input of an inverter circuit and B is connected to the output of the inverter circuit, no current flows between A and B, but an inverted signal of a signal input from A is output to B. Therefore, it can be said that "A is functionally connected to B." Furthermore, for example, if A is connected to one terminal of a capacitance element and B is connected to the other terminal of the capacitance element, and B is in a floating state, no current flows between A and B, but the potential of B changes with a change in the potential of A. Therefore, it can be said that "A is functionally connected to B."

[0029] In this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0030] In this specification, a "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F. A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be rephrased as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0031] However, there are cases where a circuit has an area with unintended capacitance, that is, "parasitic capacitance." Examples of "parasitic capacitance" include an area including different wirings connected via an insulator, and gate capacitance occurring in a transistor. In this specification, unless otherwise specified, the term "capacitive element" is explained as not including "parasitic capacitance."

[0032] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain are sometimes interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and drain" and "the other of the source and drain" are sometimes used. Furthermore, "one of the source and drain" may be referred to as "a first terminal of the transistor" or "a first electrode of the transistor," and "the other of the source and drain" may be referred to as "a second terminal of the transistor" or "a second electrode of the transistor."

[0033] Depending on the structure of the transistor, a back gate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0034] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, the multi-gate structure can provide voltage-current characteristics with a flat slope when operating in the saturation region, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. For example, voltage-current characteristics with a flat slope can be used to realize an ideal current source circuit, an active load with a very high resistance, and the like. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0035] Furthermore, even when a single circuit element is illustrated on a circuit diagram, the circuit element may actually include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected directly in series. Furthermore, two or more resistors connected directly in series may be represented as a single resistor. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected directly in parallel. Furthermore, two or more capacitance elements connected directly in parallel may be represented as a single capacitance element. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected directly in series with their sources and drains connected together, and their gates connected together. Furthermore, when two or more transistors connected directly in series with their sources and drains connected together, and their gates connected together, this may be represented as a single transistor. For example, when one transistor is shown on a circuit diagram, this includes a case where the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other. Also, a configuration in which the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other can sometimes be represented as a single transistor.

[0036] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, a switch is something that can control a current, and is not limited to a specific type.

[0037] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which current can flow between the source and drain. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor are considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0038] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0039] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0040] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0041] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0042] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0043] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0044] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0045] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0046] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0047] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". For example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Furthermore, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0048] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0049] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0050] In addition, in this specification, timing charts in the drawings may be used to explain an operation method of a semiconductor device. The timing charts used in the description show ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) shown in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other may be long. For example, to clearly illustrate the timing chart, two or more overlapping signals may be intentionally shifted.

[0051] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0052] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0053] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0054] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0055] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0056] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all of the content) described in that embodiment and another content (part or all of the content) described in one or more other embodiments.

[0057] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0058] Furthermore, a figure (part or all of its contents) described in one embodiment can be combined with at least one of another part of that figure, another figure (part or all of its contents) described in that embodiment, and one or more figures (part or all of its contents) described in another embodiment, to form even more figures.

[0059] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0060] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0061] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0062] Embodiment 1 In this embodiment, a memory circuit of one embodiment of the present invention will be described.

[0063] 1 is a circuit diagram illustrating a configuration example of a memory circuit according to one embodiment of the present invention. The memory circuit NOM illustrated in FIG. 1 is a memory circuit including a volatile memory and a nonvolatile memory.

[0064] In Figure 1, the volatile memory is shown as a holding circuit FF as an example. The nonvolatile memory is shown as a circuit BUX and a circuit BUY as an example. In particular, the circuit BUY functions as a memory element of the nonvolatile memory, and a ferroelectric capacitor using a ferroelectric material that can be fabricated at a relatively low temperature is used as the memory element. The ferroelectric material will be described in detail later.

[0065] The holding circuit FF has, for example, a terminal DI, a terminal QO, a terminal BI1, a terminal BO1A, and a terminal BO1B. For example, the holding circuit FF functions as a flip-flop circuit that holds data input to the terminal DI or the terminal BI1 and outputs the data from the terminal QO, the terminal BO1A, or the terminal BO1B. Note that the logic of the data output from the terminal QO and the terminal BO1A is the same, and the logic of the data output from the terminal BO1B is the inverted logic of the data output from the terminal BO1A.

[0066] The circuit BUX includes, for example, a circuit SA, a buffer circuit BA, and a buffer circuit BB. The circuit SA includes, for example, a first input terminal, a second input terminal, an output terminal, and a control terminal. The buffer circuits BA and BB each include, for example, an input terminal, an output terminal, and a control terminal.

[0067] The circuit BUX has a function of writing and reading data to and from the circuit BUY.

[0068] For example, the circuit SA has a function of comparing a potential input to a first input terminal with a potential input to a second input terminal and outputting a potential corresponding to the comparison result to an output terminal. For example, the circuit SA may include a differential amplifier circuit for this purpose. Furthermore, for example, the circuit SA may include a sense amplifier that amplifies the difference between the potentials input to the first input terminal and the second input terminal.

[0069] Alternatively, as an example, the circuit SA may have the function of comparing the amount of current input to the first input terminal with the amount of current input to the second input terminal, and outputting a potential corresponding to the comparison result to the output terminal.

[0070] Further, the circuit SA has, for example, a function of enabling or disabling the output of a potential from the output terminal in accordance with a potential (sometimes called an enable signal or a disable signal) input to the control terminal.

[0071] Each of the buffer circuits BA and BB has a function of outputting a potential input to an input terminal at an amplification factor of 1 to an output terminal, for example. Each of the buffer circuits BA and BB also has a function of enabling or disabling the output of a potential from the output terminal in accordance with a potential input to a control terminal (sometimes called an enable signal or a disable signal). In other words, each of the buffer circuits BA and BB functions as a three-state buffer.

[0072] The circuit BUY includes, for example, a ferroelectric capacitor FA and a ferroelectric capacitor FB. The circuit BUY also has a function of retaining data using the ferroelectric capacitor FA and the ferroelectric capacitor FB.

[0073] The input terminal of the buffer circuit BA is electrically connected to the terminal BO1A. The output terminal of the buffer circuit BA is electrically connected to the first terminal of the ferroelectric capacitor FA and the first input terminal of the circuit SA. The input terminal of the buffer circuit BB is electrically connected to the terminal BO1B. The output terminal of the buffer circuit BB is electrically connected to the first terminal of the ferroelectric capacitor FB and the second input terminal of the circuit SA. The output terminal of the circuit SA is electrically connected to the terminal BI1. The second terminal of the ferroelectric capacitor FA and the second terminal of the ferroelectric capacitor FB are each electrically connected to the wiring PL.

[0074] A wiring CNL1 is electrically connected to each control terminal of the buffer circuit BA and the buffer circuit BB. The wiring CNL1 functions as a wiring for transmitting the enable signal or disable signal described above.

[0075] In this specification, each of the buffer circuits BA and BB is defined as a buffer circuit that becomes active when a high-level potential is input to the control terminal as an enable signal, and becomes inactive when a low-level potential is input to the control terminal as a disable signal.

[0076] A wiring CNL2 is electrically connected to a control terminal of the circuit SA. The wiring CNL2 functions as a wiring for transmitting the enable signal or disable signal described above.

[0077] Although FIG. 1 shows each of the wiring CNL1 and the wiring CNL2 as a single extending wiring, each of the wiring CNL1 and the wiring CNL2 may be a wiring group having a plurality of wirings.

[0078] Each of the ferroelectric capacitors FA and FB included in the circuit BUY has a pair of electrodes and a ferroelectric material sandwiched between the pair of electrodes. In a capacitance element having a paraelectric material, dielectric polarization occurs only while an external voltage is being applied to the pair of electrodes, but in a ferroelectric capacitor, the dielectric polarization remains even when the external voltage is set to 0 V. In other words, a ferroelectric capacitor has the property of residual polarization within the ferroelectric material (in other words, a ferroelectric material can be said to have spontaneous polarization). For this reason, a memory circuit including a ferroelectric capacitor can be treated as a non-volatile memory circuit by associating the direction of the residual dielectric polarization with data.

[0079] In particular, in this embodiment, digital data that are logically paired with each other are recorded in the ferroelectric capacitor FA and the ferroelectric capacitor FB included in the circuit BUY. For example, when writing digital data "0" to the circuit BUY, "0" is written to the ferroelectric capacitor FA and "1" is written to the ferroelectric capacitor FB. Also, when writing digital data "1" to the circuit BUY, "1" is written to the ferroelectric capacitor FA and "0" is written to the ferroelectric capacitor FB. In other words, the circuit BUY has the function of holding the written digital data complementarily.

[0080] <<Configuration Example of Holding Circuit FF>> Next, a circuit configuration example of the holding circuit FF will be described.

[0081] Fig. 2 is a circuit diagram of a holding circuit FF, which is an example of the holding circuit FF shown in Fig. 1. In Fig. 2, the holding circuit FF has a selector SLC, inverters IV1, IV2, and IV3, and switches SW1 and SW2.

[0082] The selector SLC also has, for example, a first input terminal, a second input terminal, an output terminal, and a control terminal.

[0083] For example, the selector SLC has a function of establishing a conductive state between one of the first input terminal and the second input terminal and the output terminal, and establishing a non-conductive state between the other of the first input terminal and the second input terminal and the output terminal. In addition, the selector SLC selects one of the first input terminal and the second input terminal that is conductive with the output terminal and selects the other of the first input terminal and the second input terminal that is non-conductive with the output terminal, according to a potential (sometimes called a control signal) input to a control terminal.

[0084] In this specification, the selector SLC is assumed to establish a conductive state between the first input terminal and the output terminal and to establish a non-conductive state between the second input terminal and the output terminal when a high-level potential is input to the control terminal, and to establish a non-conductive state between the first input terminal and the output terminal and to establish a conductive state between the second input terminal and the output terminal when a low-level potential is input to the control terminal.

[0085] For example, an electrical switch or a mechanical switch can be used as the switches SW1 and SW2. As one of the electrical switches, a transistor or an analog switch can be used. In particular, it is preferable to use an analog switch as the switches SW1 and SW2.

[0086] In this specification, each of the switches SW1 and SW2 is defined as a switch that is turned on when a high-level potential is input to the control terminal, and is turned off when a low-level potential is input to the control terminal.

[0087] The first input terminal of the selector SLC is electrically connected to the terminal DI, the second input terminal of the selector SLC is electrically connected to the terminal BI1, and the output terminal of the selector SLC is electrically connected to the input terminal of the inverter IV1. The output terminal of the inverter IV1 is electrically connected to the first terminal of the switch SW1. The second terminal of the switch SW1 is electrically connected to the input terminal of the inverter IV2 and the first terminal of the switch SW2. The output terminal of the inverter IV2 is electrically connected to the terminal QO, the terminal BO1A, and the input terminal of the inverter IV3. The output terminal of the inverter IV3 is electrically connected to the second terminal of the switch SW2 and the terminal BO1B.

[0088] The control terminal of the selector SLC is electrically connected to the wiring SEL, which functions as a wiring for transmitting the control signal, for example.

[0089] The control terminal of the switch SW1 is electrically connected to the wiring SWL1, and the control terminal of the switch SW2 is electrically connected to the wiring SWL2. The wiring SWL1 functions as a wiring that transmits a signal for switching the switch SW1 between an on state and an off state, and the wiring SWL2 functions as a wiring that transmits a signal for switching the switch SW2 between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to each of the wirings SWL1 and SWL2 as a signal for switching between an on state and an off state.

[0090] Note that the logic of the signals input to the wiring SWL1 and the wiring SWL2 is preferably inverted. For example, when a high-level potential is input to the wiring SWL1, a low-level potential is preferably input to the wiring SWL2. Furthermore, when a low-level potential is input to the wiring SWL1, a high-level potential is preferably input to the wiring SWL2.

[0091] <<Configuration Example of Circuit BUX>> Next, a circuit configuration example of the circuit BUX will be described.

[0092] Fig. 3 is a circuit diagram of a circuit BUX, which is an example of the circuit BUX shown in Fig. 1. In particular, Fig. 3 shows an example of a specific circuit configuration of a circuit SA. Note that Fig. 3 also shows a holding circuit FF and a circuit BUY in order to show the peripheral connection configuration of the circuit BUX.

[0093] In FIG. 3, the circuit SA has a switch SWA1, a switch SWA2, a switch SWB1, a switch SWB2, an inverter IVA, and an inverter IVB.

[0094] For example, the switches applicable to the above-described switch SW1 or switch SW2 can be used for switches SWA1, SWA2, SWB1, SWB2, and SWA3. Therefore, unless otherwise specified, for switches SWA1, SWA2, SWB1, SWB2, and SWA3, the description of switches SW1 and SW2 included in holding circuit FF in FIG. 2 can be referred to.

[0095] In addition, in Figure 3, in order to clearly indicate the first input terminal, second input terminal, and output terminal of circuit SA, terminal SI1 is shown as the first input terminal of circuit SA, terminal SI2 is shown as the second input terminal of circuit SA, and terminal SO is shown as the output terminal of circuit SA.

[0096] In circuit SA, terminal SI1 (first input terminal of circuit SA) is electrically connected to first terminals of switches SWA1, SWA2, and SWA3. Terminal SI2 (second input terminal of circuit SA) is electrically connected to first terminals of switches SWB1 and SWB2. Terminal SO (output terminal of circuit SA) is electrically connected to the second terminal of switch SWA3.

[0097] As mentioned above, the terminal SI1 (the first input terminal of the circuit SA) is electrically connected to the output terminal of the buffer circuit BA and the ferroelectric capacitor FA. Therefore, it can be said that the output terminal of the buffer circuit BA and the first terminal of the ferroelectric capacitor FA are electrically connected to the first terminal of the switch SWA1, the first terminal of the switch SWA2, and the first terminal of the switch SWA3, respectively. In particular, in FIG. 3, a region where the output terminal of the buffer circuit BA, the first terminal of the ferroelectric capacitor FA, the first terminal of the switch SWA1, the first terminal of the switch SWA2, and the first terminal of the switch SWA3 can be electrically connected to each other is illustrated as a node NA.

[0098] As mentioned above, the terminal SI2 (the second input terminal of the circuit SA) is electrically connected to the output terminal of the buffer circuit BB and the first terminal of the ferroelectric capacitor FB. Therefore, it can be said that the output terminal of the buffer circuit BA and the first terminal of the ferroelectric capacitor FB are electrically connected to the first terminal of the switch SWB1 and the first terminal of the switch SWB2, respectively. In particular, in FIG. 3, the region where the output terminal of the buffer circuit BB, the first terminal of the ferroelectric capacitor FB, the first terminal of the switch SWB1, and the first terminal of the switch SWB2 can be electrically connected to each other is illustrated as a node NB.

[0099] A second terminal of the switch SWA1 is electrically connected to the wiring CVL. A second terminal of the switch SWA2 is electrically connected to the input terminal of the inverter IVA and the output terminal of the inverter IVB. A second terminal of the switch SWB1 is electrically connected to the wiring CVL. A second terminal of the switch SWB2 is electrically connected to the output terminal of the inverter IVA and the input terminal of the inverter IVB.

[0100] The control terminals of the switches SWA1 and SWB1 are electrically connected to a wiring CNL21. The control terminals of the switches SWA2 and SWB2 are electrically connected to a wiring CNL22. The control terminal of the switch SWA3 is electrically connected to a wiring CNL23.

[0101] The wiring CNL21 functions as a wiring that transmits a signal for switching the switches SWA1 and SWB1 between an on state and an off state, the wiring CNL22 functions as a wiring that transmits a signal for switching the switches SWA2 and SWB2 between an on state and an off state, and the wiring CNL23 functions as a wiring that transmits a signal for switching the switch SWA3 between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to each of the wirings SWL1 and SWL2 as a signal for switching between an on state and an off state.

[0102] The wirings CNL21 to CNL23 correspond to the wiring CNL2 shown in FIG.

[0103] The wiring CVL also functions as a wiring for applying a fixed potential. The fixed potential is preferably, for example, a low-level potential. Examples of the fixed potential other than the low-level potential include a high-level potential, a ground potential, and a negative potential.

[0104] <Operation Example of Memory Circuit> Next, an operation example of the memory circuit NOM shown in FIG. 1 will be described.

[0105] In the description of this operation example, it is assumed that the holding circuit FF included in the memory circuit NOM is the holding circuit FF shown in Fig. 2. It is also assumed that the circuit BUX included in the memory circuit NOM is the circuit BUX shown in Fig. 3.

[0106] 4 is a timing chart illustrating an operation example of the memory circuit NOM. The timing chart in FIG. 4 illustrates changes in potentials of the wiring SEL, the wiring SWL1, the wiring SWL2, the wiring CNL1, the wiring CNL21, the wiring CNL22, the wiring CNL23, the wiring PL, the terminal DI, the terminal QO, the terminal BO1A, the node NA, the node NB, and the terminal BI1 before time T01, from time T01 to time T11, and after time T11.

[0107] In the timing chart of FIG. 4, hatched periods indicate periods in which the potential is indefinite (the potential is not uniquely determined).

[0108] In this operation example, the fixed potential applied by the wiring CVL is a low-level potential.

[0109] In this operation example, when a high-level potential is applied to the first terminal and a low-level potential is applied to the second terminal of each of the ferroelectric capacitors FA and FB, the dielectric polarization in each ferroelectric capacitor is oriented from the first terminal to the second terminal, and this direction is defined as the "+" direction in this specification. When a low-level potential is applied to the first terminal and a high-level potential is applied to the second terminal, the dielectric polarization in each ferroelectric capacitor is oriented from the second terminal to the first terminal, and this direction is defined as the "-" direction in this specification.

[0110] As described above, the circuit BUY will be described as holding digital data complementarily. For example, in the circuit BUY, when the dielectric polarization of the ferroelectric capacitor FA is oriented in the + direction by writing digital data, the dielectric polarization of the ferroelectric capacitor FB is oriented in the - direction. Also, in the circuit BUY, when the dielectric polarization of the ferroelectric capacitor FA is oriented in the - direction by writing digital data, the dielectric polarization of the ferroelectric capacitor FB is oriented in the + direction.

[0111] In this operation example, between time T01 and time T02, the holding circuit FF holds the data input to the terminal DI. Between time T03 and time T05, the data held in the holding circuit FF is backed up to the circuit BUY. Between time T06 and time T11, as an example, the backed up data is written back from the circuit BUY to the holding circuit FF. These operations will be described below.

[0112] <<Before Time T01>> Before time T01, for example, a high-level potential (denoted as "High" in FIG. 4) is input to the wiring SEL, a low-level potential (denoted as "Low" in FIG. 4) is input to the wiring SWL1, and a high-level potential is input to the wiring SWL2. A low-level potential is input to each of the wirings CNL1 and CNL21 to CNL23. An intermediate potential (denoted as "Mid" in FIG. 4) that exceeds the low-level potential and is less than the high-level potential is input to the wiring PL. An arbitrary data signal (denoted as a high-level potential in FIG. 4, for example) is input to the terminal DI as data to be stored in the memory circuit NOM.

[0113] Because a high-level potential is input to the wiring SEL, the selector SLC has a conductive state between the first input terminal and the output terminal, and a non-conductive state between the second input terminal and the output terminal. Also, because a low-level potential is input to the wiring SWL1, the switch SW1 is turned off. Also, because a high-level potential is input to the wiring SWL2, the switch SW2 is turned on.

[0114] Therefore, the data signal (high-level potential) input to the terminal DI is input to the input terminal of the inverter IV1. The inverter IV1 outputs a low-level potential from its output terminal as a signal with the logic of the data signal inverted. Note that, because the switch SW1 is in the off state, the signal does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0115] Furthermore, because switch SW2 is in the on state, conduction occurs between the input terminal of inverter IV2 and the output terminal of inverter IV3. In other words, a signal can be looped by inverters IV2 and IV3. Note that, before time T01, the potentials of the output terminal of inverter IV2 (corresponding to terminal QO and terminal BO1A) and the output terminal of inverter IV3 (corresponding to terminal BO1B) are undefined (not uniquely determined). Specifically, for example, before time T01, the potential of the output terminal of inverter IV2 is either a high-level potential or a low-level potential, and the potential of the output terminal of inverter IV3 is either a high-level potential or a low-level potential.

[0116] Because a low-level potential is input to the wiring CNL1, the buffer circuits BA and BB included in the circuit BUX are each inactive. Therefore, the output terminal of the buffer circuit BA becomes high impedance regardless of the potential of the input terminal of the buffer circuit BA (corresponding to the terminal BO1A of the holding circuit FF). Similarly, the output terminal of the buffer circuit BB becomes high impedance regardless of the potential of the input terminal of the buffer circuit BB (corresponding to the terminal BO1B of the holding circuit FF).

[0117] Since a low-level potential is input to each of the wirings CNL21 to CNL23, the switches SWA1, SWB1, SWA2, SWB2, and SWA3 are turned off.

[0118] Furthermore, before time T01, the potential of the output terminal of buffer circuit BA (corresponding to node NA), the potential of the output terminal of buffer circuit BB (corresponding to node NB), and the potential of the second terminal of switch SWA3 (corresponding to terminal BI1 of holding circuit FF and terminal SO of circuit SA) are each assumed to be undefined (not uniquely determined).

[0119] <<From Time T01 to Time T02>> From time T01 to time T02, the data signal input to the terminal DI is held in the holding circuit FF.

[0120] Specifically, from time T01 to time T02, a high-level potential is input to the wiring SWL1, and a low-level potential is input to the wiring SWL2.

[0121] Since a high-level potential is input to the wiring SWL1, the switch SW1 is turned on. Since a low-level potential is input to the wiring SWL2, the switch SW2 is turned off.

[0122] At this time, the data signal (high level potential) input to terminal DI is input to the input terminal of inverter IV2 via selector SLC, inverter IV1, and switch SW1. Since the logic of the data signal (high level potential) is inverted by inverters IV1 and IV2, a high level potential is output as a data signal from the output terminal of inverter IV2. In other words, a high level potential is output from terminals QO and BO1A of holding circuit FF.

[0123] Furthermore, since the data signal (high level potential) from the output terminal of the inverter IV2 is input to the input terminal of the inverter IV3, a low level potential obtained by inverting the logic of the data signal (high level potential) is output from the output terminal of the inverter IV3. In other words, a low level potential is output from the terminal BO1B of the holding circuit FF.

[0124] Furthermore, between time T01 and time T02, after a high-level potential is output from terminal QO and terminal BO1A of holding circuit FF and a low-level potential is output from terminal BO1B of holding circuit FF, a low-level potential is input to wiring SWL1 and a high-level potential is input to wiring SWL2.

[0125] Since a low-level potential is input to the wiring SWL1, the switch SW1 is turned off. Since a high-level potential is input to the wiring SWL2, the switch SW2 is turned on.

[0126] Since the switch SW1 is in the off state, the data signal (high level potential) input from the terminal DI, or more precisely, the signal (low level potential) with the logic of the data signal inverted and output from the output terminal of the inverter IV1, does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0127] Furthermore, because the switch SW2 is in the on state, conduction occurs between the input terminal of the inverter IV2 and the output terminal of the inverter IV3. In other words, because the signal is looped by the inverters IV2 and IV3, a high-level potential is held as a data signal at the output terminal of the inverter IV2 and the input terminal of the inverter IV3 (corresponding to the terminal QO and the terminal BO1A), and a low-level potential is held at the input terminal of the inverter IV2 and the output terminal of the inverter IV3 (corresponding to the terminal BO1B).

[0128] <<Between Time T02 and Time T03>> Between time T02 and time T03, the data signal input to terminal DI transitions from high to low. At this point, because switch SW1 is in the off state, the data signal (low potential) input from terminal DI—more precisely, the inverted logic signal (high potential) output from the output terminal of inverter IV1—does not reach the input terminal of inverter IV2 or the first terminal of switch SW2. In other words, the data signal is not rewritten into the loop of inverters IV2 and IV3, and holding circuit FF continues to output high potentials as a data signal from terminal QO and terminal BO1A, and low potential from terminal BO1B.

[0129] <<From Time T03 to Time T04>> From time T03 to time T04, as an example, the data held in each of the ferroelectric capacitors FA and FB is initialized.

[0130] Specifically, a high-level potential is input to each of the wiring CNL21 and the wiring PL between time T03 and time T04.

[0131] Since a high-level potential is input to the wiring CNL21, the switches SWA1 and SWB1 included in the circuit SA are each turned on, whereby a low-level potential is applied from the wiring CVL to each of the first terminal of the ferroelectric capacitor FA (corresponding to the node NA) and the first terminal of the ferroelectric capacitor FB (corresponding to the node NB).

[0132] At this time, the potential of the second terminal (corresponding to the wiring PL) of the ferroelectric capacitor FA is at a high level, so that dielectric polarization occurs in the ferroelectric material of the ferroelectric capacitor FA, and the direction of the dielectric polarization becomes negative.

[0133] Similarly, since the potential of the second terminal (corresponding to the wiring PL) of the ferroelectric capacitor FB is also at a high level potential, dielectric polarization also occurs within the ferroelectric of the ferroelectric capacitor FB, and the direction of this dielectric polarization becomes negative.

[0134] After dielectric polarization occurs in each of the ferroelectric capacitors FA and FB, a low level potential is applied to the line CNL21, and an intermediate potential is applied to the line PL.

[0135] Since a low-level potential is input to the wiring CNL21, the switches SWA1 and SWB1 included in the circuit SA are turned off.

[0136] Furthermore, since an intermediate potential is applied to the wiring PL, the voltage between the first terminal and the second terminal of each of the ferroelectric capacitors FA and FB becomes the potential difference between the intermediate potential and the low-level potential. Note that with this potential difference, the direction of the dielectric polarization in the ferroelectrics of each of the ferroelectric capacitors FA and FB remains negative.

[0137] By the above operation, the circuit BUY can initialize the data.

[0138] <<Between time T04 and time T05>> Between time T04 and time T05, as an example, an operation is performed to write the data held in the holding circuit FF to each of the ferroelectric capacitors FA and FB as a backup.

[0139] Specifically, from time T04 to time T05, a high-level potential is input to the wiring CNL1, and a low-level potential is input to the wiring PL.

[0140] Because a high-level potential is input to the wiring CNL1, the buffer circuits BA and BB included in the circuit BUX are each in an active state. As a result, the buffer circuit BA references a data signal (high-level potential) input to its input terminal (corresponding to terminal BO1A of the holding circuit FF) and outputs a data signal (high-level potential) to its output terminal (corresponding to node NA). The buffer circuit BB references a low-level potential input to its input terminal (corresponding to terminal BO1B of the holding circuit FF) and outputs a low-level potential to its output terminal (corresponding to node NB).

[0141] At this time, the potential of the first terminal (corresponding to the node NA) of the ferroelectric capacitor FA becomes high level potential, and the potential of the second terminal (corresponding to the wiring PL) of the ferroelectric capacitor FA becomes low level potential, so that the direction of polarization in the ferroelectric of the ferroelectric capacitor FA is reversed, and the direction of the dielectric polarization changes from negative to positive.

[0142] On the other hand, the potential of the first terminal (corresponding to node NB) of the ferroelectric capacitor FB becomes low level potential. Also, the potential of the second terminal (corresponding to wiring PL) of the ferroelectric capacitor FB becomes low level potential. In other words, the voltage between the first terminal and the second terminal of the ferroelectric capacitor FB becomes 0 V. At this time, the direction of the dielectric polarization in the ferroelectric of the ferroelectric capacitor FB remains negative.

[0143] By the above operation, the data held in the holding circuit FF can be backed up in the circuit BUY.

[0144] Furthermore, after the data output from terminals BO1A and BO1B are written as backups to ferroelectric capacitors FA and FB, respectively, a low-level potential is applied to wiring CNL21 and an intermediate potential is applied to wiring PL.

[0145] Because a low-level potential is input to the wiring CNL21, the buffer circuits BA and BB are both inactive. Therefore, the output terminal of the buffer circuit BA is in a high-impedance state regardless of the potential of the input terminal of the buffer circuit BA (corresponding to the terminal BO1A of the holding circuit FF). Similarly, the output terminal of the buffer circuit BB is in a high-impedance state regardless of the potential of the input terminal of the buffer circuit BB (corresponding to the terminal BO1B of the holding circuit FF).

[0146] Furthermore, since an intermediate potential is applied to the wiring PL, the voltage between the first terminal and the second terminal of each of the ferroelectric capacitors FA and FB is the potential difference between the intermediate potential and the low-level potential. Note that this potential difference does not change the direction of the dielectric polarization in the ferroelectrics of each of the ferroelectric capacitors FA and FB.

[0147] <<From Time T05 to Time T06>> From time T05 to time T06, as an example, an operation of stopping the supply of the power supply potential to the memory circuit NOM is performed.

[0148] Therefore, the potentials of the wirings SEL, SWL1, SWL2, CNL1, CNL21 to CNL23, and PL become unstable. Similarly, the potentials of the terminals DI, QO (terminal BO1A), and BO1B also become unstable.

[0149] <<From Time T06 to Time T07>> From time T06 to time T07, for example, the supply of the power supply potential to the memory circuit NOM is started again.

[0150] Specifically, between time T06 and time T07, a high-level potential is input to the wiring SEL, a low-level potential is input to the wiring SWL1, and a high-level potential is input to the wiring SWL2. A low-level potential is input to each of the wirings CNL1, CNL22, and CNL23. An intermediate potential is input to the wiring PL. An arbitrary data signal (a low-level potential is used as an example in FIG. 4 ) is input to the terminal DI.

[0151] For operations of the holding circuit FF, the circuit BUX, and the circuit BUY when potentials are input to the wirings, the description of the operations before time T01 can be referred to.

[0152] Furthermore, between time T06 and time T07, a high-level potential is input to the wiring CNL21, which turns on each of the switches SWA1 and SWB1 included in the circuit SA, and a low-level potential is applied from the wiring CVL to each of the first terminal of the ferroelectric capacitor FA (corresponding to the node NA) and the first terminal of the ferroelectric capacitor FB (corresponding to the node NB).

[0153] After the potentials of the nodes NA and NB are set to low level potentials, a low level potential is applied to the wiring CNL21, and the switches SWA1 and SWB1 are turned off, thereby causing the nodes NA and NB to be floating, and completing the precharging of the nodes NA and NB to low level potentials.

[0154] <<From Time T07 to Time T08>> From time T07 to time T08, as an example, an operation to read data held in the ferroelectric capacitor FA and the ferroelectric capacitor FB is performed.

[0155] Specifically, a high-level potential is input to the wiring PL between time T07 and time T08.

[0156] At this time, the potential of the first terminal (corresponding to the node NA) of the ferroelectric capacitor FA is at a low level potential, and the potential of the second terminal (corresponding to the wiring PL) of the ferroelectric capacitor FA is at a high level potential, so that the direction of the dielectric polarization in the ferroelectric of the ferroelectric capacitor FA changes from the positive direction to the negative direction.

[0157] Furthermore, a change in the direction of dielectric polarization within the ferroelectric of the ferroelectric capacitor FA causes a current to flow from the first terminal of the ferroelectric capacitor FA to the node NA. Specifically, when the direction of dielectric polarization within the ferroelectric of the ferroelectric capacitor FA is in the positive direction, a positive charge is accumulated in the first terminal of the ferroelectric capacitor FA, and a negative charge is accumulated in the second terminal of the ferroelectric capacitor FA. When the direction of dielectric polarization changes from the positive direction to the negative direction, a negative charge is accumulated in the first terminal of the ferroelectric capacitor FA, and a positive charge is accumulated in the second terminal of the ferroelectric capacitor FA. That is, when the direction of dielectric polarization within the ferroelectric of the ferroelectric capacitor FA changes as described above, the positive charge at the first terminal of the ferroelectric capacitor FA is released to the node NA, resulting in an increase in the potential of the node NA. Note that in FIG. 4, the potential of the node NA is denoted as Vrd, which exceeds the low-level potential and is less than the high-level potential.

[0158] Furthermore, the potential of the first terminal of the ferroelectric capacitor FB (corresponding to the node NB) is low level, and the potential of the second terminal of the ferroelectric capacitor FB (corresponding to the wiring PL) is high level. Therefore, the direction of the dielectric polarization in the ferroelectric of the ferroelectric capacitor FA remains negative. Therefore, unlike the node NA, the potential of the node NB remains low level.

[0159] Furthermore, as described above, when the direction of the dielectric polarization in each of the ferroelectrics of the ferroelectric capacitors FA and FB is negative, an intermediate potential is applied to the wiring PL. Note that even if an intermediate potential is applied to the wiring PL, the direction of the dielectric polarization in each of the ferroelectrics of the ferroelectric capacitors FA and FB does not change.

[0160] <<From Time T08 to Time T09>> From time T08 to time T09, as an example, an operation of amplifying the data read from the ferroelectric capacitor FA and the ferroelectric capacitor FB is performed.

[0161] Specifically, a high-level potential is input to the wiring CNL22 between time T08 and time T09.

[0162] Since a high-level potential is input to the wiring CNL22, the switches SWA2 and SWB2 included in the circuit SA are each turned on. As a result, the potentials of the nodes NA and NB are amplified by the inverters IVA and IVB. Here, since the potential of the node NA is Vrd and the potential of the node NB is low, the potential of the node NA rises to a high-level potential, while the potential of the node NB remains low. The potential of the node NA corresponds to the data held in the ferroelectric capacitor FA.

[0163] <<From Time T09 to Time T10>> From time T09 to time T10, as an example, an operation is performed in which the high-level potential of the node NA is input to the holding circuit FF.

[0164] Specifically, from time T09 to time T10, a low-level potential is input to the wiring SEL, and a high-level potential is input to the wiring CNL23.

[0165] Since a low-level potential is input to the line SEL, the selector SLC has a conductive state between the second input terminal and the output terminal, and a non-conductive state between the first input terminal and the output terminal. Also, since a high-level potential is input to the line CNL23, the switch SWA3 is turned on.

[0166] Therefore, the high-level potential of the node NA is input to the terminal BI1 via the switch SWA3 as a data signal to be written back to the holding circuit FF. The data signal (high-level potential) input to the terminal BI1 is also input to the input terminal of the inverter IV1 via the selector SLC. The inverter IV1 outputs a low-level potential from its output terminal as a signal in which the logic of the data signal is inverted. Since the switch SW1 is in the off state, the signal does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0167] <<From Time T10 to Time T11>> From time T10 to time T11, for example, the data signal input to the terminal BI1 is held in the holding circuit FF.

[0168] Specifically, from time T10 to time T11, a high-level potential is input to the wiring SWL1, and a low-level potential is input to the wiring SWL2.

[0169] Since a high-level potential is input to the wiring SWL1, the switch SW1 is turned on. Since a low-level potential is input to the wiring SWL2, the switch SW2 is turned off.

[0170] At this time, the data signal (high level potential) input to terminal BI1 is input to the input terminal of inverter IV2 via selector SLC, inverter IV1, and switch SW1. Since the logic of the data signal (high level potential) is inverted by inverters IV1 and IV2, a high level potential is output as a data signal from the output terminal of inverter IV2. In other words, a high level potential is output from terminal QO and terminal BO1A of holding circuit FF.

[0171] Furthermore, since the data signal (high level potential) from the output terminal of the inverter IV2 is input to the input terminal of the inverter IV3, a low level potential obtained by inverting the logic of the data signal (high level potential) is output from the output terminal of the inverter IV3. In other words, a low level potential is output from the terminal BO1B of the holding circuit FF.

[0172] Furthermore, between time T10 and time T11, after a high-level potential is output from terminal QO and terminal BO1A of holding circuit FF and a low-level potential is output from terminal BO1B of holding circuit FF, a low-level potential is input to wiring SWL1 and a high-level potential is input to wiring SWL2.

[0173] Since a low-level potential is input to the wiring SWL1, the switch SW1 is turned off. Since a high-level potential is input to the wiring SWL2, the switch SW2 is turned on.

[0174] Since the switch SW1 is in the off state, the data signal (high level potential) input to the terminal BI1, or more precisely, the signal (low level potential) with the logic of the data signal inverted and output from the output terminal of the inverter IV1, does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0175] Furthermore, because the switch SW2 is in the on state, conduction occurs between the input terminal of the inverter IV2 and the output terminal of the inverter IV3. In other words, because the signal is looped by the inverters IV2 and IV3, a high-level potential is held as a data signal at the output terminal of the inverter IV2 and the input terminal of the inverter IV3 (corresponding to the terminal QO and the terminal BO1A), and a low-level potential is held at the input terminal of the inverter IV2 and the output terminal of the inverter IV3 (corresponding to the terminal BO1B).

[0176] <<After Time T11>> After time T11, a low-level potential is input to each of the wirings CNL22 and CNL23.

[0177] Since a low-level potential is input to the wiring CNL21, the switches SWA2 and SWB2 are both turned off. Also, since a low-level potential is input to the wiring CNL22, the switch SWA3 is turned off.

[0178] This operation makes it possible to stop the transmission of the data signal for writing back data from the circuit BUY to the holding circuit FF.

[0179] The operation examples before time T01, from time T01 to time T11, and after time T11 described above enable data to be held in the holding circuit FF, the data to be backed up in the circuit BUY, and the data to be written back from the circuit BUY to the holding circuit FF.

[0180] Note that the operation method of the memory circuit of one embodiment of the present invention is not limited to the operation example of the timing chart in Figure 4. Specifically, in the timing chart described in this specification, wiring, operation, timing, and the like whose potentials fluctuate can be changed depending on the situation. For example, between time T03 and time T04, an operation is performed to orient the dielectric polarization in each of the ferroelectrics of the ferroelectric capacitor FA and the ferroelectric capacitor FB in the negative direction. However, this operation may be performed at any timing before time T04 (between time T04 and time T05, before the data held in the holding circuit FF is backed up).

[0181] <Cross-Sectional Configuration Example of Memory Circuit> Next, a cross-sectional configuration example of the memory circuit NOM will be described.

[0182] First, the positional relationship between the holding circuit FF, the circuit BUX, and the circuit BUY in the memory circuit NOM will be described. FIG. 5A is a schematic perspective view illustrating a configuration example of a memory circuit of one embodiment of the present invention. The memory circuit NOM includes a layer CIL and a layer FEL. Note that the layer FEL is provided above the layer CIL.

[0183] The layer CIL includes, for example, a holding circuit FF and a circuit BUX. The layer FEL includes, for example, a circuit BUY. To make the configuration of the memory circuit NOM easier to understand, the layer CIL and the layer FEL are shown separately in FIG. 5B.

[0184] By stacking the layer CIL, which has the holding circuit FF and the circuit BUX, and the layer FEL, which has the circuit BUY, the connection distance between them can be shortened, thereby increasing the communication speed between them.In addition, the short connection distance reduces power consumption.

[0185] As a method for stacking the layer CIL and the layer FEL, for example, a method of monolithically stacking the layer FEL directly on the layer CIL may be used. In this specification, such stacking may be referred to as monolithic stacking. Another method may be to form the layer CIL and the layer FEL on different substrates, bond the two substrates together, and connect them using a through-via or conductive film bonding technology (such as Cu-Cu bonding technology). In particular, the monolithic stacking method does not require consideration of misalignment during bonding, which not only reduces the chip size but also reduces manufacturing costs.

[0186] 5B shows an example in which a circuit BUX included in the layer CIL and a circuit BUY included in the layer FEL are connected by a conductive layer PG. The conductive layer PG functions as a wiring or a plug.

[0187] 6A illustrates a cross-sectional structure example of a memory circuit NOM according to one embodiment of the present invention. The memory circuit NOM illustrated in FIG. 6A includes a layer CIL and a layer FEL above the layer CIL, as in the structure of the memory circuit NOM illustrated in FIG.

[0188] 6A illustrates a transistor 400 included in the layer CIL. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating film, an insulating layer 317 formed on a side surface of the gate, a semiconductor region 313 including a part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 400 may be either a p-channel transistor or an n-channel transistor.

[0189] The substrate 311 may be, for example, a single-crystal silicon substrate as a semiconductor substrate. Alternatively, a single-crystal germanium substrate may be used as another substrate. Alternatively, a compound semiconductor substrate may be used. Examples of the compound semiconductor substrate include substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.

[0190] Here, in the transistor 400 shown in FIG. 6A , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that functions as a mask for forming the convex portion may be provided in contact with the top of the convex portion. Here, a case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (Silicon On Insulator) substrate.

[0191] Note that the transistor 400 illustrated in FIG. 6A is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0192] The layer CIL may be provided with a wiring layer provided with an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, wiring and a plug electrically connected to the wiring may be integrated. That is, there may be cases where a part of a conductor functions as a wiring, and there may be cases where a part of a conductor functions as a plug.

[0193] For example, an insulating layer 320, an insulating layer 301, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 301. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0194] For the conductive layer 328 and the conductive layer 330, a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a material applicable to contact plugs or wiring. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. Alternatively, for example, a material applicable to the conductor ME1 described later can be used as a material applicable to plugs or wiring.

[0195] Furthermore, it is preferable that the material of each contact plug or wiring contains a conductor having a barrier property against water or hydrogen. In particular, it is preferable that a conductive layer having a barrier property against water or hydrogen be formed on the side surfaces of the openings formed in the insulating layer 320, the insulating layer 301, the insulating layer 324, and the insulating layer 326.

[0196] Note that, for example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and tungsten, which has high conductivity, it is possible to suppress diffusion of hydrogen while maintaining the conductivity of the wiring. In this case, a structure in which a tantalum nitride layer having a barrier property against hydrogen is in contact with the insulating layer 320, the insulating layer 301, the insulating layer 324, and the insulating layer 326 is preferable.

[0197] The insulating layer 320, the insulating layer 301, and the insulating layer 326 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0198] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0199] Furthermore, an insulating film that functions as an interlayer film may also function as a planarizing film that covers uneven shapes underneath. In particular, the insulating layer 301 may function as a planarizing film that planarizes steps caused by the transistor 400 or the like that are covered with the insulating layer 320. For example, the top surface of the insulating layer 301 may be planarized by planarization treatment using chemical mechanical polishing (CMP) to improve planarity.

[0200] The insulating layer 324 is preferably a film having a barrier property that prevents impurities such as water or hydrogen from diffusing from the substrate 311 or the transistor 400 to an upper region including the layer FEL.

[0201] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. In particular, for example, when a semiconductor element having an oxide semiconductor is formed in an upper region including the layer FEL, the characteristics of the semiconductor element may be degraded due to diffusion of hydrogen into the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the semiconductor element and the transistor 400. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0202] The insulating layer 326 preferably has a lower dielectric constant than the insulating layer 324. For example, the relative dielectric constant of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings.

[0203] 6, the conductive layer 330, which is electrically connected to the gate, source, and drain of the transistor 400, functions as a wiring included in the wiring layer.

[0204] An insulating layer 350, an insulating layer 357, an insulating layer 352, an insulating layer 353, and an insulating layer 354 are stacked in this order on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed on the insulating layer 350, the insulating layer 357, and the insulating layer 352, and a conductive layer 358 is formed on the insulating layer 353 and the insulating layer 354. The conductive layer 356 and the conductive layer 358 function as contact plugs or wirings. For example, the transistor 400 is electrically connected to one of a pair of electrodes of the ferroelectric capacitor FA (ferroelectric capacitor FB) of the layer FEL via the conductive layer 358, the conductive layer 356, the conductive layer 330, and the like. Note that although FIG. 6A illustrates a configuration in which the transistor 400 is electrically connected to the conductive layer 328, the transistor 400 may also be electrically connected to another wiring.

[0205] For the insulating layer 350 and the insulating layer 353, a film having a barrier property against hydrogen, like the insulating layer 324, is preferably used.

[0206] For the insulating layer 357 and the insulating layer 352, similarly to the insulating layer 326, it is preferable to use an insulator with a relatively low relative dielectric constant in order to reduce parasitic capacitance occurring between wirings.

[0207] The conductive layers 356 and 358 can be formed using, for example, a material similar to that of the conductive layers 328 and 330 which function as contact plugs or wirings.

[0208] For example, the insulating layer 354 functions as a base film for forming the ferroelectric capacitor FA (ferroelectric capacitor FB) thereon. In addition, since the holding circuit FF, the circuit BUX, etc. are located below the insulating layer 354, the insulating layer 354 functions as an interlayer film that separates these circuits, etc. from the circuit BUY including the ferroelectric capacitor FA (ferroelectric capacitor FB).

[0209] The insulating layer 354 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 354 can be formed using, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating. Alternatively, the insulating layer 354 can be formed using, for example, a resin. The insulating layer 353 can be formed using an appropriate combination of the above-mentioned insulating materials. The insulating layer 354 can be formed using a single layer or a stacked structure obtained by sequentially depositing two or more insulating materials.

[0210] Furthermore, it is preferable to use an insulating material with a low relative dielectric constant for the insulating layer 354. By using an insulating material with a low relative dielectric constant as an interlayer film, it is possible to reduce parasitic capacitance that occurs between wirings. Specifically, for example, the relative dielectric constant of the insulating layer 354 is preferably less than 4, and more preferably less than 3. Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.

[0211] As described above, the insulating layer 354 may be a single layer or may have a stacked structure obtained by sequentially depositing two or more layers of insulating materials. When the insulating layer 354 has two or more layers of insulating materials, at least one of the layers may be a barrier insulating film.

[0212] In order to prevent oxidation of the conductive layer 358, the conductive layer ME1, etc., it is preferable to use an insulating material for the barrier insulating film that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., the oxygen is less likely to permeate).

[0213] <<Configuration Example of Layer FEL>> Next, the layer FEL will be described.

[0214] 6A, the layer FEL has the circuit BUY shown in Figures 1, 3, and 5. Specifically, the layer FEL includes the ferroelectric capacitor FA (ferroelectric capacitor FB) of the circuit BUY.

[0215] The layer FEL has a conductive layer ME1, a conductive layer ME2, a conductive layer ME3, an insulating layer IS1, an insulating layer IS2, and an insulating layer FD for forming the ferroelectric capacitor FA (ferroelectric capacitor FB).

[0216] The conductive layer ME1 has a region in contact with the upper surface of the insulating layer 354 and the upper surface of the conductive layer 358 embedded in the insulating layer 354. Note that the conductive layer ME1 functions as wiring for applying an electric signal (for example, a potential) to the conductive layer ME2 described later, as an example.

[0217] The conductive layer ME1 is preferably made of, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements. Alternatively, the conductive layer ME1 is preferably made of, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0218] Furthermore, the conductive layer ME1 can be made of a material that can be used for the conductive layer 328 or the conductive layer 356 described above.

[0219] Furthermore, a plurality of conductive films formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0220] For example, the conductive layer ME1 may have a first conductor and a second conductor surrounded by the first conductor. For example, the first conductor may be made of a conductive material that has the function of suppressing oxygen diffusion, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and the second conductor may be made of a conductive material that is mainly composed of highly conductive tungsten, copper, or aluminum. By surrounding the second conductor with the first conductor, it is possible to prevent the conductivity of the first conductor from decreasing due to oxidation.

[0221] The insulating layer IS1 has regions in contact with the upper surface of the insulating layer 354 and the upper surface of the conductive layer ME1. In other words, the insulating layer IS1 is located above the insulating layer 354 and the conductive layer ME1. As an example, the insulating layer IS1 functions as an interlayer film separating the conductive layer ME1 and the conductive layer ME3. By providing the insulating layer IS1, it is possible to prevent the conductive layers ME1 and ME3 from directly contacting each other and causing a short circuit. Furthermore, the insulating layer IS1 has an opening KK1 in a region overlapping a portion of the conductive layer ME1.

[0222] The insulating layer IS1 preferably has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For this reason, the insulating layer IS1 formed on the insulating layer 353 and the conductive layer ME1 can be made of, for example, a material that can be used for the insulating layer 353.

[0223] 6A , the opening KK1 has a tapered shape with a taper angle that is approximately perpendicular (60° or more and 120° or less) to the substrate 311 or the conductive layer ME1, for example. Alternatively, the opening KK1 may have a tapered shape with a taper angle that is 30° or more and less than 60°, or a taper angle that is greater than 0° and less than 30°, for example, to the substrate 311 or the conductive layer ME1.

[0224] In this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is inclined with respect to the substrate surface. The angle between the inclined side surface and the substrate surface is referred to as a taper angle. In particular, in this specification and the like, a tapered shape having a taper angle greater than 0° and equal to or less than 90° is referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is referred to as a reverse taper shape.

[0225] The conductive layer ME2 has a region in contact with the side surface of the insulating layer IS1 corresponding to the side surface of the opening KK1 and the upper surface of the conductive layer ME1 corresponding to the bottom of the opening KK1.

[0226] That is, the conductive layer ME2 is formed on the bottom and inner side surfaces of the opening KK1. The conductive layer ME2 can be formed using a film formation method such as sputtering, CVD, MBE, PLD, or ALD. In particular, as shown in FIG. 6A , the conductive layer ME2 must be formed with good coverage on the bottom and inner side surfaces of the opening KK1, so it is preferable to form it using the ALD method. The ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. By using the ALD method, atomic layers can be deposited one by one on the bottom and inner side surfaces of the opening KK1, so the conductive film can be formed with good coverage on the bottom and side surfaces of the opening KK1.

[0227] When the taper angle of the side surface of the opening KK1 is less than 90°, the method for forming the conductive layer ME2 is not limited to the ALD method, and for example, a sputtering method can be used. The sputtering method can achieve a faster film formation rate than the ALD method, and therefore can shorten the takt time of the memory circuit.

[0228] The conductive layer ME2 can be made of, for example, a material that can be used for the conductive layer ME1. The conductive layer ME2 may also have, for example, a laminated structure including multiple conductive layers. For example, the conductive layer ME2 may have a first conductor that has the function of suppressing oxygen diffusion and a second conductor that has high conductivity. By having the conductive layer ME2 have a laminated structure in which the second conductor is surrounded by the first conductor, it is possible to prevent a decrease in the conductivity of the first conductor. Regarding the laminated structure, the first conductor, and the second conductor, the description of the conductive layer ME1 described above when it has a laminated structure can be referenced.

[0229] The insulating layer FD has a region in contact with the upper surface of the conductive layer ME2. In particular, it is more preferable that the insulating layer FD has a region in contact with the side surface of the conductor ME2 and the upper surface of the insulating layer IS1. By having the insulating layer FD have a region in contact with the side surface of the conductor ME2 and the insulating layer IS1, it is possible to prevent the conductive layer ME2 and a conductive layer ME3 (described later) from coming into direct contact with each other (short-circuiting).

[0230] The insulating layer FD is preferably made of, for example, a material that can have ferroelectricity. Here, the material that can have ferroelectricity refers to a material that, unlike a paraelectric material, maintains its internal dielectric polarization even when a voltage of 0 V is applied (sometimes called remanent polarization).

[0231] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (X is a real number greater than 0), materials in which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, and materials in which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. Furthermore, examples of materials that may have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of multiple materials selected from the materials listed above may be used. Incidentally, the crystal structure (characteristics) of hafnium oxide, zirconium oxide, zirconium hafnium oxide, and materials obtained by adding element J1 to hafnium oxide may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification and the like, the term "ferroelectric" refers not only to materials that exhibit ferroelectricity, but also to materials that can exhibit ferroelectricity or that are made to exhibit ferroelectricity.

[0232] Here, consider a case where an oxide containing hafnium and zirconium is used as a material that can have ferroelectricity. In this case, the insulating layer FD has a space group of Pca2 １ It is preferable that the insulating layer FD contains crystals having an orthorhombic crystal structure, where the crystals are ferroelectric. When the insulating layer FD contains such crystals, ferroelectricity is exhibited. Furthermore, by increasing the proportion of crystals having an orthorhombic crystal structure in the insulating layer FD, the amount of remanent polarization can be increased.

[0233] In an oxide containing hafnium and zirconium, oxygen deficiency (V Ｏ The higher the concentration of hafnium (also referred to as oxygen vacancy), the more likely it is that crystals having an orthorhombic crystal structure will be produced. Therefore, it is preferable to add a Group 3 element (sometimes simply referred to as a Group 3 element) in the periodic table to an oxide containing hafnium and zirconium. The Group 3 element to be added is preferably one or more selected from scandium, lanthanum, and yttrium, more preferably one or both of lanthanum and yttrium, and even more preferably yttrium.

[0234] In oxides containing hafnium and zirconium, hafnium and zirconium tend to have a valence of +4. On the other hand, in oxides containing a Group 3 element, the Group 3 element tends to have a valence of +3. Therefore, by adding an element with a valence different from that of hafnium and zirconium to an oxide containing one or both of hafnium and zirconium, the concentration of oxygen vacancies in the oxide can be increased.

[0235] However, if the amount of Group 3 element added to the oxide containing hafnium and zirconium is too large, the crystallinity of the oxide may be reduced, which may affect the expression of ferroelectricity. Therefore, the content of the Group 3 element added to the oxide containing hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the numbers of atoms of all metal elements contained in the ferroelectric. By adding the Group 3 element to the oxide in the above range, it is possible to achieve improved remanent polarization, high breakdown voltage, and reduced leakage current.

[0236] For example, the atomic ratio of the sum of hafnium (Hf) and zirconium (Zr) to the Group 3 element (J3) can be Hf + Zr:J3 = 100 - x:x (x is a real number between 0.1 and 10), or a composition close to this. The element J3 is one or more elements selected from scandium (Sc), lanthanum (La), and yttrium (Y). The "close composition" includes a range of ±30% of the desired atomic ratio. Specific examples of atomic ratios of hafnium (Hf) and zirconium (Zr) to the Group 3 element (J3) include Hf + Zr:J3 = 99.5:0.5, Hf + Zr:J3 = 99:1, Hf + Zr:J3 = 98:2, Hf + Zr:J3 = 95:5, and Hf + Zr:J3 = 90:10.

[0237] Furthermore, in an oxide containing hafnium and zirconium to which a Group 3 element has been added, the atomic ratio of hafnium (Hf) to zirconium (Zr) can be Hf:Zr = 1:1 or a composition close to this. The term "nearby composition" includes a range of ±30% of the desired atomic ratio. Taking into account the nearby composition, the ratio can be expressed as Hf:Zr = 1 + y: 1 - y (where y is a real number between -0.3 and 0.3).

[0238] Therefore, when the Group 3 element (J3) is also taken into consideration, the atomic ratio of hafnium (Hf), zirconium (Zr), and the Group 3 element (J3) can be, for example, Hf:Zr:J3 = 43:55:2, Hf:Zr:J3 = 46:52:2, Hf:Zr:J3 = 49:49:2, Hf:Zr:J3 = 52:46:2, Hf:Zr:J3 = 55:43:2, or a composition close to these.

[0239] After the insulating layer FD is formed, it is preferable to perform a heat treatment. For example, a rapid thermal annealing (RTA) apparatus, a resistance heating furnace, or a microwave heating apparatus can be used for the heat treatment. In particular, using an RTA apparatus is preferable because it may improve the ferroelectricity of the insulating layer FD. Examples of the RTA apparatus that can be used include a lamp rapid thermal annealing (LRTA) apparatus and a gas rapid thermal annealing (GRTA) apparatus. The LRTA apparatus heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus performs heat treatment using high-temperature gas. The gas used is an inert gas such as a noble gas like argon or nitrogen that does not react with the workpiece during heat treatment. Note that the method of performing heat treatment using an LRTA apparatus is sometimes called the lamp-assisted RTA method or the LRTA method.

[0240] Furthermore, when the RTA method is used for the heat treatment, the treatment temperature is preferably 400°C or higher and 700°C or lower, more preferably 400°C or higher and 600°C or lower, and even more preferably 400°C or higher and 500°C or lower. In particular, by adding a Group 3 element to an oxide containing hafnium and zirconium, it may be possible to lower the temperature required for the heat treatment compared to when no Group 3 element is added. Furthermore, the treatment time is preferably 5 seconds to 1 hour, more preferably 5 seconds to 5 minutes, and even more preferably 1 minute to 5 minutes.

[0241] As described above, for example, by using an oxide containing hafnium and zirconium and a Group 3 element as the insulating layer FD, a ferroelectric capacitor can be fabricated by heat treatment at a relatively low temperature.

[0242] Furthermore, since the ferroelectric capacitors can be fabricated by a heat treatment at a relatively low temperature, for example, when the ferroelectric capacitors FA and ferroelectric capacitors FB are fabricated above the layer CIL as shown in Figures 5A, 5B, and 6A, the influence of the heat treatment on circuit elements such as transistors included in the layer CIL can be reduced.

[0243] Therefore, by using an oxide containing hafnium, zirconium, and a Group 3 element as the ferroelectric of each of the ferroelectric capacitors FA and FB of the layer FEL, the layer FEL can be formed, for example, above a circuit including transistors and the like on a semiconductor substrate having silicon.

[0244] Furthermore, by using an oxide containing hafnium, an oxide containing hafnium and zirconium, or an oxide containing hafnium, zirconium, and a Group 3 element, it is possible to obtain ferroelectricity even in a thin film of a few nm or a few tens of nm, and therefore these materials may be used as the ferroelectric of a ferroelectric capacitor. For example, the film thickness of each of the oxides listed above can be 3 nm to 100 nm, preferably 3 nm to 50 nm, more preferably 3 nm to 20 nm, and even more preferably 4 nm to 10 nm.

[0245] The conductive layer ME3 has a region in contact with the upper surface of the insulating layer FD. Specifically, the conductive layer ME3 has a region above the insulating layer FD that overlaps with the conductive layer ME2. Also, Fig. 6A shows a configuration example in which the opening KK1 is filled with the conductor ME3.

[0246] In particular, it is preferable that the end of the conductive layer ME3 contacts the upper surface of the insulating layer FD. It is also preferable that the conductive layer ME3 has an area that overlaps with the conductive layer ME2. By positioning the end of the conductive layer ME3 above the conductive layer ME2, for example, it is possible to reduce the area where the conductive layer ME3 overlaps with conductive layers other than the conductive layer ME2, and therefore it is possible to reduce the influence of parasitic capacitance formed between the conductive layer ME3 and conductive layers other than the conductive layer ME2.

[0247] For example, the conductive layer ME3 may be made of a material that can be used for the conductive layer ME1. The conductive layer ME3 may also have a laminated structure including multiple conductive layers. For the laminated structure of the conductive layers, the description of the conductive layer ME1 described above can be referenced.

[0248] An insulating layer IS2 is stacked above the insulating layer IS1, the insulating layer FD, and the conductive layer ME3. The insulating layer IS2 functions, for example, as a barrier insulating film that prevents the diffusion of impurities into the conductive layer ME3. Examples of such impurities include oxygen. By forming the insulating layer IS2 as a barrier insulating film that suppresses the diffusion of impurities such as oxygen, such that the insulating layer IS2 has a region that contacts the upper surface of the conductive layer ME3, it is possible to prevent a decrease in the conductivity of the conductive layer ME3 due to oxidation. Therefore, for example, the insulating layer IS2 can be made of a material that can be used for the insulating layer 324 that functions as a barrier insulating film.

[0249] Furthermore, the insulating layer IS2 may be made of an insulating material with a low relative dielectric constant in order to reduce parasitic capacitance between wirings. In this case, the insulating layer IS2 may be made of a material that can be used for the insulating layer IS1.

[0250] As shown in Figures 5A, 5B, and 6A, the memory circuit NOM shown in Figure 1 can be fabricated by providing a holding circuit FF and a circuit BUX in the layer CIL and providing a circuit BUY in the layer FEL located above the layer CIL.

[0251] Note that the cross-sectional structure of the memory circuit of one embodiment of the present invention is not limited to the schematic cross-sectional view shown in Figure 6A. For example, the memory circuit of one embodiment of the present invention may have a structure in which a plurality of FEL layers are stacked.

[0252] 6B shows a schematic cross-sectional view of a memory circuit NOM in which two layers FEL, layers FEL_1 and FEL_2, are stacked in this order above a layer CIL. Each of the layers FEL_1 and FEL_2 has a ferroelectric capacitor FA (ferroelectric capacitor FB), similar to the layer FEL shown in FIG.

[0253] Furthermore, openings in which contact plugs or wiring are embedded are provided in the insulating layers IS1, IS2, and FD included in the layer FEL1. Fig. 6B shows a configuration example in which conductive layers PG1 and PG2 are embedded in the openings. The conductive layers PG1 and PG2 function as contact plugs or wiring that connect the circuit elements included in the layer CIL and the ferroelectric capacitor FA (ferroelectric capacitor FB) included in the layer FEL_2.

[0254] Note that the conductive layers PG1 and PG2 can be formed using a material similar to that of the conductive layer 356, the conductive layer 358, the conductive layer 328, or the conductive layer 330, which functions as a contact plug or a wiring, for example.

[0255] 6B as the configuration of the memory circuit NOM, it is possible to provide many ferroelectric capacitors in the memory circuit NOM. In other words, it is possible to increase the storage capacity of the circuit BUY of the memory circuit NOM. Furthermore, compared to the cross-sectional configuration example of FIG. 6A, the number of ferroelectric capacitors included in one layer FEL is reduced, and therefore the area where a pair of electrodes of the ferroelectric capacitors overlap can be increased accordingly, thereby increasing the capacitance value of the ferroelectric capacitor.

[0256] For the insulating layers, conductive layers, and the like included in each of the layers FEL_1 and FEL_2, the description of the layer FEL shown in FIG. 6A can be referred to.

[0257] Further, for example, the memory circuit of one embodiment of the present invention may have a structure in which the substrate 311 included in the layer CIL and the substrate included in the layer FEL are bonded to each other.

[0258] Specifically, flip-chip bonding may be used as a method for bonding the substrate 311 included in the layer CIL and the substrate included in the layer FEL. When using flip-chip bonding, connection terminals such as bumps may be provided above or below the substrate 311, and the substrate included in the layer FEL may be bonded to the substrate. In particular, when bumps are provided below the substrate, through electrodes may be provided in the substrate 311 using TSV (Through Silicon Via) technology, and bumps may be provided on the through electrodes. Examples of flip-chip bonding include a method of injecting a resin containing anisotropic conductive particles between the connection terminals of the substrate 311 included in the layer CIL and the substrate included in the layer FEL, and a method of bonding using SnAg solder. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in addition to the above flip-chip bonding method, an underfill agent may be used to reduce physical stress such as impact, thermal stress, etc. Furthermore, for example, a die bonding film may be used to bond the substrate 311 included in the layer CIL and the substrate included in the layer FEL together.

[0259] Furthermore, a hybrid bonding method, such as Cu-Cu (copper-copper) bonding, may be used as a method for bonding the substrate 311 included in the layer CIL and the substrate BS included in the layer FEL. Figure 7 shows an example of the cross-sectional configuration of a memory circuit NOM in which the upper part of the substrate 311 included in the layer CIL and the upper part of the substrate BS included in the layer FEL are bonded together by hybrid bonding.

[0260] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). In addition to semiconductor substrates, other substrates that can be used include, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. When the manufacturing method includes a heat treatment, it is preferable to select a substrate with high heat resistance. Alternatively, a circuit element may be provided on one of these substrates. Examples of the circuit element include a capacitance element, a resistance element, a switching element, a light-emitting element, and a memory element.

[0261] 7 , an insulating layer 385 is provided over the insulating layer 354 and the conductive layer 358. An opening overlapping the conductive layer 358 is provided in the insulating layer 385, and a conductive layer 386 is provided to fill the opening. An insulating layer 387 is provided over the insulating layer 385 and the conductive layer 386. An opening overlapping the conductive layer 386 is provided in the insulating layer 387, and a conductive layer 388 is provided to fill the opening.

[0262] The insulating layer 385 can be formed using, for example, a material that can be used for the insulating layer 354. The conductive layer 386 can be formed using a material that can be used for the conductive layer 358.

[0263] 7, an opening is provided in the insulating layer IS2 in a region overlapping with the conductive layer ME3, and a conductive layer MEN1 is provided to fill the opening. An insulating layer ISN is provided on the insulating layer IS2 and the conductive layer MEN1. An opening is provided in the insulating layer ISN that overlaps with the conductive layer MEN1, and a conductive layer MEN2 is provided to fill the opening. An insulating layer BN is provided on the insulating layer ISN and the conductive layer MEN2. An opening is provided in the insulating layer BN that overlaps with the conductive layer MEN2, and a conductive layer BM is provided to fill the opening.

[0264] For example, the insulating layer ISN may be made of a material that can be used for the insulating layer IS2. For the conductive layer MEN1 or MEN2, the material that can be used for the conductive layer ME3 may be used.

[0265] 7, for example, the insulating layer 387 functions as a bonding layer together with the insulating layer BN. The insulating layer 387 is preferably made of the same material as the insulating layer BN. Similarly, the conductive layer 388 functions as a bonding layer together with the conductive layer BM. The conductive layer 388 is preferably made of the same material as the conductive layer BM.

[0266] Specifically, it is preferable to use, for example, silicon oxide, silicon nitride, etc. for the insulating layer 387 and the insulating layer BN. Alternatively, a polymer material may be used.

[0267] Specifically, it is preferable to use copper, for example, for the conductive layer 388 and the conductive layer BM. Alternatively, aluminum, tin, zinc, tungsten, silver, platinum, gold, or the like may be used instead of copper.

[0268] As a pre-process before the bonding process, for example, a planarization process is performed on the layer CIL side to make the surfaces of the insulating layer 387 and the conductive layer 388 level, and similarly, a planarization process is performed on the layer FEL side to make the surfaces of the insulating layer BN and the conductive layer BM level.

[0269] In the bonding process, when bonding the insulating layer 387 and the insulating layer BN, that is, bonding between insulating layers, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydration through heat treatment.Hydrophilic bonding also produces bonds at the atomic level, so mechanically excellent bonding can be obtained.

[0270] Furthermore, when bonding the conductive layer 388 and the conductive layer BM, i.e., bonding between conductors, a surface activation bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or the like, and cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. In either case, bonding occurs at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0271] By performing the above-described bonding process, the conductive layer 388 on the CIL side can be brought into contact with the conductive layer BM on the FEL side, and a connection having sufficient mechanical strength can be obtained between the insulating layer 387 on the CIL side and the insulating layer BN on the FEL side.

[0272] When bonding the CIL layer and the FEL layer, since the bonding surfaces of the layers contain both insulating and metal layers, a surface activation bonding method and a hydrophilic bonding method may be combined. For example, a method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment.

[0273] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0274] Embodiment 2 In this embodiment, a structure in which a circuit including an OS transistor is provided in the memory circuit NOM described in the above embodiment will be described.

[0275] 8 is a modified example of the memory circuit NOM of FIG. 1 described in embodiment 1, and differs in configuration from the memory circuit NOM of FIG. 1 in that it includes a circuit BUZ. Therefore, in this embodiment, the memory circuit NOMA of FIG. 8 will be described in terms of parts that are different from the memory circuit NOM of FIG. 1, and descriptions of overlapping parts may be omitted.

[0276] 8 is provided with terminals BI2 and BO2 in addition to the holding circuit FF shown in FIG. 1. Like the terminals DI and BI1, the terminal BI2 receives data to be held in the holding circuit FF. Like the terminals QO and BO1A, the terminal BO2 outputs the data held in the holding circuit FF.

[0277] The memory circuit NOMA in FIG. 8 includes a circuit BUZ as a memory including an OS transistor, in addition to a circuit BUX and a circuit BUY.

[0278] The circuit BUZ includes, for example, a transistor MI, a transistor MO, and a capacitor CO. In particular, it is preferable to use, for example, OS transistors as the transistor MI and the transistor MO. In particular, it is preferable to use, for example, an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony) as the metal oxide included in the channel formation region of the OS transistor.

[0279] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the metal oxide used for the semiconductor layer. By using an oxide containing indium, gallium, and zinc as the metal oxide contained in the channel formation region of an OS transistor, the amount of off-state current flowing between the source and drain in a normally-off state (e.g., when no potential is applied to the gate, when a ground potential is applied to the gate, or when the gate-source voltage is 0 V) ​​can be made extremely small. For example, the current flowing through a transistor per 1 μm of channel width in a normally-off state is 1×10 at room temperature. −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ It will be A or below.

[0280] As the metal oxide used for the semiconductor layer, it is preferable to use an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)). Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO).

[0281] Furthermore, it is preferable that the metal oxide used in the semiconductor layer has crystallinity. For example, a metal oxide having a CAAC (c-axis aligned crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used in the semiconductor layer. By using a crystalline metal oxide layer in the semiconductor layer, the defect level density in the semiconductor layer can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. The CAAC structure allows for more clearly visible crystal grain boundaries and grains in the a-b plane than the polycrystalline structure, thereby realizing a highly reliable memory circuit.

[0282] Furthermore, as long as the off-state current of each of the transistors MI and MO can be extremely small, transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors) may be used as the transistors MI and MO. The silicon may be, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon. Examples of transistors other than OS transistors and Si transistors include a transistor containing germanium (Ge) or the like in its channel formation region, a transistor containing a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe) in its channel formation region, a transistor containing a carbon nanotube in its channel formation region, or a transistor containing an organic semiconductor in its channel formation region.

[0283] In the following description, the transistors MI and MO will be described as OS transistors.

[0284] The first terminal of the transistor MI is electrically connected to the terminal BO2 of the holding circuit FF, the second terminal of the transistor MI is electrically connected to the first terminal of the transistor MO and the first terminal of the capacitor CO, and the gate of the transistor MI is electrically connected to the wiring CNL3. The second terminal of the transistor MO is electrically connected to the terminal BI2, and the gate of the transistor MO is electrically connected to the wiring CNL4. The second terminal of the capacitor CO is electrically connected to the wiring CVLA. In particular, in FIG. 8 , a region where charges can be conducted between the second terminal of the transistor MI, the first terminal of the transistor MO, and the first terminal of the capacitor CO is illustrated as a node NC.

[0285] Note that the transistors MI and MO in the circuit BUZ each function as a switching element. Therefore, the wiring CNL3 functions as a wiring that transmits a signal for switching the transistor MI to an on state or an off state. Similarly, the wiring CNL4 functions as a wiring that transmits a signal for switching the transistor MO to an on state or an off state.

[0286] 3, the wiring CVLA functions as a wiring for applying a fixed potential. The fixed potential is preferably, for example, a low-level potential. Other than the low-level potential, the wiring CVLA may be, for example, a high-level potential, a ground potential, or a negative potential. The potentials applied to the wiring CVL and the wiring CVLA may be the same potential. In this case, the wiring CVL and the wiring CVLA may be the same wiring.

[0287] As described above, the circuit BUZ is a memory that uses an OS transistor and a capacitor CO. The circuit BUZ is configured so that data can be written by storing charge in the capacitor CO and data can be read by discharging the stored charge. The write and read speeds of the memory (circuit BUZ) that uses OS transistors are faster than those of the circuits BUX and BUY that use ferroelectric capacitors. Furthermore, because the memory (circuit BUZ) that uses OS transistors does not require a buffer circuit or a read circuit like the circuit BUX, the power consumption required for writing and reading in the circuit BUZ is lower than that of the circuits BUX and BUY that use ferroelectric capacitors.

[0288] On the other hand, because circuit BUZ retains data using transistors, even if the off-current of the transistors is low, the longer the retention time, the more the data deteriorates.In contrast, circuits BUX and BUY, which use ferroelectric capacitors, retain their dielectric polarization for a very long time, so when comparing data retention times, circuits BUX and BUY are longer than circuit BUZ.

[0289] Therefore, when it is desired to reduce power consumption, the holding circuit FF can be backed up using a memory (circuit BUZ) that uses an OS transistor and a capacitive element CO, and when it is desired to retain the backup data for a long period of time, the holding circuit FF can be backed up using circuits BUX and BUY that use ferroelectric capacitors.

[0290] <<Configuration Example of Holding Circuit FF>> Next, a circuit configuration example of the holding circuit FF shown in FIG. 8 will be described.

[0291] The holding circuit FF shown in Fig. 9 is an example of a circuit configuration that can be applied to the holding circuit FF of Fig. 8, and is also a modified example of the holding circuit FF of Fig. 2. The holding circuit FF of Fig. 9 differs from the holding circuit FF of Fig. 2 in that the selector SLC is replaced by a selector SLCA and in that terminals BI2 and BO2 are added.

[0292] The selector SLCA has, for example, a first input terminal, a second input terminal, a third input terminal, an output terminal, and a control terminal.

[0293] As an example, the selector SLCA has a function of establishing a conductive state between one selected from the first to third input terminals and the output terminal, and establishing a non-conductive state between each of the remaining two input terminals and the output terminal. In addition, the selector SLCA selects one of the first to third input terminals that is conductive with the output terminal and the remaining two that are non-conductive with the output terminal, according to a digital signal (sometimes called a control signal) input to the control terminal.

[0294] In this specification, when a digital signal "1" is input to the control terminal of the selector SLCA, the selector SLCA brings the first input terminal and the output terminal into a conductive state and brings the second and third input terminals into a non-conductive state and the output terminal, respectively. When a digital signal "2" is input to the control terminal of the selector SLCA, the selector SLCA brings the second input terminal and the output terminal into a conductive state and brings the first and third input terminals into a non-conductive state and the output terminal, respectively. When a digital signal "3" is input to the control terminal of the selector SLCA, the selector SLCA brings the third input terminal and the output terminal into a conductive state and brings the first and second input terminals into a non-conductive state and the output terminal, respectively.

[0295] In this case, the wiring SEL for transmitting digital signals is preferably a data bus wiring for transmitting digital signals.

[0296] The first input terminal of the selector SLCA is electrically connected to the terminal DI, the second input terminal of the selector SLCA is electrically connected to the terminal BI1, the third input terminal of the selector SLCA is electrically connected to the terminal BI2, and the output terminal of the selector SLCA is electrically connected to the input terminal of the inverter IV1. The output terminal of the inverter IV2 is electrically connected to the terminal QO, the terminal BO1A, the terminal BO2, and the input terminal of the inverter IV3.

[0297] The control terminal of the selector SLCA is electrically connected to the wiring SEL, which, as an example, functions as a wiring for transmitting a digital signal (control signal) as described above.

[0298] <Operation Example of Memory Circuit> Next, an operation example of the memory circuit NOMA shown in FIG. 8 will be described.

[0299] In the description of this operation example, it is assumed that the holding circuit FF included in the memory circuit NOMA is the holding circuit FF shown in Fig. 9. It is also assumed that the circuit BUX included in the memory circuit NOMA is the circuit BUX shown in Fig. 3.

[0300] 10 is a timing chart illustrating an operation example of the memory circuit NOMA. The timing chart in FIG. 10 illustrates changes in the value of digital data applied to the wiring SEL and the potentials of the wirings SWL1, SWL2, CNL1, CNL3, CNL4, CNL23, the terminal DI, the terminal QO (terminal BO1A or BO1B), the node NC, and the terminal BI2 before time T21, from time T21 to time T27, and after time T27.

[0301] In the timing chart of FIG. 10, hatched periods indicate periods in which the potential is unstable.

[0302] In this operation example, the fixed potential applied by the wiring CVLA is a low-level potential.

[0303] In this operation example, between time T21 and time T22, the hold circuit FF holds the data input to the terminal DI. Between time T23 and time T24, the data held in the hold circuit FF is backed up to the circuit BUZ. Between time T25 and time T27, as an example, the backed up data is written back from the circuit BUZ to the hold circuit FF. These operations are described below.

[0304] <<Before Time T21>> Before time T21, for example, a digital signal value of "1" is input to the wiring SEL, a low-level potential (denoted as "Low" in FIG. 10) is input to the wiring SWL1, and a high-level potential (denoted as "High" in FIG. 10) is input to the wiring SWL2. A low-level potential is input to each of the wirings CNL1, CNL3, and CNL4. An arbitrary data signal (denoted as a high-level potential in FIG. 4, for example) is input to the terminal DI as data to be stored in the memory circuit NOMA.

[0305] Since the value "1" is input to the line SEL, in the selector SLCA, the first input terminal and the output terminal are in a conductive state, and the second input terminal and the third input terminal are in a non-conductive state, respectively, and since a low-level potential is input to the line SWL1, the switch SW1 is in an off state. Furthermore, since a high-level potential is input to the line SWL2, the switch SW2 is in an on state.

[0306] Therefore, the data signal (high-level potential) input to the terminal DI is input to the input terminal of the inverter IV1. The inverter IV1 outputs a low-level potential from its output terminal as a signal with the logic of the data signal inverted. Note that, because the switch SW1 is in the off state, the signal does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0307] Furthermore, because switch SW2 is in the on state, conduction occurs between the input terminal of inverter IV2 and the output terminal of inverter IV3. In other words, a signal can be looped by inverters IV2 and IV3. Note that before time T21, the potentials of the output terminal of inverter IV2 (corresponding to terminal QO and terminal BO1A) and the output terminal of inverter IV3 (corresponding to terminal BO1B) are indefinite.

[0308] Because a low-level potential is input to the wiring CNL1, the buffer circuits BA and BB included in the circuit BUX are each inactive. Therefore, the output terminal of the buffer circuit BA is in a high-impedance state regardless of the potential of the input terminal of the buffer circuit BA (corresponding to terminal BO1A of the holding circuit FF). Similarly, the output terminal of the buffer circuit BB is in a high-impedance state regardless of the potential of the input terminal of the buffer circuit BB (corresponding to terminal BO1B of the holding circuit FF). Note that in this operation example, a low-level potential is input to the wiring CNL1 before time T21, from time T21 to time T27, and after time T27. In other words, in this operation example, the circuits BUX and BUY do not operate.

[0309] Since a low-level potential is input to each of the wirings CNL3 and CNL4, each of the transistors MI and MO is turned off.

[0310] Before time T21, the potential of the first terminal of the capacitance element CO (corresponding to the node NC) and the second terminal of the transistor MO (corresponding to the terminal BI2 of the holding circuit FF) are undefined.

[0311] <<From Time T21 to Time T22>> From time T21 to time T22, the data signal input to the terminal DI is held in the holding circuit FF.

[0312] 10, the operation from time T21 to time T22 can be seen from the operation from time T01 to time T02 in the timing chart of FIG. 4. Therefore, when switch SW1 is on and switch SW2 is off, the data signal (high-level potential) input to terminal DI is input to the input terminal of inverter IV2 via selector SLCA, inverter IV1, and switch SW1, and high-level potentials are output from terminals QO and BO1A of holding circuit FF. Also, a high-level potential, which is the same potential as terminals QO and BO1A, is output from terminal BO1B of holding circuit FF.

[0313] The data signal (high level potential) from the output terminal of the inverter IV2 is input to the input terminal of the inverter IV3, and a low level potential is output from the terminal BO1B of the holding circuit FF.

[0314] Thereafter, the switch SW2 is turned on, whereby the inverters IV2 and IV3 maintain the potentials of the terminals QO, BO1A, and BO2, and the potential of the terminal BO1B. The switch SW1 is turned off, whereby the data signal (high level potential) input from the terminal DI, or more precisely, the signal (low level potential) obtained by inverting the logic of the data signal output from the output terminal of the inverter IV1, does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0315] <<Between Time T22 and Time T23>> Between time T22 and time T23, the data signal input to terminal DI transitions from high to low. At this point, because switch SW1 is in the off state, the data signal (low potential) input from terminal DI—more precisely, the inverted logic signal (high potential) output from the output terminal of inverter IV1—does not reach the input terminal of inverter IV2 or the first terminal of switch SW2. In other words, the data signal is not rewritten into the loop of inverters IV2 and IV3, and holding circuit FF continues to output high potentials as data signals from terminals QO, BO1A, and BO2, and low potentials from terminal BO1B.

[0316] <<From Time T23 to Time T24>> From time T23 to time T24, as an example, an operation is performed to write the data held in the holding circuit FF to the circuit BUZ as a backup.

[0317] Specifically, a high-level potential is input to the wiring CNL3 between time T23 and time T24.

[0318] Because a high-level potential is input to the wiring CNL3, the transistor M1 included in the circuit BUZ is turned on, causing charges to flow from the terminal BO2 of the holding circuit FF to the first terminal of the capacitor CO, and the potential of the first terminal of the capacitor CO becomes high.

[0319] After that, a low-level potential is input to the wiring CNL3, turning off the transistor M1, so that a high-level potential is also held at the first terminal of the capacitor CO as data held in the holding circuit FF.

[0320] By the above operation, the data held in the holding circuit FF can be backed up in the circuit BUZ.

[0321] <<From Time T24 to Time T25>> From time T24 to time T25, as an example, an operation of stopping the supply of the power supply potential to the memory circuit NOMA is performed.

[0322] Therefore, the potentials of the wirings SEL, SWL1, SWL2, CNL1, CNL3, and CNL4 become unstable. Similarly, the potentials of the terminal DI, the terminal QO (terminal BO1A or terminal BO2), the terminal BO1B, and the terminal BI1 also become unstable.

[0323] <<From Time T25 to Time T26>> From time T25 to time T26, as an example, the supply of the power supply potential to the memory circuit NOMA is started again.

[0324] Specifically, between time T25 and time T26, a digital signal value of "3" is input to the wiring SEL, a low-level potential is input to the wiring SWL1, and a high-level potential is input to the wiring SWL2. A low-level potential is input to each of the wirings CNL1, CNL3, and CNL4. An arbitrary data signal (a low-level potential is used as an example in FIG. 10 ) is input to the terminal DI.

[0325] Since the value "3" is input to the line SEL, the selector SLCA is in a conductive state between the third input terminal and the output terminal, and in a non-conductive state between the first input terminal and the second input terminal and the output terminal, respectively. Therefore, the potential input to the terminal BI2 is output to the output terminal of the selector SLCA, and the potential input to the terminal DI does not reach beyond the output terminal of the selector SLCA.

[0326] For the operations of the holding circuit FF, the circuit BUX, the circuit BUY, and the circuit BUZ other than those described above, the description of the operations from time T21 to time T25 shown in FIG. 10 can be referred to.

[0327] Furthermore, between time T25 and time T26, a high-level potential is input to the wiring CNL4. The transistor MO is turned on, establishing a conductive state between the first terminal of the capacitance element CO and the input terminal of the selector SLCA. As a result, the charge stored in the first terminal of the capacitance element CO is released to at least the third input terminal of the selector SLCA. In other words, the charge is redistributed between at least the first terminal of the capacitance element CO and the third input terminal of the selector SLCA. As a result, the potentials of the node NC and the terminal BI2 each converge to a potential that is equal to or greater than half the difference between the high-level potential and the low-level potential, but less than the high-level potential. In the timing chart of FIG. 10, the potentials of the node NC and the terminal BI2 are denoted as Vrd.

[0328] <<From Time T26 to Time T27>> From time T26 to time T27, for example, the data signal input to the terminal BI2 is held in the holding circuit FF.

[0329] Specifically, from time T26 to time T27, a high-level potential is input to the wiring SWL1, and a low-level potential is input to the wiring SWL2.

[0330] Since a high-level potential is input to the wiring SWL1, the switch SW1 is turned on. Since a low-level potential is input to the wiring SWL2, the switch SW2 is turned off.

[0331] At this time, the data signal (Vrd) input to terminal BI2 is input to the input terminal of inverter IV2 via selector SLCA, inverter IV1, and switch SW1. Since Vrd is a potential that is equal to or greater than half the difference between the high-level potential and the low-level potential, but less than the high-level potential, a low-level potential is output from the output terminal of inverter IV1. Furthermore, since this low-level potential is input to the input terminal of inverter IV2, a high-level potential is output from the output terminal of inverter IV2 as a data signal. In other words, a high-level potential is output from terminal QO, terminal BO1A, and terminal BO2 of holding circuit FF.

[0332] Furthermore, since the data signal (high level potential) from the output terminal of the inverter IV2 is input to the input terminal of the inverter IV3, a low level potential obtained by inverting the logic of the data signal (high level potential) is output from the output terminal of the inverter IV3. In other words, a low level potential is output from the terminal BO1B of the holding circuit FF.

[0333] Furthermore, between time T26 and time T27, after a high-level potential is output from terminal QO and terminal BO1A of holding circuit FF and a low-level potential is output from terminal BO1B of holding circuit FF, a low-level potential is input to wiring SWL1 and a high-level potential is input to wiring SWL2.

[0334] Since a low-level potential is input to the wiring SWL1, the switch SW1 is turned off. Since a high-level potential is input to the wiring SWL2, the switch SW2 is turned on.

[0335] Since the switch SW1 is in the off state, the data signal (high level potential) input from the terminal BI, or more precisely, the signal (low level potential) with the logic of the data signal inverted and output from the output terminal of the inverter IV1, does not reach the input terminal of the inverter IV2 or the first terminal of the switch SW2.

[0336] Furthermore, because the switch SW2 is in the on state, conduction occurs between the input terminal of the inverter IV2 and the output terminal of the inverter IV3. In other words, because the signal is looped by the inverters IV2 and IV3, a high-level potential is held as a data signal at the output terminal of the inverter IV2 and the input terminal of the inverter IV3 (corresponding to the terminal QO and the terminal BO1A), and a low-level potential is held at the input terminal of the inverter IV2 and the output terminal of the inverter IV3 (corresponding to the terminal BO1B).

[0337] The operation examples before time T21, from time T21 to time T27, and after time T27 described above enable data to be held in the holding circuit FF, the data to be backed up in the circuit BUY, and the data to be written back from the circuit BUY to the holding circuit FF.

[0338] Note that the operation method of the memory circuit of one embodiment of the present invention is not limited to the operation example in the timing chart in Fig. 10. Specifically, in the timing chart described in this specification, wirings whose potentials change depending on the situation, operation, timing, and the like can be changed.

[0339] <Example of Cross-Sectional Configuration of Memory Circuit> Next, an example of the cross-sectional configuration of the memory circuit NOMA will be described.

[0340] First, the positional relationship between the holding circuit FF, the circuit BUX, the circuit BUY, and the circuit BUZ in the memory circuit NOMA will be described. Figure 11A is a schematic perspective view illustrating a configuration example of a memory circuit of one embodiment of the present invention. Note that the schematic perspective view of the memory circuit NOMA illustrated in Figure 11A is a modified example of the memory circuit NOM in Figure 5A and differs from the memory circuit NOM in Figure 5A in that a layer OSL is provided. Furthermore, the layer OSL is provided above the layer FEL.

[0341] 5A, the memory circuit NOMA in FIG. 11A includes, as an example, a holding circuit FF and a circuit BUX in the layer CIL. The layer FEL includes, as an example, a circuit BUY. The layer OSL includes, as an example, a circuit BUZ. To make the configuration of the memory circuit NOM easier to understand, the layers CIL, FEL, and OSL are shown separately in FIG. 11B.

[0342] By stacking the layer CIL, which has the holding circuit FF and the circuit BUX, the layer FEL, which has the circuit BUY, and the layer OSL, which has the circuit BUZ, the connection distance between the circuits arranged above and below can be shortened. This increases the communication speed between the circuits arranged above and below. Furthermore, because the connection distance is short, power consumption related to signal transmission and reception can be reduced.

[0343] 5A and 5B , a method may be used in which the layer CIL, the layer FEL, and the layer OSL are laminated, for example, by laminating the layer FEL directly on the layer CIL, and then laminating the layer OSL directly on the layer FEL. Alternatively, similar to the description of FIG. 5A and FIG. 5B , a method may be used in which the layer CIL, the layer FEL, and the layer OSL are formed on different substrates, and the three substrates are bonded together and connected using a through-via or a conductive film bonding technique (e.g., Cu—Cu bonding technique).

[0344] 11B shows an example in which a circuit BUX included in the layer CIL and a circuit BUY included in the layer FEL are connected by a conductive layer PG, and a holding circuit FF included in the layer CIL and a circuit BUZ included in the layer OSL are connected by a conductive layer PGA via the layer FEL. Note that the conductive layers PG and PGA function as wiring or plugs.

[0345] Next, a cross-sectional structure example of a memory circuit NOM according to one embodiment of the present invention is shown in Fig. 12. The memory circuit NOM shown in Fig. 12 includes a layer CIL, a layer FEL above the layer CIL, and a layer OSL above the layer FEL, as in the structure of the memory circuit NOMA in Figs.

[0346] 12 is a modified example of the cross-sectional configuration of the memory circuit NOM in FIG. 6A, and a layer OSL is provided in the memory circuit NOM in FIG. 6A. Furthermore, conductive layers PGA1 and PGA2, which are part of the conductive layer PGA, are newly provided in the layer FEL. Regarding the portions of the layer CIL and the layer FEL common to the memory circuit NOM in FIG. 6A, the description of the memory circuit NOM in FIG. 6A can be referred to.

[0347] In the layer FEL, the conductive layer PGA1 is, for example, embedded in an opening provided in the insulating layer IS1 in a region overlapping with a portion of the conductive layer 358. Furthermore, the conductive layer PGA2 is, for example, embedded in openings provided in the insulating layer FD and the insulating layer IS2 in a region overlapping with the conductive layer PGA1. This establishes electrical continuity between a portion of the conductive layer 358, the conductive layer PGA1, and the conductive layer PGA2.

[0348] For the conductive layers PGA1 and PGA2, for example, the description of the conductive layers PG1 and PG2 shown in FIG. 6B can be referred to.

[0349] <<Configuration Example of Layer OSL>> In Fig. 12, the layer OSL has the circuit BUZ shown in Fig. 8. Specifically, the layer OSL includes a transistor MI (transistor MO).

[0350] The layer OSL includes conductive layers ME4, ME5, ME6, ME7, PGA3, PGA41, PGA42, insulating layers IS3, IS4, IS5, GI, and semiconductor layer SC for forming the transistor MI (transistor MO).

[0351] The conductive layers PGA1 and PGA2 included in the layer FEL and the conductive layers PGA3, PGA41, ME7, and PGA42 included in the layer OSL correspond to the conductive layer PGA shown in Fig. 11B. In particular, the conductive layers PGA3, PGA41, PGA42, and ME7 will be described later.

[0352] The conductive layer ME4 has a region in contact with the upper surface of the insulating layer IS3. Note that a portion of the conductive layer ME4 functions as one of the source electrode and drain electrode of the transistor MI (transistor MO), for example. The conductive layer ME4 also functions as wiring extending in the front-to-back direction of the drawing.

[0353] The conductive layer ME4 can be made of, for example, a material that can be used for the conductive layer 328, the conductive layer 356, or the conductive layer ME1 described above.

[0354] The insulating layer IS3 has regions in contact with the upper surface of the insulating layer IS2 and the upper surface of the conductive layer ME4. In other words, the insulating layer IS3 is located above the insulating layer IS2 and the conductive layer ME4. As an example, the insulating layer IS3 functions as an interlayer film that separates the conductive layer ME4 from a conductive layer ME5, which will be described later. By providing the insulating layer IS3, it is possible to prevent the conductive layers ME4 and ME5 from coming into direct contact with each other and causing a short circuit.

[0355] For example, the conductive layer ME5 has a region in contact with the upper surface of the insulating layer IS3. In other words, the conductive layer ME5 is located above the insulating layer IS3. Note that, for example, a partial region of the conductive layer ME5 functions as the other of the source electrode and drain electrode of the transistor MI (transistor MO). The conductive layer ME5 also functions as wiring extending in the front-to-back direction of the drawing.

[0356] The insulating layer IS3 preferably has an insulating material with a low relative dielectric constant, similar to the insulating layers IS1 and IS2. Therefore, the insulating layer IS3 formed on the insulating layer IS2 and the conductive layer ME4 can be made of a material that can be used for the insulating layer IS1, the insulating layer IS2, or the insulating layer 353, for example.

[0357] The conductive layer ME5 can be made of, for example, a material that can be used for the conductive layer 328, the conductive layer 356, or the conductive layer ME1 described above.

[0358] An opening is provided in the insulating layer IS3 in a region overlapping the conductive layer PGA2, and the conductive layer PGA3 is embedded in the opening. This allows electrical conduction between the conductive layer PGA3 and the conductive layer PGA2. Furthermore, the conductive layer ME5 is not formed in the region on the insulating layer IS3 that includes the opening in which the conductive layer PGA3 is embedded.

[0359] For the conductive layer PGA3, for example, a material applicable to the conductive layer PGA1 or the conductive layer PGA2 can be used.

[0360] Furthermore, each of the insulating layer IS3 and the conductive layer ME5 has an opening KK2 in a region overlapping with a part of the conductive layer ME4.

[0361] 12, the opening KK2 has a tapered shape with a taper angle that is approximately perpendicular (60° or more and 120° or less) to the substrate 311 or the conductive layer ME4, similar to the opening KK1, for example. Alternatively, the opening KK2 may have a tapered shape with a taper angle that is 30° or more and less than 60°, or a taper angle that is greater than 0° and less than 30°, relative to the substrate 311 or the conductive layer ME1, for example.

[0362] The semiconductor layer SC has an area contacting the side surfaces of the insulating layer IS3 and conductive layer ME5 corresponding to the side surfaces of the opening KK2, the upper surface of the conductive layer ME4 corresponding to the bottom of the opening KK2, and the upper surface of the conductive layer ME5 outside the opening KK2.

[0363] That is, the semiconductor layer SC is formed on the bottom and inner side surfaces of the opening KK2. The semiconductor layer SC can be formed using a film formation method such as sputtering, CVD, MBE, PLD, or ALD. In particular, as shown in FIG. 12 , the semiconductor layer SC must be formed on the bottom and inner side surfaces of the opening KK2 with good coverage, so ALD is preferred. The ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Examples of ALD methods include thermal ALD, in which the reaction between the precursor and the reactant is carried out using only thermal energy, and plasma-enhanced ALD (PEALD), which uses a plasma-excited reactant. By using the ALD method, atomic layers can be deposited one by one on the bottom and inner side surfaces of the opening KK2, so that the conductive film can be formed with good coverage on the bottom and side surfaces of the opening KK2.

[0364] When the taper angle of the side surface of the opening KK2 is less than 90°, the method for forming the semiconductor layer SC is not limited to the ALD method, and for example, a sputtering method can be used. The sputtering method can increase the film formation speed compared to the ALD method, and therefore can shorten the takt time of the memory circuit.

[0365] The semiconductor layer SC can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, each of the transistors MI and MO is an OS transistor. For example, the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Furthermore, it is preferable that the element M is also contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, it is more preferable that the element M contains one or both of gallium and tin.

[0366] For example, it is preferable to use In—Ga—Zn oxide for the semiconductor layer SC. In particular, it is more preferable that the In—Ga—Zn oxide be a metal oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, a composition of 4:2:3 (atomic ratio) or a composition thereabout, or a composition of 3:1:2 (atomic ratio) or a composition thereabout. As another example, it is also preferable to use In—Zn oxide for the semiconductor layer SC. In particular, it is more preferable that the In—Zn oxide be a metal oxide having a composition of In:Zn=4:1 (atomic ratio) or a composition thereabout.

[0367] Furthermore, the semiconductor layer SC preferably has a stacked structure of multiple oxide layers, each having a different atomic ratio of each metal atom. For example, consider a first metal oxide and a second metal oxide formed on the first metal oxide as the metal oxide. When each metal oxide contains at least indium (In) and an element M, it is preferable that the ratio of the number of atoms of element M contained in the first metal oxide to the number of atoms of all elements constituting the first metal oxide is higher than the ratio of the number of atoms of element M contained in the second metal oxide to the number of atoms of all elements constituting the second metal oxide. It is also preferable that the atomic ratio of element M contained in the first metal oxide to In is higher than the atomic ratio of element M contained in the second metal oxide to In.

[0368] The energy of the conduction band minimum of the first metal oxide is preferably higher than the energy of the conduction band minimum of the second metal oxide, or in other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0369] Here, at the junction between the first metal oxide and the second metal oxide, the energy level of the conduction band minimum changes gradually. In other words, the energy level of the conduction band minimum at the junction between the first metal oxide and the second metal oxide changes continuously or can be said to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the first metal oxide and the second metal oxide.

[0370] Specifically, when the first metal oxide and the second metal oxide have a common element (main component) other than oxygen, a mixed layer with a low defect level density can be formed. For example, when the second metal oxide is In-Ga-Zn oxide (indium-gallium-zinc oxide), the first metal oxide can be In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide.

[0371] For example, the first metal oxide may have a composition of In:Ga:Zn=1:3:4 (atomic ratio) or thereabout, a composition of 1:3:2 (atomic ratio) or thereabout, or a composition of 1:1:0.5 (atomic ratio) or thereabout. The second metal oxide may have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabout, a composition of 4:2:3 (atomic ratio) or thereabout, or a composition of 3:1:2 (atomic ratio) or thereabout. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio.

[0372] In this case, the main carrier path is the second metal oxide. By configuring the first metal oxide as described above, the defect state density at the interface between the first metal oxide and the second metal oxide can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor can achieve high on-state current and high frequency characteristics.

[0373] The metal oxide may have a laminated structure of the second metal oxide and the first metal oxide formed on the second metal oxide. This structure can prevent an increase in contact resistance between the conductor ME1 or ME2 and the metal oxide. Furthermore, it can reduce damage to the second metal oxide caused by the formation of the insulator GI (described in detail later).

[0374] Furthermore, when a first metal oxide is formed on the bottom and inner side surfaces of the opening KK2 and a second metal oxide is formed on the first metal oxide, the first metal oxide is deposited by ALD, the second metal oxide is deposited by sputtering, and then a heat treatment is performed, thereby improving the crystallinity of the first metal oxide and the second metal oxide. In this case, the crystals contained in the second metal oxide grow continuously in the vertical direction toward the first metal oxide, and the boundary between the first metal oxide and the second metal oxide may become difficult to recognize by cross-sectional observation.

[0375] Alternatively, a three-layer structure may be formed by depositing a third metal oxide on the second metal oxide using an ALD method. After the deposition of the third metal oxide, heat treatment can be performed to improve the crystallinity of the first to third metal oxides. In this case, crystals contained in the second metal oxide grow continuously vertically toward the first and third metal oxides and then laterally. This may result in the boundary between the first and second metal oxides and the boundary between the second and third metal oxides becoming indistinguishable from cross-sectional observation.

[0376] The third metal oxide may be, for example, a material that can be used for the first metal oxide, and the composition of the third metal oxide is preferably the same as or close to the composition of the first metal oxide.

[0377] In this way, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the film thickness direction. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the film thickness direction. This makes it possible to realize a highly reliable transistor.

[0378] In a three-layer metal oxide layer in which a first metal oxide is deposited using an ALD method, a second metal oxide is deposited using a sputtering method to form a film having a CAAC structure, and a third metal oxide is deposited using an ALD method, the second metal oxide having a CAAC structure can serve as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxide layers. This enhances the overall crystallinity of the three-layer metal oxide layer. Such a metal oxide layer, or the CAAC structure as used herein, can be referred to as an axial growth CAAC (AG CAAC).

[0379] The heat treatment is preferably carried out at a temperature of 100° C. to 800° C., more preferably at a temperature of 250° C. to 650° C., and even more preferably at a temperature of 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0380] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA device or a GRTA device can be used.

[0381] Furthermore, by using a metal oxide for the semiconductor layer SC and providing a conductor (in FIG. 12, this corresponds to the conductive layers ME4 and ME5) in contact with the semiconductor layer SC, the oxygen concentration may be reduced in the vicinity of the conductor in the semiconductor layer SC. Also, a metal compound layer containing a metal contained in the conductor and a component of the semiconductor layer SC may be formed in the vicinity of the conductor in the semiconductor layer SC. In such a case, the carrier concentration increases in the region of the semiconductor layer SC near the conductor, and the region becomes a low-resistance region.

[0382] In addition to metal oxides, the semiconductor layer SC may be made of a material containing silicon, for example. Examples of the silicon include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (including low-temperature polysilicon (LTPS)), and single-crystal silicon. In the process of forming the semiconductor layer SC in the opening KK2, it is preferable that the semiconductor region in which the semiconductor layer SC is formed be transformed into a low-resistance region at the interface in contact with the conductive layer ME4 and the conductive layer ME5 and in the vicinity thereof. This allows the semiconductor layer SC to have a low-resistance region and a semiconductor region, enabling the transistors MI and MO to be Si transistors.

[0383] In this embodiment, the semiconductor layer SC is described as including a metal oxide that functions as an oxide semiconductor.

[0384] The insulating layer GI has regions in contact with the upper surface and side surfaces of the semiconductor layer SC, the upper surface and side surfaces of the conductive layer ME5, and the upper surface of the insulating layer IS3. The insulating layer GI also functions as a gate insulating film in the transistor MI (transistor MO).

[0385] The insulating layer GI may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use an insulator containing a so-called high-k material such as BST in a single layer or a multilayer configuration. Alternatively, the insulating layer GI may be made of an insulator having a high dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0386] As transistors become smaller and more highly integrated, problems such as leakage current due to thinner gate insulators can occur. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0387] The insulating layer GI may be formed by stacking the above-described high-k material and silicon oxide or silicon oxynitride, which provides a thermally stable insulating layer having a high dielectric constant and can be used as the gate insulating film of each of the transistors MI (MO).

[0388] The insulating layer GI may be a single layer, or may have a laminated structure obtained by sequentially depositing two or more layers of insulating material.

[0389] When the semiconductor layer SC contains a metal oxide that functions as an oxide semiconductor, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating layer GI (at the latest before forming the conductive layer ME6 described below). Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. Furthermore, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. When the insulating layer GI1 has a stacked structure, microwave treatment may be performed after the insulating layer GI1 has been partially deposited. For example, when the insulating layer GI1 contains a silicon oxide film or a silicon oxynitride film, the microwave treatment may be performed after the silicon oxide film or the silicon oxynitride film has been deposited.

[0390] Furthermore, microwave processing can use high-frequency waves such as microwaves or RF, oxygen plasma, oxygen radicals, etc. Furthermore, when performing microwave processing, it is preferable to use, for example, a microwave processing device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably 300 MHz to 300 GHz, and more preferably 2.4 GHz to 2.5 GHz. For example, the frequency can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave processing device is preferably 1000 W to 10,000 W, and more preferably 2000 W to 5,000 W. Furthermore, the microwave processing device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the semiconductor layer SC, which is a metal oxide. Due to the action of plasma, microwaves, etc., V included in the region of the semiconductor layer SC can be generated. Ｏ H can be split off and hydrogen can be removed from the region. Ｏ This reduces the oxygen vacancies and V in the region. ＯBy supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the region, the oxygen vacancies in the region can be further reduced, and the carrier concentration can be lowered.

[0391] The conductive layer ME6 is provided on the insulating layer GI1 so as to fill the opening KK2 and the opening of the insulating layer GI. The conductive layer ME6 is a conductor (which may also be referred to as a terminal, a wiring, or the like) that functions as a gate electrode of the transistor MI (transistor MO).

[0392] The conductive layer ME6 can be made of, for example, a material that can be used for the conductive layer 328, the conductive layer 356, or the conductive layer ME1 described above.

[0393] The insulating layer IS4 is located on the upper surface of the conductive layer ME6 and the upper surface of the insulating layer GI. In other words, the insulating layer IS4 has regions in contact with the conductive layer ME6 and the insulating layer GI.

[0394] The insulating layer IS4 preferably includes an insulating material having a low relative dielectric constant, similar to the insulating layers IS1 to IS3. For example, the insulating layer IS4 may include a material that can be used for the insulating layers IS1 to IS3 or the insulating layer 353.

[0395] Furthermore, each of the insulating layer IS4 and the insulating layer GI has an opening in a region overlapping the conductive layer PGA3. Furthermore, the conductive layer PGA41 is embedded in the opening, thereby establishing electrical continuity between the conductive layer PGA3 and the conductive layer PGA41 at the bottom of the opening.

[0396] The insulating layer IS4 also has an opening different from the above in a region overlapping the conductive layer ME6. The conductive layer PGA42 is embedded in the opening. This provides electrical continuity between the conductive layer ME6 and the conductive layer PGA42 at the bottom of the opening.

[0397] For the conductive layer PGA41 or the conductive layer PGA42, for example, a material applicable to the conductive layer PGA1, the conductive layer PGA2, or the conductive layer PGA3 can be used.

[0398] The conductive layer ME7 is located on the top surface of the conductive layer PGA41, the top surface of the conductive layer PGA42, and the top surface of the insulating layer IS4. In other words, the conductive layer ME7 has regions in contact with the conductive layer PGA41, the conductive layer PGA42, and the insulating layer IS4. This provides electrical continuity between the conductive layer PGA41 and the conductive layer PGA42 via the conductive layer ME7.

[0399] The conductive layer ME7 can be made of, for example, a material that can be used for the conductive layer 328, the conductive layer 356, or the conductive layer ME1 described above.

[0400] The insulating layer IS5 is located on the upper surface of the conductive layer ME7 and the upper surface of the insulating layer IS4. In other words, the insulating layer IS5 has regions in contact with the conductive layer ME7 and the insulating layer IS4.

[0401] The insulating layer IS5 preferably includes an insulating material having a low relative dielectric constant, similar to the insulating layers IS1 to IS4. For example, the insulating layer IS5 may include a material that can be used for the insulating layers IS1 to IS4 or the insulating layer 353.

[0402] 12 has a structure in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), and therefore the transistor MI (transistor MO) can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0403] 12, by providing the channel formation region of the transistor along the side surface of the opening in the insulator that functions as an interlayer film, the formation area of ​​the transistor can be made smaller than when the channel formation region of the transistor is provided along the plane of the substrate 311. Furthermore, since the source electrode, semiconductor, and drain electrode of the transistor MI (transistor MO) can be provided in an overlapping manner, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistor MI (transistor MO), the area of ​​the circuit can be reduced. As a result, this can lead to the miniaturization of a semiconductor device or display device including the circuit.

[0404] 12, the conductive layer ME7 is preferably formed above the conductive layer ME5 with the insulating layer GI and the insulating layer IS4 interposed therebetween. Increasing the distance between the conductive layer ME7 and the conductive layer ME5 increases the distance between the gate electrode and the other of the source and drain electrodes of the transistor MI (transistor MO), thereby reducing the parasitic capacitance generated between the gate electrode and the other of the source and drain electrodes. This allows the memory circuit NOMA to operate stably. Depending on the circumstances, the conductive layer ME6 may be formed along the top surface of the insulating layer GI so as to be in direct contact with the conductive layer PGA3 or the conductive layer PGA41.

[0405] 8, it is possible to select a memory to which the data of the holding circuit FF is to be backed up depending on the situation. For example, when it is desired to reduce power consumption, a memory (circuit BUZ) using an OS transistor and a capacitive element CO can be used to back up the holding circuit FF, and when it is desired to retain the backup data for a long period of time, the holding circuit FF can be backed up using circuits BUX and BUY using ferroelectric capacitors.

[0406] Furthermore, as described in the first embodiment, the characteristics of the transistors included in the memory circuit may be deteriorated due to the influence of heat treatment on the ferroelectric capacitor FA (ferroelectric capacitor FB) included in the layer FEL. Therefore, as shown in FIGS. 11A, 11B, and 12, it is preferable to form the layer FEL first, perform heat treatment on the ferroelectric capacitor FA (ferroelectric capacitor FB), and then form the layer OSL. In this way, by forming a stacked structure in the order of the layer CIL, the layer FEL, and the layer OSL, and performing heat treatment on the ferroelectric capacitor FA (ferroelectric capacitor FB) after the layer FEL is formed, the thermal influence on the transistor MI (transistor MO) included in the layer OSL can be avoided. This allows the transistor MI (transistor MO) with good characteristics to be formed in the layer OSL, thereby improving the reliability of the circuit BUZ of the memory circuit NOMA.

[0407] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0408] Embodiment 3 In this embodiment, a processing apparatus according to one embodiment of the present invention will be described.

[0409] 13 is a schematic perspective view of a processing device 960. The processing device 960 shown in FIG. 13 can be applied to, for example, a CPU (Central Processing Unit). The processing device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0410] The processing device 960 shown in FIG. 13 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0411] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991 or register 996 via a bus interface 998.

[0412] The processing device 960 shown in FIG. 13 is merely an example of a simplified configuration, and actual processing devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the processing device 960 shown in FIG. 13 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computing performance. The greater the number of cores, the more preferable it is, but it can be, for example, two, preferably four, more preferably eight, even more preferably twelve, even more preferably sixteen, or even more preferably more. Furthermore, when extremely high computing performance is required, such as for server applications, a multi-core configuration with 16 or more cores, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the processing device 960 can handle via its internal computing circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or more.

[0413] An instruction input to the processing unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0414] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the processing unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the processing unit 960.

[0415] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0416] In the processing device 960 shown in FIG. 13 , a register controller 997 selects a holding operation in the register 996 in accordance with an instruction from the ALU 991. The register 996 can be the memory circuit NOM or the memory circuit NOMA described in the above embodiment. For example, if the memory circuit NOM shown in FIG. 1 is used as the register 996, an instruction from the ALU 991 determines whether data is to be held in the hold circuit FF or in the ferroelectric capacitors FA and FB of the circuit BUY. In particular, when data holding by the hold circuit FF is selected, a power supply potential is supplied to the hold circuit FF in the register 996. Furthermore, when data holding by the ferroelectric capacitors FA and FB of the circuit BUY is selected, the supply of power supply potential to each circuit in the memory circuit NOM can be stopped.

[0417] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0418] Embodiment 4 In this embodiment, an application example of a memory circuit (sometimes referred to as a memory device) according to one embodiment of the present invention will be described.

[0419] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 14A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 14A , from the top layer, there are memory integrated as a register in an arithmetic processing unit (sometimes referred to as a processing unit) such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches may also be included.

[0420] The memory circuit NOM described in the above embodiment can be used as a memory included in the arithmetic processing unit. For example, the memory circuit NOM can be used as a register, an L1 cache, an L2 cache, an L3 cache, or the like.

[0421] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0422] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0423] The main memory has a function of holding programs, data, etc. read from storage.

[0424] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0425] A memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has high operation speed and can retain data for a long period of time. For example, the OS memory has the characteristics shown in Table 1.

[0426]

[0427] By utilizing the characteristics of the OS memory shown in the table above, a storage device according to one aspect of the present invention can be suitably used in both the tier where the cache is located and the tier where the main memory is located, as shown in Figure 14A. The storage device according to one aspect of the present invention can also be applied to the tier where the storage is located.

[0428] FIG. 14B also shows an example in which a static random access memory (SRAM) is used as part of the cache, and an OS memory of one embodiment of the present invention is used as the other part.

[0429] The lowest level cache can be called a Last Level Cache (LLC). While an LLC does not require faster operation speed than higher-level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operation speed and can retain data for a long period of time, and therefore can be suitably used for an LLC. The OS memory of one embodiment of the present invention can also be applied to a Final Level Cache (FLC).

[0430] For example, as shown in Fig. 14B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 14B, not only the OS memory but also DRAM can be applied to the main memory.

[0431] In supercomputers and servers using supercomputers, the power consumption of the L3 cache and the DRAM serving as the main memory is large, which is one of the causes of global warming. In FIG. 14A , OS memory is used for both the L3 cache and the main memory. In FIG. 14B , OS memory is used for the LLC. In this manner, by using an oxide semiconductor according to one embodiment of the present invention for a storage device, the power consumption of a supercomputer can be reduced, and the power consumption of a supercomputer can be reduced to the same level as that of a personal computer.

[0432] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0433] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0434] [Electronic Component] Fig. 15A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 15A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 15A omits some parts in order to show the inside of electronic component 700.

[0435] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0436] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0437] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and electrically connecting them on the printed circuit board.

[0438] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 15B , the semiconductor device 710 includes a drive circuit layer 715 (e.g., corresponding to the layer CIL described in the first and second embodiments) and a memory layer 716 (e.g., corresponding to the layer FEL described in the first and second embodiments, and also corresponding to the layer OSL described in the second embodiment). The memory layer 716 may be configured by stacking multiple memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 may be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (e.g., TSV, etc.) and Cu-Cu (copper-copper) bonding technology. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0439] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0440] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0441] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0442] Next, Fig. 15C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 15C does not use lead frame 712 as in electronic component 700, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0443] 15C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, substrate 701 is provided with through-hole vias, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below substrate 701 so as to be in contact with them below conductive layer 732.

[0444] Furthermore, the electrodes 733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0445] Furthermore, electronic component 700 can be mounted on other substrates using various mounting methods other than BGA and PGA, such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0446] 15D , an electronic component 700A includes an interposer 731 provided over a package substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided over the interposer 731.

[0447] 15D shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0448] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0449] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 734 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0450] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0451] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0452] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using OS transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. A structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0453] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0454] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 16A . The electronic device 6500 shown in FIG. 16A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0455] 16B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be used for the display portion 6615, the control device 6616, and the like.

[0456] The semiconductor device of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced.

[0457] [Mainframe] Next, Fig. 16C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 16C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0458] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0459] The PC card is an example of a processing board equipped with a processing unit such as a CPU, a GPU, etc. For example, the electronic component 700 can be used as the processing unit.

[0460] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0461] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0462] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0463] Fig. 17 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 17, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification also includes the thermosphere, mesosphere, and stratosphere.

[0464] 17 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0465] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0466] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0467] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0468] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0469] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0470] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0471] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0472] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power supply for maintaining the data, and cooling equipment required for maintaining the data.

[0473] By using the memory circuit of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the memory circuit that stores data. This makes it possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of cooling equipment. This makes it possible to save space in the data center.

[0474] Furthermore, the memory circuit of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the memory circuit of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0475] Fig. 18 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 18 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0476] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0477] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0478] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0479] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0480] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0481] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0482] In this example, the ferroelectric capacitors described in the first and second embodiments and dielectrics applicable to the ferroelectric capacitors will be described. Various measurements related to the ferroelectric capacitors will also be described.

[0483] Fig. 19 shows a schematic structure of the ferroelectric capacitor used in the measurement. The ferroelectric capacitor KYC in Fig. 19 has a substrate JBS, a conductive layer JME1, an insulating layer JIS, a conductive layer JME2, an insulating layer JFD, and a conductive layer JME3.

[0484] In this example, the ferroelectric capacitor KYC was fabricated on a substrate JBS. Specifically, a conductive layer JME1, which functions as wiring, and an insulating layer JIS were deposited in this order on the substrate JBS. Next, an opening with a diameter of 60 nmφ was formed in the insulating layer JIS, reaching the conductive layer JME1. In the formed opening, a conductive layer JME2, which functions as one of a pair of electrodes of the ferroelectric capacitor KYC, was formed on the top surface of the conductive layer JME1, which forms the bottom of the opening, the side surface of the insulating layer JIS, which forms the inner wall of the opening, and the top surface of the insulating layer JIS. Next, an insulating layer JFD, which functions as a dielectric, was formed on the top surface of the conductive layer JME2 and the top surface of the insulating layer JIS. Then, a conductive layer JME3 was formed on the top surface of the insulating layer JFD.

[0485] A silicon wafer was used as the substrate JBS. The conductive layer JME1 had a structure in which a 5-nm-thick tantalum nitride layer and a 10-nm-thick tungsten layer were stacked in this order. The insulating layer JIS had a stacked structure of silicon nitride, silicon oxide, and aluminum oxide with a total thickness of 510 nm. The conductive layer JME2 had a 5-nm-thick titanium nitride layer. The insulating layer JFD was a 10-nm-thick dielectric layer containing zirconium hafnium oxide and yttrium oxide. The conductive layer JME3 had a structure in which a 5-nm-thick titanium nitride layer and a 100-nm-thick tungsten layer were stacked in this order. After the conductive layer JME3 was formed, it was planarized using chemical mechanical polishing (CMP).

[0486] Furthermore, the atomic ratio of the metal elements of the oxide containing hafnium (Hf), zirconium (Zr), and yttrium (Y) contained in the insulating layer JFD was measured using X-ray photoelectron spectroscopy (XPS), and the result obtained was Hf:Zr:Y = 44.2:53.9:1.9.

[0487] Next, in the manufacturing process of the insulating layer JFD (dielectric) of the ferroelectric capacitor KYC shown in FIG. 19 , a heat treatment for crystallization was performed in a nitrogen atmosphere at 600° C. for 1 minute. The results of measuring the dielectric polarization-voltage characteristics of the ferroelectric capacitor KYC are shown in FIGS. 20A and 20B . The measurement involved a configuration in which 1 million ferroelectric capacitors KYC were connected in parallel. In the measurement of FIG. 20A , the measurement voltage range was from −1.8 V to 1.8 V, and in the measurement of FIG. 20B , the measurement voltage range was from −2.5 V to 2.5 V. As shown in FIGS. 20A and 20B , hysteresis loops indicating ferroelectricity were confirmed under both constant voltage conditions.

[0488] Next, the results of an endurance test (a test to measure data rewrite endurance) conducted for the measurement voltage ranges of −1.8 V to 1.8 V and −2.5 V to 2.5 V are shown in FIGS. 20C and 20D. The endurance test was conducted at a driving frequency of 100 kHz for 10 ８ The rewriting was repeated 10 times, and the polarization P was measured after a predetermined number of times. ８ It was confirmed that dielectric polarization was occurring normally even after repeated rewriting.

[0489] BA: buffer circuit, BB: buffer circuit, BI: terminal, BI1: terminal, BI2: terminal, BO1A: terminal, BO1B: terminal, BO2: terminal, SI1: terminal, SI2: terminal, SO: terminal, BM: conductive layer, BN: insulating layer, BS: substrate, BUX: circuit, BUY: circuit, BUZ: circuit, CIL: layer, SA: circuit, CNL1: wiring, CNL2: wiring, CNL3: wiring, CNL4: wiring, CNL21: wiring, CNL22: wiring, CNL23: wiring, CO: capacitance element, CVL: wiring, CVLA: wiring, DI: terminal, FA: ferroelectric capacitor, FB: ferroelectric capacitor , FD: insulating layer, FEL_1: layer, FEL_2: layer, FEL: layer, FF: holding circuit, GI: insulating layer, IS1: insulating layer, IS2: insulating layer, IS3: insulating layer, IS4: insulating layer, IS5: insulating layer, ISN: insulating layer, IV1: inverter, IV2: inverter, IV3: inverter, IVA: inverter, IVB: inverter, JBS: substrate, JFD: insulating layer, JIS: insulating layer, KK1: opening, KK2: opening, KYC: ferroelectric capacitor, ME1: conductive layer, ME2: conductive layer, ME3: conductive layer, ME4: conductive layer, ME5: conductive layer, ME6: conductive layer, ME7: conductive layer, MEN: conductive layer, MI: transistor, MO: transistor, NA: node, NB: node, NC: node, NOM: memory circuit, NOMA: memory circuit, OSL: layer, PG: conductive layer, PG1: conductive layer, PG2: conductive layer, PGA: conductive layer, PGA1: conductive layer, PGA2: conductive layer, PGA3: conductive layer, PGA41: conductive layer, PGA42: conductive layer, PL: wiring, QO: terminal, SC: semiconductor layer, SEL: wiring, SLC: selector, SLCA: selector, SWA1: switch, SWA2: switch, SWA3: switch, SWB1: switch, SWB2: switch switch, T10: time, T11: time, T21: time, T22: time, T23: time, T24: time, T25: time, T26: time, T27: time, 301: insulating layer, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 317: insulating layer, 320: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 353: insulating layer, 354: insulating layer, 356: conductive layer, 357: insulating layer, 358: conductive layer, 385: insulating layer, 386: conductive layer,387: insulating layer, 388: conductive layer, 400: transistor, 700A: electronic component, 700C: electronic component, 700: electronic component, 701: substrate, 710: semiconductor device, 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 960: processing device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 560 0: mainframe computer, 5610: rack, 5620: computer, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614 : external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: storage,

Claims

A first layer and a second layer located above the first layer, the first layer includes a semiconductor substrate having silicon, and a first circuit and a second circuit formed in the semiconductor substrate; the second layer includes a first ferroelectric capacitor and a second ferroelectric capacitor; each of the first ferroelectric capacitor and the second ferroelectric capacitor has a dielectric; the first circuit has a function as a flip-flop circuit that holds first digital data; the second circuit has a function of writing the first digital data, which are paired in logic with each other, into the first ferroelectric capacitor and the second ferroelectric capacitor, respectively; The dielectric material comprises an oxide containing hafnium and zirconium. memory circuit. 　 In claim 1, the first circuit includes a selector; the second circuit has a function of reading the first digital data from the first ferroelectric capacitor and the second ferroelectric capacitor; the selector has a first input terminal and a second input terminal; the selector has a function of selecting one of the first digital data read out from the first ferroelectric capacitor and the second ferroelectric capacitor and input to the first input terminal, and the second digital data input to the second input terminal; the first circuit holds the digital data selected by the selector; memory circuit. 　 In claim 2, a third layer located above the second layer, the third layer includes a first transistor, a second transistor, and a capacitive element; the first transistor and the second transistor each include an oxide semiconductor in a channel formation region; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a pair of electrodes of the capacitance element; the first digital data read from the first circuit is input to the other of the source and the drain of the first transistor; the first digital data is stored in one of a pair of electrodes of the capacitive element; a potential corresponding to the first digital data read from the capacitive element is output to the selector from the other of the source and the drain of the second transistor; the selector has a function of selecting any one of the first digital data read out from the first ferroelectric capacitor and the second ferroelectric capacitor, the first digital data read out from the capacitive element, and the second digital data input from an external source. memory circuit. 　 In claim 3, the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony; memory circuit. 　 In any one of claims 1 to 4, the dielectric material comprises yttrium; The content of the yttrium in the oxide is 0.1 atomic% or more and 3 atomic% or less. memory circuit. 　 A memory circuit according to claim 5, a register controller, and an arithmetic circuit, the register controller has a function of causing the first digital data held in the first circuit in the memory circuit to be written to the second circuit in accordance with an instruction from the arithmetic circuit; Processing unit. 　 An electronic device comprising the processing device according to claim 6 and a housing.