A / d converter and a / d conversion method

Abstract

This A / D converter performs A / D conversion including folding integration. The A / D converter comprises: a gain stage for generating a calculated value based on an input value; and an A / D conversion circuit that compares the calculated value generated by the gain stage with a conversion reference voltage to output a calculated value usable for generating a digital value. The gain stage generates a calculated value VO (M-1) by using an integration gain G(M-1) in the M-1th integration operation among M integration operations performed, and generates an operation value VO (M) by using an integration gain G(M) in the Mth integration operation. The integration gain G(M-1) is greater than the integration gain G(M).

Description

A / D converter and A / D conversion method

[0001] The present disclosure relates to an A / D converter and an A / D conversion method.

[0002] Patent Documents 1 to 6 disclose A / D converters that generate digital values ​​from analog signals. For example, the A / D converters disclosed in Patent Documents 1 to 4 perform folding integral A / D conversion and cyclic A / D conversion by switching a switch. Specifically, the A / D converter first performs folding integral A / D conversion. Next, the A / D converter performs cyclic A / D conversion on the analog signal that is the calculation result of the folding integral A / D conversion.

[0003] International Publication No. 2018 / 088476 JP 2017-201751 A JP 2017-139583 A International Publication No. 2012 / 111821 JP 2017-55174 A JP 2007-49637 A

[0004] When switching between folding integral and cyclical A / D converters by switching a switch, as in the A / D converters disclosed in Patent Documents 1 to 4, the calculation result (analog signal) of the folding integral type, which is the operation in the first stage, is kept within a range acceptable for the cyclical type, which is the operation in the second stage. Therefore, in the folding integral type operation, an integral gain is adopted that keeps the calculation result of the integral operation within a desired range.

[0005] The integral gain affects the noise reduction effect in the integral operation. The larger the integral gain, the greater the noise reduction effect. However, the smaller the integral gain, the less effective the noise reduction. In other words, if you want to keep the calculation result of the integral operation within a desired range, you have no choice but to reduce the integral gain. As a result, the noise reduction effect decreases.

[0006] The present disclosure describes an A / D converter and an A / D conversion method that can obtain a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0007] One aspect of the present disclosure is an A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling an input signal and integrating the sampled value. The A / D converter includes a gain stage that outputs a calculated value based on the analog signal, and an A / D conversion circuit that compares the calculated value output by the gain stage with a conversion reference voltage and outputs a result that can be used to generate a digital value. The gain stage generates a calculated value based on the analog signal using a first integral gain in a k-th operation (k is an integer equal to or less than M-1) out of M (M is an integer equal to or greater than 2) operations that are performed. The gain stage generates a calculated value based on the analog signal using a second integral gain in a k+1-th operation. The second integral gain is smaller than the first integral gain.

[0008] The A / D converter reduces the integral gain of the kth integral operation, which corresponds to the next integral operation, from the integral gain of the k−1th integral operation among multiple integral operations. In other words, in order to keep the calculated value obtained by M integral operations within a predetermined value, the A / D converter suppresses the integral gain of subsequent integral operations in which the calculated value becomes larger, without suppressing the integral gain of all of the M integral operations. As a result, sufficient integral gain is obtained in integral operations such as the k−1th integral operation in which the integral gain is not suppressed. As a result, a sufficient noise reduction effect can be ensured. The integral gain of subsequent integral operations is suppressed. As a result, it is possible to prevent the calculated value obtained as a result of M integral operations from becoming larger than a predetermined value. In other words, the A / D converter can obtain a good noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0009] In one embodiment, the gain stage may generate a calculated value based on the analog signal using a third integral gain in the first operation. The third integral gain may be greater than the first integral gain. This configuration can achieve a more effective noise reduction effect.

[0010] In one embodiment, the first integral gain may be used in the second through (M-1)th operations, and the second integral gain may be used in the Mth operation. This configuration also provides an even better noise reduction effect.

[0011] In one embodiment, the first integral gain may be equal to or greater than 1. The second integral gain may be equal to or greater than 0 and less than 1. This configuration also makes it possible to obtain an even better noise reduction effect.

[0012] Another aspect of the present disclosure is an A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing operations including sampling an input signal and integrating the sampled value. The A / D converter of another aspect includes a gain stage that outputs a calculation value based on the analog signal, and an A / D conversion circuit that compares the calculation value output by the gain stage with a conversion reference voltage to output a result that can be used to generate a digital value. The gain stage has a stage input that receives the analog signal, an operational amplifier circuit that generates a calculation value based on the analog signal, a stage output that outputs the calculation value to the A / D conversion circuit, a front-stage capacitance section that is connectable to the stage input and the input of the operational amplifier circuit and includes at least one front-stage capacitor, and a feedback capacitance section that is connectable to the stage input and the output of the operational amplifier circuit and includes one feedback capacitor. The gain stage selectively configures a first circuit and a second circuit different from the first circuit for sampling the input signal. The first circuit stores an analog signal in at least one upstream capacitor by connecting the upstream capacitor to a stage input so that the ratio between the capacitance of the upstream capacitor and the capacitance of the feedback capacitor is a predetermined capacitance ratio, and stores the analog signal in the feedback capacitor by connecting the feedback capacitor to the stage input. The second circuit stores an analog signal in at least one upstream capacitor by connecting the upstream capacitor to the stage input so that the ratio between the capacitance of the upstream capacitor and the capacitance of the feedback capacitor is smaller than the capacitance ratio in the first circuit, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitor from the stage input.

[0013] Like the A / D converter according to one embodiment of the present disclosure described above, this A / D converter can also obtain a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0014] In another embodiment, the ratio of the capacitance of the front-stage capacitance section to the capacitance of the feedback capacitance section may be set in accordance with the magnitude of the integral gain. This configuration also makes it possible to obtain an even better noise reduction effect.

[0015] In another embodiment, the operation may be executed M times (M is an integer equal to or greater than 2). In the first operation, the input signal is sampled using a first circuit to set the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section to a predetermined capacitance ratio. This configuration also provides an even better noise reduction effect.

[0016] In another embodiment, the operation may be executed M times (M is an integer equal to or greater than 2). In the second through (M-1) samplings of the input signal, a second circuit may be used to set the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section to a capacitance ratio smaller than the predetermined capacitance ratio in the first circuit. This configuration also provides an even better noise reduction effect.

[0017] In another embodiment, the operation may be executed M times (M is an integer equal to or greater than two). In the second to (M-1)th operations of sampling the input signal, the number of upstream capacitors storing the analog signal in the second circuit may be two or more, so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first circuit. In the Mth operation of sampling the input signal, the number of upstream capacitors storing the analog signal in the second circuit may be zero or one, so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a second capacitance ratio that is smaller than the first capacitance ratio. This configuration also provides an even better noise reduction effect.

[0018] Alternatively, the capacitance of the feedback capacitor may be greater than the capacitance of the previous stage capacitor, which also provides a better noise reduction effect.

[0019] In another embodiment, the capacitance of the feedback capacitor may be greater than the capacitance of the first pre-stage capacitor, and the capacitance of the first pre-stage capacitor may be different from the capacitance of a second pre-stage capacitor that is different from the first pre-stage capacitor. This configuration also provides an even better noise reduction effect.

[0020] Another aspect of the present disclosure is an A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling an input signal and integrating the sampled value. The A / D conversion method in yet another aspect includes the steps of: generating a first calculated value based on the analog signal by performing an operation using a first integral gain; and, after the step of generating the first calculated value, generating a second calculated value based on the analog signal by performing an operation using a second integral gain. The second integral gain is smaller than the first integral gain.

[0021] This A / D conversion method, like the A / D converter according to one embodiment of the present disclosure, can also obtain a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0022] In yet another embodiment, the method may further include, before the step of generating the first calculated value, performing an operation using a third integral gain to generate a third calculated value based on the analog signal. The third integral gain may be greater than the first integral gain. This embodiment also provides an even better noise reduction effect.

[0023] In yet another embodiment, the operation may be performed M times (M is an integer equal to or greater than 2). In the second operation to the (M-1)th operation, a step of generating a first calculated value may be performed. In the Mth operation, a step of generating a second calculated value may be performed. This embodiment also makes it possible to obtain an even better noise reduction effect.

[0024] In yet another embodiment, the first integral gain may be equal to or greater than 1, and the second integral gain may be equal to or greater than 0 and less than 1. This embodiment also makes it possible to obtain an even better noise reduction effect.

[0025] According to yet another aspect of the present disclosure, there is provided an A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing operations including sampling an input signal and integrating the sampled values. The A / D conversion method of yet another aspect includes: a sampling step of an input signal, in which an analog signal is stored in at least one upstream capacitance section connectable to a stage input of a gain stage that outputs an operational value based on the analog signal, the upstream capacitance section including at least one upstream capacitor and a feedback capacitance section including one feedback capacitor; and an integrating step of generating an operational value at the output of an operational amplifier circuit included in the gain stage by connecting at least the upstream capacitance section to the input of the operational amplifier circuit, wherein the sampling step of the input signal includes either a first storage step or a second storage step different from the first storage step. The first storage step involves storing the analog signal in at least one upstream capacitor by connecting the upstream capacitance section to the stage input, and storing the analog signal in the feedback capacitor by connecting the feedback capacitance section to the stage input, so that a ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is set to a predetermined capacitance ratio. In the second storage, the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section is set to a capacitance ratio smaller than the predetermined capacitance ratio in the first storage, so that an analog signal is stored in at least one upstream capacitor by connecting the upstream capacitance section to the stage input, and an analog signal is not stored in the feedback capacitor by disconnecting the feedback capacitance section from the stage input.

[0026] This A / D conversion method, like the A / D converter according to one embodiment of the present disclosure, can also obtain a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0027] In yet another embodiment, the ratio of the capacitance of the front-stage capacitance section to the capacitance of the feedback capacitance section may be set in accordance with the magnitude of the integral gain, which also makes it possible to obtain an even better noise reduction effect.

[0028] In yet another embodiment, the operation may be executed M times (M is an integer equal to or greater than 2). In the input signal sampling step of the first operation, a first storage may be executed to set the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section to a predetermined capacitance ratio. This embodiment also provides an even better noise reduction effect.

[0029] In yet another embodiment, the operation may be performed M times (M is an integer equal to or greater than 2). In the input signal sampling steps in the second through (M-1) operations, a second storage may be performed to set the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section to a capacitance ratio smaller than the predetermined capacitance ratio in the first storage. This embodiment also provides an even better noise reduction effect.

[0030] In yet another embodiment, the operation may be executed M times (M is an integer equal to or greater than two). In the second to (M-1)th operations of sampling the input signal, the number of upstream capacitors storing the analog signal in the second storage may be set to two or more so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is set to a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage. In the Mth operation of sampling the input signal, the number of upstream capacitors storing the analog signal in the second storage may be set to 0 or 1 so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is set to a second capacitance ratio that is smaller than the first capacitance ratio. This embodiment also provides an even better noise reduction effect.

[0031] According to the present disclosure, an A / D converter and an A / D conversion method are described that are capable of obtaining a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range.

[0032] FIG. 1 is a circuit diagram showing the configuration of an A / D converter according to a first embodiment. FIG. 2 is a diagram illustrating integral gain in the operation of the A / D converter of FIG. 1. FIGS. 3(a), 3(b), 3(c), 3(d), 3(e), and 3(f) are diagrams illustrating the operation of folding integral A / D conversion in the A / D converter shown in FIG. 1. FIG. 4 is an example of input / output characteristics of the A / D converter. FIGS. 5(a), 5(b), and 5(c) are diagrams illustrating the operation of cyclic A / D conversion in the A / D converter shown in FIG. 1. FIG. 6 is a circuit diagram showing the configuration of an A / D converter according to a second embodiment. FIG. 7 is a diagram illustrating integral gain in the operation of the A / D converter of FIG. 6. FIGS. 8(a), 8(b), 8(c), 8(d), 8(e), and 8(f) are diagrams illustrating the operation of folding integral A / D conversion in the A / D converter shown in FIG. 6. 9(a), 9(b), and 9(c) are diagrams illustrating the operation of cyclic A / D conversion in the A / D converter shown in FIG. 6. FIG. 10 is a diagram illustrating integral gain in the operation of the A / D converter of Modification 1. FIGS. 11(a), 11(b), 11(c), 11(d), 11(e), and 11(f) are diagrams illustrating the operation of folding integral A / D conversion in the A / D converter of Modification 1. FIG. 12(a) is a diagram illustrating integral gain in the operation of the A / D converter of Modification 2. FIG. 12(b) is a diagram illustrating integral gain in the operation of the A / D converter of Modification 3. FIG. 13 is a diagram illustrating the configuration of an image sensor cell. FIG. 14(a) is a result of Analysis Example 1 illustrating A / D conversion characteristics. FIG. 14(b) is a result of Analysis Example 1 illustrating nonlinearity. FIG. 15(a) is a result of Analysis Example 2 illustrating A / D conversion characteristics. Fig. 15(b) shows the results of analysis example 2, which shows nonlinearity. Fig. 16(a) shows the results of analysis example 3, which shows A / D conversion characteristics. Fig. 16(b) shows the results of analysis example 3, which shows nonlinearity.

[0033] The teachings of the present disclosure can be easily understood by considering the following detailed description with reference to the accompanying drawings, which are shown by way of example. Subsequently, with reference to the accompanying drawings, an embodiment of an A / D converter and an A / D conversion method, which are one aspect of the present disclosure, will be described. Where possible, the same reference numerals will be used to designate the same parts, and redundant explanations will be omitted.

[0034] 1 is a circuit diagram of an A / D converter 11 according to one embodiment of the present disclosure. The A / D converter 11 performs a first A / D conversion operation, which is a so-called folding integral type A / D conversion, and a second A / D conversion operation, which is a cyclic type A / D conversion, using the same circuit configuration. The A / D converter 11 realizes the first A / D conversion operation and the second A / D conversion operation by changing the time-series control pattern of the switches included in the A / D converter 11.

[0035] As shown in FIG. 1, the A / D converter 11 includes a gain stage 15, an A / D conversion circuit 17, a logic circuit 19, a D / A conversion circuit 21, a clock generator 61, and a reference voltage generation unit 70.

[0036] The gain stage 15 receives an input value V, which is an analog signal that is converted to a digital value. ＩＮ and an input 15a (stage input) that receives the calculated value V Ｏ The gain stage 15 includes an operational amplifier circuit 23, a first capacitor 25 (first pre-stage capacitor), a second capacitor 27 (second pre-stage capacitor), and a third capacitor 29 (feedback capacitor).

[0037] The operational amplifier circuit 23 includes a first input 23a, an output 23b, and a second input 23c. The phase of the signal sent from the output 23b is inverted relative to the phase of the signal given to the first input 23a. For example, the first input 23a is an inverting input terminal. The second input 23c is a non-inverting input terminal. For example, the second input 23c of the operational amplifier circuit 23 is connected to a first reference potential GND1. The second input 23c is connected to a reference potential V ＣＯＭ Receive.

[0038] The first capacitor 25, the second capacitor 27, and the third capacitor 29 are capacitances for storing and calculating various signal values.

[0039] The first capacitor 25 and the second capacitor 27 constitute a front-stage capacitance section 41. The front-stage capacitance section 41 can be connected to the input 15a by a plurality of switches 43, 82, and 83. The front-stage capacitance section 41 can also be disconnected from the input 15a by a plurality of switches 43, 82, and 83. The front-stage capacitance section 41 is also connected to the D / A conversion circuit 21.

[0040] The third capacitor 29 constitutes a feedback capacitance section 42. The feedback capacitance section 42 is connected to the input 23a of the operational amplifier circuit 23. The feedback capacitance section 42 can be connected to the input 15a by switches 43 and 51. The feedback capacitance section 42 can also be disconnected from the input 15a by switches 43 and 51. The feedback capacitance section 42 can be connected to the output 23b of the operational amplifier circuit 23 by switch 81. The feedback capacitance section 42 can also be disconnected from the output 23b of the operational amplifier circuit 23 by switch 81.

[0041] The capacitance C of the third capacitor 29 ２ (third capacitance) is the capacitance C of the first capacitor 25 １ａ (first capacitance). Also, the capacitance C of the third capacitor 29 is ２ is the capacitance C of the second capacitor 27 １ｂ (second capacitance). These capacitances C １ａ and capacitance C １ｂ According to the above, the input value V input in the first A / D conversion operation, which is a folding integral type A / D conversion, is ＩＮ is the capacitance ratio (C １ａ / C ２ , C １ｂ / C ２ ) is attenuated according to the calculated value V Ｏ The voltage range of the capacitors decreases in accordance with the capacitance ratio of the capacitors. With this configuration, the A / D converter 11 can be configured as a single-ended converter.

[0042] More specifically, the capacitance C of the third capacitor 29 ２ is the capacitance C of the first capacitor 25 １ａ The capacitance C of the third capacitor 29 is twice as large as the capacitance C of the third capacitor 29. ２ is the capacitance C of the second capacitor 27 １ｂ It is twice as much as C １ａ = 1 / 2 × C ２ and C １ｂ = 1 / 2 × C ２ According to the A / D converter 11 having such a capacitor, the input value V ＩＮ is attenuated by 1 / 2. The attenuated input value V ＩＮ is sampled and integrated. Therefore, the calculated value V Ｏ The voltage range of the first A / D converter is halved in accordance with the capacitance ratio of the capacitors. This provides an input voltage suitable for the single-ended A / D converter in the second A / D conversion operation, which is a cyclic A / D conversion.

[0043] The gain stage 15 includes a plurality of switches 43, 47, 49, 51, 53, 81, 82, and 83. These switches connect or disconnect the input 15a of the gain stage 15 to the first capacitor 25, the second capacitor 27, and the third capacitor 29. These switches connect or disconnect the first capacitor 25, the second capacitor 27, and the third capacitor 29 to or from the operational amplifier circuit 23. The arrangement of the switches 43, 47, 49, 51, 53, 81, 82, and 83 shown in FIG. 1 is an example. The switches 43, 47, 49, 51, 53, 81, 82, and 83 are controlled by a control signal φ generated in a clock generator 61. ｓａ , φ ｓｂ , φ １ , φ ２ , φ Ｆ , φ Ｉ , φ Ｔ , φ Ｒ is controlled by

[0044] The A / D converter 11 repeats the integration operation from the first time to the Mth time. In these integration operations, the gain stage 15 calculates the input value VＩＮ The value obtained by multiplying this by a predetermined integral gain is the calculated value V Ｏ The integral gain in each integral operation is indicated as G(k). The letter "k" in parentheses means the number of integral operations (number of cycles), k = 1 to M. These integral gains G(k) are not constant. For example, the integral gains G(k) may be set as follows: Integral gain G(1) = 1.5 (third integral gain) Integral gains G(2) to G(M-1) = 1.0 (first integral gain) Integral gain G(M) = 0.5 (second integral gain)

[0045] The integral gain G(1) of the first (initial) integral operation is the largest. The integral gain G(M) of the Mth (last) integral operation is the smallest. The integral gains G(2) to G(M-1) of the second to (M-1)th integral operations are constant. The integral gain G is the integral gain G of the input value V ＩＮ The input value V ＩＮ The capacitor that stores the signal can be selected by a plurality of switches included in the gain stage 15. The specific operation will be described in detail later.

[0046] The A / D conversion circuit 17 converts the calculated value V Ｏ Based on this, the first conversion reference voltage V ＲＣＨ and / or a second conversion reference voltage V ＲＣＬ A digital value D is generated in response to the

[0047] The A / D conversion circuit 17 includes a comparator 17a (first comparator) and a comparator 17b (second comparator). The A / D conversion circuit 17 generates a 1.5-bit digital value D using both comparators 17a and 17b. The digital value D indicates an A / D conversion value. The A / D conversion circuit 17 may also generate a 1-bit digital value D using either comparator 17a or 17b.

[0048] The first input of the comparator 17a is connected to the output 15b of the gain stage 15. The first input of the comparator 17a receives the calculated value V ＯThe second input of the comparator 17a is connected to the reference voltage generating unit 70 via the switches 17a1 and 17a2. The second input of the comparator 17a receives the first converted reference voltage V ＲＣＨ or the first conversion reference voltage V ＲＣＣＨ The switches 17a1 and 17a2 receive either one of the control signals S Ｆ , S Ｃ is controlled by

[0049] When the A / D conversion operation is of the folding integral type, the comparator 17a converts the first conversion reference voltage V ＲＣＨ At this time, the switch 17a1 is conductive and the switch 17a2 is non-conductive. During cyclic A / D conversion, the comparator 17a receives the first conversion reference voltage V ＲＣＣＨ At this time, the switch 17a2 is conductive and the switch 17a1 is non-conductive. The comparator 17a receives the calculated value V Ｏ and the first conversion reference voltage V ＲＣＨ Comparison with, or calculated value V Ｏ and the first conversion reference voltage V ＲＣＣＨ By comparing with the bit (B １ ) to generate the

[0050] In the comparator 17a, the first conversion reference voltage V ＲＣＨ The input is connected to a reference potential V through a capacitor (not shown). ＣＯＭ This configuration allows filtering for high frequency noise.

[0051] The first input of the comparator 17b is connected to the output 15b of the gain stage 15. The first input of the comparator 17b is connected to the calculated value V Ｏ The second input of the comparator 17b is connected to the reference voltage generating unit 70 via the switches 17b1 and 17b2. The second input of the comparator 17a receives the second converted reference voltage V ＲＣＬor the second conversion reference voltage V ＲＣＣＬ The switches 17b1 and 17b2 receive either the control signal S output from the clock generator 61. Ｆ , S Ｃ is controlled by

[0052] When the A / D conversion operation is of the folding integral type, the comparator 17b outputs the second conversion reference voltage V ＲＣＬ At this time, the switch 17b1 is conductive and the switch 17b2 is non-conductive. During cyclic A / D conversion, the comparator 17b receives the second conversion reference voltage V ＲＣＣＬ At this time, the switch 17b2 is conductive and the switch 17b1 is non-conductive. The comparator 17b receives the calculated value V Ｏ and the second conversion reference voltage V ＲＣＬ Comparison with, or calculated value V Ｏ and the second conversion reference voltage V ＲＣＣＬ By comparing with the bit (B ０ ) to generate the

[0053] When the A / D conversion circuit 17 generates a 1.5-bit digital value D, the bits (B ０ , B １ Depending on the combination of V, the digital value D for one integration operation or one cycle can take three values ​​(D=0, D=1, D=2). In this case, the comparators 17a and 17b operate as follows: Ｏ >V ＲＣＨ When D = 2 (B １ = 1, B ０ = 1) V ＲＣＬ <V Ｏ ≦V ＲＣＨ When D = 1 (B １ = 0, B ０ = 1) V Ｏ ≦V ＲＣＬ When D = 0 (B １ = 0, B ０ = 0)

[0054] When the A / D conversion circuit 17 generates a 1-bit digital value D, the bit (B １Depending on the value of V, the digital value D for one integration operation or one cycle can take two values ​​(D=0 or D=1). At this time, the comparator 17a in the A / D conversion circuit 17 operates. Therefore, the signal used as a reference when generating the 1-bit digital value D is the first conversion reference voltage V ＲＣＨ In this case, the comparator 17a operates as follows: Ｏ ≧V ＲＣＨ When B １ = 1 V Ｏ <V ＲＣＨ When B １ =0

[0055] The reference voltage generating unit 70 is connected to the reference voltage sources 33 and 35. The reference voltage generating unit 70 receives the reference reference voltage V ＲＨ The reference voltage generating unit 70 also receives the reference voltage V from the reference voltage source 35. ＲＬ The reference voltage generating unit 70 is connected to the A / D conversion circuit 17. The reference voltage generating unit 70 outputs a first conversion reference voltage V ＲＣＨ , V ＲＣＣＨ The reference voltage generating unit 70 outputs the second conversion reference voltage V ＲＣＬ , V ＲＣＣＬ The first conversion reference voltage V ＲＣＨ and the second conversion reference voltage V ＲＣＬ is used for folding integral type A / D conversion operation. The first conversion reference voltage V ＲＣＣＨ and the second conversion reference voltage V ＲＣＣＬ is used for cyclic A / D conversion operations.

[0056] The first conversion reference voltage V ＲＣＨ , V ＲＣＣＨ and the second conversion reference voltage V ＲＣＬ , V ＲＣＣＬ may be fixed values. ＲＣＨ , V ＲＣＣＨ and the second conversion reference voltage V ＲＣＬ , V ＲＣＣＬFor example, in a folding integral type A / D conversion operation, the reference voltage generating unit 70 generates an input value V ＩＮ The first conversion reference voltage V ＲＣＨ and the second conversion reference voltage V ＲＣＬ The reference voltage generating section 70 may also control the calculated value V Ｏ The first conversion reference voltage V ＲＣＨ and the second conversion reference voltage V ＲＣＬ may be controlled.

[0057] The logic circuit 19 is connected to the D / A conversion circuit 21. The logic circuit 19 outputs a control signal V ＣＯＮＴ The logic circuit 19 is connected to the outputs of the comparators 17a and 17b. The logic circuit 19 receives the calculated value B from the comparator 17a. １ and receives the calculated value B from the comparator 17b. ０ The logic circuit 19 receives the control signal V according to the digital value D. ＣＯＮＴ (For example, φ ＤＨａ , φ ＤＨｂ , φ ＤＬａ , φ ＤＬｂ ) can be generated.

[0058] The D / A conversion circuit 21 receives a first reference voltage V ＲＨ and a second reference voltage V ＲＬ The D / A conversion circuit 21 receives the first standard reference voltage V ＲＨ and a second reference voltage V ＲＬ , the control signal V ＣＯＮＴ The D / A conversion circuit 21 has four outputs 21 a 1 , 21 a 2 , 21 b 1 , and 21 b 2 and a switch circuit 31 .

[0059] The output 21a1 is connected to the first capacitor 25. The output 21a1 is connected to the control signal φ ＤＨａ A first reference voltage V is applied to the first capacitor 25 in response to ＲＨ The output 21b1 is connected to the second capacitor 27. ...ＤＨｂ The first reference voltage V ＲＨ The output 21a2 is connected to the first capacitor 25. ... ＤＬａ A second reference voltage V is applied to the first capacitor 25 in response to ＲＬ The output 21b2 is connected to the second capacitor 27. ... ＤＬｂ A second reference voltage V is applied to the second capacitor 27 in response to ＲＬ Output.

[0060] The switch circuit 31 includes switches 31a1, 31a2, 31b1, and 31b2. The switch 31a1 is connected to the output 21a1 and receives a control signal φ ＤＨａ The first reference voltage V ＲＨ The switch 31b1 is connected to the output 21b1 and receives a control signal φ ＤＨｂ The first reference voltage V ＲＨ The switch 31a2 is connected to the output 21a2 and receives a control signal φ ＤＬａ The second reference voltage V ＲＬ The switch 31b2 is connected to the output 21b2 and receives a control signal φ ＤＬｂ The second reference voltage V ＲＬ Switch between providing and stopping the service.

[0061] Next, a first A / D conversion operation in the A / D converter 11 shown in Fig. 1 will be described. The first A / D conversion operation converts an input value V ＩＮ 2, the folding integral type operation includes a first storage operation P1A, a first calculation operation P1B, a second storage operation P2A, a second calculation operation P2B, a third storage operation P3A, and a third calculation operation P3B.

[0062] First, the A / D converter 11 performs a first storage operation P1A and a first calculation operation P1B. These first storage operation P1A and first calculation operation P1B correspond to the first (k=1) integral operation of M integral operations. The integral gain G(1) in the first storage operation P1A and first calculation operation P1B is 1.5.

[0063] The A / D converter 11 performs a first storage operation P1A. FIG. 3A shows a circuit configuration for the first storage operation P1A. This circuit configuration is implemented by a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =1) and a control signal (φ ｓａ = 1, φ ｓｂ = 0, φ １ = 1, φ ２ = 0, φ Ｆ = 1, φ Ｉ = 1, φ Ｔ = 0, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0064] 3A, the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 27 is connected to the output 21b2 of the D / A converter circuit 21 and the second reference potential GND2. As a result, the second capacitor 27 receives the second reference voltage V ＲＬ The third capacitor 29 is connected to the input 15a of the gain stage 15 and the operational amplifier circuit 23. Specifically, one end of the third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. As a result, the third capacitor 29 receives the input value V ＩＮ That is, when the integral gain G is set to 1.5, the input value V ＩＮ is stored in the first capacitor 25 and the third capacitor 29 .

[0065] Following the first storage operation P1A, the A / D converter 11 performs a first calculation operation P1B (see FIG. 2). FIG. 3B shows the circuit configuration in the first calculation operation P1B. This circuit configuration is implemented by a control signal (φ ＤＨａ = 1, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =1) and a control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0066] 3B, the first capacitor 25 is connected to the output 21a1 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the first capacitor 25 is connected to the first reference voltage V ＲＨ The second capacitor 27 is connected to the output 21b2 of the D / A converter circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the second capacitor 27 receives the second standard reference voltage V ＲＬ The third capacitor 29 is connected to the first input 23 a of the operational amplifier circuit 23 and to the output 23 b of the operational amplifier circuit 23 .

[0067] Furthermore, the comparator 17a converts the first conversion reference voltage V ＲＣＨ The comparator 17a receives the calculated value V Ｏ (1) into the first conversion reference voltage V ＲＣＨ and the calculated value B according to the comparison result is １ Furthermore, the comparator 17b outputs the second conversion reference voltage V ＲＣＬ The comparator 17b receives the calculated value V Ｏ (1) into the second conversion reference voltage V ＲＣＬ and the calculated value B according to the comparison result is ０ Output (1).

[0068] Specifically, the output (digital value D) of the A / D conversion circuit 17 is as follows:

[0069] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (1) is generated.

[0070] Next, the A / D converter 11 alternately performs a second storage operation P2A and a second calculation operation P2B multiple times (see FIG. 2). The second storage operation P2A and the second calculation operation P2B correspond to the second to (M-1) integral operations out of the M integral operations performed. The integral gains G(2) to G(M-1) in the second storage operation P2A and the second calculation operation P2B are 1.0. In other words, the integral gains G(2) to G(M-1) are smaller than the integral gain G(1).

[0071] 3C shows the circuit configuration for the second store operation P2A. This circuit configuration is configured in response to the control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =0) and a control signal (φ ｓａ = 1, φ ｓｂ = 1, φ １ = 1, φ ２ = 0, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0072] 3C, the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 27 is connected to the input 15a of the gain stage 15 and to the second reference potential GND2. As a result, the second capacitor 27 receives the input value V ＩＮThe third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. In other words, when the integral gain G is set to 1.0, the input value V ＩＮ is stored in the first capacitor 25 and the second capacitor 27 .

[0073] Following the second storage operation P2A, the A / D converter 11 performs a second calculation operation P2B. As shown in FIG. 3(d), the second calculation operation P2B is executed by the same circuit configuration (see FIG. 3(b)) as the first calculation operation P1B described above. Therefore, a detailed description of the second calculation operation P2B will be omitted.

[0074] In the second calculation operation P2B, the output of the A / D conversion circuit 17 is as follows:

[0075] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (k) is generated.

[0076] In the first calculation operation P1B, the second calculation operation P2B, and the third calculation operation P3B described later, for example, the second standard reference voltage V ＲＬ and provides a first reference voltage V to the second capacitor 27. ＲＨ When the second calculation operation P2B in which the integral gain G is 1.0 is repeated multiple times, the first capacitor 25 is supplied with the first reference voltage V ＲＨ and provides a second reference voltage V to the second capacitor 27. ＲＬ and a first circuit configuration for providing a second reference voltage V to a first capacitor 25. ＲＬ and provides a first reference voltage V to the second capacitor 27. ＲＨ and a second circuit configuration providing:

[0077] Next, the A / D converter 11 performs a third storage operation P3A and a third calculation operation P3B. These third storage operation P3A and third calculation operation P3B correspond to the Mth integration operation out of M integration operations performed. The integral gain G(M) in the third storage operation P3A and third calculation operation P3B is 0.5. That is, the integral gain G(M)=0.5 is smaller than the integral gain G(1)=1.5. Furthermore, the integral gain G(M)=0.5 is smaller than the integral gains G(2) to G(M-1)=1.0.

[0078] 3(e) shows the circuit configuration in the third store operation P3A. This circuit configuration is configured in accordance with the control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =1) and a control signal (φ ｓａ = 1, φ ｓｂ = 0, φ １ = 1, φ ２ = 0, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0079] 3(e), the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 27 is connected to the output 21b2 of the D / A converter circuit 21 and the second reference potential GND2. As a result, the second capacitor 27 receives the second reference voltage V ＲＬ The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. That is, when the integral gain G is set to 0.5, the input value V ＩＮ is stored only in the first capacitor 25.

[0080] Next, following the third storage operation P3A, the A / D converter 11 performs a third calculation operation P3B. As shown in FIG. 3(f), the third calculation operation P3B is executed by the same circuit as the first calculation operation P1B described above. Therefore, a detailed description of the third calculation operation P3B will be omitted.

[0081] In the third calculation operation P3B, the output of the A / D conversion circuit 17 is as follows:

[0082] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (M) is generated.

[0083] By the way, the conversion reference voltage is V ＲＣＨ , V ＲＣＬ When two types of integration are used, log ２ (2M) bit A / D conversion is possible. For example, an input value V ＩＮ For the calculated value V Ｏ The amplitude of V becomes 1.5 V, which may exceed the 1.0 V input range of the cyclic type in the subsequent stage. ＩＮ By reducing the capacitance of the capacitor that stores the integral gain G, the calculated value V Ｏ However, suppressing the integral gain G causes two problems.

[0084] The first problem is a reduction in the number of output bits. ＲＣＨ and the second conversion reference voltage V ＲＣＬ In principle, when M integrations are performed, 2M (2M-2 or 2M-3) aliasing occurs. However, in order to prevent the integration from diverging, if the input amplitude is 1V, the integral voltage without aliasing (1×M×G) and the sum of the aliasing voltages (2×M×V Ｒ ) must be equal. Ｒ= (1 × M × G) / (2 × M) = 0.5 × G. However, due to the need to share the circuit with the subsequent cyclic A / D converter, V Ｒ = G, so the number of turns is n = (M × G) / V Ｒ =(M×G) / G=M(log ２ (M) bits), and the number of bits that should be obtained is log ２ The resolution is one bit less than that of (2M).

[0085] The second problem is a decrease in noise reduction performance. By reducing the integral gain to 1 / 2, the noise reduction performance by integration is reduced to 1 / √2.

[0086] Therefore, this A / D converter 11 reduces the number of capacitors that store analog signals in the k-th integration operation, which corresponds to the next integration operation, from the number of capacitors that store analog signals in the k-1th integration operation among the multiple integration operations. With this configuration, it becomes possible to make the k-th integration gain G, which corresponds to the next integration operation, smaller than the k-1th integration gain G among the multiple integration operations. In other words, in the multiple integration operations, the input value V ＩＮ The capacitance of the capacitor that stores the calculated value V obtained by M integral operations is not constant, but is changed according to the number of integral operations. Ｏ In order to keep the integral gain G within a predetermined value, the integral gain G is not suppressed in all of the M integral operations, and the calculated value V Ｏ As a result, in the integration operation such as the k-1th time where the integral gain G is not suppressed, a sufficient integral gain G can be obtained, and the noise reduction effect can be sufficiently ensured. On the other hand, since the integral gain G is suppressed in the integration operation in the latter time, the calculated value V obtained as a result of the Mth integration operation can be suppressed. Ｏ It is possible to prevent the value from becoming larger than a predetermined value.

[0087] 4 shows an example of the conversion characteristics of the A / D converter 11. In this example, the number of integrations is set to 5 (M=5), the integral gains G(k) are set to G(1)=1.5, G(2)=1.0, G(3)=1.0, G(4)=1.0, and G(5)=0.5, and the first conversion reference voltage V ＲＣＨ is set to 1.0 V, and the second conversion reference voltage V ＲＣＬ was set to 0.5 V. Graph P5a corresponds to the first integral operation, graph P5b corresponds to the second integral operation, graph P5c corresponds to the third integral operation, graph P5d corresponds to the fourth integral operation, and graph P5e corresponds to the fifth integral operation. In particular, as shown in graph P5e, the calculated value V Ｏ is able to fall within the desired range (here, 1.0 V). Therefore, the A / D converter 11 of this embodiment can obtain a good noise reduction effect and high resolution while keeping the calculation result of the integral operation within the desired range.

[0088] In short, in the A / D converter 11 using folding integration used in an image sensor, the integral gain G is made variable over multiple integration operations. As a result, the A / D converter 11 of the first embodiment can increase the resolution by one bit and double the integral gain (S / N ratio is √2 times). Therefore, the A / D converter 11 of the first embodiment has high resolution and low noise.

[0089] Next, a second A / D conversion operation in the A / D converter 11 shown in Fig. 1 will be described. The second A / D conversion operation is a cyclic A / D conversion operation Y. The cyclic A / D conversion operation Y in the A / D converter 11 will be described below.

[0090] 5(a), 5(b), and 5(c) are circuit diagrams for explaining the second A / D conversion operation, in which the A / D conversion circuit 17 generates a digital value D using two comparators 17a and 17b.

[0091] First, the gain stage 15 performs a second initial storage operation Y1A as shown in FIG. 5A. In the second initial storage operation Y1A, the calculated value VＯ (M) is stored in the first capacitor 25, the second capacitor 27, and the third capacitor 29. In the second initial storage operation Y1A, the gain stage 15 stores the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 1, φ ２ = 0, φ Ｆ = 1, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 1, S Ｆ = 0, S Ｃ The D / A converter circuit 21 receives a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ In the second initial storage operation Y1A, the calculated value V Ｏ (M) is provided to the comparators 17a and 17b. The comparators 17a and 17b use the provided calculated value V Ｏ A digital value D is generated based on (M).

[0092] Subsequently, following the second initial storage operation Y1A, the gain stage 15 stores the digital value D (=B １ +B ０ 5B or 5C, the gain stage 15 performs a second calculation operation Y1B according to the value of V. In the second calculation operation Y1B, the gain stage 15 generates a calculation value V by using the operational amplifier circuit 23, the first capacitor 25, the second capacitor 27, and the third capacitor 29. Ｏ Generate.

[0093] In the second calculation operation Y1B, the gain stage 15 receives the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 0, S ＣIn the second operational operation Y1B, the third capacitor 29 is connected between the output 23b and the first input 23a of the operational amplifier circuit 23. The first capacitor 25 and the second capacitor 27 are connected to the D / A converter circuit 21, and the digital value D (=B １ +B ０ ) the voltages provided to the first capacitor 25 and the second capacitor 27 are controlled.

[0094] When D=2, the switch circuit 31 outputs a control signal (φ ＤＨａ = 1, φ ＤＨｂ = 1, φ ＤＬａ = 0, φ ＤＬｂ As a result, when D=2, the first reference voltage V ＲＨ In this case, the first capacitor 25 and the second capacitor 27 are respectively connected to the first reference voltage V ＲＨ Receive.

[0095] When D=0, the switch circuit 31 outputs a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 1, φ ＤＬｂ As a result, when D=0, the second reference voltage V ＲＬ In this case, the first capacitor 25 and the second capacitor 27 are respectively connected to the second reference voltage V ＲＬ Receive.

[0096] When D=1, the switch circuit 31 outputs a control signal (φ ＤＨａ = 1, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ As a result, when D=1, the output 21a1 of the D / A converter circuit 21 receives the first reference voltage V ＲＨ The output 21b2 is provided with a second reference voltage V ＲＬ In this case, the first capacitor 25 is connected to the first reference voltage V ＲＨ The second capacitor 27 receives a second reference voltage VＲＬ Receive.

[0097] Subsequently, the gain stage 15 performs the second storage operation Y1A following the second calculation operation Y1B, as shown in FIG. 5A. In the second storage operation Y1A, the calculated value V Ｏ is stored in the first capacitor 25, the second capacitor 27, and the third capacitor 29.

[0098] The gain stage 15 then repeats the second calculation operation Y1B and the second storage operation Y1A a predetermined number of times as a cyclic A / D conversion operation. Ｏ If the digital value obtained after the jth cyclic operation for (M) is represented by D(j), the calculated value V Ｏ (M)-V ＣＯＭ The relationship between the digital value D(j) and the digital value D(j) is given by equation (10).

[0099] Second Embodiment Now, 1.5, 1.0, and 0.5 have been exemplified as integral gain G that can be set by the A / D converter 11 of the first embodiment. As will be shown in a modified example later, the A / D converter 11A can also set the integral gain G to 2.0 or 0. In other words, the A / D converter 11A of the first embodiment can set the integral gain G in increments of 0.5. The A / D converter of the second embodiment can set the integral gain G in increments that are finer than the A / D converter of the first embodiment.

[0100] 6 is a circuit diagram of an A / D converter 11A of the second embodiment. The difference from the A / D converter 11 of the first embodiment shown in FIG. 1 is that the second capacitor 27 of the A / D converter 11 is divided into two capacitors (a second capacitor 28A and a fourth capacitor 28B). That is, the A / D converter 11A of the second embodiment includes a first capacitor 25, a second capacitor 28A, a third capacitor 29, and a fourth capacitor 28B. The relationship between the capacitances of the respective capacitors is as follows, where C is the capacitance of the third capacitor 29: １ａ: C / 2 Capacitance C of the second capacitor 28A １ｂａ : C / 4 Capacitance C of the third capacitor 29 ２ : C: Capacitance C of the fourth capacitor 28B １ｂｂ : C / 4 (fourth capacitance) The fourth capacitor 28B is connected in parallel to the second capacitor 28A. Therefore, the total capacitance of the second capacitor 28A and the fourth capacitor 28B in the second embodiment is 1 / 4 of the capacitance C of the second capacitor 27 in the first embodiment. １ｂ In other words, the second capacitor 28A and the fourth capacitor 28B in the second embodiment are obtained by dividing the second capacitor 27 in the first embodiment.

[0101] For example, the integral gain G(k) can be set as follows: That is, in the A / D converter 11A, the integral gain G can be set in increments of 0.25: Integral gain G(1) = 1.75 Integral gains G(2) to G(M-1) = 1.0 Integral gain G(M) = 0.25 Note that the above values ​​of integral gain G(k) are examples.

[0102] It should be noted that the total capacitance of the second capacitor 28A and the fourth capacitor 28B needs to be the same as the capacitance of the second capacitor 27, so the capacitance C １ｂａ and the capacitance C of the fourth capacitor 28B １ｂｂ is not limited to the same value (=C / 4) as described above. For example, the capacitance C of the second capacitor 28A is １ｂａ is set to 0.1×C, and the capacitance C of the fourth capacitor 28B １ｂｂ may be set to 0.4×C.

[0103] Furthermore, the A / D converter 11A has two additional switches 84 and 85. The switch 84 allows the fourth capacitor 28B to be connected to the reference voltage source 35. The switch 85 allows the fourth capacitor 28B to be connected to the input 15a of the gain stage 15A.

[0104] The operation of the A / D converter 11A will be described. As shown in Fig. 7, the A / D converter 11A performs a first storage operation P1A and a first calculation operation P1B. These first storage operation P1A and first calculation operation P1B correspond to the first integration operation of M integration operations (see Fig. 7). The integral gain G(1) in the first storage operation P1A and first calculation operation P1B is 1.75.

[0105] The A / D converter 11A performs a first storage operation P1A. FIG. 8A shows a circuit configuration for the first storage operation P1A. This circuit configuration is implemented by a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =0) and a control signal (φ ｓａ = 1, φ ｓｂ = 1, φ １ = 1, φ ２ = 0, φ ３ = 0, φ ４ = 1, φ Ｆ = 1, φ Ｉ = 1, φ Ｔ = 0, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0106] 8A, the first capacitor 25 is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 28A is connected to the input 15a of the gain stage 15A and to the second reference potential GND2. As a result, the second capacitor 28A also receives the input value V ＩＮ The third capacitor 29 is connected to the input 15a of the gain stage 15A and the operational amplifier circuit 23. Specifically, one end of the third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. As a result, the third capacitor 29 also receives the input value V ＩＮ The fourth capacitor 28B is connected to the reference voltage source 35 and the second reference potential GND2. As a result, the fourth capacitor 28B receives the second reference voltage VＲＬ That is, when the integral gain G is set to 1.75, the input value V ＩＮ is stored in the first capacitor 25, the second capacitor 28A and the third capacitor 29.

[0107] Following the first storage operation P1A, the A / D converter 11A performs a first calculation operation P1B. FIG. 8B shows the circuit configuration for the first calculation operation P1B. This circuit configuration is implemented by controlling the control signal (φ ＤＨａ = 1, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =1) and a control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ ３ = 0, φ ４ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0108] 8B, the first capacitor 25 is connected to the output 21a1 of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the first capacitor 25 is connected to the first reference voltage V ＲＨ The second capacitor 28A is connected to the output 21b2 of the D / A converter circuit 21 and the first input 23a of the operational amplifier circuit 23. As a result, the second capacitor 28A receives the second standard reference voltage V ＲＬ The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the reference voltage source 35 and the first input 23a of the operational amplifier circuit 23. As a result, the fourth capacitor 28B receives the second reference voltage V ＲＬ Receive.

[0109] Furthermore, the comparator 17a converts the first conversion reference voltage V ＲＣＨ The comparator 17a receives the calculated value V Ｏ(1) into the first conversion reference voltage V ＲＣＨ and the calculated value B according to the comparison result is １ Furthermore, the comparator 17b outputs the second conversion reference voltage V ＲＣＬ The comparator 17b receives the calculated value V Ｏ (1) into the second conversion reference voltage V ＲＣＬ and the calculated value B according to the comparison result is ０ Output (1).

[0110] Specifically, the output (digital value D) of the A / D conversion circuit 17 is as follows:

[0111] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (1) is generated.

[0112] Next, the A / D converter 11A performs a second storage operation P2A and a second calculation operation P2B. The integral gain G(2) in the second storage operation P2A and the second calculation operation P2B is 1.0.

[0113] 8C shows the circuit configuration for the second storage operation P2A in which the integral gain G(2) is set to 1.0. This circuit configuration is implemented by controlling the control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ =0) and a control signal (φ ｓａ = 1, φ ｓｂ = 1, φ １ = 1, φ ２ = 0, φ ３ = 1, φ ４ = 0, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0114] 8C, the first capacitor 25 is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 28A is connected to the input 15a of the gain stage 15A and to the second reference potential GND2. As a result, the second capacitor 28A also receives the input value V ＩＮ The third capacitor 29 is connected to the first input 23a of the operational amplifier circuit 23 and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the input 15a of the gain stage 15A and the second reference potential GND2. As a result, the fourth capacitor 28B also receives the input value V ＩＮ Receive.

[0115] That is, when the integral gain G is set to 1.0, the input value V ＩＮ is stored in the first capacitor 25, the second capacitor 28A and the fourth capacitor 28B.

[0116] Following the second storage operation P2A, the A / D converter 11A performs a second calculation operation P2B, as shown in FIG. 8(d). The second calculation operation P2B is executed by the same circuit configuration (see FIG. 8(b)) as the first calculation operation P1B described above. Therefore, a detailed description of the second calculation operation P2B will be omitted.

[0117] In the second calculation operation P2B, the output of the A / D conversion circuit 17 is as follows:

[0118] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (k) is generated.

[0119] Next, the A / D converter 11A performs a third storage operation P3A and a third calculation operation P3B. The integral gain G(M) in the third storage operation P3A and the third calculation operation P3B is 0.25. FIG. 8(e) shows the circuit configuration in the third storage operation P3A. This circuit configuration is implemented by controlling the control signal (φ ＤＨａ = 0, φ ＤＨｂ= 0, φ ＤＬａ = 1, φ ＤＬｂ =0) and a control signal (φ ｓａ = 0, φ ｓｂ = 1, φ １ = 1, φ ２ = 0, φ ３ = 0, φ ４ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0120] 8(e), the first capacitor 25 is connected to the output 21a2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the second reference voltage V ＲＬ The second capacitor 28A is connected to the input 15a of the gain stage 15A and to the second reference potential GND2. As a result, the second capacitor 28A receives the input value V ＩＮ The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. The fourth capacitor 28B is connected to the reference voltage source 35 and the second reference potential GND2. As a result, the fourth capacitor 28B also receives the second reference voltage V ＲＬ Receive.

[0121] That is, when the integral gain G is set to 0.25, the input value V ＩＮ is stored only in the second capacitor 28A.

[0122] Following the third storage operation P3A, the A / D converter 11A performs a third calculation operation P3B, as shown in FIG. 8(f). The third calculation operation P3B is executed by the same circuit configuration (see FIG. 8(b)) as the first calculation operation P1B described above. Therefore, a detailed description of the third calculation operation P3B will be omitted.

[0123] In the third calculation operation P3B, the output of the A / D conversion circuit 17 is as follows:

[0124] According to this connection configuration, the output 23b of the operational amplifier circuit 23 is the calculated value V Ｏ (M) is generated.

[0125] Next, a second A / D conversion operation in the A / D converter 11A shown in Fig. 6 will be described. A cyclic A / D conversion operation in the A / D converter 11A will be described below.

[0126] 9A, 9B, and 9C are circuit diagrams for explaining the second A / D conversion operation.

[0127] First, the gain stage 15A performs a second initial storage operation Y1A as shown in FIG. 9A. In the second initial storage operation Y1A, the calculated value V Ｏ (M) is stored in the first capacitor 25, the second capacitor 28A, the third capacitor 29, and the fourth capacitor 28B. In the second initial storage operation Y1A, the gain stage 15A stores the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 1, φ ２ = 0, φ ３ = 1, φ ４ = 0, φ Ｆ = 1, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 1, S Ｆ = 0, S Ｃ The D / A converter circuit 21 receives a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ In the second initial storage operation Y1A, the calculated value V Ｏ (M) is provided to the comparators 17a and 17b. The comparators 17a and 17b use the provided calculated value V Ｏ A digital value D is generated based on (M).

[0128] Subsequently, following the second initial storage operation Y1A, the gain stage 15A stores the digital value D (=B１ +B ０ 9B or 9C, the gain stage 15A performs a second calculation operation Y1B according to the value of V. In the second calculation operation Y1B, the gain stage 15A generates a calculation value V by using the operational amplifier circuit 23, the first capacitor 25, the second capacitor 28A, the third capacitor 29, and the fourth capacitor 28B. Ｏ Generate.

[0129] When the output of the A / D conversion circuit 17 is D=2, the switch circuit 31 outputs a control signal (φ ＤＨａ = 1, φ ＤＨｂ = 1, φ ＤＬａ = 0, φ ＤＬｂ When the output of the A / D conversion circuit 17 is D=2, the gain stage 15A receives the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ ３ = 1, φ ４ = 0, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 0, S Ｃ 9B). That is, the first capacitor 25, the second capacitor 28A, and the fourth capacitor 28B receive the first reference voltage V ＲＨ Receive.

[0130] When the output of the A / D conversion circuit 17 is D=0, the switch circuit 31 outputs a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 1, φ ＤＬｂ When the output of the A / D conversion circuit 17 is D=0, the gain stage 15A receives the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ ３ = 0, φ ４ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φＲ = 0, S Ｆ = 0, S Ｃ 9B). That is, the first capacitor 25, the second capacitor 28A, and the fourth capacitor 28B receive the second reference voltage V ＲＬ Receive.

[0131] When the output of the A / D conversion circuit 17 is D=1, the switch circuit 31 outputs a control signal (φ ＤＨａ = 1, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ When the output of the A / D conversion circuit 17 is D=1, the gain stage 15A receives the control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 0, φ ２ = 1, φ ３ = 0, φ ４ = 1, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 0, S Ｃ 9C). That is, the first capacitor 25 receives the first reference voltage V ＲＨ The second capacitor 28A and the fourth capacitor 28B receive a second reference voltage V ＲＬ Receive.

[0132] The gain stage 15A then repeats the second storage operation Y1A and the second calculation operation Y1B a predetermined number of times as a cyclic A / D conversion operation, thereby obtaining an output value that is a digital value from an input value that is an analog value.

[0133] The A / D converter 11A of the second embodiment can also achieve a favorable noise reduction effect while keeping the calculation result of the integral operation within a desired range, as with the A / D converter 11 of the first embodiment. Furthermore, the A / D converter 11A of the second embodiment divides the second capacitor 27 of the first embodiment into a second capacitor 28A and a fourth capacitor 28B, that is, increases the number of capacitors that store analog signals, thereby enabling the integral gain G to be set more precisely than in the A / D converter 11 of the first embodiment.

[0134] The A / D converter and the A / D conversion method according to the present disclosure have been described above. The A / D converter and the A / D conversion method according to the present disclosure are not limited to the above embodiments.

[0135] <Modification 1> In M folding integral type A / D conversion operations, the setting of the integral gain G is not limited to the manner described in the first embodiment. In Modification 1, as shown in FIG. 10 , the integral gain G(k) may be set as follows: Integral gain G(1) = 2.0 Integral gains G(2) to G(M-1) = 1.0 Integral gain G(M) = 0 That is, in Modification 1, the integral gain G(1) in the first integral operation is set to 2. Then, the integral gain G(M) in the Mth integral operation is set to 0. Note that the integral gains G(2) to G(M-1) in the second to (M-1)th integral operations are the same (= 1) as in the first embodiment.

[0136] Fig. 11(a) shows the circuit configuration in the first storage operation P1A in which the integral gain G(1) = 2.0. Fig. 11(e) shows the circuit configuration in the third storage operation PNA in which the integral gain G(M) = 0. Note that the circuit configurations shown in Figs. 11(b), 11(c), 11(d), and 11(f) are the same as those shown in Figs. 3(b), 3(c), 3(d), and 3(f), respectively, described in the first embodiment.

[0137] The circuit configuration shown in FIG. 11(a) is a circuit diagram of a clock generator 61. ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 0, φ ＤＬｂ=0) and a control signal (φ ｓａ = 1, φ ｓｂ = 1, φ １ = 1, φ ２ = 0, φ Ｆ = 1, φ Ｉ = 1, φ Ｔ = 0, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0138] 11A, the first capacitor 25 is connected to the input 15a of the gain stage 15 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the input value V ＩＮ The second capacitor 27 is connected to the input 15a of the gain stage 15 and to the second reference potential GND2. As a result, the second capacitor 27 also receives the input value V ＩＮ The third capacitor 29 is connected to the input 15a of the gain stage 15 and the operational amplifier circuit 23. As a result, the third capacitor 29 also receives the input value V ＩＮ That is, when the integral gain G is set to 2.0, the input value V ＩＮ is stored in the first capacitor 25, the second capacitor 27 and the third capacitor 29.

[0139] The circuit configuration shown in FIG. 11(e) is a circuit configuration in which a control signal (φ ＤＨａ = 0, φ ＤＨｂ = 0, φ ＤＬａ = 1, φ ＤＬｂ =1) and a control signal (φ ｓａ = 0, φ ｓｂ = 0, φ １ = 1, φ ２ = 0, φ Ｆ = 0, φ Ｉ = 0, φ Ｔ = 1, φ Ｒ = 0, S Ｆ = 1, S Ｃ = 0).

[0140] 11(e), the first capacitor 25 is connected to the output 21a2 of the D / A conversion circuit 21 and the second reference potential GND2. As a result, the first capacitor 25 is connected to the second reference voltage V ＲＬ The second capacitor 27 is connected to the output 21b2 of the D / A converter circuit 21 and the second reference potential GND2. As a result, the second capacitor 27 also receives the second reference voltage V ＲＬ The third capacitor 29 is connected to the first input 23a and the output 23b of the operational amplifier circuit 23. In other words, when the integral gain G is set to 0, the input value V ＩＮ is not stored in any capacitor.

[0141] <Modification 2> Furthermore, in Modification 2, as shown in Fig. 12(a), integral gain G(k) may be set as follows: integral gain G(1) = 0.5 integral gain G(2) to G(M) = 1.0 integral gain G(M+1) = 0.5 In other words, in Modification 2, integral gain G(1) in the first integral operation is set to 0.5. integral gains G(2) to G(M) in the second to Mth integral operations are 1.0, and integral gain G(M+1) in the M+1th integral operation is 0.5.

[0142] <Modification 3> Furthermore, in Modification 3, as shown in Fig. 12(b), integral gain G(k) may be set as follows: Integral gain G(1) to G(M) = 1.0 Integral gain G(M+1) = 0 In other words, in Modification 3, integral gains G(1) to G(M) in the first to Mth integral operations are set to 1. Then, integral gain G(M+1) in the M+1th integral operation is set to 0.

[0143] Some of the exemplary A / D converters described above can be applied to an image sensor device. FIG. 13 is a diagram showing a pixel of the image sensor. The image sensor device includes a cell array and a converter array. The cell array includes a plurality of image sensor cells 2a arranged two-dimensionally. The converter array is connected to the cell array and includes a plurality of A / D converters 11. The A / D converters 11 are connected to the image sensor cells 2a via column lines 8 of the cell array.

[0144] The image sensor cell 2a is, for example, a CMOS image sensor cell. The photodiode DF receives light L for one pixel associated with an image. The selection transistor M Ｓ The gate of the reset transistor M is connected to a row selection line S extending in the row direction. Ｒ The gate of the transfer transistor M is connected to the reset line R. Ｔ The gate of the photodiode DF is connected to a transfer selection line TX extending in the row direction. Ｔ The floating diffusion layer FD is connected to the reset transistor M Ｒ and connected to the reset potential line Reset via the transistor M Ａ is connected to the gate of the transistor M Ａ One current terminal (e.g., drain) of the select transistor M Ｓ is connected to the column line 8 via the transistor M Ａ selects the potential of the transistor M according to the amount of charge in the floating diffusion layer FD. Ｓ Column lines via

[0145] The image sensor cell 2a having this structure generates a first signal indicating a reset level and a second signal indicating a signal level superimposed on the reset level. That is, in the image sensor cell 2a, first, a control signal provided to the reset line R is applied to the reset transistor M Ｒ , and the floating diffusion layer FD is reset. Ａ This reset level is read out via the charge transfer control signal. Ｔ, and a light-induced signal charge is transferred from the photodiode DF to the floating diffusion layer FD. Ａ In this manner, the image sensor cell 2a can generate a first signal S1 indicating a reset level and a second signal S2 indicating a signal level superimposed on the reset level.

[0146] <Analysis Example 1> Fig. 14(a) shows the relationship between the input and output of the gain stage 15. This Fig. 14(a) is the result of a simulation. The horizontal axis represents the input value V ＩＮ The vertical axis indicates the calculated value V Ｏ In this simulation, the number of integrations was 16 (M=16, 5 bits). In the 16 integration operations, the first integration gain G(1) was set to 1.5, the second to fifteenth integration gains G(2) to G(15) were set to 1.0, and the 16th integration gain G(16) was set to 0.5. Furthermore, the following values ​​were used for the simulation. First standard reference voltage / V ＲＨ : 2.0V Second standard reference voltage / V ＲＬ : 1.0V First conversion reference voltage / folding integral type / V ＲＣＨ : 1.95V Second conversion reference voltage / folding integral type / V ＲＣＬ The values ​​for the cyclic operation are as follows: First conversion reference voltage / cyclic / V ＲＣＣＨ : 1.625V Second conversion reference voltage / cyclic type / V ＲＣＣＬ : 1.375V

[0147] As shown in FIG. 14(a), the output calculated value V Ｏ The range of V can be kept within the range of +1V to +2V. Furthermore, according to the setting of the integral gain G described above, the average integral gain in the 16 integral operations is 1. In other words, even if the average integral gain is set to 1, the calculated value V ＯIt was found that it was possible to keep it within the desired range (+1V to +2V). In this case, the integral gain is doubled compared to when the integral gain from the 1st to 16th times is set to 0.5. As a result, it was confirmed that the S / N ratio for random noise is improved by √2 times. Furthermore, by setting the integral gains G(2) to G(15) to 1.0, matching with the folding voltage (0.5V) is achieved. As a result, the resolution is log ２ It was also confirmed that (2M) bits could be obtained.

[0148] 14B is a graph showing an evaluation of the integral nonlinearity of the total A / D conversion operation with the above settings and seven cyclic A / D conversion operations (8 bits). From FIG. 14B, it was confirmed that the nonlinearity was within a range of ±0.5 bits. It was also confirmed that this range did not have a significant effect on the required number of bits.

[0149] <Analysis Example 2> Figure 15(a) shows the results of another simulation showing the relationship between the input and output of the gain stage 15. In this simulation, the number of integrations was set to 17 (M = 17, 5 bits). In the 17 integration operations, the first integration gain G(1) was set to 0.5, the second to sixteenth integration gains G(2) to G(16) were set to 1.0, and the seventeenth integration gain G(17) was set to 0.5. Furthermore, for the simulation, the following numerical values ​​were adopted, the same as in Analysis Example 1: first standard reference voltage / V ＲＨ : 2.0V Second standard reference voltage / V ＲＬ : 1.0V First conversion reference voltage / folding integral type / V ＲＣＨ : 1.95V Second conversion reference voltage / folding integral type / V ＲＣＬ The values ​​for the cyclic operation are as follows: First conversion reference voltage / cyclic / V ＲＣＣＨ : 1.625V Second conversion reference voltage / cyclic type / V ＲＣＣＬ : 1.375V

[0150] As shown in FIG. 15(a), even with the above-mentioned setting of the integral gain G, the calculated value VＯ It was confirmed that the range of the voltage difference was within the range of +1 V to +2 V. FIG. 15(b) is a graph evaluating the integral nonlinearity of the total A / D conversion operation with the above settings and seven cyclic A / D conversion operations (8 bits). As in analysis example 1, FIG. 15(b) confirms that the nonlinearity is within a range of ±0.5 bits. It was also confirmed that this range does not have a significant effect on the required number of bits.

[0151] <Analysis Example 3> Figure 16(a) shows the results of a simulation showing the relationship between input and output, taking into account not only folding integral type A / D conversion operation but also cyclic type operation. In this simulation, the number of integrations was 16 (M = 16, 5 bits). In the 16 integration operations, the first integration gain G(1) was set to 2.0, the second to fifteenth integration gains G(2) to G(15) were set to 1.0, and the 16th integration gain G(16) was set to 0. Furthermore, the following values ​​were used for the simulation: first standard reference voltage / V ＲＨ : 2.0V Second standard reference voltage / V ＲＬ : 1.0V First conversion reference voltage / folding integral type / V ＲＣＨ : 2.1V Second conversion reference voltage / folding integral type / V ＲＣＬ The values ​​for the cyclic operation are as follows: First conversion reference voltage / cyclic / V ＲＣＣＨ : 1.625V Second conversion reference voltage / cyclic type / V ＲＣＣＬ : 1.375V

[0152] As shown in Figure 16(a), it was confirmed that the output range could be kept within the range of +1.0 V to +1.6 V (0.6 V). Figure 16(b) is a graph evaluating the integral nonlinearity of the total A / D conversion operation when the folding integral type A / D conversion operation was performed with eight integrations (M = 8, 4 bits) and when the cyclic A / D conversion operation was performed eight times (9 bits) with the above voltage settings. Figure 16(b) confirms that the mismatch error, which indicates nonlinearity, was 0.1% when the amplifier gain was 85 dB.

[0153] [Note] The A / D converter and A / D conversion method described above are as described in the following [1] to

[11] . These have been described in detail based on the above-mentioned embodiments and modifications.

[0154] [1] A first example is an A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling an input signal and integrating the sampled value, and includes: a gain stage that outputs a calculated value based on the analog signal; and an A / D conversion circuit that compares the calculated value output by the gain stage with a conversion reference voltage and outputs a result that can be used to generate the digital value, wherein the gain stage generates the calculated value based on the analog signal using a first integral gain in a k-th operation (k is an integer equal to or less than M-1) of the operations that are performed M times (M is an integer equal to or greater than 2), and generates the calculated value based on the analog signal using a second integral gain in a k+1-th operation, and the second integral gain is smaller than the first integral gain.

[0155] [2] A second example is an A / D converter according to the first example, wherein the gain stage generates the calculated value based on the analog signal using a third integral gain in a first operation, and the third integral gain is greater than the first integral gain.

[0156] [3] A third example is an A / D converter according to the first or second example, in which the third A / D converter uses the first integral gain in the second to (M-1)th operations in the first or second A / D converter, and uses the second integral gain in the Mth operation.

[0157] [4] A fourth example is an A / D converter selected from the first, second, and third examples, in which the first integral gain is 1 or greater, and the second integral gain is 0 or greater and less than 1.

[0158] [5] A fifth example is an A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integration of the sampled value, and includes: a gain stage that outputs an arithmetic value based on the analog signal; and an A / D conversion circuit that compares the arithmetic value output by the gain stage with a conversion reference voltage and outputs a result that can be used to generate the digital value, wherein the gain stage has a stage input that receives the analog signal, an operational amplifier circuit that generates the arithmetic value based on the analog signal, a stage output that outputs the arithmetic value to the A / D conversion circuit, a front-stage capacitance unit that can be connected to the stage input and an input of the operational amplifier circuit and includes at least one front-stage capacitor, and a feedback capacitance unit that can be connected to the stage input and an output of the operational amplifier circuit and includes one feedback capacitor, The gain stage selectively configures a first circuit and a second circuit different from the first circuit for sampling the input signal, and the first circuit stores the analog signal in at least one of the upstream capacitors by connecting the upstream capacitance section to the stage input so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a predetermined capacitance ratio, and stores the analog signal in the feedback capacitor by connecting the feedback capacitance section to the stage input, and the second circuit stores the analog signal in at least one of the upstream capacitors by connecting the upstream capacitance section to the stage input so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a capacitance ratio smaller than the capacitance ratio in the first circuit, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitance section from the stage input.

[0159] [6] A sixth example is the A / D converter according to the fifth example, in which the ratio of the capacitance of the front-stage capacitance section to the capacitance of the feedback capacitance section depends on the magnitude of the integral gain.

[0160] [7] A seventh example is an A / D converter according to the fifth or sixth example, in which the operation is executed M times (M is an integer equal to or greater than 2), and in the first operation, the first circuit is used to sample the input signal so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is the predetermined capacitance ratio.

[0161] [8] An eighth example is an A / D converter selected from the fifth, sixth, and seventh examples, in which the operation is executed M times (M is an integer greater than or equal to 2), and in sampling the input signal in the second to (M-1)th operations, the second circuit is used to set the ratio of the capacitance of the front-stage capacitance section to the capacitance of the feedback capacitance section to a capacitance ratio smaller than the predetermined capacitance ratio when using the first circuit.

[0162] [9] A ninth example is an A / D converter selected from the fifth, sixth, seventh, and eighth examples, in which the operation is executed M times (M is an integer greater than or equal to 2), and in the sampling of the input signal in the second to (M-1)th operations, the number of upstream capacitors that store the analog signal in the second circuit is set to 2 or more so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first circuit, and in the sampling of the input signal in the Mth operation, the number of upstream capacitors that store the analog signal in the second circuit is set to 0 or 1 so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a second capacitance ratio that is smaller than the first capacitance ratio.

[0163]

[10] A tenth example is an A / D converter selected from the fifth, sixth, seventh, eighth, and ninth examples, in which the capacitance of the feedback capacitor is greater than the capacitance of the previous stage capacitor.

[0164]

[11] An eleventh example is an A / D converter selected from the fifth, sixth, seventh, eighth, and ninth examples, in which the capacitance of the feedback capacitor is larger than the capacitance of a first preceding capacitor, and the capacitance of the first preceding capacitor is different from the capacitance of a second preceding capacitor that is different from the first preceding capacitor.

[0165]

[12] A twelfth example is an A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling an input signal and integrating the sampled value, the method comprising: a step of generating a first calculated value based on the analog signal by performing the operation using a first integral gain; and a step of generating a second calculated value based on the analog signal by performing the operation using a second integral gain after the step of generating the first calculated value, wherein the second integral gain is smaller than the first integral gain.

[0166]

[13] A thirteenth example is an A / D conversion method according to the twelfth example, further comprising, before the step of generating the first calculated value, a step of generating a third calculated value based on the analog signal by performing the operation using a third integral gain, and the third integral gain is greater than the first integral gain.

[0167]

[14] A fourteenth example is an A / D conversion method according to the twelfth or thirteenth example, in which the operation is executed M times (M is an integer equal to or greater than 2), and in the second to (M-1)th operations, the step of generating the first calculated value is executed, and in the Mth operation, the step of generating the second calculated value is executed.

[0168]

[15] A fifteenth example is an A / D conversion method selected from the twelfth example, the thirteenth example, and the fourteenth example, in which the first integral gain is 1 or more, and the second integral gain is 0 or more and less than 1.

[0169]

[16] A sixteenth example is an A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integration of the sampled value, the method including: a sampling step of the input signal, in which the analog signal is stored in at least a front-stage capacitance section connectable to a stage input of a gain stage that outputs an operational value based on the analog signal, the front-stage capacitance section including at least one front-stage capacitor, and a feedback capacitance section including one feedback capacitor; and an integration step of the sampled value, in which the operational value is generated at an output of an operational amplifier circuit provided in the gain stage by connecting at least the front-stage capacitance section to an input of the operational amplifier circuit, the first storing comprises storing the analog signal in at least one of the upstream capacitors by connecting the upstream capacitance unit to the stage input so that a ratio between the capacitance of the upstream capacitance unit and the capacitance of the feedback capacitance unit is a predetermined capacitance ratio, and storing the analog signal in the feedback capacitor by connecting the feedback capacitance unit to the stage input; and the second storing comprises storing the analog signal in at least one of the upstream capacitors by connecting the upstream capacitance unit to the stage input so that a ratio between the capacitance of the upstream capacitance unit and the capacitance of the feedback capacitance unit is a capacitance ratio smaller than the predetermined capacitance ratio in the first storing, and not storing the analog signal in the feedback capacitor by disconnecting the feedback capacitance unit from the stage input.

[0170]

[17] A seventeenth example is the A / D conversion method according to the sixteenth example, in which the ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section depends on the magnitude of the integral gain.

[0171]

[18] An 18th example is an A / D conversion method according to the 16th or 17th example, in which the operation is executed M times (M is an integer equal to or greater than 2), and in the sampling step of the input signal in the first operation, the first storage is executed to set the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section to the predetermined capacitance ratio.

[0172]

[19] A 19th example is an A / D conversion method selected from the 16th, 17th, and 18th examples, in which the operation is executed M times (M is an integer equal to or greater than 2), and in the sampling steps of the input signal in the second to (M-1)th operations, the second storage is executed to set the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section to a capacitance ratio smaller than the predetermined capacitance ratio in the first storage.

[0173]

[20] A twentieth example is an A / D conversion method selected from the sixteenth, seventeenth, eighteenth, and nineteenth examples, in which the operation is executed M times (M is an integer greater than or equal to 2), and in the second to (M-1)th operations of sampling the input signal, the number of the upstream capacitors that store the analog signal in the second storage is set to 2 or more so that the ratio between the capacitance of the upstream capacitance unit and the capacitance of the feedback capacitance unit is set to a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage, and in the Mth operation of sampling the input signal, the number of the upstream capacitors that store the analog signal in the second storage is set to 0 or 1 so that the ratio between the capacitance of the upstream capacitance unit and the capacitance of the feedback capacitance unit is set to a second capacitance ratio that is smaller than the first capacitance ratio.

[0174] 2a...image sensor cell, 11...A / D converter, 15...gain stage, 15a...input, 15b...output, 17...A / D conversion circuit, 17a, 17b...comparator, 19...logic circuit, 21...D / A conversion circuit, 23...operational amplifier circuit, 23a...first input, 23b...second input, 25...first capacitor, 27...second capacitor, 29...third capacitor, 31...switch circuit, 43, 49, 51, 53...switches, 33, 35...reference voltage source, 61...clock generator, 70...reference voltage generation unit, B １ , B ０ ...calculated value, C １ａ , C １ｂ , C ２ ...capacitance, D...digital value, V ＣＯＭ ...Reference potential, V ＣＯＮＴ ...Control signal, V ＩＮ ...input value, V Ｏ ...Calculated value, V ＲＣＨ...first conversion reference voltage, V ＲＣＬ ...second conversion reference voltage, V ＲＨ ...first reference voltage, V ＲＬ ...second reference voltage.

Claims

1. An A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integrating the sampled value, comprising: a gain stage that outputs a calculation value based on the analog signal; and an A / D conversion circuit that outputs a result that can be used for generating the digital value by comparing the calculation value output by the gain stage with a conversion reference voltage, wherein the gain stage generates the calculation value based on the analog signal using a first integral gain in a k-th operation (k is an integer equal to or less than M-1) out of the operations that are executed M times (M is an integer equal to or greater than 2), and generates the calculation value based on the analog signal using a second integral gain in a k+1-th operation, and the second integral gain is smaller than the first integral gain.

2. The A / D converter according to claim 1, wherein the gain stage generates the calculated value based on the analog signal using a third integral gain in a first operation, and the third integral gain is greater than the first integral gain.

3. The A / D converter according to claim 1, wherein the first integral gain is used in the second to (M-1)th operations, and the second integral gain is used in the Mth operation.

4. The A / D converter according to claim 1, wherein the first integral gain is equal to or greater than 1, and the second integral gain is equal to or greater than 0 and less than 1.

5. An A / D converter that performs A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and integration of the sampled value, comprising: a gain stage that outputs an arithmetic value based on the analog signal; and an A / D conversion circuit that outputs a result that can be used to generate the digital value by comparing the arithmetic value output by the gain stage with a conversion reference voltage, wherein the gain stage has: a stage input that receives the analog signal; an operational amplifier circuit that generates the arithmetic value based on the analog signal; a stage output that outputs the arithmetic value to the A / D conversion circuit; a front-stage capacitance section that is connectable to the stage input and an input of the operational amplifier circuit and includes at least one front-stage capacitor; and a feedback capacitance section that is connectable to the stage input and an output of the operational amplifier circuit and includes one feedback capacitor, wherein the gain stage selectively configures a first circuit and a second circuit different from the first circuit in sampling the input signal, an A / D converter, wherein the first circuit stores the analog signal in at least one of the front-stage capacitors by connecting the front-stage capacitance section to the stage input in order to set a predetermined capacitance ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section, and stores the analog signal in the feedback capacitor by connecting the feedback capacitance section to the stage input; and the second circuit stores the analog signal in at least one of the front-stage capacitors by connecting the front-stage capacitance section to the stage input in order to set a capacitance ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section smaller than the capacitance ratio in the first circuit, and does not store the analog signal in the feedback capacitor by disconnecting the feedback capacitance section from the stage input.

6. The A / D converter according to claim 5, wherein a ratio between the capacitance of said front-stage capacitance section and the capacitance of said feedback capacitance section corresponds to a magnitude of integral gain.

7. An A / D converter as described in claim 5, wherein the operation is executed M times (M is an integer equal to or greater than 2), and in sampling the input signal in the first operation, the first circuit is used to set the ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section to the specified capacitance ratio.

8. An A / D converter as described in claim 5, wherein the operation is executed M times (M is an integer equal to or greater than 2), and in sampling the input signal in the second to M-1th operations, the second circuit is used to set a capacitance ratio between the capacitance of the front stage capacitance section and the capacitance of the feedback capacitance section to a capacitance ratio smaller than the specified capacitance ratio when the first circuit is used.

9. The A / D converter of claim 5, wherein the operation is executed M times (M is an integer equal to or greater than 2), and wherein in sampling of the input signal in the second to M-1th operations, the number of the front-stage capacitors that store the analog signal in the second circuit is set to 2 or more so that the ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section is a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first circuit, and wherein in sampling of the input signal in the Mth operation, the number of the front-stage capacitors that store the analog signal in the second circuit is set to 0 or 1 so that the ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section is a second capacitance ratio that is smaller than the first capacitance ratio.

10. The A / D converter according to claim 5, wherein the capacitance of said feedback capacitor is greater than the capacitance of said pre-stage capacitor.

11. The A / D converter according to claim 5, wherein the capacitance of the feedback capacitor is greater than the capacitance of a first of the preceding stage capacitors, and the capacitance of the first of the preceding stage capacitors is different from the capacitance of a second of the preceding stage capacitors that is different from the first of the preceding stage capacitors.

12. An A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing an operation including sampling of an input signal and integrating the sampled value, comprising: a step of generating a first calculated value based on the analog signal by performing the operation using a first integral gain; and a step of generating a second calculated value based on the analog signal by performing the operation using a second integral gain after the step of generating the first calculated value, wherein the second integral gain is smaller than the first integral gain.

13. The A / D conversion method according to claim 12, further comprising, prior to the step of generating the first calculation value, a step of generating a third calculation value based on the analog signal by performing the operation using a third integral gain, wherein the third integral gain is greater than the first integral gain.

14. The A / D conversion method according to claim 12, wherein the operation is executed M times (M is an integer equal to or greater than 2), and the second operation to the M-1th operation execute a step of generating the first calculated value, and the Mth operation executes a step of generating the second calculated value.

15. The A / D conversion method according to claim 12, wherein the first integral gain is equal to or greater than 1, and the second integral gain is equal to or greater than 0 and less than 1.

16. An A / D conversion method for performing A / D conversion including folding integration to obtain a digital value from an analog signal by repeatedly performing operations including sampling of an input signal and integration of a sampled value, comprising: a sampling step of the input signal, storing the analog signal in at least a front-stage capacitance section that is connectable to a stage input of a gain stage that outputs an operational value based on the analog signal and that includes at least one front-stage capacitor and a feedback capacitance section that includes one feedback capacitor; and an integration step of the sampled value, generating the operational value at an output of an operational amplifier circuit provided in the gain stage by connecting at least the front-stage capacitance section to an input of the operational amplifier circuit provided in the gain stage; wherein the sampling step of the input signal executes either a first storage or a second storage different from the first storage, and the first storage is performed by storing the analog signal in at least one front-stage capacitor by connecting the front-stage capacitance section to the stage input so that a ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section is a predetermined capacitance ratio, and storing the analog signal in the feedback capacitor by connecting the feedback capacitance section to the stage input; The second storage is an A / D conversion method in which the analog signal is stored in at least one of the upstream capacitors by connecting the upstream capacitance section to the stage input so that the ratio of the capacitance of the upstream capacitance section to the capacitance of the feedback capacitance section is smaller than the specified capacitance ratio in the first storage, and the analog signal is not stored in the feedback capacitor by disconnecting the feedback capacitance section from the stage input.

17. The A / D conversion method according to claim 16, wherein a ratio between the capacitance of said front-stage capacitance section and the capacitance of said feedback capacitance section corresponds to a magnitude of integral gain.

18. An A / D conversion method as described in claim 16, wherein the operation is executed M times (M is an integer equal to or greater than 2), and in the input signal sampling step in the first operation, the first storage is executed so that the ratio between the capacitance of the front-stage capacitance section and the capacitance of the feedback capacitance section becomes the predetermined capacitance ratio.

19. An A / D conversion method as described in claim 16, wherein the operation is executed M times (M is an integer equal to or greater than 2), and in the input signal sampling steps in the second to (M-1) operations, the second storage is executed to set the ratio of the capacitance of the front-stage capacitance section to the capacitance of the feedback capacitance section to a capacitance ratio smaller than the specified capacitance ratio in the first storage.

20. The A / D conversion method according to claim 16, wherein the operation is executed M times (M is an integer equal to or greater than 2), and wherein in sampling of the input signal in the second to M-1th operations, the number of the upstream capacitors that store the analog signal in the second storage is set to 2 or more so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a first capacitance ratio that is smaller than the predetermined capacitance ratio in the first storage, and wherein in sampling of the input signal in the Mth operation, the number of the upstream capacitors that store the analog signal in the second storage is set to 0 or 1 so that the ratio between the capacitance of the upstream capacitance section and the capacitance of the feedback capacitance section is a second capacitance ratio that is smaller than the first capacitance ratio.