Method for processing wafer

Abstract

(Problem) We propose a novel technology that prevents delamination between insulating layers, interlayer delamination between metal layers, and the generation of burrs on metal layers when dividing a wafer by cutting with a cutting blade along a street where metal layers are arranged and formed. (Solution) A method for processing a wafer in which a device (11) is formed in each area partitioned by a plurality of intersecting streets (13), and an insulating layer (17a, 17b) and a metal layer (18) are laminated on at least some of the streets (13). The method comprises a removal step in which the metal layer (18) is removed by cutting along the streets (13) with the cutting blade (51a) having a blade thickness (51w) greater than the width (18w) of the metal layer (18) in the width direction (Y-axis direction) of the streets (13), and the cutting blade (51a) is positioned at a depth reaching the bottom of the metal layer (18), and the cutting blade (51a) is used to remove the metal layer (18); and a dividing step in which the wafer (10) is divided along the streets (13) after the removal step is performed.

Description

Technology Field

[0001] The present invention relates to a method for processing a wafer in which a device is formed in each region divided by a plurality of intersecting streets, and an insulating layer and a metal layer are laminated on at least some of the streets. Background Technology

[0002] Typically, a semiconductor device consists of a functional layer formed on the surface of a wafer made of semiconductor material. This functional layer includes a wiring layer made of metal and an insulating layer (interlayer insulating film) formed between the wiring layers. As the material for the insulating layer, a low dielectric constant material called a so-called Low-k material is used.

[0003] Low-k materials include inorganic materials such as SiO2, SiOC, and SiLK, organic materials such as polymers such as polyimide, parylene, and polytetrafluoroethylene, and porous silica materials such as methyl-containing polysiloxane.

[0004] The device portion where the wiring layer is formed is formed in each region partitioned by streets arranged in a grid pattern, and insulating layers are stacked to span the streets between adjacent devices. When this insulating layer is cut with a cutting blade, the insulating layer peels off into a mica-like structure, and this peeling affects the insulating layer within the device, causing interlayer delamination between the wiring layer and the insulating layer within the device.

[0005] This interlayer delamination is also called delamination, and Patent Document 1 discloses a method of forming a laser processing groove by a laser processing device and then cutting the laser processing groove with a cutting blade, taking into account the problem of this delamination. Prior art literature

[0006] Japanese Published Patent Application No. 2006-190779 The problem to be solved

[0007] However, laser processing devices as disclosed in Patent Document 1 are generally expensive, and there is a desire to process while preventing the occurrence of delamination by a cutting device.

[0008] In addition, when there is a metal layer constituting a TEG (Test Element Group) on the street, if ablation processing is performed with a laser processing device, debris containing metal adheres to the surface of the wafer, and it is confirmed that this debris containing metal becomes enlarged over time.

[0009] If debris containing enlarged metal comes into contact with the terminals of a device or a mounting board, there is a risk of causing a short circuit in the wiring or electrodes of the chip. Therefore, this risk exists even in methods using a laser processing device such as Patent Document 1.

[0010] Furthermore, there are various types of metal layers, such as TEGs, marks for alignment patterns during device manufacturing, and metal structures embedded as countermeasures against dishing during polishing. Some of these metal layers are exposed on the wafer surface, while others are embedded within the wafer, and it is necessary to consider all these forms of metal layers.

[0011] Meanwhile, assuming cutting by a cutting device, if a metal layer is present on the street, phenomena such as delamination between the metal layer and the insulating layer, or the formation of burrs on the metal layer, occur. If burrs occur, there is a concern that the insulating layer on the street will be pushed up, affecting the insulating layer within the device and causing delamination between the wiring layer and the insulating layer within the device.

[0012] The present invention proposes a novel technology that, in consideration of the above problems, enables the prevention of delamination between insulating layers, interlayer delamination between metal layers, and the generation of burrs on metal layers when dividing a wafer by cutting with a cutting blade along a street where metal layers are arranged and formed. means of solving the problem

[0013] The problem to be solved by the present invention is as described above, and next, means for solving this problem will be explained.

[0014] According to one aspect of the present invention, a method for processing a wafer in which a device is formed in each area divided by a plurality of intersecting streets, and an insulating layer and a metal layer are laminated on at least some of the streets, is provided by a removal step in which the tip of a cutting blade having a blade thickness greater than the width of the metal layer in the width direction of the street is positioned at a depth reaching the bottom of the metal layer and the metal layer is removed by cutting along the street with the cutting blade, and a dividing step in which the wafer is divided along the street after performing the removal step.

[0015] In addition, according to one aspect of the present invention, after performing the removal step on a plurality of wafers, a blade shape verification step is provided to verify the tip shape of the cutting blade.

[0016] In addition, according to one embodiment of the present invention, in the dividing step, the wafer is divided by cutting along the street with a second cutting blade that is thinner than the cutting blade.

[0017] In addition, according to one aspect of the present invention, prior to the removal step, a metal layer verification step is additionally provided to verify the street on which the metal layer is arranged and formed, the position and width of the metal layer in the width direction of the street, and the position and thickness of the metal layer in the thickness direction of the street, and the removal step is performed only for the point on which the metal layer is arranged. Effects of the invention

[0018] As an effect of the present invention, it exhibits the effects as described below.

[0019] That is, according to one embodiment of the present invention, since the cutting blade thickness of the cutting blade for removing the metal layer is set to be greater than the width of the metal layer, the entire metal layer can be removed without leaving any residue, including the boundary portion between the metal layer and the insulating layer. By removing the boundary portion between the metal layer and the insulating layer, where interlayer delamination is likely to occur, interlayer delamination of the insulating layer within the street is suppressed, and furthermore, the occurrence of interlayer delamination (delamination) between the insulating layer and the wiring layer present in the device can be suppressed. In addition, the occurrence of burrs on the metal layer or the pushing up of the insulating layer by the metal layer can also be prevented.

[0020] In addition, according to one embodiment of the present invention, the removal step can be performed only at the points where the metal layer is placed among all streets, thereby shortening the overall processing time.

[0021] In addition, according to one embodiment of the present invention, it is possible to prevent the formation of a residual portion without the metal layer being completely removed. Brief explanation of the drawing

[0022] FIG. 1 is a drawing showing one embodiment of a wafer processed by a processing method related to the present invention. FIG. 2 is a drawing showing an enlarged view of a cross-section of a wafer and a portion of a street. FIG. 3 is a drawing showing one embodiment of a cutting device. FIG. 4 is a flowchart showing the flow of one embodiment of a processing method related to the present invention. FIG. 5 is a drawing showing cutting processing by a cutting blade. FIG. 6 is a drawing illustrating the removal step. FIG. 7 is a drawing illustrating the division step. FIG. 8(A) is a drawing illustrating the wear of a cutting blade. FIG. 8(B) is a drawing illustrating the cross-section of a groove formed by a worn cutting blade. Specific details for implementing the invention

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0024] FIG. 1 is a drawing showing one embodiment of a wafer (10) processed by a processing method related to the present invention.

[0025] On the surface (10a) of the wafer (10), devices (11, 11) are formed in areas partitioned by a plurality of intersecting streets (13). The streets (13) are extended in mutually orthogonal directions (F1) and (F2) and are set to be arranged in a grid pattern.

[0026] The material of the wafer (10) can be silicon, glass, sapphire, SiC, etc., and is not particularly limited.

[0027] Figure 2 is a drawing showing an enlarged view of a cross-section of a wafer and a portion of a street.

[0028] A functional layer (14) is laminated on the surface (10a) of a wafer (10). A device (11) is formed between the streets (13, 13), and at a point on the device (11), a plurality of wiring layers made of metal and an insulating layer formed between the wiring layers are laminated to form an integrated circuit.

[0029] The insulating layer is composed of Low-k materials (low dielectric constant materials) and is also referred to as a Low-k film. Low-k materials include inorganic materials such as SiO2, SiOC, and SiLK, organic materials which are polymers such as polyimide, parylene, and polytetrafluoroethylene, and porous silica materials such as methyl-containing polysiloxane.

[0030] At the point of street (13), a plurality of insulating layers (17a, 17b...) are laminated. These insulating layers (17a, 17...b) are continuous with the insulating layers present in the part of the device (11).

[0031] At the point of the street (13), a metal layer (18) is formed between a plurality of stacked insulating layers (17a, 17b). This metal layer (18) is, for example, a TEG, a mark for an alignment pattern during device manufacturing, a metal structure embedded as a countermeasure for dishing during polishing, etc.

[0032] The metal layer (18) may be embedded at multiple points between the multiple insulating layers (17a, 17b) that are stacked, as in the example of FIG. 2, or may be exposed to the wafer surface (the surface of the street (13)).

[0033] In addition to being formed in some of the streets (13), the metal layer (18) may be formed in all of the streets (13). Also, in addition to being formed in a place where the streets (13) intersect, the metal layer (18) may be formed in a place between adjacent devices (11, 11) with the streets (13) in between.

[0034] FIG. 3 is a drawing showing an example of a cutting device used for cutting a wafer (10).

[0035] The cutting device (50) has two cutting units (51, 52) and is configured as a dual die cutter.

[0036] A holding table (60) is formed and arranged on the base (55) of the cutting device (50). The holding table (60) is configured to reciprocate in the X-axis direction, which is the processing feed direction, by means of a moving mechanism not shown. In addition, it is configured to rotate within a horizontal plane by means of a rotating mechanism not shown.

[0037] In the holding table (60), wafer units (U) in which wafers (10) are attached to tape (T) are sequentially supplied, and on the holding surface (61a) of the holding table (60), the wafers (10) are sucked and held through the tape (T).

[0038] A door-shaped column (56) is formed on the base (55), and a moving mechanism (57, 58) is formed on the column (56) to support the first cutting unit (51) and the second cutting unit (52) so as to be movable in the Y-axis direction and the Z-axis direction, respectively. A cutting blade (51a, 52a) is formed on each cutting unit (51, 52) which is rotated by a motor not shown.

[0039] Around the holding table (60), a plurality of clamps (63) or water covers (64) are arranged and formed. On the upper surface of the water covers (64), a sub-chuck table (68) is formed to expose and hold the upper surface of the dress board (67). The water covers (64) move in the X-axis direction together with the holding table (60), and the sub-chuck table (68) also moves in the X-axis direction along with the movement of the water covers (64).

[0040] Next, an example of a wafer processing method related to the present invention will be described.

[0041] FIG. 4 is a flowchart illustrating the flow of an embodiment of a processing method related to the present invention. Each step will be described in the following order.

[0042] <Metal Layer Verification Step>

[0043] As shown in FIG. 2, the step is to determine the position and width (18w) of the metal layer (18) in the width direction (Y-axis direction) of the street (13) and the position and thickness (18h) of the metal layer (18) in the thickness direction (Z-axis direction) of the street (13).

[0044] When design information of a wafer (10) including information such as the placement position of the metal layer (18) in the wafer or the size of the metal layer (18) is available, the street (13) where the metal layer (18) exists, the position and width (18w) (size) of the metal layer (18) in the width direction (Y-axis direction) of the street within the street (13), and the position and thickness in the thickness direction (Z-axis direction) of the street are determined based on this design information. These information is stored in a controller (100) (Fig. 3), and the controller (100) determines the processing point and processing conditions for the subsequent removal step based on this information. In addition, based on the design information, etc., an operator may input processing conditions (such as the position of the cutting blade in the Y-axis direction within the street to completely remove the metal layer, or the depth of cut) and store them in the controller.

[0045] If design information of the wafer (10), including information such as the placement position of the metal layer (18) in the wafer or the size of the metal layer (18), is not available, for example, a wafer having the same pattern formed in advance is cut with a cutting blade, and the street (13) in which the metal layer (18) exists, the position and width (18w) (size) of the metal layer (18) in the width direction (Y-axis direction) of the street within the street (13), and the position and thickness in the thickness direction (Z-axis direction) of the street are specified and stored in the controller (100). The controller (100) determines the processing point and processing conditions for the subsequent removal step based on this information. In addition, based on this specified information, the operator may input processing conditions (the position of the cutting blade in the Y-axis direction within the street to completely remove the metal layer, the depth of cut, etc.) and store them in the controller.

[0046] <Removal Step>

[0047] As shown in FIGS. 5 and 6, the tip of a cutting blade (51a) having a blade thickness (51w) greater than the width (18w) of the metal layer (18) in the width direction (Y-axis direction) of the street (13) is positioned at a depth reaching the bottom of the metal layer (18), and the metal layer (18) is removed by cutting along the street (13) with the cutting blade (51a).

[0048] Thus, in the street (13), the insulating layer (17a, 17b) and the metal layer (18) are removed in a range corresponding to the cutting blade thickness (51w) of the cutting blade (51a). Since the cutting blade thickness (51w) of the cutting blade (51a) is set to be larger than the width (18w) of the metal layer (18), the entire metal layer (18) is removed without leaving any behind, including the boundary portion between the metal layer (18) and the insulating layer (17a, 17b).

[0049] Here, by removing the boundary portion between the metal layer (18) and the insulating layer (17a, 17b) where interlayer delamination is likely to occur, interlayer delamination of the insulating layer (17a, 17b) within the street (13) is suppressed, and furthermore, the occurrence of interlayer delamination (delamination) between the insulating layer and the wiring layer present in the device (11) can be suppressed. In addition, the occurrence of burrs on the metal layer (18) or the pushing up of the insulating layer by the metal layer (18) can also be prevented.

[0050] Also, as shown in FIG. 6, the blade thickness (51w) of the cutting blade (51a) may be set larger than the width (18w) of the widest metal layer (18) in the wafer (10) so as to be able to remove all metal layers (18) present in the wafer (10).

[0051] Alternatively, in a configuration having two cutting units (51, 52) equipped with cutting blades (51a, 52a) having different blade thicknesses, such as the configuration of the cutting device (50) shown in FIG. 3, the two cutting units (51, 52) may be used separately according to the width (18w) (Fig. 6) of the metal layer (18) to be removed, thereby removing all of the metal layer (18).

[0052] Also, as shown in FIG. 6, the tip of the cutting blade (51a) is set to be lower than the bottom of the metal layer (18) in the depth direction (Z-axis direction), while being preferably cut within the range of the functional layer (14). In short, it is not cut into the wafer (10).

[0053] According to this, it is possible to reliably remove the metal layer (18) and reduce the load applied to the cutting blade (51a) during cutting. In addition, it is possible to increase the processing transfer speed of the wafer (10) and furthermore, reduce the time required for the removal step.

[0054] In addition, the total processing time can be shortened by performing this removal step only on the street where the metal layer (18) is placed among all streets, or only on the point where the metal layer is placed among each street. Also, by performing cutting with a cutting blade (51a) on all streets, a common shallow groove (19) (Fig. 7) may be formed on all streets.

[0055] <Split Step>

[0056] As shown in Fig. 7, after performing the removal step, the wafer (10) is divided along the street (13).

[0057] The example of FIG. 7 is an example of full cutting with a cutting blade (52a) that has a thinner blade thickness than the cutting blade (51a) (Fig. 6) used in the removal step, and in the dual die cutter shown in FIG. 3, after forming a shallow groove (19) by performing a removal step with a cutting unit (51), a full cut is performed by the other cutting unit (52), so-called step cutting is performed.

[0058] In addition, in this step cut, in addition to the removal step and the split step being performed sequentially for each street (13), the split step may be performed after the removal step has been performed for all streets (13).

[0059] As shown in FIG. 7, when cutting with the cutting blade (52a), the metal layer (18) (Fig. 6) is completely removed, so the metal layer (18) (Fig. 6) is not cut by the cutting blade (52a), and the insulating layer (17c) or wafer (10) left along the street can be cut.

[0060] In addition, the dividing step may be performed by full cutting with a cutting blade (52a) as shown in FIG. 7, or by expanding and dividing after forming a modified layer along the street with a laser processing device, or by dividing by laser ablation processing.

[0061] <Blade Shape Verification Step>

[0062] As shown in FIG. 8(A), this is a step of checking the tip shape (edge ​​shape) of the cutting blade (51a) at a predetermined timing.

[0063] In the removal step, it is necessary to completely remove the metal layer (18) (Fig. 6), but as shown in Fig. 8(A), if the removal step is repeated, the cutting edge of the cutting blade (51a) is worn away and the tip edge is removed, forming a U-shaped tip cross-sectional shape. In this case, as shown in Fig. 8(B), for example, when the removal step is performed on another wafer (10), a groove is formed in which the bottom surface of the groove is U-shaped, and the metal layer (18) is not completely removed and a residual portion (18a) is formed.

[0064] Therefore, for example, the tip shape of the cutting blade (51a) is checked at a predetermined timing, such as after performing a removal step on a predetermined number of wafers, and appropriately, the necessary response is taken. By doing so, it is possible to prevent the metal layer (18) from being completely removed and the remaining portion (18a) from being formed. In addition, the predetermined timing can be considered to be during the processing of a single wafer or after the processing of a single wafer, in addition to after performing a removal step on a predetermined number of wafers.

[0065] The necessary countermeasures include, for example, increasing the depth of cut so that the metal layer (18) can be removed (height adjustment in the Z-axis direction), flattening the cutting edge by flat dress, or replacing the cutting blade. Flat dress is performed by flattening the cutting edge by cutting the upper surface of the dress board (67) shown in FIG. 3.

[0066] Confirmation of the tip shape of the cutting blade (51a) is, for example, first, by lowering the cutting blade rotating from above the wafer at the outer edge of the wafer and cutting it into the wafer, a cutting mark is formed in which the tip shape of the cutting blade is transferred to both ends. Alternatively, while cutting the outer edge of the wafer with a cutting blade positioned at a predetermined height, the cutting blade is withdrawn during cutting to form a cutting mark in which the tip shape of the cutting blade is transferred to one end. The formed cutting mark can be confirmed by image analysis.

[0067] Alternatively, during the execution of the removal step, when the cutting blade reaches an outer surplus area of ​​the wafer where the device is not formed, the cutting blade may be withdrawn above the wafer and the formed cutting mark may be image analyzed.

[0068] In addition, the test specimen may be held in the sub-chuck table (68) shown in FIG. 3 and the cutting mark formed on the test specimen may be confirmed by image analysis of the cutting mark, or the cross-section of the wafer may be directly captured and confirmed by image analysis.

[0069] As described above, according to the present invention, since the blade thickness (51w) of the cutting blade (51a) for removing the metal layer (18) is set to be larger than the width (18w) of the metal layer (18), the entire metal layer (18) can be removed without leaving any trace, including the boundary portion between the metal layer (18) and the insulating layer (17a, 17b). By removing the boundary portion between the metal layer (18) and the insulating layer (17a, 17b), where interlayer delamination is likely to occur, interlayer delamination of the insulating layer (17a, 17b) within the street (13) is suppressed, and furthermore, the occurrence of interlayer delamination (delamination) between the insulating layer and the wiring layer present in the device (11) can be suppressed. In addition, the occurrence of burrs on the metal layer (18) or the pushing up of the insulating layer by the metal layer (18) can also be prevented. Explanation of the symbols

[0070] 10: Wafer 10a : Surface 11 : Device 13: Street 14: Functional layer 17a: Insulating layer 17b : Insulating layer 18: Metal layer 50 : Cutting device 51 : Cutting unit 51a: Cutting blade 52 : Cutting unit 52a: Cutting blade 55 : Expectation 56 : Column 57: Mobile devices 58: Mobile devices 60 : Maintenance table 61a : Retention surface 63 : Clamp 64 : Water cover 67 : Dress Board 68: Sub Chuck Table T : Tape U : Wafer unit

Claims

Claim 1 A method for processing a wafer in which a device is formed in each area of ​​a plurality of intersecting streets, and an insulating layer and a metal layer are laminated on at least some of the streets, comprising: a removal step in which the tip of a cutting blade having a blade thickness greater than the width of the metal layer in the width direction of the street is positioned at a depth reaching the bottom of the metal layer and the metal layer is removed by cutting along the street with the cutting blade; and a dividing step in which the wafer is divided along the street after performing the removal step; and further comprising, prior to the removal step, a metal layer verification step in which the street in which the metal layer is arranged and formed, the position and width of the metal layer in the width direction of the street, and the position and thickness of the metal layer in the thickness direction of the street are verified. Claim 2 A method for processing a wafer according to claim 1, characterized in that the removal step is performed only on the street where the insulating layer and the metal layer are stacked. Claim 3 A method for processing wafers according to claim 1 or 2, characterized by having a blade shape verification step for verifying the tip shape of a cutting blade after performing a removal step on a plurality of wafers. Claim 4 A method for processing a wafer according to claim 1 or 2, characterized in that, in the dividing step, the wafer is divided by cutting along the street with a second cutting blade that is thinner than the cutting blade. Claim 5 A method for processing a wafer according to claim 1 or 2, characterized in that the removal step is performed only at the point where the metal layer is disposed. Claim 6 A method for processing a wafer according to claim 1 or 2, characterized in that, in the removal step, the metal layer is removed with a cutting blade having a blade thickness greater than the width of the widest metal layer within the wafer.

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