Charge pump, phase-locked loop, radar sensor, and electronic device

Abstract

A charge pump, a phase-locked loop, a radar sensor, and an electronic device. The charge pump is applicable to the phase-locked loop, and the phase-locked loop enters a locked state when two input clock signals are in the same frequency and the same phase. The charge pump comprises: a discharging circuit (200) and a charging circuit (300), both the discharging circuit (200) and the charging circuit (300) being connected to an output end of the charge pump. The discharging circuit (200) reduces a current of the output end under the control of a first control signal, and the charging circuit (300) increases the current of the output end under the control of a second control signal, the first control signal and the second control signal being corresponding error signals between the two clock signals. The charge pump further comprises a voltage control circuit, wherein the voltage control circuit is connected to a first node in the discharging circuit (200) and / or a second node in the charging circuit (300), so as to maintain the locked state of the phase-locked loop by controlling voltages of the corresponding nodes, the first node and the second node being both connected to the output end.

Description

Charge pumps, phase-locked loops, radar sensors, and electronic devices

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 25, 2022, with application number 202211313865.4 and invention name “Charge Pump Circuit, Phase-Locked Loop, Radar Sensor and Electronic Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of frequency modulated continuous wave technology, and in particular to a charge pump, a phase-locked loop, a radar sensor, and an electronic device. Background Art

[0003] In systems like radar and wireless communications, the quality of the Frequency Modulated Continuous Wave (FMCW) signal crucially impacts the entire system. The FMCW signal is generated by the system's Phase Lock Loop (PLL), so the quality of the PLL-generated FMCW signal is crucial to system performance. A charge pump-phase lock loop (CP-PLL) adds a charge pump structure between the frequency detector and the loop filter. By driving the capacitors in the loop filter, it forms an integrator, increasing the loop gain to infinity.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a charge pump, a phase-locked loop, a signal transmitting device, a radar sensor, and an electronic device.

[0007] In one aspect, an embodiment of the present disclosure provides a charge pump applicable to a phase-locked loop, wherein the phase-locked loop enters a locked state when two input clock signals have the same frequency and phase. The charge pump includes: a discharge circuit and a charging circuit, wherein both the discharge circuit and the charging circuit are connected to an output terminal of the charge pump, wherein the discharge circuit reduces the current at the output terminal under the control of a first control signal, and the charging circuit increases the current at the output terminal under the control of a second control signal, wherein the first control signal and the second control signal are error signals corresponding to the difference between the two clock signals. The charge pump also includes a voltage control circuit;

[0008] The voltage control circuit is connected to the first node in the discharge circuit and / or the second node in the charging circuit, and maintains the locked state of the phase-locked loop by controlling the voltage of the corresponding node; wherein the first node and the second node are both connected to the output end.

[0009] In an exemplary embodiment, the discharge circuit includes a first node and a first switching transistor located between the first node and the output end, and the voltage control circuit includes a first control circuit. When the discharge circuit does not reduce the current at the output end, the first control circuit controls the conduction speed of the first switching transistor by adjusting the voltage of the first node.

[0010] In an exemplary embodiment, the charging circuit includes a second node and a second switching transistor located between the second node and the output end, and the voltage control circuit includes a second control circuit, which is connected to the second node. When the charging circuit does not increase the current at the output end, the second control circuit controls the conduction speed of the second switching transistor by adjusting the voltage of the second node.

[0011] In an exemplary embodiment, the first control circuit includes a first charge buffer and a first control transistor connected in series, the first charge buffer stores charge, an input terminal of the first control transistor is connected to an output terminal of the first charge buffer, an output terminal of the first control transistor is connected to the first node, a control terminal of the first control transistor is configured to receive the first control signal, and the first control transistor functions as a switch to release the charge stored in the first charge buffer to the first node;

[0012] The second control circuit includes a second charge buffer and a second control transistor connected in series, the second charge buffer stores charge, the input end of the second control transistor is connected to the output end of the second charge buffer, the output end of the second control transistor is connected to the second node, the control end of the second control transistor is configured to receive a second control signal, and the second control transistor acts as a switch to release the charge stored in the second charge buffer to the second node.

[0013] In an exemplary embodiment, the first control circuit further includes a first current source and a first adjustable resistor connected in series, wherein an input terminal of the first current source is connected to a power supply voltage terminal, an output terminal of the first current source is connected to a first terminal of the first adjustable resistor, a second terminal of the first adjustable resistor is connected to a ground terminal, a third terminal of the first adjustable resistor is connected to a first input terminal of the first charge buffer, a second input terminal of the first charge buffer is connected to its own output terminal, and an output terminal of the first charge buffer is connected to an input terminal of the first control transistor;

[0014] The second control circuit also includes a second current source and a second adjustable resistor connected in series, the input end of the second current source is connected to the power supply voltage end, the output end of the second current source is connected to the first end of the second adjustable resistor, the second end of the second adjustable resistor is connected to the ground end, the third end of the second adjustable resistor is connected to the first input end of the second charge buffer, the second input end of the second charge buffer is connected to its own output end, and the output end of the second charge buffer is connected to the input end of the second control transistor.

[0015] In an exemplary embodiment, the voltage control circuit includes a charge buffer and a control transistor connected in series, the charge buffer stores charge, and an input terminal of the control transistor is connected to an output terminal of the charge buffer;

[0016] The output terminal of the control transistor is connected to the first node, the control terminal of the control transistor is configured to receive a first control signal, and the control transistor acts as a switch to release the charge stored in the charge buffer to the first node; or

[0017] The output terminal of the control transistor is connected to the second node. The control terminal of the control transistor is configured to receive a second control signal. The control transistor acts as a switch to release the charge stored in the charge buffer to the second node.

[0018] In an exemplary embodiment, the voltage control circuit further includes a current source and an adjustable resistor connected in series, wherein the input end of the current source is connected to the power supply voltage end, the output end of the current source is connected to the first end of the adjustable resistor, the second end of the adjustable resistor is connected to the ground end, the third end of the adjustable resistor is connected to the first input end of the charge buffer, and the second input end of the charge buffer is connected to its own output end.

[0019] In an exemplary embodiment, during the phase-locked loop locking period, the net charge output by the charge pump is 0 or substantially 0.

[0020] In an exemplary embodiment, the voltage control circuit adjusts a turn-on speed of the charging circuit and / or the discharging circuit so that the charging circuit and the discharging circuit are turned on at the same time.

[0021] On the other hand, an embodiment of the present disclosure further provides a phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, an oscillator and a frequency divider; wherein: the phase frequency detector is respectively connected to the input end of the phase-locked loop and the output end of the frequency divider to receive two clock signals, and the output end of the phase frequency detector is connected to the input end of the charge pump; the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the oscillator, and the output end of the oscillator is connected to the input end of the frequency divider; wherein the charge pump is the charge pump described in any of the aforementioned embodiments.

[0022] In an exemplary embodiment, the frequency divider converts the output signal fout of the phase-locked loop into one of the clock signals DIVCLK received by the phase frequency detector according to a fixed frequency division ratio N; or

[0023] The frequency divider is connected to a modulator to convert the FMCW signal output by the phase-locked loop into one of the clock signals DIVCLK received by the phase frequency detector using the adjustable frequency division ratio N output by the modulator;

[0024] In which, during the operation of any frequency divider, the charge pump is used to maintain the phase-locked loop locked state.

[0025] On the other hand, the embodiment of the present disclosure further provides a radar sensor, including a signal receiver, a signal transmitter and a clock source.

[0026] wherein the signal transmitter receives the output signal from the clock source and transmits the output signal via a transmitting antenna to form a detection signal wave;

[0027] The signal receiver uses a receiving antenna to receive the echo formed by the detection signal wave reflected by the target object, and performs down-conversion processing to output an intermediate frequency signal; wherein the clock source includes the phase-locked loop described in any of the above embodiments to generate the output signal.

[0028] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the phase-locked loop or radar sensor described in any of the aforementioned embodiments.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0032] FIG1 is a schematic diagram of the structure of a phase-locked loop;

[0033] FIG2 is a circuit diagram of a charge pump;

[0034] FIG3 is a timing diagram of a clock signal and a control signal;

[0035] FIG4 is a schematic structural diagram of a charge pump provided by an embodiment of the present disclosure;

[0036] FIG5 is a circuit diagram of a first control circuit provided in an embodiment of the present disclosure;

[0037] FIG6 is a schematic diagram of a circuit for providing a VREF1 voltage according to an embodiment of the present disclosure;

[0038] FIG7 is a circuit diagram of a second control circuit provided in an embodiment of the present disclosure;

[0039] FIG8 is a schematic diagram of a circuit for providing a VREF2 voltage according to an embodiment of the present disclosure;

[0040] FIG9 is a circuit diagram of another charge pump provided by an embodiment of the present disclosure;

[0041] FIG10 is a circuit diagram of another charge pump provided by an embodiment of the present disclosure;

[0042] FIG11A is a schematic diagram of Iup, Idn, and net current generated by the circuit shown in FIG10 at a VREF voltage;

[0043] FIG11B is a schematic diagram of Iup, Idn, and net current generated by the circuit shown in FIG10 at another VREF voltage;

[0044] FIG12 is a schematic structural diagram of a radar sensor provided by an embodiment of the present disclosure;

[0045] FIG13 is a schematic structural diagram of another radar sensor provided in an embodiment of the present disclosure.

[0046] Details

[0047] The present disclosure describes a number of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0048] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a technical solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other technical solutions to form another technical solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0049] In the embodiment of the present disclosure, the term "connection" may have the meaning of electrical coupling. As used herein, the term "connection" may indicate that two elements or devices may be directly connected to each other or connected to each other via electrical elements, electrical signals or mechanical elements (such as but not limited to, for example, wires or cables, depending on the actual application) through one or more intermediate elements or devices. Examples of connections described herein include: direct electrical connection, electrical induction connection, or optical coupling connection, etc. For example, the electrical connection between two electrical devices is achieved using the connection method used in the semiconductor manufacturing process. For another example, a signal connection between two electrical devices is achieved using a non-contact connection method such as an optical coupling component or an inductive sensing component. For another example, the electrical connection or signal connection between two electrical devices is assisted by the connection method between a chip pin and a slot.

[0050] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where the current mainly flows. In this specification, the gate electrode is the control terminal (or control electrode), the first electrode can be the drain electrode, the second electrode can be the source electrode, or the first electrode can be the source electrode, and the second electrode can be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0051] Figure 1 shows a system block diagram of a PLL, which includes a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), an oscillator (VCO), and a divider (DIV). The PLL is primarily used to generate clock signals or frequency modulated continuous wave (FMCW) signals. As shown in Figure 1, the reference clock signal REFCLK and the divided signal DIVCLK are input to the PFD. The PFD compares the phases of REFCLK and DIVCLK and generates error signals, or control signals (UP and DOWN), corresponding to the phase difference between the two signals. For example, when DIVCLK lags REFCLK, the PFD generates a high-level signal UP. When DIVCLK leads REFCLK, the PFD generates a low-level signal DOWN. The UP or DOWN signal is input to the CP, which adjusts the output current under the control of the error signal. This current is filtered by the LPF and converted into a voltage signal, which is output to the VCO. The VCO adjusts the frequency of the output oscillator signal based on the voltage of the received voltage signal. This oscillator signal is divided by the frequency divider to generate DIVCLK. When the two input clock signals REFCLK and DIVCLK are at the same frequency and in the same phase, the PLL enters the locked state.

[0052] When the loop is locked, the phase of the REFCLK and DIVCLK clocks no longer changes. If the CP and LPF are ideal models, the REFCLK and DIVCLK clocks are aligned, and the CP should no longer output a net charge to the LPF. If the linearity of the CP is not ideal (for example, when the two CLKs are aligned, the net charge output by the CP is not zero and the difference is large), then when the PLL is locked, additional charge will still enter the LPF, causing the REFCLK and DIVCLK clocks to be misaligned, that is, there will be a fixed phase difference between the two CLKs.

[0053] The inventors of this application have discovered that the reasons why REFCLK and DIVCLK are not aligned and the net charge output by the CP is not zero include: the inconsistent switching speeds of the PMOS (Positive Channel Metal Oxide Semiconductor) current mirror and the NMOS (N-Metal-Oxide-Semiconductor) current mirror switches in the CP. Figure 2 is a schematic diagram of the CP structure, and Figure 3 is a timing diagram of the two clock signals REFCLK and DIVCLK input to the PFD and the control signals UP and DOWN output. In Figure 1, when REFCLK arrives, the PFD will output a control signal UP to control the charging current Iup to charge the LPF; when DIVCLK arrives, the PFD will output a control signal DOWN (DN for short) to control the discharge current Idown (Idn for short) to discharge the LPF. As shown in Figure 3, when the REFCLK signal appears, i.e., the rising edge of REFLCK, the PFD generates the UP signal, which disappears after a delay. When the DIVCLK signal appears, i.e., the rising edge of DIVCLK, the PFD generates the DOWN signal, which disappears after a delay. In Figure 2, when the DN signal is high, the gate of M1 is high, and M1 is turned on. At this time, node B begins to discharge from a voltage greater than VA-Vthm2 (VA is the voltage of node A, and Vthm2 is the turn-on threshold voltage of M2. If the voltage of node B is less than VA-Vthm2, M2 turns on and continues to charge node B) until it falls below VA-Vthm2. At this time, M2 begins to conduct, and Idn begins to increase until node B is discharged close to 0 through M1, at which point Idn reaches its maximum value. Therefore, the process of Idn from 0 to the maximum value is the process of node B discharging from a voltage of VA-Vthm2 to close to 0. Similarly, the process of Iup from 0 to the maximum value is the process of node D charging from a voltage less than VC+|Vthm3| to V DDprocess. Since the VA and VC voltage values ​​are not necessarily the same, and the turn-on threshold voltages of M2 and M3 are also different, the parasitic capacitances of nodes B and D are also different, resulting in different charging and discharging speeds, which in turn causes different turn-on speeds of M2 and M3. When the turn-on speeds are different, even if the phases of REFCLK and DIVCLK are aligned (that is, the UP signal and the DOWN signal appear at the same time), there will be net charge to the LPF. After the loop is adjusted, the phases of REFCLK and DIVCLK will be misaligned.

[0054] In Figure 2 , signal UPB represents the inverse of signal UP, and similarly, signal DNB represents the inverse of signal DN. The charge pump includes multiple transistors. In the embodiment shown in the present disclosure, the transistors may be metal oxide semiconductor field effect (MOS) transistors. The MOS transistors used in this example charge pump include N-channel MOS transistors (NMOS) and P-channel MOS transistors (PMOS). The PMOS transistor is represented by a circle at the gate in the figure.

[0055] An embodiment of the present disclosure provides a charge pump, as shown in Figure 4, including a discharge circuit 200 and a charging circuit 300, wherein the discharge circuit 200 and the charging circuit 300 are both connected to the output end of the charge pump, the discharge circuit 200 is configured to reduce the current at the output end under the control of a first control signal, and the charging circuit 300 is configured to increase the current at the output end under the control of a second control signal, the first control signal and the second control signal are error signals corresponding to the two clock signals (for example, the first control signal is the aforementioned signal DN, and the second control signal is an inverse signal of the aforementioned signal UP), and the charge pump further includes a voltage control circuit, wherein: the voltage control circuit is connected to the first node in the discharge circuit and / or the second node in the charging circuit to maintain the locked state of the phase-locked loop by controlling the voltages of the corresponding nodes (the first node and / or the second node); wherein the first node and the second node are both connected to the output end. That is, the voltage control circuit is configured to control the voltage of the first node in the discharge circuit and / or the voltage of the second node in the charging circuit so that when the first control signal and the second control signal indicate that there is no error between the two clock signals, the net charge output by the charge pump can maintain the locked state of the phase-locked loop.

[0056] By controlling the voltage of the first node in the discharge circuit 200 and / or the voltage of the second node in the charging circuit 300, when the first control signal and the second control signal are aligned (arrive at the same time), that is, when the discharge circuit 200 and the charging circuit 300 are operating simultaneously, the difference between the charging current Iup and the discharging current Idn (i.e., the net current) is 0 or approximately 0, that is, the output charge of the charge pump is 0 or approximately 0, thereby improving the linearity of the CP, enabling the charge pump to provide a long-term stable clock signal, and reducing the possibility of the phase-locked loop losing lock. The voltage control circuit adjusts the turn-on speed of the charging circuit and / or the discharge circuit so that the charging circuit and the discharge circuit are turned on simultaneously. For example, the voltage control circuit can control the voltage of the first node in the discharge circuit so that the discharge circuit conduction speed is close to the charging circuit conduction speed. When the discharge circuit and the charging circuit are turned on simultaneously, the net charge output by the charge pump is 0 or approximately 0. Alternatively, the voltage control circuit can control the voltage of the second node in the charging circuit so that the conduction speed of the charging circuit is close to the conduction speed of the discharging circuit. When the discharging circuit and the charging circuit are simultaneously turned on, the net charge output by the charge pump is 0 or approximately 0. Alternatively, the voltage control circuit can separately control the voltage of the first node in the discharging circuit and the voltage of the second node in the charging circuit so that the charging circuit and the discharging circuit are simultaneously turned on. As used herein, "simultaneously turned on" includes not only the charging circuit and the discharging circuit being turned on at the same time, but also the charging circuit and the discharging circuit being turned on within a preset time period. As long as the charging circuit and the discharging circuit are turned on within the preset time period, it can ensure that the phase-locked loop enters a locked state.

[0057] In an exemplary embodiment, the discharge circuit includes a first node (e.g., node B in Figures 9 and 10) and a first switching transistor (e.g., transistor M2 in Figures 9 and 10) located between the first node and the output terminal. The voltage control circuit includes a first control circuit connected to the first node. The first control circuit is configured to control (e.g., adjust) the voltage at the first node to control the conduction speed of the first switching transistor when the discharge circuit does not reduce the current at the output terminal under the control of a first control signal (in the examples of Figures 9 and 10, the first control signal is a DN signal) so that when the first control signal and the second control signal indicate that there is no error between the two clock signals, the discharge circuit and the charging circuit are conductive within a preset time period. For example, the discharge circuit includes a discharge current branch from the output terminal of the charge pump to the ground terminal. The first control circuit can be connected to a first node in the discharge current branch to adjust the voltage of the first node according to the first control signal when the discharge circuit is not discharging. Taking FIG. 2 as an example, since the discharge process is a process in which Idn increases from 0 to a maximum value, that is, the first node B discharges from the voltage VA-Vthm2 to a value close to 0, the turn-on speed of the transistor M2 in the discharge current branch can be controlled by pre-controlling the voltage at point B. By adjusting the voltage at point B so that the turn-on speed of the transistor M2 is the same as or similar to the turn-on speed of the transistor M3 in the charging circuit, the net charge output by the charge pump can be guaranteed to be 0 or approximately 0 when the signals UP and DN are aligned.

[0058] In one exemplary embodiment, the charging circuit includes a second node and a second switching transistor (e.g., transistor M3 in FIG9 and FIG10 ) located between the second node (e.g., node D in FIG9 and FIG10 ) and the output terminal. The voltage control circuit includes a second control circuit connected to the second node. The second control circuit is configured to control the conduction speed of the second switching transistor by controlling (e.g., adjusting) the voltage of the second node under the control of a second control signal (in the examples of FIG9 and FIG10 , the second control signal is the aforementioned signal UPB) when the charging circuit is not increasing the current at the output terminal, so that when the first control signal and the second control signal indicate that the two clock signals are error-free, the discharge circuit and the charging circuit are conductive within a predetermined time period. For example, the charging circuit includes a charging current branch from a power supply terminal to the output terminal of the charge pump. The second control circuit can be connected to a second node in the charging current branch to adjust the voltage of the second node according to the second control signal when the charging circuit is not charging. Taking FIG2 as an example, since the charging process is Iup from 0 to the maximum value, that is, the voltage of the second node D is charged from a voltage less than VC+|Vthm3| to VDD Therefore, by controlling the voltage at point D in advance, the turn-on speed of the transistor M3 in the charging current branch can be controlled. By adjusting the turn-on speed of the transistor M3 to be the same as or similar to the turn-on speed of the transistor M2 in the discharge circuit, the net charge output by the charge pump can be guaranteed to be 0 or approximately 0 when the signal UP is aligned with the signal DN.

[0059] In an exemplary embodiment, to enable the first control circuit to control the voltage of the first node according to the control of the first control signal when the discharge circuit is not discharging, a control transistor serving as a switch may be provided in the first control circuit. By connecting the control terminal of the control transistor to the first control signal, the control transistor is turned on when the discharge circuit is not operating. Optionally, the voltage may be provided to the first control circuit by an external power supply, or a charge buffer may be used as a charge storage container to provide the voltage. The charge buffer may be an amplifier or a capacitor configured to store charge. For example, as shown in FIG5 , the first control circuit may include a first charge buffer (in FIG5 , the charge buffer is shown as an amplifier OP1) and a first control transistor M11 connected in series. The first charge buffer is configured to store charge. The first control transistor M11 serves as a switch. The input terminal of the first control transistor M11 is connected to the output terminal of the first charge buffer. The output terminal of the first control transistor M11 is connected to the first node (such as point B in FIG5 ). The control terminal of the first control transistor M11 is configured to receive the first control signal (DNB in ​​the figure) and releases the charge stored in the first charge buffer to the first node according to the control of the first control signal.

[0060] For example, an external power supply can be used to provide a voltage to the first charge buffer, or a current source and a resistor can be used to generate a voltage. For example, as shown in FIG6 , the first control circuit can further include a first current source I BG1 (where GB represents a bandgap reference) and a first adjustable resistor R1, taking the first charge buffer as the first amplifier OP1 as an example, the first current source I BG1 The input terminal and the supply voltage terminal V DD Connect the first current source I BG1The output end of is connected to the first end of the first adjustable resistor R1, the second end of the first adjustable resistor R1 is connected to the ground end, the third end of the first adjustable resistor R1 (in this example, the effective resistance value of the first adjustable resistor R1 can be changed by adjusting the position of the third end) is connected to the first input end (i.e., the non-inverting input end) of the first amplifier OP1 (as shown in FIG5 ), providing the input voltage VREF1 of the first amplifier OP1, the second input end (the inverting input end) of the first amplifier OP1 is connected to the output end of the first amplifier OP1, the output end of the first amplifier OP1 is connected to the input end of the first control transistor M11, and the output voltage of the first amplifier OP1 is the first node voltage (such as Vbias1 as shown in FIG5 ). In some embodiments, ordinary resistors can also be used instead of adjustable resistors to achieve this.

[0061] Similarly, in an exemplary embodiment, to enable the second control circuit to control the voltage of the first node based on the second control signal when the charging circuit is not charging, a control transistor serving as a switch can be provided within the second control circuit. By connecting the control terminal of the control transistor to the second control signal, the control transistor is turned on when the charging circuit is not operating (when the charging circuit is operating, it receives the inverse of the second control signal). Alternatively, an external power source can be used to provide voltage to the second control circuit, or a charge buffer can be used as a charge storage container to provide voltage. The charge buffer can be a charge storage container such as an amplifier or a capacitor. For example, as shown in Figure 7, the second control circuit may include a second charge buffer (the charge buffer is illustrated as amplifier OP2 in Figure 7) and a second control transistor M12 connected in series, the second charge buffer is configured to store charge, the second control transistor M12 serves as a switch, the input end of the second control transistor M12 is connected to the output end of the second charge buffer, the output end of the second control transistor M12 is connected to a second node (such as point B in Figures 7 and 9), and the control end of the second control transistor M12 is configured to receive the second control signal (UP in the figure), and releases the charge stored in the second charge buffer to the second node according to the control of the signal.

[0062] For example, an external power supply can be used to provide a voltage to the second charge buffer, or a current source and a resistor can be used to generate a voltage. For example, as shown in FIG8 , the second control circuit can further include a second current source I BG2 and the second adjustable resistor R2, taking the second charge buffer as the second amplifier OP2 as an example, the second current source I BG2 The input terminal and the supply voltage terminal V DD Connect the second current source I BG2The output end of is connected to the first end of the second adjustable resistor R2, the second end of the second adjustable resistor R2 is connected to the ground end, the third end of the second adjustable resistor R2 (in this example, the effective resistance value of the second adjustable resistor R2 can be changed by adjusting the position of the third end) is connected to the first input end (i.e., the non-inverting input end) of the second amplifier OP2 (as shown in FIG7 ), providing the input voltage VREF2 of the second amplifier OP2, the second input end (the inverting input end) of the second amplifier OP2 is connected to the output end of the second amplifier OP2, the output end of the second amplifier OP2 is connected to the input end of the second control transistor M12, and the output voltage of the second amplifier OP2 is the second node voltage (such as Vbias2 as shown in FIG7 ). In some embodiments, ordinary resistors can also be used instead of adjustable resistors to achieve this.

[0063] It should be noted that the first control signal can be a DN signal or a DNB signal as needed. When the first control signal is a DN signal, the inverse signal of the first control signal is the DNB signal, and vice versa. Whether the control is performed by the first control signal itself or by the inverse signal of the first control signal, it can be considered that the control is performed by the first control signal. The second control signal can be an UP signal or a UPB signal as needed. When the second control signal is an UP signal, the inverse signal of the second control signal is the UPB signal, and vice versa. Similarly, whether the control is performed by the second control signal itself or by the inverse signal of the second control signal, it can be considered that the control is performed by the second control signal.

[0064] 9 is a circuit diagram of a charge pump provided by an embodiment of the present disclosure. The charge pump includes a discharge circuit 200 and a charge circuit 300 , wherein the discharge circuit 200 includes a discharge current branch 201 and a first control circuit 202 , and the charge circuit 300 includes a charge current branch 301 and a second control circuit 302 .

[0065] In an exemplary embodiment of the present disclosure, the first control circuit 202 includes a first amplifier OP1 and a first control transistor (the eleventh transistor M11 in the figure) connected in series, the first amplifier OP1 is configured to store charge, the first control transistor M11 serves as a switch, the input end of the first control transistor M11 is connected to the output end of the first amplifier OP1, the output end of the first control transistor M11 is connected to a first node (node ​​B in this example), the control end of the first control transistor is configured to receive an inverse signal DNB of the signal DN, and the first control transistor M11 is configured to release the charge stored in the first amplifier OP1 to the first node when the discharge current branch is not working according to the control of the control signal.

[0066] In this example, the circuit for providing charge to the first amplifier OP1 may include a first current source I BG1 and the first adjustable resistor R1, the first current source I BG1 The input terminal and the supply voltage terminal V DD Connect the first current source I BG1 The output end of the first adjustable resistor R1 is connected to the first end of the first adjustable resistor R1, the second end of the first adjustable resistor R1 is grounded, the third end of the first adjustable resistor R1 is connected to the non-inverting input end of the first amplifier OP1, the inverting input end of the first amplifier OP1 is connected to the output end of the first amplifier OP1, the output end of the first amplifier OP1 is connected to the input end of the first control transistor M11, the output end of the first control transistor M11 is connected to the node B, and the control end of the first control transistor M11 is configured to receive the inverting signal DNB of the signal DN.

[0067] The discharge current branch 201 includes a first transistor M1 and a second transistor M2 connected in series between the ground terminal and the output terminal Out of the charge pump.

[0068] The second control circuit 302 includes a second amplifier OP2 and a second control transistor (the twelfth transistor M12 in the figure) connected in series. The second amplifier OP2 is configured to store charge. The second control transistor M12 serves as a switch. The input end of the second control transistor M12 is connected to the output end of the second amplifier OP2. The output end of the second control transistor M12 is connected to a second node (node ​​D in this example). The control end of the second control transistor M12 is configured to receive the second control signal UP. The second control transistor M12 is configured to release the charge stored in the second amplifier OP2 to the second node when the charging circuit is not charging, that is, when the charging current branch is not working.

[0069] In this example, the circuit for providing charge to the second amplifier OP2 may include a second current source I BG2 and the second adjustable resistor R2, the second current source I BG2 The input terminal and the supply voltage terminal V DD Connect the second current source I BG2 The output end of is connected to the first end of the second adjustable resistor R2, the second end of the second adjustable resistor R2 is grounded, the third end of the second adjustable resistor R2 is connected to the non-inverting input end of the second amplifier OP2, the inverting input end of the second amplifier OP2 is connected to the output end of the second amplifier OP2, the output end of the second amplifier OP2 is connected to the input end of the second control transistor M12, the output end of the second control transistor M12 is connected to the node D, and the control end of the second control transistor M12 is configured to receive the second control signal UP.

[0070] The charging current branch 301 includes a circuit connected in series between the output terminal Out of the charge pump and the supply voltage terminal V DD The third transistor M3 and the fourth transistor M4 are located between them.

[0071] The transistor type included in the discharge current branch 201 is different from the transistor type included in the charge current branch 301. For example, the transistor type included in the charge current branch 301 is a PMOS transistor, and the transistor type included in the discharge current branch 201 is an NMOS transistor. This disclosure does not limit this.

[0072] As shown in the figure, the charge pump further includes a current generating circuit 100. The current generating circuit 100 includes a first current generating branch 101 and a second current generating branch 102. The first current generating branch 101 is configured to provide a mirror current for the second current generating branch 102. The second current generating branch 102 includes a first sub-branch 1021 and a second sub-branch 1022 connected in series. The first sub-branch 1021 and the discharge current branch 201 form a current mirror, and the second sub-branch 1022 and the charge current branch 301 form a current mirror.

[0073] The following description is based on an example in which the transistor included in the charging current branch 301 is a PMOS transistor and the transistor included in the discharging current branch 201 is an NMOS transistor. In the following example, the first control signal is DN, the inverse signal of the first control signal is DNB, the second control signal is UP, and the inverse signal of the second control signal is UPB.

[0074] As shown in Figure 9, the output end of the first transistor M1 is connected to the ground end, the input end of the first transistor M1 is connected to the output end of the second transistor M2, the control end of the first transistor M1 is set to input the first control signal DN, the input end of the second transistor M2 is connected to the output end Out of the charge pump, and the control end of the second transistor M2 is connected to the first output end of the current generating branch (for example, the first sub-branch 1021 of the second current generating branch 102).

[0075] The output terminal of the third transistor M3 is connected to the output terminal Out of the charge pump, the input terminal of the third transistor M3 is connected to the output terminal of the fourth transistor M4, the control terminal of the third transistor M3 is connected to the second output terminal of the current generating circuit (for example, the second sub-branch 1022 of the second current generating branch 102), and the input terminal of the fourth transistor M4 is connected to the power supply voltage terminal V DD The control terminal of the fourth transistor M4 is configured to receive an inverted signal UPB of the signal UP.

[0076] The first current generating branch 101 includes a circuit connected in series with a ground terminal and a power supply voltage terminal V DDThe second current generating branch 102 includes a ninth transistor M9, a tenth transistor M10 and a current source Ibias connected in series with the ground terminal and the power supply voltage terminal V DD The first sub-branch 1021 includes the fifth transistor M5 and the sixth transistor M6 connected in series; the second sub-branch 1022 includes the seventh transistor M7 and the eighth transistor M8 connected in series.

[0077] In the embodiment of the present disclosure, the ninth transistor M9, the tenth transistor M10, the fifth transistor M5, and the sixth transistor M6 are of the same type as the first transistor M1, for example, all are NMOS transistors. The seventh transistor M7 and the eighth transistor M8 are of the same type as the third transistor M3, for example, all are PMOS transistors, which is not limited in the present disclosure.

[0078] In the first current generating branch 101, the output terminal of the ninth transistor M9 is connected to the ground terminal, the input terminal of the ninth transistor M9 is connected to the output terminal of the tenth transistor M10, and the control terminal of the ninth transistor M9 is connected to the power supply voltage terminal V DD The input terminal of the tenth transistor M10 is connected to the first terminal of the current source Ibias, and the control terminal of the tenth transistor M10 is connected to the input terminal of the tenth transistor M10. The second terminal of the current source Ibias is connected to the supply voltage terminal V DD .

[0079] In the first sub-branch 1021 of the second current generating branch 102, the output terminal of the fifth transistor M5 is connected to the ground terminal, the input terminal of the fifth transistor M5 is connected to the output terminal of the sixth transistor M6, and the control terminal of the fifth transistor M5 is connected to the power supply voltage terminal V DD The input end of the sixth transistor M6 is connected to the output end of the seventh transistor M7 , the control end of the sixth transistor M6 is connected to the control end of the tenth transistor M10 , and is connected to the control end of the second transistor M2 .

[0080] In the second sub-branch 1022 of the second current generating branch 102, the input terminal of the seventh transistor M7 is connected to the output terminal of the eighth transistor M8, the control terminal of the seventh transistor M7 is connected to the control terminal of the third transistor M3, and the input terminal of the eighth transistor M8 is connected to the power supply voltage terminal V DD The control terminal of the eighth transistor M8 is connected to the ground VSS.

[0081] The following describes the working process of the charge pump by taking the ninth transistor M9, the tenth transistor M10, the fifth transistor M5 and the sixth transistor M6 as the same type as the first transistor M1, all of which are NMOS transistors, and the seventh transistor M7 and the eighth transistor M8 as the same type as the third transistor M3, all of which are PMOS transistors as an example. In the embodiment of the present disclosure, the first current generating branch 101 can provide a mirror current for the second current generating branch 102, and the first sub-branch 1021 included in the second current generating branch 102 and the discharge current branch 201 form a current mirror (N current mirror) to provide a mirror current for the discharge current branch 201. Similarly, the second sub-branch 1022 included in the second current generating branch 102 and the charging current branch 301 form a current mirror (P current mirror) to provide a mirror current for the charging current branch 301.

[0082] To ensure that the charge pump's charging current equals its discharging current when the phase-locked loop reaches a balanced state, as shown in the figure, the charge pump may further include a comparator 400 (implemented using an operational amplifier OP in this example), wherein the comparator 400 has a first input (inverting input) connected to the output Out of the charge pump, a second input (non-inverting input) connected to the common end of the first sub-branch 1021 and the second sub-branch 1022, and an output connected to the control end of the third transistor M3. This ensures that when the phase-locked loop reaches a balanced state, the charge pump's charging current equals the discharge current of the charge pump, thereby ensuring the stability of the phase-locked loop. For example, the comparator 400 can minimize the difference between the output current of the third transistor M3 and the output current of the second transistor M2 by making the voltage at the output Out of the charge pump equal to the voltage at the node C, thereby minimizing the static phase error.

[0083] Figure 10 is a circuit diagram of a charge pump according to another embodiment of the present disclosure. The difference from the charge pump shown in Figure 9 is that, in this example, the second control circuit 302 may not include the second current source and the second adjustable resistor, and the voltage of the second amplifier OP2 is provided by the comparator 400, that is, the second input terminal (non-inverting input terminal) of the second amplifier is connected to the output terminal of the comparator, or to the control terminal of the third transistor M3 in the charging current branch.

[0084] As shown in FIG10 , when the first control signal DN is at a high level and the inverted signal DNB of the first control signal is at a low level, the first transistor M1 is turned on and the first control transistor M11 is turned off, and the N current mirror operates normally. When the first control signal DN is at a low level and the inverted signal DNB of the first control signal is at a high level, the first transistor M1 is turned off and the first control transistor M11 is turned on. At this time, the first current source I BG1The generated current passes through first resistor R1 to generate an adjustable reference voltage VREF1. VREF1 passes through a buffer formed by a first amplifier OP1 to generate voltage Vbias1. Vbias1 charges node B through first control transistor M11, charging node B to Vbias1. The next time the first control signal DN is high and its inverted signal DNB is low, the initial voltage at node B becomes Vbias1. A similar analysis applies to the P current mirror: when the second control signal UP is high and its inverted signal UPB is low, the fourth transistor M4 turns on and the second control transistor M12 turns off, allowing the P current mirror to operate normally. When the second control signal UP is low and its inverted signal UPB is high, the fourth transistor M4 is turned off, the third transistor M3 is turned off, and the second control transistor M12 is turned on. The voltage at node C passes through the buffer formed by OP2 and is subsequently recorded as voltage Vbias2. Vbias2 charges node D through the second control transistor M12, making the voltage at node D equal to Vbias2, that is, equal to the voltage at node C, and making the VGS of the third transistor M3 equal to 0. The next time the second control signal UP is high and its inverted signal UPB is low, the initial voltage at node D becomes Vbias2.

[0085] Figure 11 shows the Iup, Idn, and net current generated by the circuit shown in Figure 10 at different VREF voltages. Integrating the net current over one cycle yields the net charge. In Figure 11A, the VREF voltage is 450mV, resulting in a net charge of -29f. In Figure 11B, the VREF voltage is 535mV, resulting in a net charge of -2f. This shows that adjusting the VREF voltage can adjust the net charge output by the CP when the two PLL input clocks are aligned.

[0086] As previously mentioned, parasitic capacitance within semiconductor components, such as switches or amplifiers within the CP, can cause the CP to continue outputting current even when the PLL is locked. This can cause the frequency of the oscillation signal output by the VCO to vary, making the PLL prone to losing lock. For signal transmitters that use a PLL to generate FMCW signals, this issue affects the frequency linearity of the FMCW signal. For system clock circuits that also use a PLL to generate clock signals, this issue is detrimental to the long-term stability of the clock signal.

[0087] The present disclosure also provides a phase-locked loop (PLL). Taking a radar sensor as an example, the PLL is one of the key circuits in the radar sensor. Radar sensors contain multiple PLLs, including one for generating FMCW signals and one for providing clock signals to digital circuits.

[0088] A PLL that generates an FMCW signal includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), an oscillator (VCO), a frequency divider (DIV), and a modulator. The phase frequency detector (PFD) is connected to the input of the phase-locked loop (PLL) and the output of the frequency divider (the first input of the PFD is the input of the PLL, and the second input of the PFD is connected to the output of the frequency divider (DIV)) to receive two clock signals. The output of the phase frequency detector (PFD) is connected to the input of the charge pump (CP). The output of the charge pump (CP) is connected to the input of the loop filter (LPF), the output of the loop filter (LPF) is connected to the input of the oscillator (VCO), and the output of the oscillator (VCO) is connected to the input of the frequency divider (DIV). The modulator is connected to the control terminal of the frequency divider (DIV). The charge pump is any of the charge pumps described in any of the preceding embodiments, such as the charge pumps in FIG. 4 , FIG. 9 , or FIG. 10 , and is used to maintain the locked state of the PLL.

[0089] During actual operation, the reference clock signal REFCLK is the input signal of the phase-locked loop, the divided signal DIVCLK is the feedback signal of the phase-locked loop, and Out is the output signal of the phase-locked loop. The phase frequency detector PFD and the charge pump CP are responsible for converting the phase difference between the signals REFCLK and DIVCLK into a current signal and outputting it to the loop filter LPF. The loop filter LPF converts the current signal into a voltage signal and filters out the high-frequency signal and outputs it to the oscillator VCO. The oscillator VCO converts the voltage signal into a phase signal and outputs it. The divider DIV divides the phase signal output by the oscillator VCO according to the preset frequency ratio N (or dividing ratio). When the phase-locked loop is locked, fout = fref*N, where fout is the frequency of the output signal and fref is the frequency of the reference clock signal. Different fout can be obtained by changing different N values. In this embodiment, the modulator can change the N value according to a certain rule over time and output an adjustable frequency division ratio N, so that the phase-locked loop outputs a corresponding FMCW signal. The frequency divider converts the FMCW signal output by the phase-locked loop into one of the clock signals DIVCLK received by the phase frequency detector according to the adjustable frequency division ratio N.

[0090] In one exemplary embodiment, a PLL (Phase Frequency Detector) (PFD) outputting a clock signal includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), an oscillator (VCO), and a frequency divider (DIV). Unlike the circuit structure of the PLL generating FMCW signals described above, the frequency divider in this example divides the frequency by a fixed factor (N), enabling the PLL to output a stable clock signal after locking. For example, the frequency divider (DIV) converts the phase-locked loop's output signal (fout) into one of the clock signals (DIVCLK) received by the phase frequency detector (LPF). This clock signal is used by digital circuits in the radar sensor (e.g., MCU, data interface, CPU, memory, etc.) to perform sequential operations such as data processing, digital calculations, logical computations, transmission, or read / write operations.

[0091] In another exemplary embodiment, for a phase-locked loop (PLL) generating an FMCW signal, the charge pump provided in this embodiment can significantly improve FMCW linearity and effectively maintain PLL lock within its bandwidth. For a PLL generating a clock signal, this charge pump can provide a long-term stable clock signal, reducing the likelihood of the PLL losing lock.

[0092] An embodiment of the present disclosure also provides a radar sensor, as shown in Figure 12, including a signal receiving module (or signal receiver) 10, a signal transmitting module (or signal transmitter) 20 and a clock source 30, wherein the signal transmitter 20 is configured to receive an output signal (clock signal) from the clock source 30, and transmit the output signal through a transmitting antenna to form a detection signal wave, and the clock source includes a phase-locked loop for generating an output signal; the signal receiver 10 is configured to use a receiving antenna to receive an echo formed by the detection signal wave reflected by the target object, and perform down-conversion processing based on the output signal of the clock source 30 to generate and output an intermediate frequency signal; wherein the phase-locked loop is the phase-locked loop provided in any of the above embodiments.

[0093] Optionally, in an exemplary embodiment of the present disclosure, the frequency modulated continuous wave signal is a millimeter wave signal, so that the electronic device can be applied to fields such as autonomous driving, industrial automation, smart home appliances, and security inspection.

[0094] As shown in Figure 13, in an exemplary embodiment, the radar sensor may also include an analog-to-digital conversion module 40 and a signal processing module 50, wherein the signal receiver 10 generates and outputs an intermediate frequency signal to the analog-to-digital conversion module 40, which is processed by the analog-to-digital conversion module 40 and transmitted to the signal processing module 50, and the signal processing module 50 is used to perform signal processing on the digital signal output by the analog-to-digital conversion module 40.

[0095] For example, the signal transmitter generates a chirp signal using a preset continuous frequency modulation scheme; a radio frequency (RF) transmission signal is obtained through frequency multiplication and fed to a transmitting antenna to transmit a corresponding detection signal wave. When the detection signal wave is reflected by an object, an echo signal wave is generated. The echo signal wave is converted into a RF receive signal by a receiving antenna. The signal receiver is configured to down-convert, filter, and perform analog-to-digital conversion on the RF receive signal using the RF transmit signal, thereby outputting a baseband digital signal representing the difference frequency between the detection signal wave and the echo signal wave. The signal processing module is configured to extract measurement information from the baseband digital signal through signal processing and output corresponding measurement data. The signal processing includes performing phase, frequency, and time domain digital signal processing calculations based on at least one signal to be processed provided by at least one receiving antenna. The measurement data includes at least one of the following: distance data indicating the relative distance of at least one detected obstacle; velocity data indicating the relative velocity of at least one detected obstacle; and angle data indicating the relative angle of at least one detected obstacle.

[0096] Optionally, the frequency modulated continuous wave signal is a millimeter wave signal, and the radar sensor may be an AiP millimeter wave radar chip with an integrated antenna. In other embodiments of the present disclosure, the radar sensor may also be other types of radar chips, which is not limited in the present disclosure.

[0097] In summary, in the phase-locked loop and radar sensor provided in the embodiments of the present disclosure, the frequency-modulated continuous wave signal output by the phase-locked loop can have good linearity and can maintain the phase-locked loop locked within the bandwidth range, thereby improving the performance of the radar system when applied to the radar system.

[0098] In an exemplary embodiment, the present disclosure further provides an electronic device including the aforementioned phase-locked loop or radar sensor.

[0099] Exemplarily, the electronic device includes: a device body; and an electronic device, such as a phase-locked loop or radar sensor, disposed on the device body. The device body is a structure that carries and is signal-connected to a radio device. The radio device transmits and / or receives radio signals that have been phase-shifted by a phase shifter, enabling functions such as target detection and / or communication within a beam scanning range. This provides the device body with detection target information and / or communication information, thereby assisting or even controlling the operation of the device body.

[0100] In an optional embodiment, the electronic device comprising the device body and the aforementioned at least one radio device may be a component or product used in fields such as smart housing, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, and health care. For example, the device body may be intelligent transportation equipment (such as cars, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as bracelets, glasses, etc.), smart home devices (such as sweeping robots, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as gates, smart traffic lights, smart signs, traffic cameras, and various industrial robotic arms (or robots), etc. It may also be various instruments for detecting vital signs and various devices equipped with the instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, smart medical equipment, consumer electronic devices, etc.

Claims

1. A charge pump, suitable for a phase-locked loop, wherein the phase-locked loop enters a locked state when two input clock signals have the same frequency and phase, and the charge pump comprises: A discharge circuit and a charging circuit, both of which are connected to the output end of the charge pump, the discharge circuit reduces the current of the output end under the control of a first control signal, and the charging circuit increases the current of the output end under the control of a second control signal, the first control signal and the second control signal are error signals corresponding to the two clock signals, and the charge pump further includes a voltage control circuit, wherein: The voltage control circuit is connected to a first node in the discharge circuit and / or a second node in the charging circuit to maintain the locked state of the phase-locked loop by controlling the voltage of the corresponding node; wherein the first node and the second node are both connected to the output end.

2. The charge pump according to claim 1, wherein: The discharge circuit includes a first node and a first switch transistor located between the first node and the output terminal; The voltage control circuit includes a first control circuit connected to the first node. When the discharge circuit does not reduce the current at the output end, the first control circuit controls the conduction speed of the first switching transistor by adjusting the voltage of the first node.

3. The charge pump according to claim 1 or 2, wherein: The charging circuit includes a second node and a second switch transistor located between the second node and the output terminal; The voltage control circuit includes a second control circuit connected to the second node. When the charging circuit does not increase the current at the output end, the second control circuit controls the conduction speed of the second switch transistor by adjusting the voltage of the second node.

4. The charge pump according to claim 3, wherein: The first control circuit comprises a first charge buffer and a first control transistor connected in series, the first charge buffer stores charge, an input end of the first control transistor is connected to an output end of the first charge buffer, an output end of the first control transistor is connected to the first node, a control end of the first control transistor is configured to receive the first control signal, and the first control transistor acts as a switch to release the charge stored in the first charge buffer to the first node; The second control circuit includes a second charge buffer and a second control transistor connected in series, the second charge buffer stores charge, the input end of the second control transistor is connected to the output end of the second charge buffer, the output end of the second control transistor is connected to the second node, the control end of the second control transistor is configured to receive a second control signal, and the second control transistor acts as a switch to release the charge stored in the second charge buffer to the second node.

5. The charge pump according to claim 4, wherein: The first control circuit further includes a first current source and a first adjustable resistor connected in series, wherein an input end of the first current source is connected to a power supply voltage end, an output end of the first current source is connected to a first end of the first adjustable resistor, a second end of the first adjustable resistor is connected to a ground end, a third end of the first adjustable resistor is connected to a first input end of the first charge buffer, a second input end of the first charge buffer is connected to its own output end, and an output end of the first charge buffer is connected to an input end of the first control transistor; The second control circuit also includes a second current source and a second adjustable resistor connected in series, the input end of the second current source is connected to the power supply voltage end, the output end of the second current source is connected to the first end of the second adjustable resistor, the second end of the second adjustable resistor is connected to the ground end, the third end of the second adjustable resistor is connected to the first input end of the second charge buffer, the second input end of the second charge buffer is connected to its own output end, and the output end of the second charge buffer is connected to the input end of the second control transistor.

6. The charge pump according to claim 1, wherein: The voltage control circuit comprises a charge buffer and a control transistor connected in series, the charge buffer stores charge, and the input end of the control transistor is connected to the output end of the charge buffer; The output end of the control transistor is connected to the first node, the control end of the control transistor is configured to receive a first control signal, and the control transistor acts as a switch to release the charge stored in the charge buffer to the first node; or The output end of the control transistor is connected to the second node, the control end of the control transistor is configured to receive a second control signal, and the control transistor acts as a switch to release the charge stored in the charge buffer to the second node.

7. The charge pump according to claim 6, wherein: The voltage control circuit also includes a current source and an adjustable resistor connected in series, the input end of the current source is connected to the power supply voltage end, the output end of the current source is connected to the first end of the adjustable resistor, the second end of the adjustable resistor is connected to the ground end, the third end of the adjustable resistor is connected to the first input end of the charge buffer, and the second input end of the charge buffer is connected to its own output end.

8. The charge pump according to claim 1, wherein: During the phase-locked loop locking period, the net charge output by the charge pump is 0 or substantially 0.

9. The charge pump according to claim 1, wherein: The voltage control circuit adjusts the start-up speed of the charging circuit and / or the discharging circuit so that the charging circuit and the discharging circuit are turned on at the same time.

10. A phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, an oscillator and a frequency divider; wherein: The phase frequency detector is connected to the input end of the phase locked loop and the output end of the frequency divider respectively to receive two clock signals, the output end of the phase frequency detector is connected to the input end of the charge pump; the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the oscillator, and the output end of the oscillator is connected to the input end of the frequency divider; Wherein, the charge pump comprises a charge pump as described in any one of claims 1-9.

11. The phase-locked loop according to claim 10, wherein: The frequency divider converts the output signal fout of the phase-locked loop into one of the clock signals DIVCLK received by the phase frequency detector according to a fixed frequency division ratio N; or The frequency divider is connected to a modulator to utilize the adjustable frequency division ratio N output by the modulator to convert the FMCW signal output by the phase-locked loop into one of the clock signals DIVCLK received by the frequency detector and phase detector; Wherein, during the operation of any frequency divider, the charge pump is used to maintain the phase-locked loop locked state.

12. A radar sensor, comprising a signal receiver, a signal transmitter and a clock source, wherein the signal transmitter receives an output signal from the clock source and transmits the output signal via a transmitting antenna to form a detection signal wave; The signal receiver uses a receiving antenna to receive the echo formed by the detection signal wave reflected by the target object, and performs down-conversion processing to output an intermediate frequency signal; wherein, The clock source comprises a phase-locked loop as claimed in claim 10 or 11 to generate the output signal.

13. An electronic device comprising the phase-locked loop according to claim 10 or 11 or the radar sensor according to claim 12.

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