Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A manufacturing method for a semiconductor device, the method comprising: by means of a one-step patterning process, forming a laminated structure into a patterned laminated structure, and forming a through hole, wherein the patterned laminated structure comprises a patterned conductive layer and a patterned insulating layer, which are alternately disposed in sequence; the through hole penetrates the patterned laminated structure in a direction perpendicular to a substrate; the patterned conductive layer and the patterned insulating layer are exposed from a side wall of the through hole; and the through hole is configured to accommodate a word line.

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 20, 2023, with application number 202310137930.0 and invention name “3D memory, manufacturing method thereof, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of device design and manufacturing of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] Based on their application, semiconductor memory can be divided into volatile memory (RAM, including DRAM and SRAM) and non-volatile memory (ROM and non-ROM). Taking DRAM as an example, conventional DRAM has multiple repeated "memory cells," each of which consists of a capacitor and a transistor. A capacitor can store one bit of data. After charging and discharging, the amount of charge stored in the capacitor corresponds to the binary data "1" and "0," respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] To minimize product costs, people hope to create as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device.

[0008] On the one hand, embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the semiconductor device comprising multiple layers of memory cells stacked in a direction perpendicular to a substrate and word lines extending in a direction perpendicular to the substrate. The memory cells comprise transistors and capacitors, the transistors comprising a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding and insulated from the gate electrode. The capacitors comprise a first plate and a second plate. The method for manufacturing the semiconductor device comprises:

[0009] Providing a substrate, and alternately depositing a first insulating film and a conductive film on the substrate to form a stacked structure;

[0010] Through a single patterning process, the stacked structure is formed into a patterned stacked structure and a through hole is formed; the patterned stacked structure includes a patterned conductive layer and a patterned insulating layer that are alternately arranged in sequence; the through hole penetrates the patterned stacked structure in a direction perpendicular to the substrate, and the sidewall of the through hole exposes the patterned conductive layer and the patterned insulating layer; the through hole is configured to accommodate the word line.

[0011] In some embodiments, forming the stacked structure into a patterned stacked structure and forming the through-holes through a single patterning process includes: performing a patterning process on the stacked structure using a mask pattern on a film layer to form the patterned stacked structure and form the through-holes. The mask pattern is a pattern having both a structure and a hole structure.

[0012] In some embodiments, the film layer is photoresist.

[0013] In some embodiments, the film layer is a hard mask layer.

[0014] In some embodiments, the method for manufacturing a semiconductor device further includes: forming a first sacrificial layer filling the through hole; forming a filling layer surrounding the side wall of the patterned stacked structure; removing part of the filling layer and part of the patterned insulating layer to expose part of the patterned conductive layer, so that the exposed patterned conductive layer serves as the first electrode, and forming the second electrode in the area where the filling layer and the patterned insulating layer are removed; etching to remove the first sacrificial layer; etching the patterned conductive layer in a direction away from the through hole on a plane parallel to the substrate, the through hole causing the patterned conductive layer to form a first electrode and a second electrode separated from each other; depositing mutually insulated semiconductor films and gate electrode films in sequence on the side walls of the through hole to form the semiconductor layer, the gate electrode and the word line.

[0015] In some embodiments, forming a first sacrificial layer that fills the through hole includes:

[0016] Depositing a first sacrificial layer thin film on the substrate, wherein the first sacrificial layer thin film covers a portion of the surface of the substrate, covers the side surfaces and the upper surface of the patterned stacked structure, and fills the through hole;

[0017] The first sacrificial layer film is subjected to a composition process to remove the first sacrificial layer film covering the surface of the substrate and the first sacrificial layer film covering the side and upper surfaces of the patterned stacked structure, and the first sacrificial layer film filling the through hole is retained to form the first sacrificial layer.

[0018] In some embodiments, after forming the filling layer surrounding the sidewall of the patterned stacked structure, the manufacturing method further includes: grinding the surface of the filling layer so that the surface of the filling layer away from the substrate is flush with the surface of the patterned stacked structure away from the substrate.

[0019] In some embodiments, a portion of the filling layer and a portion of the patterned insulating layer are removed to expose a portion of the patterned conductive layer, and the exposed patterned conductive layer is used as the first electrode plate. Before the second electrode plate is formed in the region where the filling layer and the patterned insulating layer are removed, the manufacturing method further includes:

[0020] removing the filling layer and the patterned insulating layer on at least one side of the film pattern to expose one end of the patterned conductive layer;

[0021] A supporting layer is formed on the exposed end of the patterned conductive layer, wherein the supporting layer includes a fixing groove, and the fixing groove fixes the exposed end of the patterned conductive layer.

[0022] In some embodiments, the support layer comprises an insulating material.

[0023] The present disclosure also provides a semiconductor device manufactured by the method for manufacturing a semiconductor device as described above, comprising: multiple layers of memory cells and word lines stacked in a direction perpendicular to a substrate, wherein the word lines extend in a direction perpendicular to the substrate and penetrate the memory cells in different layers. The memory cells include: a transistor and a capacitor, wherein the transistor includes a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, wherein the semiconductor layer extends on the sidewalls of the gate electrode to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; and the capacitor includes a first plate and a second plate.

[0024] In some embodiments, the semiconductor device further includes a supporting layer, which is located on the side of the first electrode away from the gate electrode. The supporting layer includes a fixing groove, the opening of the fixing groove faces one end of the first electrode, and one end of the first electrode extends into the fixing groove.

[0025] In some embodiments, the second electrode plate is located between the support layer and the word line, surrounds the first electrode plate, and extends on a sidewall of the first electrode plate to form a ring extending in a direction parallel to the substrate.

[0026] An embodiment of the present disclosure further provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0027] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which simultaneously form a patterned stacked structure and a through hole K1 through a single composition process, thereby simplifying the process flow, facilitating implementation, and improving production efficiency. It has the advantages of easy process implementation, low production cost, and high yield.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0029] Summary of the Figures

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution.

[0031] FIG1A is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction perpendicular to a substrate;

[0032] 1B is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to the substrate;

[0033] 1C is a partially enlarged schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate provided by an exemplary embodiment;

[0034] 1D is another partially enlarged schematic cross-sectional view of a semiconductor device along a direction perpendicular to the substrate provided by an exemplary embodiment;

[0035] FIG2 is a schematic diagram of a semiconductor device after a stacked structure is formed during the manufacturing process according to an exemplary embodiment;

[0036] 3A is a schematic diagram of a semiconductor device after a first mask is placed during the manufacturing process according to an exemplary embodiment;

[0037] 3B is a schematic diagram 1 of a semiconductor device after forming a patterned conductive layer, a patterned insulating layer, and a through hole in a manufacturing process provided by an exemplary embodiment;

[0038] 3C is a second schematic diagram of a semiconductor device after forming a patterned conductive layer, a patterned insulating layer, and a through hole in a manufacturing process provided by an exemplary embodiment;

[0039] 3D is a third schematic diagram of a semiconductor device after forming a patterned conductive layer, a patterned insulating layer, and a through hole in a manufacturing process provided by an exemplary embodiment;

[0040] 4A is a schematic diagram of a semiconductor device after forming a first sacrificial layer film during the manufacturing process according to an exemplary embodiment;

[0041] 4B is a schematic diagram of a semiconductor device after a first sacrificial layer is formed during the manufacturing process according to an exemplary embodiment;

[0042] FIG4C is a schematic diagram of a semiconductor device after a filling layer is formed during the manufacturing process according to an exemplary embodiment;

[0043] 5A is a schematic diagram of a semiconductor device after a second mask is placed during the manufacturing process according to an exemplary embodiment;

[0044] FIG5B is a schematic diagram of a semiconductor device after a groove is formed during the manufacturing process according to an exemplary embodiment;

[0045] FIG5C is a first schematic diagram of a semiconductor device after forming a support layer during manufacturing of the semiconductor device according to an exemplary embodiment;

[0046] FIG5D is a second schematic diagram of a semiconductor device after a support layer is formed during the manufacturing process according to an exemplary embodiment;

[0047] 6A is a schematic diagram 1 after forming a first hollow portion and a second hollow portion during the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0048] 6B is a second schematic diagram of a semiconductor device after forming a first hollow portion and a second hollow portion during manufacturing of the semiconductor device according to an exemplary embodiment;

[0049] FIG7A is a schematic diagram 1 of a semiconductor device after forming a second electrode plate during the manufacturing process according to an exemplary embodiment;

[0050] 7B is a second schematic diagram after forming a second electrode plate during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0051] FIG8 is a schematic diagram of a semiconductor device after the first sacrificial layer is removed during the manufacturing process according to an exemplary embodiment;

[0052] 9A is a schematic diagram 1 after forming a first electrode and a second electrode during the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0053] 9B is a second schematic diagram after forming a first electrode and a second electrode during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0054] 10A is a schematic diagram of a semiconductor device after a semiconductor layer and a gate insulating layer are formed during the manufacturing process of an exemplary embodiment;

[0055] 10B is a schematic diagram of a semiconductor device after a second sacrificial layer is formed during the manufacturing process according to an exemplary embodiment;

[0056] FIG11A is a schematic diagram of a semiconductor device after etching a second sacrificial layer during manufacturing according to an exemplary embodiment;

[0057] FIG. 11B is a schematic diagram of a semiconductor device after etching back the second sacrificial layer during manufacturing of the semiconductor device according to an exemplary embodiment.

[0058] Details

[0059] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0060] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0061] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of one or more components in the drawings do not reflect the true scale. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0062] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0063] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases described in this disclosure are not limited and can be appropriately replaced according to the circumstances.

[0064] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; physical connections or signal connections; direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0065] In the present disclosure, a transistor may include a gate (also referred to as a gate electrode), a channel, and a first electrode (hereinafter referred to as the first electrode 51) and a second electrode (hereinafter referred to as the second electrode 52), wherein the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. The source electrode may also be referred to as a drain electrode terminal, a drain region or a drain electrode, and the drain electrode may also be referred to as a source electrode terminal, a source region or a source electrode. In cases where transistors of opposite polarity are used or where the direction of current changes during circuit operation, the functions of the “source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present disclosure, the “source electrode” and the “drain electrode” may be interchanged.

[0066] In this disclosure, "connected" or "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0067] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0068] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0069] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or located in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0070] In the embodiments of the present disclosure, "A and B are an integrated structure" may include a film layer patterned to form a connected film layer as an integrated structure. For example, A and B are made of the same material into a film layer and are simultaneously formed into a connected structure through the same patterning process.

[0071] In the embodiment of the present disclosure, the parasitic MOS tube (parasitic MOS for short) can be reduced or eliminated by removing the semiconductor layer between the layers through etching.

[0072] Figure 1A is a schematic cross-sectional view of a semiconductor device provided in an exemplary embodiment along a direction perpendicular to the substrate; Figures 1C and 1D may be partially enlarged views of the schematic cross-sectional view of a semiconductor device provided in an exemplary embodiment along a direction perpendicular to the substrate. Figures 1C and 1D may be enlarged views of point a in Figure 1A; the direction perpendicular to the substrate may be the third direction D3 in Figure 1A. As shown in Figures 1A and 1C, the semiconductor device provided in this embodiment may include: multiple layers of memory cells stacked in a direction perpendicular to substrate 1, and word lines 40, wherein the word lines 40 extend in a direction perpendicular to substrate 1 and penetrate the memory cells in different layers.

[0073] As used herein, the term "substrate" means and includes the base material or structure on which materials such as vertical field-effect transistors are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0074] The memory cell may include a transistor, comprising a first electrode 51, a second electrode 52, a gate electrode 26 extending in a direction perpendicular to the substrate, and a semiconductor layer 23 surrounding and insulated from the gate electrode 26. The semiconductor layer 23 extends on the sidewalls of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate. The first electrode 51 and the second electrode 52 are located on opposite sides of the gate electrode 26 in a first direction D1. At least a portion of the semiconductor layer 23 is located between the first electrode 51 and the gate electrode 26, and between the second electrode 52 and the gate electrode 26, respectively. The channel between the first electrode 51 and the second electrode 52 is a horizontal channel. The semiconductor layers 23 of the transistors of at least some adjacent layers of the memory cell are spaced apart in a direction perpendicular to the substrate, and the gate electrode 26 is connected to the word line 40. The first direction D1 is parallel to the plane of the substrate.

[0075] Among them, the word line is a lead shared by multiple transistors stacked vertically, and the lead is connected to the gates of multiple transistors. In the stacked structure shown in Figure 1A, the word line 40 can be a line extending longitudinally and shared by three transistors. The gate refers to the gate electrode of a transistor. In Figure 1A, the gate 26 can be a part of the word line 40. The word line 40 extends along the longitudinal direction (for example, the third direction D3) as a whole, but the cross-sectional size at different positions can be the same or different. For example, the area on the word line 40 corresponding to the effective channel of each transistor is the effective gate. The cross-section of the effective gate can be larger than other areas on the word line 40 (such as shown in Figure 1D) or smaller than other areas, which is not limited in this application. The other areas can be areas that do not correspond to the effective channel of the transistor, for example, the area between two vertically stacked transistors.

[0076] In the semiconductor device provided by this embodiment, the semiconductor layers of transistors in adjacent layers are spaced apart in a direction perpendicular to the substrate 1, thereby reducing or eliminating at least some parasitic MOS between the layers and improving device stability. This spacing can be understood as separating the adjacent semiconductor layers of transistors in adjacent layers. For example, the semiconductor layer formed on the inner wall of the hole is hollowed out or modified in the separated area, rendering the separated area incapable of functioning as a semiconductor.

[0077] A horizontal channel is a channel in which the carrier transport direction is generally in a plane parallel to the substrate.

[0078] In an exemplary embodiment, the semiconductor layers 23 of the transistors of the memory cells of different layers are spaced apart in a direction perpendicular to the substrate. For example, the semiconductor layers 23 of the transistors of the memory cells of all adjacent layers are spaced apart in a direction perpendicular to the substrate, thereby eliminating parasitic MOS between all adjacent layers and improving device stability.

[0079] In one exemplary embodiment, the semiconductor layer 23 may be fully encircled, completely surrounding the sidewalls of the gate electrode 26. That is, a cross-section of the semiconductor layer 23 parallel to the substrate is a closed loop. Exemplarily, the semiconductor layer 23 is annular, and the annular shape conforms to the cross-sectional outer contour of the gate electrode 26. Exemplarily, the cross-section of the gate electrode 26 is, for example, a square.

[0080] In one exemplary embodiment, as shown in Figures 1A and 1C, the gate electrode 26 includes a central portion 261 and a peripheral portion 262 located outside the central portion 261. The central portion 261 extends only in a direction perpendicular to the substrate 1. The central portion 261 can completely overlap with the orthographic projection of the word line 40 on the substrate 1. The central portion 261 can be integrally formed with the word line 40, using the same material and manufactured using the same manufacturing process. The peripheral portion 262 surrounds the central portion 261 on all sides and can completely surround the sidewalls of the central portion 261. At least a portion of the peripheral portion 262 contacts the sidewalls of the central portion 261. The peripheral portion 262 does not overlap with the orthographic projection of the word line 40 on the substrate 1, but does overlap with the orthographic projection of the semiconductor layer 23 on the substrate 1.

[0081] In an exemplary embodiment, the transistor may further include a gate insulating layer 24 surrounding a sidewall of the gate electrode 26 . The gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23 to insulate the gate electrode 26 from the semiconductor layer 23 .

[0082] In an exemplary embodiment, transistors in different layers may share a ring-shaped gate insulating layer 24 extending in a direction perpendicular to the substrate.

[0083] In an exemplary embodiment, the gate insulating layers 24 of at least some transistors in adjacent layers are spaced apart from each other in a direction perpendicular to the substrate.

[0084] In an exemplary embodiment, the gate insulating layers 24 of transistors in different layers are spaced apart from each other in a direction perpendicular to the substrate.

[0085] In one exemplary embodiment, the first electrode 51 and the second electrode 52 of the same transistor can be located in the same conductive film layer along a direction perpendicular to the substrate. The first electrode 51 and the second electrode 52 can be formed by patterning a single conductive film layer, which is approximately parallel to the upper surface of the substrate. The first electrode 51 and the second electrode 52 can be provided in the same layer. That is, the first electrode 51 and the second electrode 52 can be formed simultaneously through the same patterning process, but the embodiments of the present disclosure are not limited thereto. The first electrode 51 and the second electrode 52 can be manufactured separately through different patterning processes.

[0086] In an exemplary embodiment, the first electrode 51 or the second electrode 52 of different transistors may be located in different conductive film layers.

[0087] In an exemplary embodiment, stacked transistors in different layers may share the word line 40 extending in a direction perpendicular to the substrate.

[0088] In an exemplary embodiment, the semiconductor layers 23 corresponding to transistors of different layers may be located on the sidewalls of the word lines 40 and respectively located in different regions extending in a direction perpendicular to the substrate.

[0089] In an exemplary embodiment, an insulating layer is exposed between the spaced semiconductor layers 23, and the insulating layer is a gate insulating layer 24 located between the gate electrode 26 and the semiconductor layer 23. This embodiment provides a solution in which the first electrode 51 and the gate electrode 26 are isolated by the gate insulating layer 24, thereby preventing over-etching that exposes the first electrode 51 and causes a short circuit between the first electrode 51 and the gate electrode 26.

[0090] FIG1B is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to the substrate. In an exemplary embodiment, as shown in FIG1B , the memory cells in the same layer form an array distributed along a first direction D1 and a second direction D2, respectively, and the memory cells in each layer further include: a bit line 30, and the bit line 30 is connected to the second electrode 52 of the transistor in the same layer and the same column. FIG1B shows that each layer includes three rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell. The first direction D1 may be parallel to the substrate, the second direction D2 may be parallel to the substrate, and the first direction D1 and the second direction D2 intersect. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0091] In an exemplary embodiment, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30. The second electrodes 52 of the transistors in two adjacent columns in the same layer and the bit line 30 may be an integrated structure.

[0092] In an exemplary embodiment, the second electrode 52 of the transistor may be a portion of the bit line 30 to which the second electrode 52 is connected.

[0093] In one exemplary embodiment, the bit lines 30 may extend along the second direction D2 .

[0094] In an exemplary embodiment, the first electrode 51 may extend along a first direction D1.

[0095] In an exemplary embodiment, the semiconductor device may further include a data storage element.

[0096] In an exemplary embodiment, the data storage element may be a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto, and the data storage element may be combined with other transistors to form a 2T0C storage structure, and so on.

[0097] In an exemplary embodiment, as shown in Figures 1A and 1B, the capacitor may include a first plate 41 and a second plate 42, wherein the first plate 41 is connected to the first electrode 51. The second plate 42 surrounds the first plate 41 and is insulated from the first plate 41. The second plate 42 extends on the sidewall of the first plate 41 to form a ring extending in a direction parallel to the substrate.

[0098] In one exemplary embodiment, as shown in Figures 1A and 1B, the semiconductor device may further include a support layer 43. The support layer 43 is located on a side of the first electrode 41 away from the gate electrode 26, and the second electrode 42 is located between the support layer 43 and the word line 40. The support layer 43 includes a fixing groove 44. The opening of the fixing groove 44 faces one end of the first electrode 41. The end of the first electrode 41 away from the bit line 30 extends into the fixing groove 44, so that the support layer 43 fixes the first electrode 41 to ensure the mechanical stability of the first electrode 41. During the manufacturing process of the semiconductor device, the first electrode 41 can be exposed first, and then the support layer 43 is formed. The support layer 43 fixes one end of the first electrode 41 to ensure the mechanical stability of the first electrode 41. Finally, the second electrode 42 is formed surrounding the first electrode 41.

[0099] In an exemplary embodiment, the first electrode plate 41 and the first electrode 51 may be an integrated structure.

[0100] In an exemplary embodiment, the second plates 42 of the capacitors in the same column of different layers can be connected into an integrated structure. As shown in FIG1B , the second plates 42 of the capacitors in the first column of different layers are connected into an integrated structure. The second plates 42 of the capacitors in the second column of different layers are connected into an integrated structure, that is, the capacitors in the same column of different layers share the same plate as the second plate 42.

[0101] In an exemplary embodiment, the capacitor may further include a third insulating layer 13 disposed between the first electrode plate 41 and the second electrode plate 42. The third insulating layer 13 serves as a dielectric between the first electrode plate 41 and the second electrode plate 42.

[0102] In an exemplary embodiment, as shown in FIG1B , on a cross section parallel to the substrate direction, the semiconductor device may further include a detection pin 61, wherein the detection pin 61 is disposed on one side of the memory cell, and the detection pin 61 is electrically connected to the bit line 30 of each layer of the memory cell. The detection unit may be electrically connected to the detection pin 61, and a detection signal may be input to the bit line 30 of the memory cell through the detection pin 61 to detect the memory cell.

[0103] In one exemplary embodiment, the projections of the first electrodes of adjacent transistors perpendicular to the substrate overlap, the projections of the second electrodes overlap, and the projections of the gate electrodes overlap. This embodiment provides a solution that simplifies the process by stacking conductive and insulating layers and then forming a multilayer stack of first and second electrodes and through-holes K1 using a single mask. Furthermore, this can make the semiconductor device more compact.

[0104] The semiconductor device according to the embodiment of the present application can form a 1T1C storage structure with a capacitor, or form a 2T0C storage structure with other transistors, and so on.

[0105] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without limitation. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film," and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0106] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

[0107] In one exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0108] In step 101 , a first insulating film 10 and a first conductive film 11 are alternately deposited on a substrate 1 to form a stacked structure, as shown in FIG2 .

[0109] In an exemplary embodiment, the first insulating film 10 and the first conductive film 11 may be deposited using a chemical vapor deposition (CVD) method.

[0110] As used herein, the term "substrate" means and includes a base material or structure on which materials such as vertical field effect transistors are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer. In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate.

[0111] In an exemplary embodiment, the first insulating thin film 10 can be a dielectric layer with a relatively small dielectric constant, such as silicon dioxide (SiO2) and the like.

[0112] In an exemplary embodiment, the first conductive thin film 11 can include, but is not limited to, a multi-layer structure of titanium nitride (TiN) / tungsten (W).

[0113] The stacked structure shown in FIG. 2 includes four layers of the first insulating thin film 10 and three layers of the first conductive thin film 11, for example only. In other embodiments, the stacked structure can include more or fewer alternately arranged layers of the first insulating thin film 10 and the first conductive thin film 11.

[0114] Step 102: On the basis of the substrate 1 on which the foregoing pattern is formed, first form the first mask plate 2 (which can be understood as a mask pattern) on the surface of the stacked structure on the side away from the substrate 1, as shown in FIG. 3A. The mask pattern can be a pattern on a photoresist (PR) or a hard mask layer. The hard mask layer can use SiO2, Si3N4, TiN, amorphous carbon (ACHM), etc., and is mainly used for multiple exposure processes and the like. In some examples, a photoresist can be coated on the substrate on which the foregoing pattern is formed, and the mask pattern is formed by removing a part of the photoresist.

[0115] In some examples, as shown in FIGS. 3A to 3C, the mask pattern can be a pattern having both a framework and a hole structure. The framework of the mask pattern can be generally in the shape of a fishbone. For example, the framework of the mask pattern can include a "Feng" character-shaped structure and a rectangular block connected to one end of the "Feng" character-shaped structure. For example, the "Feng" character-shaped structure can include six branches extending along the first direction D1 and a main branch extending along the second direction Y. The six branches can be symmetrically arranged on both sides of the main branch in the first direction D1, and the rectangular block can be connected to one end of the main branch. The six branches can all be strips extending along the first direction D1, and the main trunk can be a strip extending along the second direction Y. The orthographic projection shapes of the branches and the main trunk on the substrate can be generally rectangular, and the length of the rectangular block along the first direction D1 can be greater than the length of the main trunk along the first direction D1.

[0116] In some examples, the hole structure of the mask pattern may include six holes arranged in a three-row and two-column array. Two holes arranged along the first direction D1 form a row, and three holes arranged along the second direction D2 form a column. The six holes are respectively located on the six branches of the "丰" character structure. In some examples, on a plane parallel to the substrate, the orthographic projection shape of the hole may be rectangular, such as square. This embodiment does not limit this. In other examples, the orthographic projection shape of the hole may be other shapes, such as circular, etc.

[0117] In this example, through one mask pattern, the architecture part of the semiconductor device and the through holes for setting word lines can be etched at one time, which can avoid the situation that the alignment deviation caused by separately etching the through holes affects the dimensional structure electrical characteristics of the semiconductor device and the miniaturization effect of the whole structure, thereby ensuring the structural size stability of the semiconductor device, being beneficial to achieving the miniaturization effect, and improving the yield of the semiconductor device; moreover, by etching the architecture area of the semiconductor device and the through holes for setting word lines at one time, the etching process can be reduced, the process can be simplified, and the cost can be reduced.

[0118] Subsequently, through the first mask 2, a patterning process is performed on the stacked structure, so that the stacked structure forms a patterned stacked structure, multiple first conductive thin films 11 form a patterned conductive layer 12, multiple first insulating thin films 10 form a patterned insulating layer 14, and multiple through holes K1 are formed. The patterned stacked structure includes a patterned conductive layer 12 and a patterned insulating layer 14 alternately arranged in sequence. The through hole K1 extends along a direction perpendicular to the substrate and penetrates the patterned stacked structure in the direction perpendicular to the substrate, as shown in FIGS. 3B and 3C. Among them, the orthographic projections of the patterned conductive layer 12 and the patterned insulating layer 14 on the substrate 1 may completely overlap, that is, the size and shape of the patterned conductive layer 12 are the same as those of the patterned insulating layer 14.

[0119] Figure 3C is a second schematic diagram of a semiconductor device fabrication process after forming a patterned conductive layer, a patterned insulating layer, and a through-hole, according to an exemplary embodiment. Figure 3C is a cross-sectional view parallel to the substrate. In an exemplary embodiment, as shown in Figure 3C, the patterned conductive layer 12 may include a bit line 30, multiple first sub-sections 21, and multiple second sub-sections 22. The bit line 30 connects the first sub-sections 21 and the second sub-sections 22. The first sub-sections 21 may extend along a first direction D1, the second sub-sections 22 may extend along the first direction D1, and the bit line 30 may extend along a second direction D2. The multiple first sub-sections 21 are spaced apart along the second direction D2, and one end of each of the multiple first sub-sections 21 is connected to the bit line 30. The multiple second sub-sections 22 are spaced apart along the second direction D2, and one end of each of the multiple second sub-sections 22 is connected to the bit line 30. The first sub-sections 21 subsequently form the first electrode 51 and the second electrode 52 of one transistor, and the second sub-sections 22 subsequently form the first electrode 51 and the second electrode 52 of another adjacent transistor.

[0120] FIG3D is a third schematic diagram of a semiconductor device after a patterned conductive layer, a patterned insulating layer, and a through hole are formed during the manufacturing process of an exemplary embodiment. FIG3D is a cross-sectional view perpendicular to the substrate direction, and FIG3D may be a cross-sectional view along the aa' direction in FIG3C. In an exemplary embodiment, as shown in FIG3D , a through hole K1 passes through a plurality of patterned conductive layers 12 and a plurality of patterned insulating layers 14, and the sidewalls of the through hole K1 expose each patterned conductive layer 12 and each patterned insulating layer 14. The first subsection 21 and the second subsection 22 are both provided with the through hole K1. The through hole K1 may extend in a direction perpendicular to the substrate. The bottom wall of the through hole K1 may or may not expose the substrate.

[0121] In an exemplary embodiment, the stacked structure may be dry-etched through the first mask 2 , and the etching may be performed using a high aspect ratio etching (HAR ET) method. In an exemplary embodiment, the aspect ratio is greater than 6:1.

[0122] In an exemplary embodiment, the orthographic projection of the through hole K1 on a plane parallel to the substrate may be a square, but this embodiment is not limited thereto.

[0123] In an exemplary embodiment, the orthographic projection of the through hole K1 on a plane parallel to the substrate is located within the orthographic projection of the patterned conductive layer 12. For example, on a plane parallel to the substrate, the orthographic projection of the through hole K1 passing through the first sub-portion 21 is located within the orthographic projection of the first sub-portion 21, and the orthographic projection of the through hole K1 passing through the second sub-portion 22 is located within the orthographic projection of the second sub-portion 22.

[0124] In step 103, a first sacrificial layer film 15 is deposited on the substrate 1 based on the substrate 1 on which the aforementioned pattern is formed. The first sacrificial layer film 15 covers a portion of the surface of the substrate 1, covers the side and upper surfaces of the patterned stacked structure, and fills the through hole K1. The first sacrificial layer film 15 fills the through hole K1 so that the surface of the stacked structure away from the substrate 1 is flush, as shown in FIG4A .

[0125] In step 104, based on the substrate 1 having the aforementioned pattern, the first sacrificial layer film 15 is subjected to a patterning process, and the first sacrificial layer film 15 covering the surface of the substrate 1 and the first sacrificial layer film 15 covering the side and upper surfaces of the patterned stacked structure are etched away, leaving the first sacrificial layer film 15 filling the through hole K1 to form a first sacrificial layer 16. The first sacrificial layer 16 fills the through hole K1, as shown in FIG4B .

[0126] Step 105 , forming a filling layer 17 on the substrate 1 based on the substrate 1 with the aforementioned pattern formed thereon. The filling layer 17 is provided on the same layer as the patterned stacked structure, surrounds the sidewall of the patterned stacked structure, and contacts the sidewall of the patterned stacked structure.

[0127] The surface of the filling layer 17 is ground so that the surface of the filling layer 17 away from the substrate is flush with the surface of the patterned stacked structure away from the substrate. The filling layer 17 and the patterned stacked structure form a regularly shaped film layer pattern. For example, the regularly shaped film layer pattern can be a rectangular parallelepiped, as shown in FIG4C .

[0128] The filling layer 17 may be made of insulating material, such as oxide.

[0129] Step 106 : Based on the substrate 1 with the aforementioned pattern formed thereon, a second mask 3 is placed on the surface of the film layer pattern away from the substrate 1 , as shown in FIG. 5A .

[0130] Subsequently, the film layer pattern is patterned by a second mask 3 to remove part of the filling layer 17 and part of the patterned insulating layer 14 on opposite sides of the film layer pattern to form a groove 18. The groove 18 exposes part of the surface of the substrate 1, exposing the end of the first sub-portion 21 away from the bit line 30 (including the end face and part of the side face of the first sub-portion 21), and exposing the end of the second sub-portion 22 away from the bit line 30 (including the end face and part of the side face of the second sub-portion 22), as shown in Figure 5B.

[0131] Subsequently, a second insulating film and a supporting layer material are sequentially deposited within the recess 18, so that the second insulating film forms a second insulating layer 19, and the supporting layer material forms a supporting layer 43. The second insulating layer 19 covers the exposed area of ​​the first sub-portion 21 and the exposed area of ​​the second sub-portion 22. In other words, the second insulating layer 19 covers the end surface and a portion of the sidewall of the first sub-portion 21 away from the bit line 30, as well as the end surface and a portion of the sidewall of the second sub-portion 22 away from the bit line 30. The second insulating layer 19 is disposed between the supporting layer 43 and the exposed area of ​​the first sub-portion 21, and between the second sub-portion 22 and the exposed area.

[0132] A support layer 43 is formed on the exposed end of the first sub-portion 21 away from the bit line 30, and on the exposed end of the second sub-portion 22 away from the bit line 30. The support layer 43 includes a fixing groove that secures the exposed end of the first sub-portion 21 away from the bit line 30 and the exposed end of the second sub-portion 22 away from the bit line 30. The support layer 43 is used to support the first sub-portion 21 and the second sub-portion 22, ensuring the mechanical stability of the first sub-portion 21 and the second sub-portion 22 during the formation of the second electrode plate 42, as shown in Figures 5C and 5D, where Figure 5D is a cross-sectional view parallel to the substrate.

[0133] The support layer 43 may be made of an insulating material, such as an oxide, to avoid generating capacitance with the subsequently formed second electrode plate 42 and thus affecting device performance.

[0134] Step 107, based on the substrate 1 formed with the aforementioned pattern, remove the filling layer 17 and the patterned insulating layer 14 located in the capacitor region. Part of the side surface of the first sub-section 21 is exposed, and part of the side surface of the second sub-section 22 is exposed. A first hollow portion 71 is formed between the exposed side surfaces of adjacent first sub-sections 21 in the same layer, and between the exposed side surfaces of the first sub-sections 21 in adjacent layers; a second hollow portion 72 is formed between the exposed side surfaces of adjacent second sub-sections 22 in the same layer, and between the exposed side surfaces of the second sub-sections 22 in adjacent layers. The capacitor region is the region of the capacitor formed by the first electrode 41 and the second electrode 42, and the capacitor region is located between the support layer 43 and the bit line 30.

[0135] In a direction parallel to the substrate, the first hollow portion 71 is located between the support layer 43 and the through hole K1, and surrounds the exposed side surface of the first sub-section 21. The second hollow portion 72 is located between the support layer 43 and the through hole K1, and surrounds the exposed side surface of the second sub-section 22, as shown in Figures 6A and 6B. Figure 6B is a cross-sectional view parallel to the substrate.

[0136] Step 108, on the basis of the substrate 1 with the aforementioned pattern formed, a third insulating film and a conductive material are sequentially deposited in the first hollow portion 71 and the second hollow portion 72, so that the third insulating film forms a third insulating layer 13, and the conductive material forms a second electrode 42, and the third insulating layer 13 covers the exposed area of ​​the first sub-portion 21 and the exposed area of ​​the second sub-portion 22, as shown in Figures 7A and 7B, and Figure 7B is a cross-sectional view parallel to the direction of the substrate.

[0137] The second electrode plate 42 surrounds the first electrode plate 41 , is located between the support layer 43 and the gate electrode 26 , and extends on the sidewall of the first electrode plate 41 to form a ring extending in a direction parallel to the substrate.

[0138] The third insulating layer 13 serves as a medium between the capacitor plates, the second plate 42 serves as one electrode of the capacitor, and the exposed first sub-portion 21 or the exposed second sub-portion 22 serves as the other electrode of the capacitor, namely the first plate.

[0139] In an exemplary embodiment, the third insulating film and the conductor material may be deposited by atomic layer deposition (ALD).

[0140] In an exemplary embodiment, the third insulating film may be a High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0141] In an exemplary embodiment, the conductor material includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.

[0142] Step 108: Based on the substrate 1 with the aforementioned pattern formed thereon, the first sacrificial layer 16 located in the through hole K1 is removed by etching, as shown in Figure 8. Figure 8 is a cross-sectional view parallel to the substrate.

[0143] Step 109: Etch the patterned conductive layer 12 in a direction parallel to the substrate and away from the through hole K1. Etch the through hole K1 on the first sub-portion 21 and the second sub-portion 22 of each patterned conductive layer 12 in a direction away from the through hole K1. Expand the area of ​​the through hole K1 located in the patterned conductive layer 12 away from the through hole K1, thereby increasing the area of ​​the orthographic projection of the through hole K1 on the substrate 1. This forms a first electrode 51 and a second electrode 52 separated from each other in each patterned conductive layer 12, as shown in Figures 9A and 9B. Figure 9A is a cross-sectional view parallel to the substrate, Figure 9B is a cross-sectional view perpendicular to the substrate, and Figure 9B is a cross-sectional view taken along the bb' direction in Figure 9A.

[0144] The area where the through hole K1 is located in the patterned insulating layer 14 is not etched, so that on a plane parallel to the substrate, the orthographic projection of the through hole K1 located in the patterned insulating layer 14 on the substrate falls within the orthographic projection of the through hole K1 located in the patterned conductive layer 12 on the substrate, that is, the through hole K1 forms a plurality of dumbbell-shaped structures.

[0145] In one exemplary embodiment, wet etching can be performed using an acid solution with a high selectivity for the patterned insulating layer 14 and the patterned conductive layer 12, and the patterned conductive layer 12 can be laterally etched to a certain thickness L in a direction away from the through hole K1. Due to the high selectivity, the patterned insulating layer 14 is hardly etched. For example, if the cross-section of the through hole K1 parallel to the substrate is a square, the side length of the through hole K1 in the patterned conductive layer 12 is D, and the side length of the through hole K1 in the patterned insulating layer 14 is d, where D = d + 2*L. In one exemplary embodiment, D is, for example, 80 nm to 110 nm, d is, for example, 50 nm ± 10%, and L is, for example, 15 nm to 30 nm. For example, D can be 80 nm and L can be 15 nm, or D can be 90 nm and L can be 20 nm, or D can be 100 nm and L can be 25 nm, or D can be 110 nm and L can be 30 nm.

[0146] Step 110 : forming a semiconductor layer 23 , a gate insulating layer 24 and a second sacrificial layer 25 .

[0147] The formation of the semiconductor layer 23, the gate insulating layer 24, and the second sacrificial layer 25 includes: sequentially depositing a semiconductor film and a gate insulating film on the sidewalls of the through hole K1 to form the semiconductor layer 23 and the gate insulating layer 24; after the deposition of the semiconductor layer 23 and the gate insulating layer 24, the size of the through hole K1 located in the parasitic MOS region 300 is smaller than the size of the through hole K1 located in the transistor channel region 200 in the first direction D1, as shown in FIG10A. FIG10A is a cross-sectional view perpendicular to the substrate.

[0148] Subsequently, a second sacrificial layer thin film is deposited in the through hole K1 to form a second sacrificial layer 25, which fills the through hole K1. The second sacrificial layer 25 serves as a protective layer for the semiconductor layer 23 in the transistor channel region 200 during the subsequent etching of the semiconductor layer 23 and gate insulation layer 24 on the sidewalls of the parasitic MOS region 300. The second sacrificial layer 25 fills the through hole K1. The size of the second sacrificial layer 25 in the transistor channel region 200 is larger in the first direction D1 than the size of the second sacrificial layer 25 in the parasitic MOS region 300. This facilitates protection of the semiconductor layer 23 in the transistor channel region 200 during the subsequent removal of the conductor 23 and gate insulation layer 24 in the parasitic MOS region 300, as shown in Figure 10B. Figure 10B is a cross-sectional view perpendicular to the substrate.

[0149] In one exemplary embodiment, the material of the second sacrificial layer film can be a conductive material, such as the same material as the subsequent gate electrode film. Thus, after etching away the semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the parasitic MOS region 300, the second sacrificial layer 25 does not need to be removed before depositing the gate electrode film. The gate electrode film can be directly deposited, and the second sacrificial layer 25, which serves as a protective layer, and the deposited gate electrode film together serve as the gate electrode of the final device. However, the disclosed embodiments are not limited to this. The material of the sacrificial layer film can be different from that of the gate electrode film. After etching away the semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the parasitic MOS region 300, the second sacrificial layer 25 does not need to be removed before depositing the gate electrode film.

[0150] In an exemplary embodiment, the semiconductor film, the gate insulating film, and the second sacrificial layer film may be deposited by ALD.

[0151] In one exemplary embodiment, the semiconductor thin film includes, but is not limited to, at least one of the following: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO). Using IGZO as the semiconductor layer offers the advantages of low leakage current and short refresh time.

[0152] In an exemplary embodiment, the gate insulating film may be a High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0153] In an exemplary embodiment, the second sacrificial layer thin film includes but is not limited to at least one of the following: indium tin oxide (ITO), TiN / W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).

[0154] Step 111 : removing the semiconductor layer 23 and the gate insulating layer 24 located in the through hole K1 of the parasitic MOS region 300 .

[0155] In an exemplary embodiment, a mask may be used to open the through hole K1, and then a three-step etching process may be performed, comprising a first dry etch (anisotropic dry etch), a wet etch (isotropic wet etch), and a second dry etch (anisotropic dry etch), to remove the semiconductor layer 23 and the gate insulating layer 24 from the sidewalls of the parasitic MOS region 300. Specifically, the removal of the semiconductor layer 23 and the gate insulating layer 24 from the parasitic MOS region 300 may include etching the second sacrificial layer 25 using the first dry etch. Due to the anisotropic etching, the second sacrificial layer 25 located on the sidewalls of the through hole K1 in the parasitic MOS region 300 is completely etched, while a portion of the second sacrificial layer 25 located on the sidewalls of the through hole K1 in the transistor channel region 200 remains, as shown in FIG11A , which is a cross-sectional view perpendicular to the substrate.

[0156] Because the second sacrificial layer 25 remaining on the sidewall of the through hole K1 located in the transistor channel region 200 is too thick, when the semiconductor layer 23 and the gate insulating layer 24 of the parasitic MOS region 300 are subsequently etched using a dry method, it may block the etching of the semiconductor layer 23 and the gate insulating layer 24 of the next parasitic MOS region 300. Therefore, the second sacrificial layer 25 retained on the sidewall of the through hole K1 located in the transistor channel region 200 is recessed using a wet etching method, and a portion of the second sacrificial layer 25 is retained during the recessed etching to serve as a protective layer for the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200, thereby preventing the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200 from being damaged during the subsequent dry etching of the semiconductor layer 23 and the gate insulating layer 24 of the parasitic MOS region 300. That is, the second sacrificial layer 25 serves as an inner spacer to protect the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200. As shown in FIG. 11B , FIG. 11B is a cross-sectional view perpendicular to the substrate direction.

[0157] The semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the through hole K1 in the parasitic MOS region 300 are completely etched away by dry etching from the top layer to the bottom layer.

[0158] Step 112 , forming the gate electrode 26 .

[0159] In some examples, forming the gate electrode 26 includes: depositing a gate electrode thin film in the through hole K1 to form the gate electrode 26 , wherein the gate electrode 26 fills the through hole K1 , as shown in FIG. 1A .

[0160] In one exemplary embodiment, the gate electrode thin film may be deposited by ALD.

[0161] In an exemplary embodiment, the gate electrode film may include but is not limited to at least one of the following: indium tin oxide (ITO), TiN / W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).

[0162] In step 113, a portion of the patterned stacked structure located on one side of the memory cell is etched away to form a through hole K2. A conductive film is deposited in the through hole K2 to form a detection pin 61 formed from the conductive film. The detection pin 61 is electrically connected to the bit line 30 of each layer of the memory cell, as shown in FIG1B .

[0163] The solution provided in this embodiment forms a patterned stacked structure and the through hole K1 simultaneously through a single patterning process, which simplifies the process flow, is easy to implement, and improves production efficiency. It has the advantages of easy process implementation, low production cost, and high yield.

[0164] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0165] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of memory cells stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate, the memory cells comprising: A transistor and a capacitor, wherein the transistor comprises a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, and the capacitor comprises a first plate and a second plate; and the manufacturing method of the semiconductor device comprises: Providing a substrate, and alternately depositing a first insulating film and a conductive film on the substrate in sequence to form a stacked structure; The stacked structure is formed into a patterned stacked structure and a through hole through a single composition process; the patterned stacked structure includes a patterned conductive layer and a patterned insulating layer that are alternately arranged in sequence; the through hole penetrates the patterned stacked structure in a direction perpendicular to the substrate, and the side wall of the through hole exposes the patterned conductive layer and the patterned insulating layer, and the through hole is configured to accommodate the word line.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming the stacked structure into a patterned stacked structure and forming a through hole through a single composition process includes: performing a composition process on the stacked structure through a mask pattern on a film layer to form the stacked structure into a patterned stacked structure and form a through hole; the mask pattern is a pattern having both an architecture and a hole structure.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The film layer is photoresist.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The film layer is a hard mask layer.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, further comprising: forming a first sacrificial layer filling the through hole; forming a filling layer surrounding the sidewalls of the patterned stacked structure; Removing part of the filling layer and part of the patterned insulating layer to expose part of the patterned conductive layer, making the exposed patterned conductive layer serve as the first electrode plate, and forming the second electrode plate in the area where the filling layer and the patterned insulating layer are removed; Etching and removing the first sacrificial layer; On a plane parallel to the substrate, etching the patterned conductive layer in a direction away from the through hole, wherein the through hole enables the patterned conductive layer to form a first electrode and a second electrode separated from each other; A mutually insulated semiconductor film and a gate electrode film are sequentially deposited on the sidewalls of the through hole to form the semiconductor layer, the gate electrode and the word line.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The forming of a first sacrificial layer filling the through hole comprises: Depositing a first sacrificial layer thin film on the substrate, wherein the first sacrificial layer thin film covers a portion of the surface of the substrate, covers the side surfaces and the upper surface of the patterned stacked structure, and fills the through hole; The first sacrificial layer film is subjected to a composition process to remove the first sacrificial layer film covering the surface of the substrate and the first sacrificial layer film covering the side and upper surface of the patterned stacked structure, and the first sacrificial layer film filling the through hole is retained to form the first sacrificial layer.

7. The method for manufacturing a semiconductor device according to claim 5, after forming a filling layer surrounding the sidewall of the patterned stacked structure, the method further comprises: The surface of the filling layer is ground to make the surface of the filling layer away from the substrate flush with the surface of the patterned stacked structure away from the substrate.

8. The method for manufacturing a semiconductor device according to claim 5, wherein the removing of a portion of the filling layer and a portion of the patterned insulating layer exposes a portion of the patterned conductive layer, and the exposed patterned conductive layer is used as a first electrode plate. Before the region where the filling layer and the patterned insulating layer are removed to form a second electrode plate, the method further comprises: Removing the filling layer and the patterned insulating layer on at least one side of the film layer pattern to expose one end of the patterned conductive layer; A support layer is formed on the exposed end of the patterned conductive layer, wherein the support layer comprises a fixing groove, and the fixing groove fixes the exposed end of the patterned conductive layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The support layer includes an insulating material.

10. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising: Multiple layers of memory cells and word lines stacked in a direction perpendicular to a substrate, wherein the word lines extend in a direction perpendicular to the substrate and penetrate through the memory cells of different layers; The storage unit includes: a transistor and a capacitor, the transistor includes a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, the semiconductor layer extends on the side wall of the gate electrode to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; the capacitor includes a first plate and a second plate.

11. The semiconductor device according to claim 10, further comprising: A support layer is located on a side of the first electrode plate away from the gate electrode, the support layer comprises a fixing groove, the opening of the fixing groove faces one end of the first electrode plate, and one end of the first electrode plate extends into the fixing groove.

12. The semiconductor device according to claim 11, wherein The second electrode plate is located between the support layer and the word line, the second electrode plate surrounds the first electrode plate, and the second electrode plate extends on the side wall of the first electrode plate to form a ring extending in a direction parallel to the substrate.

13. An electronic device comprising the semiconductor device according to any one of claims 10 to 12.

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