Memory system and operation method thereof, and computer readable storage medium

Abstract

Embodiments of the present disclosure provide a memory system and an operation method thereof, and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled to the memory device. The memory controller is configured to: trigger an assertion when firmware of the memory system is abnormal in the operation process; when a hardware sequence command is not released within a preset duration after the firmware is abnormal, configure a flag for stopping the hardware sequence command; and in response to the flag for stopping the hardware sequence command, stop the hardware sequence command such that the hardware sequence command is released.

Description

Memory system and operation method thereof, and computer-readable storage medium Technical Field

[0001] The present disclosure relates to, but is not limited to, a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems, such as solid-state drives (SSDs), are appearing in electronic devices. SSDs, due to their fast read and write speeds, vibration resistance, low power consumption, quiet operation, low heat generation, and lightweight design, have found widespread application in military, automotive, industrial, medical, and aviation applications.

[0003] However, there are still many problems that need to be solved in the memory system in the related art.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, a memory system is provided, comprising a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0006] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0007] When the hardware sequence command is not released within a preset time after an abnormality occurs in the firmware, a flag for terminating the hardware sequence command is set;

[0008] In response to the flag for suspending the hardware sequence command, the hardware sequence command is suspended, so that the hardware sequence command is released.

[0009] In some embodiments, the memory controller is configured to:

[0010] When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

[0011] In some embodiments, the preset time is greater than 2 seconds.

[0012] In some embodiments, the memory controller is configured to:

[0013] After the hardware sequence command is released, a command is sent to save abnormal scene information into the memory device.

[0014] In some embodiments, the memory controller is configured to:

[0015] Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller;

[0016] After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

[0017] In some embodiments, the memory controller is configured to:

[0018] Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

[0019] In some embodiments, the memory controller is configured to:

[0020] After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, the assertion processing mode is determined to be triggered.

[0021] In some embodiments, the memory controller is configured to:

[0022] After the assertion is triggered, when it is determined that the exception is caused by an error correction code operation and the exception caused by the error correction code operation occurs for the first time at the location of the corresponding memory device causing the exception, the assertion processing mode is determined to be triggered.

[0023] In some embodiments, the memory controller is configured to:

[0024] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0025] Based on the abnormality scene information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the abnormality caused by executing the error correction code operation occurs for the first time at the location of the corresponding memory device causing the abnormality.

[0026] In some embodiments, the memory controller is configured to:

[0027] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0028] According to a second aspect of an embodiment of the present disclosure, another memory system is provided, comprising a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0029] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0030] When the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception is not the first time that the exception caused by executing an error correction code operation occurs, it is determined not to trigger the assertion processing mode.

[0031] In some embodiments, the memory controller is configured to:

[0032] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0033] Based on the abnormality site information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

[0034] In some embodiments, the memory controller is configured to:

[0035] After determining that the assertion processing mode is not triggered, a command is sent to save event log information into the memory device.

[0036] In some embodiments, the memory controller is configured to:

[0037] When the exception is not an exception caused by executing an error correction code operation, or when the exception is an exception caused by executing an error correction code operation and the location of the corresponding memory device that caused the exception occurs for the first time, it is determined that the assertion processing mode is triggered.

[0038] In some embodiments, the memory controller is configured to:

[0039] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0040] According to a third aspect of an embodiment of the present disclosure, a method for operating a memory system is provided, the method comprising:

[0041] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0042] When the hardware sequence command is not released within a preset time after an abnormality occurs in the firmware, a flag for terminating the hardware sequence command is set;

[0043] In response to the flag for suspending the hardware sequence command, the hardware sequence command is suspended, so that the hardware sequence command is released.

[0044] In some embodiments, the method further comprises:

[0045] When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

[0046] In some embodiments, the preset time is greater than 2 seconds.

[0047] In some embodiments, the method further comprises:

[0048] After the hardware sequence command is released, a command is sent to save abnormal scene information into the memory device.

[0049] In some embodiments, the method further comprises:

[0050] Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller;

[0051] After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

[0052] In some embodiments, the method further comprises:

[0053] Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

[0054] In some embodiments, the method further comprises:

[0055] After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, the assertion processing mode is determined to be triggered.

[0056] In some embodiments, the method further comprises:

[0057] After the assertion is triggered, when it is determined that the exception is caused by an error correction code operation and the exception caused by the error correction code operation occurs for the first time at the location of the corresponding memory device causing the exception, the assertion processing mode is determined to be triggered.

[0058] In some embodiments, the method further comprises:

[0059] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0060] Based on the abnormality scene information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the abnormality caused by executing the error correction code operation occurs for the first time at the location of the corresponding memory device causing the abnormality.

[0061] In some embodiments, the method further comprises:

[0062] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0063] According to a fourth aspect of an embodiment of the present disclosure, another method for operating a memory system is provided, the method comprising:

[0064] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0065] When the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception is not the first time that the exception caused by executing an error correction code operation occurs, it is determined not to trigger the assertion processing mode.

[0066] In some embodiments, the method further comprises:

[0067] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0068] Based on the abnormality site information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

[0069] In some embodiments, the method further comprises:

[0070] After determining that the assertion processing mode is not triggered, a command is sent to save event log information into the memory device.

[0071] In some embodiments, the method further comprises:

[0072] When the exception is not an exception caused by executing an error correction code operation, or when the exception is an exception caused by executing an error correction code operation and the location of the corresponding memory device that caused the exception occurs for the first time, it is determined that the assertion processing mode is triggered.

[0073] In some embodiments, the method further comprises:

[0074] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0075] According to a fifth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any one of the schemes in some implementation methods is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0077] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0078] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0079] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0080] FIG3 b is a schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0081] FIG4 is a cross-sectional schematic diagram of a memory array including memory strings according to an embodiment of the present disclosure;

[0082] FIG5 is a schematic diagram of an exemplary memory including a memory array and peripheral circuits according to an embodiment of the present disclosure;

[0083] FIG6 is a schematic diagram of an implementation flow of an operating method of a memory system according to an embodiment of the present disclosure;

[0084] FIG7 is a schematic diagram of a framework flow of an operating method of a memory system according to an embodiment of the present disclosure;

[0085] FIG8 is a schematic diagram of an implementation flow of an operating method of a memory system according to another embodiment of the present disclosure;

[0086] FIG9 is a schematic diagram of a framework flow of an operating method of a memory system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0088] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0089] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0090] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0091] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0092] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0093] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0094] FIG1 shows a block diagram of an exemplary system 100 with memory according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 may include a host 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit) or a system on chip (e.g., an application processor) of an electronic device. Host 108 can be configured to send data to memory device 104 or receive data from memory device 104.

[0095] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0096] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is also configured to process error correction codes for data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., a host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with the external device using at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect protocol, a peripheral component interconnect high-speed protocol, an advanced technology attachment protocol, a serial advanced technology attachment protocol, a parallel advanced technology attachment protocol, a minicomputer small form factor interface protocol, an enhanced minidisk interface protocol, an integrated drive electronics protocol, a firmware protocol, and the like.

[0097] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example, as shown in FIG2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some implementations, the storage capacity and / or operating speed of SSD 206 is greater than the storage capacity and / or operating speed of memory card 202 .

[0098] Figure 3a illustrates a schematic structural diagram of a memory array of a three-dimensional NAND memory. As shown in Figure 3a, the memory array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cells parallel to gate isolation structures. Every four rows of memory cells are separated by gate isolation structures and upper select gate isolation structures, and each memory cell row includes multiple memory cells. The gate isolation structures may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks (blocks). The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas (finger). An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this number. The memory cells in a memory slice coupled to a word line may be referred to as a memory page (page), where a memory page is a physical page.

[0099] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory disclosed herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0100] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to memory array 301. For illustration, memory array 301 is described as a three-dimensional NAND-type memory array, wherein memory cells 306 are NAND memory cells, and memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0101] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0102] As shown in FIG3b , each memory string 308 may include a bottom selected transistor (BST) 310 at its source terminal and a top selected transistor (TST) 312 at its drain terminal. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having TST 312) or a deselect voltage (e.g., 0 V) ​​to the corresponding TST 312 via one or more TSLs (Top selected lines) 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having BST 310) or a deselect voltage (e.g., 0 V) ​​to the corresponding BST 310 via one or more BSLs (Bottom Selected lines) 315.

[0103] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits can be related to the number of memory strings 308 coupled by the word line 318 in a memory block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and a gate line coupled to the control gates. Referring to FIG. 3 a above, a memory page 320 includes multiple memory cells 306, each of which is isolated by an upper select gate isolation structure and a gate isolation structure. The multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0104] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 according to aspects of the present disclosure. As shown in FIG4 , memory strings 308 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be alternately stacked, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array 301 is primarily related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0105] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0106] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0107] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0108] Referring back to FIG3 b , the peripheral circuitry 302 can be coupled to the memory array 301 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, FIG5 illustrates some exemplary peripheral circuitry, where the peripheral circuitry 302 includes a page buffer / sense amplifier 504 , a column decoder / bit line driver 506 , a row decoder / word line driver 508 , a voltage generator 510 , a control logic unit 512 , a register 514 , an interface 516 , and a data bus 518 . It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0109] The page buffer / sense amplifier 504 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated by the voltage generator 510.

[0110] The row decoder / wordline driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect memory blocks 304 of the memory array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / wordline driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / wordline driver 508 can also select / deselect and drive the BSL 315 and TSL 313. As described in detail below, the row decoder / wordline driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0111] The control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, as well as buffer status information received from the control logic unit 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0112] Operations of the memory system (eg, a write data operation, a read data operation, an erase data operation, etc.) may be implemented by running firmware stored in the memory system.

[0113] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0114] During firmware execution, firmware failures (bugs) inevitably occur. Traditionally, these failures directly trigger assertions, which in turn trigger the assertion handling mode, terminating program execution and saving the error information. With increasing demands for 3D NAND memory, ensuring that error information is successfully saved after a firmware error occurs and improving user testing efficiency have become pressing issues.

[0115] In view of one or more of the above problems, an embodiment of the present disclosure provides an operating method of a memory system, as shown in FIG6 , the method comprising:

[0116] Step S1001: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0117] Step S1002: When the hardware sequence command is not released within a preset time after the firmware is abnormal, a flag for terminating the hardware sequence command is set;

[0118] Step S1003: In response to the flag for terminating the hardware sequence command, terminating the hardware sequence command, so that the hardware sequence command is released.

[0119] The operation method of the memory system will be described in detail below with reference to FIG6 and FIG7 .

[0120] Here, firmware is a program written into an erasable programmable read-only memory or an electrically erasable programmable read-only memory. It refers to the device "driver" stored inside the memory system. Through firmware, the operating system can implement specific operating actions according to standard device drivers. Firmware is the software that performs the most basic and lowest-level work of a system.

[0121] In some specific examples, the firmware is stored in a read-only memory in a memory controller of the memory system or in a memory device.

[0122] Exceptions are inevitable during firmware operation. These exceptions trigger assertions and, under certain conditions, assertion handling, saving information about the exception. This information can include coredump information such as the PC pointer, stack usage, and registers. Saving this information preserves the fault scene and provides data support for subsequent system recovery.

[0123] When a firmware exception occurs, it may be executing or about to execute a hardware sequence command. A hardware sequence command specifies the order in which read, write, and erase commands are executed. When an exception occurs during firmware execution, the current task must be cleared and the hardware sequence command released before the exception-scene information can be saved. However, if the hardware sequence command cannot be released, the firmware will be stuck in an infinite loop ("while" in English), causing the exception-scene information to fail to be saved.

[0124] Regarding how to release the hardware sequence command, the embodiments of the present disclosure provide different implementation methods according to different situations.

[0125] In some embodiments, in the assertion triggering processing mode, when a hardware sequence command is not released within a preset time after an exception occurs in the firmware, a flag for terminating the hardware sequence command is set.

[0126] It can be understood that the abnormal scene information can only be saved after the hardware sequence command is released. When the hardware sequence command is not released within the preset time, it means that the firmware is stuck in the while loop and cannot be released automatically. In the embodiment of the present disclosure, a flag for terminating the hardware sequence command is set, and the hardware sequence command is forced to be released in response to the flag for terminating the hardware sequence command in the subsequent process, thereby avoiding the problem of failure to save the abnormal scene information due to the inability to automatically release the hardware sequence command.

[0127] In some embodiments, the method further comprises:

[0128] When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

[0129] It is understandable that the hardware sequence command can also be released automatically, and the time required for the hardware sequence command to complete the automatic release is generally short. When the hardware sequence command is released within the preset time, it means that the firmware is not stuck in the while loop, and the hardware sequence command has completed the automatic release. Therefore, there is no need to set an additional flag to terminate the hardware sequence command to force the release of the hardware sequence command.

[0130] In some embodiments, the preset time is greater than 2 seconds.

[0131] It should be noted that the preset time range given in the above embodiment is only for illustrative purposes and is not intended to limit the preset time range of the embodiment of the present disclosure. In actual applications, the preset time range can be set according to the normal automatic release time of the hardware sequence command.

[0132] In some specific examples, as shown in FIG7 , it may be checked whether a flag for terminating the hardware sequence command is set. If the flag for terminating the hardware sequence command is set, the hardware sequence command is directly forced to be terminated, so that the hardware sequence command completes the forced release.

[0133] In some embodiments, the method further comprises:

[0134] After the hardware sequence command is released, a command is sent to save abnormal scene information into the memory device.

[0135] In some embodiments, the method further comprises:

[0136] Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller;

[0137] After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

[0138] Here, when an exception occurs during firmware operation, an assertion will be triggered. After the assertion is triggered, the exception field information will be cached in the cache of the memory controller. When the hardware sequence command is released, the exception field information stored in the memory controller will be transferred to a specific storage block in the memory device.

[0139] In some embodiments, as shown in FIG7 , the method further includes:

[0140] Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

[0141] It is understandable that when sending a command to save the abnormal scene information to the memory device, the memory device may still be executing other commands, resulting in the inability to execute the command to save the abnormal scene information. Therefore, before sending a command to save the abnormal scene information to the memory device, the memory device needs to be reset first so that the abnormal scene information can be saved.

[0142] The occurrence of an exception during the firmware operation will trigger an assertion. The assertion can further judge the abnormal situation of the firmware and determine whether the abnormal situation meets certain set conditions. If certain set conditions are not met, the assertion processing mode will not be triggered, the program will continue to run, and the on-site problem information will not be saved; only when certain set conditions are met will the assertion processing mode be triggered again. In the assertion processing mode, the program will be terminated and the abnormal on-site information will be saved.

[0143] In some embodiments, the method further comprises:

[0144] After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, the assertion processing mode is determined to be triggered.

[0145] In some embodiments, the method further comprises:

[0146] After the assertion is triggered, when it is determined that the exception is caused by an error correction code operation and the exception caused by the error correction code operation occurs for the first time at the location of the corresponding memory device causing the exception, the assertion processing mode is determined to be triggered.

[0147] It is understood that exceptions that occur during firmware execution can occur in a variety of situations. For example, when a special exception occurs, such as an exception caused by executing an error correction code (including 0x43C and 0xA107), and the location of the memory device where the exception occurred has previously occurred, the firmware cannot guarantee that such an exception will not occur again. Therefore, it is not necessary to save the exception scene information every time. The 0x43C and 0xA107 exceptions can occur during garbage collection and host reads, respectively.

[0148] In some embodiments, the method further comprises:

[0149] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0150] Based on the abnormality scene information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the abnormality caused by executing the error correction code operation occurs for the first time at the location of the corresponding memory device causing the abnormality.

[0151] It can be understood that after the current exception occurs, the exception scene information of the exception that occurred before the corresponding memory device position that caused the exception to occur, which is stored in the memory device, can be read to determine whether the current exception has occurred before at the corresponding position of the memory device, thereby determining whether this exception occurs for the first time at this position, and then determining whether to trigger the assertion processing mode.

[0152] In some embodiments, the method further comprises:

[0153] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0154] In the embodiment of the present disclosure, after the assertion is triggered, the abnormal situation is further judged. When it is determined that the abnormality is not an abnormality caused by executing an error correction code operation, or when it is determined that the abnormality is an abnormality caused by executing an error correction code operation, and the position of the corresponding memory device that caused the abnormality occurs for the first time, it is determined to trigger the assertion processing mode, thereby avoiding the repeated occurrence of the abnormality caused by executing the error correction code operation at the same position, triggering the assertion processing mode, thereby avoiding unnecessary termination of the running program and unnecessary saving of abnormal scene information, thereby improving user testing efficiency.

[0155] An embodiment of the present disclosure provides an operating method for a memory system, the method comprising: triggering an assertion when an exception occurs in the firmware of the memory system during operation; setting a flag for terminating the hardware sequence command when a hardware sequence command is not released within a preset time after the firmware exception occurs; terminating the hardware sequence command in response to the flag for terminating the hardware sequence command, so that the hardware sequence command is released. In an embodiment of the present disclosure, when an exception occurs in the firmware during operation, the release status of the hardware sequence command is judged. When the hardware sequence command is not released within the preset time, it indicates that the firmware is stuck in an infinite loop and cannot be released automatically. By setting a flag for terminating the hardware sequence command, the hardware sequence command is forcibly terminated, thereby forcing the hardware sequence command to be released, thereby avoiding the problem of the inability to save abnormal scene information due to the inability to release the hardware sequence command.

[0156] An embodiment of the present disclosure provides another method for operating a memory system, as shown in FIG8 , the method comprising:

[0157] Step S2001: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0158] Step S2002: When the exception is caused by executing an ECC operation, and the location of the corresponding memory device causing the exception is not the first occurrence of the exception caused by executing an ECC operation, determine not to trigger the assertion processing mode.

[0159] In some specific examples, the exceptions that occur during firmware operation include various situations. When some special exceptions occur, such as the exceptions caused by executing error correction code operations (including 0x43C and 0xA107), if the memory system discovers that these two exceptions have occurred, it will generally mark the corresponding position of the memory device that caused the exception as a medium error (expressed in English as Medium Error), and the program will continue to run, but this exception at this position may continue to trigger the assertion processing mode, causing the test to be disconnected midway. Moreover, the location of the memory device corresponding to the exception has previously experienced this exception, and the firmware cannot guarantee that such an exception will not occur. Therefore, it is not necessary to save the exception scene information every time. The two exceptions 0x43C and 0xA107 can be caused during garbage collection and host read processes respectively.

[0160] It is understandable that if the assertion processing mode is triggered, since the assertion processing mode will terminate the running program and save the exception scene information, it will take a certain amount of time, resulting in low user testing efficiency. After the assertion is triggered, the embodiment of the present disclosure further judges the abnormal situation. When the abnormality is caused by the execution of the error correction code operation, and the location of the corresponding memory device that causes the abnormality is not the first time that the abnormality caused by the execution of the error correction code operation occurs, the assertion processing mode is not triggered, thereby avoiding unnecessary termination of the running program and unnecessary saving of the exception scene information when the abnormality caused by the execution of the error correction code operation occurs repeatedly at the same location, thereby improving user testing efficiency.

[0161] The operation method of the memory system will be described in detail below with reference to FIG8 and FIG9 .

[0162] In some embodiments, the method further comprises:

[0163] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0164] Based on the abnormality site information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

[0165] It can be understood that after the current exception occurs, the exception field information of the exception that occurred before the position of the corresponding memory device that caused the exception can be read in the memory device, so as to determine whether the current exception has occurred before at the corresponding position of the memory device, thereby determining whether the exception has occurred at this position, and then determining whether to trigger the assertion processing mode.

[0166] In some embodiments, the method further comprises:

[0167] After determining that the assertion processing mode is not triggered, a command is sent to save event log information into the memory device.

[0168] Here, the event log information simply records the abnormality, for example, the time when the abnormality occurs and the location of the corresponding memory device.

[0169] In some embodiments, the method further comprises:

[0170] When the exception is not an exception caused by executing an error correction code operation, or when the exception is an exception caused by executing an error correction code operation and the location of the corresponding memory device that caused the exception occurs for the first time, it is determined that the assertion processing mode is triggered.

[0171] In some embodiments, the method further comprises:

[0172] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0173] It is understandable that the firmware provided to users generally does not trigger assertions. If an assertion is triggered, it means that a serious problem has occurred and the program will not continue to run in a loop. However, the two exceptions 0x43C and 0xA107 are more special. They are caused by the generation of uncorrectable UECC on the memory device. After the exception problem is handled later, the firmware cannot guarantee that such an exception will not occur again. Therefore, there is no need to repeatedly record the exception scene information of such an exception, nor is there any need to terminate the program. Since terminating the program and saving the exception scene information both consume a lot of time, this will make the test efficiency low.

[0174] An embodiment of the present disclosure provides an operating method for a memory system, the method comprising: when an exception occurs during the operation of the firmware of the memory system, triggering an assertion; when the exception is an exception caused by the execution of an error correction code operation, and the location of the corresponding memory device that caused the exception is not the first time that the exception caused by the execution of the error correction code operation has occurred, determining not to trigger an assertion processing mode. In an embodiment of the present disclosure, when an exception occurs during the operation of the firmware, the abnormal situation is further judged, and when the exception is an exception caused by the execution of an error correction code operation, and the location of the corresponding memory device that caused the exception is not the first time that the exception caused by the execution of the error correction code operation has occurred, the assertion processing mode is not triggered, thereby avoiding unnecessary suspension of program operation and unnecessary storage of abnormal field information, thereby improving test efficiency and saving capacity for storing abnormal field information.

[0175] Based on the above-mentioned operating method of the memory system, an embodiment of the present disclosure further provides a memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0176] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0177] When the hardware sequence command is not released within a preset time after an abnormality occurs in the firmware, a flag for terminating the hardware sequence command is set;

[0178] In response to the flag for suspending the hardware sequence command, the hardware sequence command is suspended, so that the hardware sequence command is released.

[0179] In some embodiments, the memory controller is configured to:

[0180] When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

[0181] In some embodiments, the preset time is greater than 2 seconds.

[0182] In some embodiments, the memory controller is configured to:

[0183] After the hardware sequence command is released, a command is sent to save abnormal scene information into the memory device.

[0184] In some embodiments, the memory controller is configured to:

[0185] Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller;

[0186] After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

[0187] In some embodiments, the memory controller is configured to:

[0188] Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

[0189] In some embodiments, the memory controller is configured to:

[0190] After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, the assertion processing mode is determined to be triggered.

[0191] In some embodiments, the memory controller is configured to:

[0192] After the assertion is triggered, when it is determined that the exception is caused by an error correction code operation and the exception caused by the error correction code operation occurs for the first time at the location of the corresponding memory device causing the exception, the assertion processing mode is determined to be triggered.

[0193] In some embodiments, the memory controller is configured to:

[0194] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0195] Based on the abnormality scene information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the abnormality caused by executing the error correction code operation occurs for the first time at the location of the corresponding memory device causing the abnormality.

[0196] In some embodiments, the memory controller is configured to:

[0197] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0198] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0199] Based on the above-mentioned operating method of the memory system, an embodiment of the present disclosure further provides another memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0200] When an exception occurs in the firmware of the memory system during operation, an assertion is triggered;

[0201] When the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception is not the first time that the exception caused by executing an error correction code operation occurs, it is determined not to trigger the assertion processing mode.

[0202] In some embodiments, the memory controller is configured to:

[0203] acquiring abnormality site information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs;

[0204] Based on the abnormality site information of the corresponding memory device location causing the abnormality stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

[0205] In some embodiments, the memory controller is configured to:

[0206] After determining that the assertion processing mode is not triggered, a command is sent to save event log information into the memory device.

[0207] In some embodiments, the memory controller is configured to:

[0208] When the exception is not an exception caused by executing an error correction code operation, or when the exception is an exception caused by executing an error correction code operation and the location of the corresponding memory device that caused the exception occurs for the first time, it is determined that the assertion processing mode is triggered.

[0209] In some embodiments, the memory controller is configured to:

[0210] After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

[0211] Here, the specific structure and composition of the memory system can be referred to the detailed description of Figures 1, 2a, 2b, 3a, 3b, 4, and 5. For the sake of brevity, they will not be described here in detail.

[0212] Based on the operating method of the above-mentioned memory system, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any of the above-mentioned embodiments is executed.

[0213] Here, all or part of the processes in the above-mentioned embodiments can be implemented by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD), or a solid-state drive; the storage medium can also include a combination of the above-mentioned types of memory.

[0214] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0215] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0216] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system, comprising a memory device and a memory controller coupled to the memory device; the memory controller is configured to: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered; When the hardware sequence command is not released within a preset time after the firmware is abnormal, a flag for terminating the hardware sequence command is set; In response to the flag for terminating the hardware sequence command, the hardware sequence command is terminated, so that the hardware sequence command is released.

2. The memory system according to claim 1, wherein: The memory controller is configured to: When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

3. The memory system according to claim 1 or 2, wherein: The preset time is greater than 2s.

4. The memory system according to claim 1 or 2, wherein: The memory controller is configured to: After the hardware sequence command is released, a command is sent to save the abnormal scene information into the memory device.

5. The memory system according to claim 4, wherein: The memory controller is configured to: Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller; After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

6. The memory system according to claim 4, wherein: The memory controller is configured to: Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

7. The memory system according to claim 1 or 2, wherein: The memory controller is configured to: After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, a trigger assertion processing mode is determined.

8. The memory system according to claim 1 or 2, wherein: The memory controller is configured to: After the assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation and the location of the corresponding memory device causing the exception first occurs the exception caused by the execution of an error correction code operation, the assertion processing mode is determined.

9. The memory system according to claim 8, wherein: The memory controller is configured to: Acquire abnormal scene information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs; According to the abnormality site information of the position of the corresponding memory device causing the abnormality which is stored in the memory device before the abnormality occurs, it is determined whether the position of the corresponding memory device causing the abnormality occurs for the first time due to the execution of the error correction code operation.

10. The memory system according to claim 7, wherein: The memory controller is configured to: After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

11. A memory system, comprising a memory device and a memory controller coupled to the memory device; the memory controller being configured to: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered; When the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception is not the first time that the exception caused by executing an error correction code operation occurs, it is determined not to trigger the assertion processing mode.

12. The memory system according to claim 11, wherein: The memory controller is configured to: Acquire abnormal scene information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs; Based on the abnormality site information of the location of the corresponding memory device causing the abnormality that is stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

13. The memory system according to claim 11, wherein: The memory controller is configured to: After determining that the assertion handling mode is not triggered, a command is sent to save event log information into the memory device.

14. The memory system according to claim 11, wherein: The memory controller is configured to: When the exception is not an exception caused by executing an error correction code operation, or when the exception is an exception caused by executing an error correction code operation, and the location of the corresponding memory device that caused the exception occurs the first time the exception caused by executing an error correction code operation, it is determined that the assertion processing mode is triggered.

15. The memory system of claim 14, wherein: The memory controller is configured to: After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

16. A method for operating a memory system, the method comprising: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered; When the firmware fails to release the hardware sequence command within the preset time, the setting is aborted. The flag of the hardware sequence command; In response to the flag for terminating the hardware sequence command, the hardware sequence command is terminated, so that the hardware sequence command is released.

17. The operating method according to claim 16, wherein: The method further comprises: When the hardware sequence command is released within the preset time, the flag for terminating the hardware sequence command is not set.

18. The operating method according to claim 16 or 17, wherein: The preset time is greater than 2s.

19. The operating method according to claim 16 or 17, wherein: The method further comprises: After the hardware sequence command is released, a command is sent to save the abnormal scene information into the memory device.

20. The operating method according to claim 19, wherein: The method further comprises: Before sending a command to save the abnormal context information to the memory device, sending a command to store the abnormal context information in a buffer of the memory controller; After the hardware sequence command is released, a command is sent to save the abnormal context information stored in the buffer of the memory controller to the memory device.

21. The operating method according to claim 19, wherein: The method further comprises: Before sending a command to save abnormal scene information in the memory device, a command to reset the memory device is sent.

22. The operating method according to claim 16 or 17, wherein: The method further comprises: After the assertion is triggered, when it is determined that the exception is not an exception caused by executing the error correction code operation, a trigger assertion processing mode is determined.

23. The operating method according to claim 16 or 17, wherein: The method further comprises: After the assertion is triggered, when it is determined that the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception occurs for the first time, the error correction code operation is executed. When an exception is caused, determine the assertion processing mode to be triggered.

24. The operating method according to claim 23, wherein: The method further comprises: Acquire abnormal scene information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs; According to the abnormality site information of the position of the corresponding memory device causing the abnormality which is stored in the memory device before the abnormality occurs, it is determined whether the position of the corresponding memory device causing the abnormality occurs for the first time due to the execution of the error correction code operation.

25. The operating method according to claim 22, wherein: The method further comprises: After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

26. A method for operating a memory system, the method comprising: When an exception occurs in the firmware of the memory system during operation, an assertion is triggered; When the exception is caused by executing an error correction code operation, and the location of the corresponding memory device causing the exception is not the first time that the exception caused by executing an error correction code operation occurs, it is determined not to trigger the assertion processing mode.

27. The operating method according to claim 26, wherein: The method further comprises: Acquire abnormal scene information of a location of a corresponding memory device causing the abnormality to occur, which is stored in the memory device before the abnormality occurs; Based on the abnormality site information of the location of the corresponding memory device causing the abnormality that is stored in the memory device before the abnormality occurs, it is determined whether the location of the corresponding memory device causing the abnormality is not the first time that the abnormality caused by executing the error correction code operation occurs.

28. The operating method according to claim 26, wherein: The method further comprises: After determining that the assertion handling mode is not triggered, a command is sent to save event log information into the memory device.

29. The operating method according to claim 26, wherein: The method further comprises: When the exception is not caused by executing the error correction code operation, or, when the exception is caused by When an exception caused by executing an error correction code operation occurs for the first time at a location of a corresponding memory device causing the exception, it is determined to trigger an assertion processing mode.

30. The operating method according to claim 29, wherein: The method further comprises: After determining that the assertion processing mode is triggered, a command to terminate the running program is sent.

31. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the operating method according to any one of claims 16 to 30.

Images