Display panel

Abstract

A display panel. The display panel comprises a base substrate (110) and a plurality of sub-pixels provided on the base substrate (110); each of at least some of the sub-pixels comprises a pixel driving circuit and a light-emitting device (EM); the pixel driving circuit comprises a first metal pattern (M1), an active pattern (AC), and a second metal pattern (M2) that are provided on the base substrate (110); the light-emitting device (EM) comprises an electrode pattern 1041 electrically connected to the second metal pattern (M2); at least some of the sub-pixels comprise a first color sub-pixel and a second color sub-pixel; the first color sub-pixel and the second color sub-pixel are configured to emit different colors of light; in the first color sub-pixel, the ratio of the overlapping area of the active pattern (AC) and the first metal pattern (M1) to the area of the electrode pattern is X1, in the second color sub-pixel, the ratio of the overlapping area of the active pattern (AC) and the first metal pattern (M1) to the area of the electrode pattern is X2, and 1 / 2≤X1 / X2<1. The display panel has a better display effect.

Description

Display panel

[0001] This application claims priority to Chinese Patent Application No. 202310572985.4 filed on May 19, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a display panel. Background Art

[0003] OLED (Organic Light Emitting Diode) displays offer a range of advantages, including self-luminescence, high contrast, high definition, wide viewing angle, low power consumption, fast response, and low manufacturing costs. They have become a key development direction for next-generation display devices and are therefore attracting increasing attention. Currently, optimizing the structure of display devices is a topic of ongoing research for those skilled in the art.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display panel, which includes a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein each of at least some of the sub-pixels includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes a first metal pattern, an active pattern, and a second metal pattern arranged on the base substrate, the light-emitting device includes an electrode pattern electrically connected to the second metal pattern, and at least some of the sub-pixels include a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel are configured to emit light of different colors, in the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1, and in the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2, and 1 / 2≤X1 / X2<1.

[0006] For example, in the display panel provided in at least one embodiment of the present disclosure, the active pattern is arranged on a side of the first metal pattern close to the base substrate or on a side away from the base substrate, the second metal pattern is arranged on a side of the active pattern away from the base substrate, and the electrode pattern is arranged on a side of the second metal pattern away from the base substrate.

[0007] For example, in a display panel provided by at least one embodiment of the present disclosure, the luminance of the first color sub-pixel is L1, the luminance of the second color sub-pixel is L2,

[0008] Wherein, α is the brightness expectation parameter, and the value range of α is: -2.00<α<9.50; β is the capacitance compensation parameter, and the value range of β is: 0.95<β<1.05.

[0009] For example, in the display panel provided by at least one embodiment of the present disclosure, the active pattern is electrically connected to the second metal pattern through a first via, and the second metal pattern is electrically connected to the electrode pattern through a second via; in the first color sub-pixel, the distance between the center point of the first via and the center point of the second via is y1, and in the second color sub-pixel, the distance between the center point of the first via and the center point of the second via is y2.

[0010] Where a and b are constants.

[0011] For example, in the display panel provided by at least one embodiment of the present disclosure,

[0012] γ is a light intensity control compensation parameter, and the value range of γ is: γ<-0.4 or γ>0.3.

[0013] For example, in the display panel provided by at least one embodiment of the present disclosure,

[0014] For example, the display panel provided by at least one embodiment of the present disclosure also includes: a planarization layer, which is arranged on the side of the second metal pattern away from the base substrate, wherein the second via penetrates the planarization layer, and the second via has a first opening on the surface of the planarization layer away from the base substrate, and a second opening on the surface of the planarization layer close to the base substrate, the orthographic projection of the second opening on the base substrate is located within the orthographic projection of the first opening on the base substrate, and in the first color sub-pixel, the overlapping area of ​​the orthographic projection of the first opening on the base substrate and the orthographic projection of the second metal pattern on the base substrate is Y1, and in the second color sub-pixel, the overlapping area of ​​the orthographic projection of the first opening on the base substrate and the orthographic projection of the second metal pattern on the base substrate is Y2, and Y1>Y2.

[0015] For example, in the display panel provided by at least one embodiment of the present disclosure, the slope angle α1 of the planarization layer at the second via hole has a value range of: 75 degrees ≥ α1 ≥ 40 degrees.

[0016] For example, in the display panel provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the thickness h of the planarization layer has a value range of: h≤5.5 microns.

[0017] For example, the display panel provided by at least one embodiment of the present disclosure also includes: a pixel defining layer, which is arranged on the side of the electrode pattern away from the base substrate, wherein the pixel defining layer includes a plurality of first blocking dams extending along a first direction and a plurality of second blocking dams extending along a second direction, and the plurality of first blocking dams and the plurality of second blocking dams are configured to define sub-pixel openings of the plurality of sub-pixels, and the first direction is different from the second direction; the light-emitting device also includes a light-emitting material layer arranged in the sub-pixel opening, in a direction perpendicular to the base substrate, the thickness of the first blocking dam is greater than the thickness of the second blocking dam, at the position of the second via hole, along the second direction, at the boundary of the second metal pattern, the thickness of the planarization layer is h1, at the boundary of the light-emitting material layer, the thickness of the planarization layer is h2, and at the boundary of the electrode pattern, the thickness of the planarization layer is h3, h1 / h2<h2 / h3.

[0018] For example, in the display panel provided by at least one embodiment of the present disclosure, the diameter of the first opening is L1, the diameter of the second opening is L2, L1>L2+2*f*(h / tanα1),

[0019] Wherein, f is a constant, and 1.5≤f≤3.4.

[0020] For example, in the display panel provided by at least one embodiment of the present disclosure, L1 / L2≥2.5.

[0021] For example, in a display panel provided by at least one embodiment of the present disclosure, h=k*h2,

[0022] k is a constant, and 0.5 <k<1。

[0023] For example, in the display panel provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the second blocking dam includes a first portion overlapping with the second via hole and a second portion not overlapping with the second via hole, and the thickness of the first portion is greater than the thickness of the second portion.

[0024] For example, in the display panel provided by at least one embodiment of the present disclosure, the slope angle of the first portion at the boundary of the second via hole is smaller than the slope angle α1 of the planarization layer at the second via hole.

[0025] For example, in the display panel provided by at least one embodiment of the present disclosure, in the first direction, in at least some sub-pixels, the shortest distance between the center of the second via hole and the edge of the second blocking dam covering the second via hole is different.

[0026] For example, in the display panel provided by at least one embodiment of the present disclosure, in the second direction, in at least some sub-pixels, the distances between the center of the second via hole and two adjacent first barrier dams are different.

[0027] For example, in the display panel provided by at least one embodiment of the present disclosure, the first color sub-pixel is a blue sub-pixel, and the second color sub-pixel is a green sub-pixel or a red sub-pixel.

[0028] For example, in the display panel provided by at least one embodiment of the present disclosure, the at least part of the sub-pixels also include a third color sub-pixel, and the display panel also includes a plurality of reset signal lines, configured to transmit a reset signal to the at least part of the sub-pixels, wherein the reset signal line for transmitting the reset signal to the first color sub-pixel extends for a length D1 in the second direction, the reset signal line for transmitting the reset signal to the second color sub-pixel extends for a length D2 in the second direction, and the reset signal line for transmitting the reset signal to the third color sub-pixel extends for a length D3 in the second direction, D3>D2, D3>D1.

[0029] For example, in the display panel provided by at least one embodiment of the present disclosure, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a red sub-pixel.

[0030] For example, in the display panel provided by at least one embodiment of the present disclosure, at least some of the multiple reset signal lines include portions extending along a first direction and portions extending along a second direction, and the first direction is different from the second direction.

[0031] For example, in the display panel provided in at least one embodiment of the present disclosure, in the second direction, both sides of the electrode pattern have signal lines extending along the first direction, and in at least some of the sub-pixels, the signal lines extending along the first direction on both sides of the electrode pattern transmit different signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1A is a circuit diagram of a 3T1C pixel driving circuit of a display panel;

[0034] FIG1B is a timing diagram of the circuit diagram in FIG1A ;

[0035] FIG2 is a partial cross-sectional schematic diagram of a sub-pixel in a display panel provided by at least one embodiment of the present disclosure;

[0036] FIG3 is a partial cross-sectional schematic diagram of a sub-pixel in another display panel provided by at least one embodiment of the present disclosure;

[0037] 4A to 4G are plan views of various functional layers in a display panel according to at least one embodiment of the present disclosure;

[0038] 5A-5D are plan views schematically illustrating stacking of multiple functional layers in a display panel according to at least one embodiment of the present disclosure;

[0039] FIG6 is a partial cross-sectional schematic diagram of a planarization layer of a display panel near a second via hole according to at least one embodiment of the present disclosure;

[0040] FIG7 is a partial plan view of a pixel definition layer of a display panel according to at least one embodiment of the present disclosure;

[0041] FIG8 is a schematic cross-sectional view of the pixel definition layer along line AA in FIG7 ;

[0042] FIG9 is a schematic cross-sectional view of the pixel definition layer along line BB in FIG7 ; and

[0043] FIG10 is a partial cross-sectional schematic diagram of a planarization layer and a pixel defining layer near a second via hole in a display panel provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0046] In some embodiments, the display area of ​​the OLED display panel can use a 3T1C pixel driving circuit to drive the light-emitting device to emit light. For example, FIG1A shows a circuit diagram of a 3T1C pixel driving circuit, and FIG1B is a timing diagram of the pixel driving circuit in FIG1A.

[0047] For example, as shown in Figures 1A and 1B, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The storage capacitor includes a first capacitor and a second capacitor connected in parallel. The first capacitor is composed of a first capacitor electrode ACT and a second capacitor electrode SHL, and the second capacitor is composed of a first capacitor electrode ACT and a third capacitor electrode SD. The pixel driving circuit is connected to signal lines such as a data line DT, a sensing line SN, a high-level power line VDD, and a low-level power line VSS, as well as components such as an analog-to-digital converter ADC and a digital-to-analog converter DAC connected to the sensing line SN through a switch S1 and a switch S2, respectively, and has a connection relationship as shown in Figure 1A.

[0048] During the operation of the above-mentioned 3T1C pixel driving circuit, in conjunction with Figures 1A and 1B, in the light-emitting stage D, during the t1 period, the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, and the data signal dt is transmitted to the gate of the third transistor T3 through the first transistor T1. The third transistor T3 is turned on, and the sensing IC writes the reset signal Vint to the first electrode (e.g., the anode) of the light-emitting device through the sensing line SN and the second transistor T2.

[0049] During period t2, the first control signal G1 and the second control signal G2 are off signals, the voltage across the storage capacitor remains unchanged, the third transistor T3 operates in a saturated state with a constant current, and drives the light emitting device to emit light.

[0050] At this time, if the pixel row where the light-emitting device is located needs to be compensated, the sensing phase S is entered, that is, the period t3-t6.

[0051] During the t3 period, the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are turned on. The data signal dt is transmitted to the gate of the third transistor T3 through the first transistor T1. The third transistor T3 is turned on. The sensing IC writes the reset signal Vint to the first electrode (for example, the anode) of the light-emitting device through the sensing line SN and the second transistor T2.

[0052] During the t4 period, the first transistor T1 is turned off, the second transistor T2 and the third transistor T3 are turned on, and the parasitic capacitance of the sensing line SN is discharged through point S until the Vgs of the third transistor T3 equals Vth. The third transistor T3 is then turned off. At this time, the sensing IC obtains the potential of S and can calculate the Vth of the third transistor. The characteristic parameters of the third transistor, such as the mobility, can also be calculated based on the discharge curve at point S during the sensing phase.

[0053] During the t5 period, the first transistor T1 is turned on, and the data line DT writes a data voltage to the gate of the third transistor T3. Due to the sensing stage, the pixel row where the light-emitting device is located does not emit light, which will cause a dark line to appear during the display. Therefore, after the t4 stage ends, a data voltage is written immediately to make the pixels in this row emit light, reducing the impact of the dark line on the display effect.

[0054] During the t6 period, the first transistor T1 and the second transistor T2 are turned off, and the light emitting device emits light.

[0055] The above-mentioned t5 and t6 periods are timings added for power-on compensation, and these two stages are not required for power-off compensation.

[0056] The pixel driving circuit can be implemented using a variety of circuit layouts, and different layouts may affect the display effect of the display device.

[0057] At least one embodiment of the present disclosure provides a display panel, which includes a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein each of at least some of the sub-pixels includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes a first metal pattern, an active pattern, and a second metal pattern arranged on the base substrate, the light-emitting device includes an electrode pattern electrically connected to the second metal pattern, at least some of the sub-pixels include a first color sub-pixel and a second color sub-pixel, the first color sub-pixel and the second color sub-pixel are configured to emit light of different colors, in the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1, and in the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2, and 1 / 2≤X1 / X2<1.

[0058] The above-mentioned display panel provided by the embodiment of the present disclosure can balance the speed at which the pixel driving circuit in each sub-pixel transmits signals to the light-emitting device and the size of the signal by designing the ratio of the overlapping area between the active pattern and the first metal pattern in sub-pixels of different colors to the area of ​​the electrode pattern, thereby balancing the light-emitting time of each sub-pixel and improving the display effect of the display panel.

[0059] The display panel provided by the embodiments of the present disclosure is described below through several specific embodiments.

[0060] At least one embodiment of the present disclosure provides a display panel. FIG2 shows a partial cross-sectional schematic diagram of a sub-pixel in the display panel. As shown in FIG2 , the display panel includes a base substrate 110 and a plurality of sub-pixels arranged on the base substrate 110. Each of at least some of the sub-pixels includes a pixel driving circuit and a light-emitting device EM. The pixel driving circuit includes a first metal pattern M1, an active pattern AC, and a second metal pattern M2 arranged on the base substrate 110. The light-emitting device EM includes an electrode pattern 1041 electrically connected to the second metal pattern M2.

[0061] At least some of the sub-pixels include a first color sub-pixel and a second color sub-pixel, and the first color sub-pixel and the second color sub-pixel are configured to emit light of different colors. For example, in the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041 is X1. In the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041 is X2, and 1 / 2≤X1 / X2<1.

[0062] For example, the larger the overlapping area between the active pattern AC and the first metal pattern M1, the greater the amount of charge that can be stored in the storage capacitor formed by the active pattern AC and the first metal pattern M1. Consequently, the better the signal retention function and the longer the light-emitting device EM will emit light. Due to differences in the size of the electrode patterns 1041 of different sub-pixels, differences in the signal transmission paths, and differences in the luminescent properties of the light-emitting material layer of the light-emitting device EM, the luminescent properties of different sub-pixels vary. By designing the ratio of the overlapping area between the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041, the speed and size of signal transmission from the pixel driving circuit to the light-emitting device EM in each sub-pixel can be balanced, thereby balancing the luminescent duration of each sub-pixel and improving the display quality of the display panel.

[0063] For example, in some embodiments, the at least some sub-pixels may include blue sub-pixels, green sub-pixels, and red sub-pixels. For example, the first color sub-pixel may be a blue sub-pixel, and the second color sub-pixel may be a green sub-pixel or a red sub-pixel.

[0064] For example, in some embodiments, the pixel driving circuit includes multiple thin-film transistors. FIG2 shows a cross-sectional schematic diagram of a thin-film transistor T electrically connected to the light-emitting device EM. For example, when the pixel driving circuit is the aforementioned 3T1C pixel driving circuit, the thin-film transistor shown in FIG2 is the third transistor in FIG1A . As shown in FIG2 , the thin-film transistor T includes an active layer 1021, a gate 1022, and source and drain electrodes 1023 and 1024, among other structures.

[0065] For example, in some embodiments, as shown in Figure 2, the active pattern AC is arranged on a side of the first metal pattern M1 away from the base substrate 110. At this time, the first metal pattern M1 can be a light-shielding pattern SHL, and the light-shielding pattern SHL can shield the active pattern ACT. For example, the active pattern AC is arranged on the same layer as the active layer 1021 of the thin film transistor, or the active pattern AC is reused as the active layer 1021.

[0066] Alternatively, in other embodiments, as shown in Figure 3, the active pattern AC is arranged on a side of the first metal pattern M1 close to the base substrate 110. In this case, the first metal pattern M1 can be in the gate metal layer, that is, arranged on the same layer as the gate 1022 of the thin film transistor T, or the first metal pattern M1 is reused as the gate 1022, and the active pattern AC is arranged on the same layer as the active layer 1021 of the thin film transistor T, or the active pattern AC is reused as the active layer 1021.

[0067] For example, as shown in Figures 2 and 3, the second metal pattern M2 is disposed on a side of the active pattern AC away from the base substrate 110. For example, the second metal pattern M2 is disposed on the same layer as the source and drain electrodes 1023 of the thin film transistor T or is reused as the source and drain electrodes 1023 of the thin film transistor T. The electrode pattern 1041 is disposed on a side of the second metal pattern M2 away from the base substrate 110. The electrode pattern 1041 can serve as the anode of the light-emitting device EM.

[0068] It should be noted that in the embodiments of the present disclosure, "same-layer setting" means that two (or more) functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process.

[0069] For example, in a direction perpendicular to the base substrate 110, the active pattern AC and the light-shielding pattern SHL at least partially overlap, so that the active pattern AC and the light-shielding pattern SHL can form a first capacitor of the storage capacitor. For example, the active pattern AC and the second metal pattern M2 at least partially overlap, so that the active pattern AC and the second metal pattern M2 can form a second capacitor of the storage capacitor, and the first capacitor and the second capacitor are connected in parallel.

[0070] For example, in some embodiments, under the same driving conditions, such as the same driving current, the luminance of the first color sub-pixel is L1, the luminance of the second color sub-pixel is L2,

[0071] In the above formula, α is the brightness expectation parameter, and the value range of α is: -2.00<α<9.50. For example, α can be approximately -1.00, 3.00, 4.00, 5.00, 6.00 or 8.00, etc. β is the capacitance compensation parameter, and the value range of β is: 0.95<β<1.05. For example, β can be approximately 1.00, etc.

[0072] For example, in the above embodiment, the first color sub-pixel may be a blue sub-pixel, and the second color sub-pixel may be a green sub-pixel or a red sub-pixel. Since the luminance of the blue sub-pixel is lower than that of the green sub-pixel or the red sub-pixel, the above design can balance the luminance differences between the sub-pixels of different colors, keeping them within an acceptable range and improving the display effect of the display substrate.

[0073] For example, corresponding to the embodiment shown in FIG2 , FIG4A to FIG4G show planar schematic diagrams of various functional layers in the display panel, and FIG5A to FIG5D show planar schematic diagrams of stacked layers of multiple functional layers in the display panel.

[0074] It should be noted that in the embodiments shown in Figures 4A-4G and 5A-5D, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B constitute a pixel unit, and in the row direction, that is, the horizontal direction in the figures, the red sub-pixels R, green sub-pixels G, and blue sub-pixels B are arranged sequentially to form a plurality of pixel units arranged periodically. For example, Figures 4A-4G and 5A-5D each illustrate two pixel units located in the same row as an example, and the display panel adopts the 3T1C pixel driver circuit shown in Figure 1A.

[0075] For example, FIG4A shows a schematic plan view of the first conductive layer where the light shielding pattern SHL of the display panel is located.

[0076] As shown in FIG4A , the first conductive layer includes a reset signal line 131, a power line segment 141, and a light shielding pattern SHL (as a first metal pattern M1) that are insulated from each other. For example, the light shielding pattern SHL can achieve a light shielding effect and can serve as a capacitor electrode of a storage capacitor of a pixel driving circuit.

[0077] For example, in some embodiments, in the same pixel unit, the shading pattern SHL in the red sub-pixel R and the shading pattern SHL in the green sub-pixel G are basically symmetrically arranged, and the distance between the shading pattern SHL in the red sub-pixel R and the shading pattern SHL in the green sub-pixel G is greater than the distance between the shading pattern SHL in the green sub-pixel G and the shading pattern SHL in the blue sub-pixel B.

[0078] For example, in some embodiments, the display panel includes a plurality of reset signal lines 131, and the plurality of reset signal lines 131 are configured to transmit reset signals to at least some of the sub-pixels. For example, the at least some of the sub-pixels include a first color sub-pixel (e.g., a blue sub-pixel B), a second color sub-pixel (e.g., a green sub-pixel G), and a third color sub-pixel (e.g., a red sub-pixel R). As shown in FIG4A , in at least some of the pixel units, the reset signal line transmitting the reset signal to the first color sub-pixel extends along a second direction (horizontal direction in the figure) by a length D1, the reset signal line transmitting the reset signal to the second color sub-pixel extends along a second direction by a length D2, and the reset signal line transmitting the reset signal to the third color sub-pixel extends along a second direction by a length D3, where D3>D2 and D3>D1.

[0079] For example, in the above embodiment, since the lengths of the reset signal lines connected to the reset node S (refer to FIG1A ) are different in the pixel driving circuit, the same signal gives different signal sizes to sub-pixels of different colors. Since the red sub-pixel R has a long life, the reset signal line of the red sub-pixel R is the longest, the reset potential is low, the charging is fast, and the brightness is high.

[0080] For example, in some embodiments, at least some of the multiple reset signal lines include a portion 131A extending along a first direction and a portion 131B extending along a second direction, where the first direction is different from the second direction. For example, the portion 131B extending along the second direction is connected to the detection line SN, while the portion 131A extending along the first direction is used to connect to the circuits of each sub-pixel. For example, the width of the portion 131A extending along the first direction is greater than the width of the portion 131B extending along the second direction, so as to facilitate electrical connection of the portion 131A extending along the first direction to circuits located on other layers, such as through vias, thereby improving the reliability of the electrical connection.

[0081] For example, the power line segment 141 is configured to be electrically connected to the first power line VDD for transmitting a power signal.

[0082] For example, FIG4B shows a plan view of a semiconductor material layer where the active pattern AC of the display panel is located, and FIG5A shows a plan view of a stack of the semiconductor material layer and the first conductive layer.

[0083] As shown in Figures 4B and 5A, the semiconductor material layer includes an active pattern T1a for a first transistor, an active pattern T2a for a second transistor, and an active pattern T3a for a third transistor, which are spaced apart from each other. The semiconductor material layer also includes an active pattern AC, which is integrally connected to the active pattern T2a of the second transistor, or a portion of the active pattern AC serves as the active pattern T2a of the second transistor. The active pattern AC at least partially overlaps with the light-shielding pattern SHL, thereby forming a first capacitor of the storage capacitor.

[0084] For example, FIG4C shows a plan view of the second conductive layer where the gate of the display panel is located, and FIG5B shows a plan view of the stacked layers of the second conductive layer, the semiconductor material layer, and the first conductive layer.

[0085] As shown in Figures 4C and 5B, the second conductive layer includes a first scan line 150 and a second scan line 160 that are insulated from each other, and also includes gates of each transistor that are insulated from each other. For example, the gates of each transistor are the portions where the first scan line 150 and the second scan line 160 overlap with the active layer, such as the gate T1g of the first transistor, the gate T2g of the second transistor, and the gate T3g of the third transistor.

[0086] For example, the portion where the first scan line 150 and the second scan line 160 intersect with the data line, the sensing line SN, and the first power line VDD (described later) is configured as a ring structure RIN, i.e., a dual-channel structure, which can effectively improve the yield of the device. For example, the location where the signal lines intersect is prone to electrostatic breakdown due to parasitic capacitance, resulting in a short circuit. During the detection process, if a short circuit is detected in one channel of the ring structure, the channel can be removed (for example, by laser cutting), and the circuit structure can still operate normally through the other channel.

[0087] For example, FIG4D shows a plan view of the third conductive layer where the source and drain electrodes of the display panel are located, and FIG5C shows a plan view of the stacked third conductive layer, the second conductive layer, the semiconductor material layer, and the first conductive layer.

[0088] As shown in Figures 4D and 5C, the third conductive layer includes data lines DL1, DL2, and DL3 that are insulated from each other, a sensing line SN, and a first power line VDD for providing a high-level power signal, etc., and also includes the source and drain electrodes of each transistor, such as the source and drain electrodes T1d and T1s of the first transistor, the source and drain electrodes T2d and T2s of the second transistor, and the source and drain electrodes T3d and T3s of the third transistor. For example, the third conductive layer also includes a second metal pattern M2, which is connected to the source and drain electrodes T2s of the second transistor and the source and drain electrodes T3s of the third transistor as a whole. In other words, the two opposing portions of the second metal pattern M2 serve as the source and drain electrodes T2s of the second transistor and the source and drain electrodes T3s of the third transistor, respectively. For example, the second metal pattern M2 (as SD in Figure 1A) can form a second capacitor of the storage capacitor with the active pattern AC, and the second capacitor is connected in parallel with the first capacitor.

[0089] For example, as shown in FIG2 , the display panel further includes a gate insulating layer 1014 disposed on a side of the active pattern AC away from the base substrate 110 and an interlayer insulating layer 1015 disposed on a side of the gate electrode 1022 away from the base substrate 110. As shown in FIG2 and FIG5C , the gate insulating layer 1014 and the interlayer insulating layer 1015 have a first via hole V1 therein, and the active pattern AC is electrically connected to the second metal pattern M2 through the first via hole V1.

[0090] For example, FIG4E shows a planar schematic diagram of the planarization layer of the display panel, and FIG5C also shows a planar schematic diagram of the stacked layers of the planarization layer, the third conductive layer, the second conductive layer, the semiconductor material layer, and the first conductive layer.

[0091] As shown in Figures 2, 4E and 5C, the display panel also includes a planarization layer 1016, which is arranged on a side of the second metal pattern M2 (i.e., the above-mentioned third conductive layer) away from the base substrate 110. The planarization layer 1016 includes a second via V2, which passes through the planarization layer 1016. The second metal pattern M2 (the source and drain electrodes 1023 of the thin film transistor) is electrically connected to the electrode pattern 1041 through the second via V2.

[0092] For example, the second via V2 has a first opening O1 on the surface of the planarization layer 1016 away from the base substrate 110 (i.e., the upper surface in FIG. 2 ), and a second opening O2 on the surface of the planarization layer 1016 close to the base substrate 110 (i.e., the lower surface in FIG. 2 ). The orthographic projection of the second opening O2 on the base substrate 110 is located within the orthographic projection of the first opening O1 on the base substrate 110. For example, the size of the second opening O2 is smaller than that of the first opening O1.

[0093] For example, in a first color sub-pixel (e.g., a blue sub-pixel B), an overlapping area between the orthographic projection of the first opening O1 on the substrate 110 and the orthographic projection of the second metal pattern M2 on the substrate 110 is Y1, and in a second color sub-pixel (e.g., a red sub-pixel R or a green sub-pixel G), an overlapping area between the orthographic projection of the first opening O1 on the substrate 110 and the orthographic projection of the second metal pattern M2 on the substrate 110 is Y2, and Y1>Y2.

[0094] For example, at the location of the second via hole V2, as shown in Figure 4D, the second metal pattern M2 of the blue sub-pixel B is larger, for example, with an additional block BX, than the second metal patterns M2 of the green sub-pixel G and the red sub-pixel R. Because blue is less bright than red and green, the thin-film transistor T of the blue sub-pixel B needs to better reduce leakage current. Therefore, the second metal pattern M2 in the thin-film transistor T of the blue sub-pixel B is larger in area, and the second via hole V2 on the second metal pattern M2 has a larger overlap with the second metal pattern M2. This provides a more stable environment, allowing the thin-film transistor T to operate better.

[0095] On the other hand, since the position of the thin film transistor T of the blue sub-pixel B is shifted to the right as a whole on the display panel, there may be problems with the overlap of the second metal pattern M2 and the electrode pattern 1041 at the second via hole V2, and there may also be problems with the flatness below the second via hole V2. Therefore, making the second metal pattern M2 larger is more conducive to the overlap of the second metal pattern M2 and the electrode pattern 1041. In addition, the area below the second via hole V2 will also be flatter, which is conducive to inkjet printing of organic light-emitting materials on the electrode pattern 1041 during the preparation process.

[0096] For example, as shown in FIG5C , in a first color sub-pixel (e.g., a blue sub-pixel B), the distance between the center point of the first via hole V1 and the center point of the second via hole V2 is y1, and in a second color sub-pixel (e.g., a red sub-pixel R or a green sub-pixel G), the distance between the center point of the first via hole V1 and the center point of the second via hole V2 is y2.

[0097] Where a and b are constants. In sub-pixels of different colors, when a signal is transmitted from the active pattern AC through the first via V1 to the second metal pattern M2, and then through the second metal pattern M2 and the second via V2 to the electrode pattern 1041, different signal transmission paths can result in different signal losses. For example, the theoretical maximum luminous duration of each sub-pixel is directly proportional to the ratio of the overlapping area between the active pattern AC and the first metal pattern M1 to the area of ​​the electrode pattern 1041, and inversely proportional to the distance between the center point of the first via V1 and the center point of the second via V2.

[0098] For example, in some embodiments,

[0099] γ is a light intensity control compensation parameter, and the value range of γ is: γ < -0.4 or γ > 0.3, for example, γ is about -0.5 or 0.4. Through the above design, the luminous duration and luminous brightness of each sub-pixel can be further balanced, thereby improving the display effect of the display panel.

[0100] For example, in some embodiments,

[0101] Through the above design, the luminous duration and luminous brightness of each sub-pixel can be adjusted more accurately, thereby achieving a balance between the luminous duration and luminous brightness of each sub-pixel and improving the display effect of the display panel.

[0102] For example, FIG6 shows a partial cross-sectional schematic diagram of the planarization layer 1016 near the second via hole V2. As shown in FIG6, the planarization layer 1016 has a slope angle α1 at the second via hole V2. For example, the slope angle α1 has a value range of 75 degrees ≥ α1 ≥ 40 degrees.

[0103] For example, the slope angle α1 can be 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, or 70 degrees, etc. In the embodiment of the present disclosure, the smaller the slope angle α1 of the planarization layer 1016 at the second via hole V2, the larger the aperture ratio of the sub-pixel. However, if the slope angle α1 of the planarization layer 1016 at the second via hole V2 is too large, the risk of the electrode pattern 1041 breaking at the second via hole V2 is also greater. Therefore, the slope angle α1 of the planarization layer 1016 at the second via hole V2 is designed to be within the above range. Through experiments, the above range can balance the aperture ratio of the sub-pixel and the risk of the electrode pattern 1041 breaking. That is, when the slope angle α1 of the planarization layer 1016 at the second via hole V2 is within the above range, it can simultaneously ensure that the aperture ratio of the sub-pixel and the electrode pattern 1041 will not break at the second via hole V2, thereby ensuring the reliability of the display panel.

[0104] For example, in some embodiments, as shown in FIG. 2 and FIG. 6 , in a direction perpendicular to the base substrate 110 , that is, in the vertical direction in the figures, the thickness h of the planarization layer 1016 may be in the range of: h≤5.5 μm.

[0105] For example, 1.0 micron ≤ h ≤ 5.5 microns, for example, h can be 2.0 microns, 3.0 microns, 4.0 microns or 5.0 microns, etc. The thinner the planarization layer 1016 is, the simpler the etching process for forming a via (such as a second via) in the planarization layer 1016 is, and the thicker the planarization layer 1016 is, the better the flattening effect is. Therefore, when the thickness of the planarization layer 1016 is within the above-mentioned size range, the above-mentioned two effects can be balanced.

[0106] For example, Figure 4F shows a plan schematic diagram of the fourth conductive layer where the electrode pattern of the display panel is located, Figure 4G shows a plan schematic diagram of the pixel defining layer of the display panel, and Figure 5D shows a plan schematic diagram of the pixel defining layer and the fourth conductive pattern, the planarization layer, the third conductive layer and the second conductive layer, the semiconductor material layer, and the first conductive layer stack.

[0107] As shown in FIG. 4F , the electrode pattern 1041 is rectangular in shape as a whole, and is electrically connected to the second metal pattern M2 through a second via V2 at one side of the rectangle (eg, the position of the square frame in the figure).

[0108] For example, in some embodiments, as shown in Figures 4D and 5D, in the second direction, both sides of the electrode pattern 1041 have signal lines extending along the first direction, such as data lines DL1-DL3, a detection line SN, and a first power line VDD. In at least some sub-pixels, such as the red sub-pixel R and the blue sub-pixel B, the signal lines extending along the first direction on both sides of the electrode pattern 1041 transmit different signals. For example, in the red sub-pixel R, the signal lines extending along the first direction on both sides of the electrode pattern 1041 are the data line DL1 and the first power line VDD, respectively. In the blue sub-pixel B, the signal lines extending along the first direction on both sides of the electrode pattern 1041 are the data line DL3 and the detection line SN, respectively.

[0109] 2 and 4G , the display panel further includes a pixel defining layer 1017 , which is disposed on a side of the electrode pattern 1041 away from the base substrate 110 . The pixel defining layer 1017 includes a plurality of sub-pixel openings 1017A for exposing the electrode patterns 1041 of the plurality of sub-pixels.

[0110] For example, as shown in FIG2 , the light-emitting device EM further includes a light-emitting material layer 1042 disposed within a sub-pixel opening 1017A and an electrode layer 1043 disposed at least partially within the sub-pixel opening 1017A. The electrode layer 1043 serves as, for example, a cathode of the light-emitting device EM. The sub-pixel opening 1017A defines a light-emitting region of the sub-pixel. The portion of the light-emitting material layer 1042 located within the sub-pixel opening 1017A contacts the electrode pattern 1041, thereby being sandwiched between the electrode pattern 1041 and the electrode layer 1043. Driven by the electrode pattern 1041 and the electrode layer 1043, the light-emitting device EM can emit light within the region defined by the sub-pixel opening 1017A.

[0111] For example, the sub-pixel opening 1017A may be an elliptical shape or other shape with curved edges. The shapes and sizes of the sub-pixel openings 1017A corresponding to sub-pixels of different colors may be the same or different. In the embodiment shown in FIG4G , the shapes and sizes of the sub-pixel openings 1017A corresponding to sub-pixels of different colors are the same, but in other embodiments, different designs may be used.

[0112] For example, FIG7 shows a simplified schematic diagram of pixel-defining layer 1017. As shown in FIG4G and FIG7 , pixel-defining layer 1017 includes a plurality of first barrier dams 1017B extending along a first direction and a plurality of second barrier dams 1017C extending along a second direction. Specifically, first barrier dams 1017B are positioned between adjacent sub-pixel openings 1017A in the second direction, and second barrier dams 1017C are positioned between adjacent sub-pixel openings 1017A in the first direction. The plurality of first barrier dams 1017B and the plurality of second barrier dams 1017C are configured to define the sub-pixel openings 1017A of a plurality of sub-pixels. The first direction is different from the second direction; for example, the first direction is perpendicular to the second direction.

[0113] For example, in the example of FIG7 , the first direction is the vertical direction in the figure, that is, the column direction of the sub-pixels, and the second direction is the horizontal direction in the figure, that is, the row direction of the sub-pixels. In other embodiments, the first direction may be the horizontal direction and the second direction may be the vertical direction.

[0114] For example, when the luminescent material layer 1042 is formed in the sub-pixel opening 1017A by inkjet printing or the like, the first blocking dam 1017B and the second blocking dam 1017C can block the luminescent material so that the luminescent material is fully printed into the sub-pixel opening 1017A.

[0115] For example, Figure 8 illustrates a schematic cross-sectional view of the pixel-defining layer along line AA in Figure 7 , showing a cross-section of the first barrier dam 1017B, and Figure 9 illustrates a schematic cross-sectional view of the pixel-defining layer along line BB in Figure 7 , showing a cross-section of the second barrier dam 1017C. In some embodiments, as shown in Figures 8 and 9 , in a direction perpendicular to the base substrate 110, a thickness H1 of the first barrier dam 1017B is greater than a thickness H2 of the second barrier dam 1017C.

[0116] For example, in some embodiments, sub-pixels in the same column emit the same color, i.e., the light-emitting devices in the sub-pixels in the same column have the same light-emitting material layer. Therefore, by making the thickness H1 of the first barrier dam 1017B greater than the thickness H2 of the second barrier dam 1017C, when forming the light-emitting material layer 1042 in the sub-pixel opening 1017A using a method such as inkjet printing, the first barrier dam 1017B can effectively prevent crosstalk between light-emitting materials of different colors. The thickness H2 of the second barrier dam 1017C is relatively low, allowing the light-emitting materials of the light-emitting devices in the sub-pixels in the same column to flow through each other, thereby evenly distributing the light-emitting materials in the sub-pixel openings 1017A in the same column. This helps to make the light-emitting material layer 1042 formed in the sub-pixel opening 1017A more uniform after the solvent evaporates, thereby improving the display uniformity of the entire display substrate.

[0117] For example, Figure 10 shows a partial cross-sectional view of the planarization layer and the pixel defining layer near the second via hole. In some embodiments, as shown in Figure 10 , at the location of the second via hole V2, along the second direction (horizontal direction in the figure), at the boundary of the second metal pattern M2, the thickness of the planarization layer 1016 is h1, at the boundary of the light-emitting material layer 1042, the thickness of the planarization layer 1016 is h2, and at the boundary of the electrode pattern 1041, the thickness of the planarization layer 1016 is h3, where h1 / h2<h2 / h3.

[0118] Therefore, the slope of the planarization layer 1016 at the second via hole V2 gradually becomes gentler in the direction away from the second via hole V2, thereby achieving a better planarization effect.

[0119] For example, in some embodiments, as shown in FIG6 , the diameter of the first opening O1 is L1, the diameter of the second opening O2 is L2, L1>L2+2*f*(h / tanα1),

[0120] Wherein, f is a constant, and 1.5≤f≤3.4.

[0121] For example, the larger the slope angle α1 of the planarization layer 1016 at the second via hole V2, the smaller the diameter L1 of the first opening. When f is within the above value range, the size and structure of the second via hole V2 are within the appropriate range, thereby helping to achieve a high aperture ratio and maintain structural stability.

[0122] For example, in some embodiments, L1 / L2≥2.5. When L1 / L2 is too small, the electrode pattern 1041 may break in the second via hole V2. Within the above size range, the structure of the display panel near the second via hole V2 is more stable, thereby improving the reliability of the display panel.

[0123] For example, in some embodiments, h = k*h2, where k is a constant and 0.5 < k < 1. Thus, the relationship between the thickness of the planarization layer 1016 at the boundary of the light-emitting material layer 1042 and the thickness of the planarization layer 1016 is constructed.

[0124] For example, in some embodiments, as shown in FIG. 10, in a direction perpendicular to the substrate 110, the second barrier 1017C includes a first portion 1017D overlapping with the second via V2 and a second portion 1017F not overlapping with the second via 1017C. The thickness h4 of the first portion 1017D is greater than the thickness h5 of the second portion 1017F. For example, the slope angle α2 of the first portion 1017D at the boundary of the second via V2 is less than the slope angle α1 of the planarization layer 1016 at the second via V2. Thus, the second barrier 1017C can at least partially fill the second via V2, or even completely fill the second via V2, to prevent the uneven structure at the second via V2 from affecting the display effect of the display panel.

[0125] For example, in some embodiments, in the first direction, in at least some of the sub-pixels, the shortest distance between the center of the second via V2 and the edge of the second barrier 1017C covering the second via V2 is different. For example, as shown in FIG. 7, the shortest distance between the center of the second via V2 and the lower edge of the second barrier covering the second via V2 is h6, and the shortest distance between the center of the second via V2 and the upper edge of the second barrier covering the second via V2 is h7. h6 is different from h7. For example, h6 is less than h7.

[0126] For example, in some embodiments, in the second direction, in at least some of the sub-pixels, the distances between the center of the second via V2 and two adjacent first barriers 1017B are different. For example, as shown in FIG. 7, the distance between the center of the second via V2 and the left adjacent first barrier 1017B is h8, and the distance between the center of the second via V2 and the right adjacent first barrier 1017B is h9. h8 is different from h9. For example, h8 is greater than h9.

[0127] Thus, the second via V2 is relatively shifted to the right in the area occupied by the sub-pixel. Thereby, the size of the storage capacitor in the pixel driving circuit of the sub-pixel can be reduced, and further the light-emitting time of the sub-pixel can be reduced, so as to improve the lifetime of the sub-pixel, and thus achieve the effect of uniformizing the lifetimes of different color sub-pixels. [[ID=The embodiments of the present disclosure do not limit the materials of each functional layer and the other structures it has. For example, the base substrate 110 can be a rigid substrate such as glass, quartz, or a flexible substrate such as polyimide, the light shielding layer SHL can be a metal material or alloy material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc., and the gate 1022 can be a metal material or alloy material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc., for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium / aluminum / titanium. The source and drain electrodes 1023 and 1024 can be a metal material or alloy material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc., for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium / aluminum / titanium. The semiconductor material layer can be made of silicon-based materials (such as amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (such as IGZO, ZnO, AZO, IZTO, etc.) or organic materials (such as sexithiophene, polythiophene, etc.).

[0129] For example, as shown in Figures 2 and 3, the display panel may further include a barrier layer 1112 and a buffer layer 1013 disposed on the base substrate 110. The barrier layer 1112 and the buffer layer 1013 may prevent impurities in the base substrate 110 from entering the multiple functional layers on the display panel 110, thereby providing protection. For example, the barrier layer 1112 and the buffer layer 1013 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the gate insulating layer 1014 and the interlayer insulating layer 1015 may also be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0130] For example, as shown in Figures 2 and 3, the display panel may further include spacers 108 for defining an encapsulation space and an encapsulation layer EN for encapsulating the light-emitting device EM. The encapsulation layer EN is, for example, a composite encapsulation layer including a first inorganic encapsulation layer 1051, an organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. For example, the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The spacers 108 and the organic encapsulation layer 1052 may be made of an organic insulating material such as polyimide or resin.

[0131] For example, the planarization layer 1016 and the pixel definition layer 1017 may be made of organic insulating materials such as polyimide and resin.

[0132] For example, the display panel may further include other structures in addition to the above structures. For details, please refer to the relevant technology and will not be described in detail here.

[0133] In addition, it should be noted that in the embodiments of the present disclosure, each thin film transistor can be a P-type thin film transistor or an N-type thin film transistor, and the structure can be a bottom gate type, a top gate type or a double gate type. The structure shown in the accompanying drawings is only exemplary, and the embodiments of the present disclosure do not limit the specific form of each thin film transistor.

[0134] At least one embodiment of the present disclosure provides a display device comprising any of the aforementioned display panels. The display device can be implemented as a large-size, narrow-frame display device. For example, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0135] There are a few points to note:

[0136] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0137] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0138] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0139] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein: At least some of the sub-pixels each include a pixel driving circuit and a light emitting device, The pixel driving circuit includes a first metal pattern, an active pattern, and a second metal pattern arranged on the base substrate, and the light emitting device includes an electrode pattern electrically connected to the second metal pattern. The at least part of the sub-pixels include a first color sub-pixel and a second color sub-pixel, wherein the first color sub-pixel and the second color sub-pixel are configured to emit light of different colors, In the first color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X1, In the second color sub-pixel, the ratio of the overlapping area of ​​the active pattern and the first metal pattern to the area of ​​the electrode pattern is X2, 1 / 2≤X1 / X2<1.

2. The display panel according to claim 1, wherein: The active pattern is arranged on a side of the first metal pattern close to the base substrate or on a side away from the base substrate. The second metal pattern is arranged on a side of the active pattern away from the base substrate, The electrode pattern is disposed on a side of the second metal pattern away from the base substrate.

3. The display panel according to claim 1 or 2, wherein: The luminance of the first color sub-pixel is L1, and the luminance of the second color sub-pixel is L2. Among them, α is the brightness expectation parameter, and the value range of α is: -2.00<α<9.50, β is a capacitance compensation parameter, and the value range of β is: 0.95<β<1.

05.

4. The display panel according to any one of claims 1 to 3, wherein: The active pattern is electrically connected to the second metal pattern through a first via hole, and the second metal pattern is electrically connected to the electrode pattern through a second via hole; In the first color sub-pixel, the distance between the center point of the first via hole and the center point of the second via hole is y1. In the second color sub-pixel, the distance between the center point of the first via hole and the center point of the second via hole is y2, Where a and b are constants.

5. The display panel according to claim 3, wherein: γ is a light intensity control compensation parameter, and the value range of γ is: γ<-0.4 or γ>0.

3.

6. The display panel according to claim 5, wherein:

7. The display panel according to claim 4, further comprising: a planarization layer, disposed on a side of the second metal pattern away from the base substrate, wherein the second via hole penetrates the planarization layer, The second via hole has a first opening on a surface of the planarization layer away from the base substrate, and has a second opening on a surface of the planarization layer close to the base substrate, wherein an orthographic projection of the second opening on the base substrate is within an orthographic projection of the first opening on the base substrate. In the first color sub-pixel, an overlapping area of ​​an orthographic projection of the first opening on the base substrate and an orthographic projection of the second metal pattern on the base substrate is Y1. In the second color sub-pixel, an overlapping area of ​​an orthographic projection of the first opening on the base substrate and an orthographic projection of the second metal pattern on the base substrate is Y2. Y1>Y2.

8. The display panel according to claim 7, wherein: The slope angle α1 of the planarization layer at the second via hole has a value range of: 75 degrees ≥ α1 ≥ 40 degrees.

9. The display panel according to claim 7 or 8, wherein: In a direction perpendicular to the substrate, the thickness h of the planarization layer has a value range of: h≤5.5 micrometers.

10. The display panel according to any one of claims 7 to 9, further comprising: a pixel defining layer, disposed on a side of the electrode pattern away from the base substrate, wherein the pixel defining layer comprises a plurality of first blocking dams extending along a first direction and a plurality of second blocking dams extending along a second direction, the plurality of first blocking dams and the plurality of second blocking dams being configured to define sub-pixel openings of the plurality of sub-pixels, the first direction being different from the second direction; The light emitting device further comprises a light emitting material layer disposed in the sub-pixel opening, In a direction perpendicular to the substrate, the thickness of the first barrier dam is greater than the thickness of the second barrier dam. At the position of the second via hole, along the second direction, at the boundary of the second metal pattern, the thickness of the planarization layer is h1, at the boundary of the light-emitting material layer, the thickness of the planarization layer is h2, and at the boundary of the electrode pattern, the thickness of the planarization layer is h3, h1 / h2<h2 / h3.

11. The display panel according to claim 10, wherein: The diameter of the first opening is L1, the diameter of the second opening is L2, L1>L2+2*f*(h / tanα1), Wherein, f is a constant, and 1.5≤f≤3.

4.

12. The display panel according to claim 11, wherein: L1 / L2≥2.

5.

13. The display panel according to claim 12, wherein: h=k*h2, k is a constant, and 0.5 <k<1。 14. The display panel according to any one of claims 10 to 13, wherein: In a direction perpendicular to the base substrate, the second blocking dam includes a first portion overlapping with the second via hole and a second portion not overlapping with the second via hole. The thickness of the first portion is greater than the thickness of the second portion.

15. The display panel according to claim 14, wherein: A slope angle of the first portion at a boundary of the second via hole is smaller than a slope angle α1 of the planarization layer at the second via hole.

16. The display panel according to any one of claims 10 to 15, wherein: In the first direction, in at least some sub-pixels, the shortest distance between the center of the second via hole and the edge of the second blocking dam covering the second via hole is different.

17. The display panel according to any one of claims 10 to 16, wherein: In the second direction, in at least some sub-pixels, the distances between the center of the second via hole and two adjacent first blocking dams are different.

18. The display panel according to any one of claims 1 to 17, wherein: The first color sub-pixel is a blue sub-pixel, and the second color sub-pixel is a green sub-pixel or a red sub-pixel.

19. The display panel according to any one of claims 1 to 18, wherein: The at least some sub-pixels further include a third color sub-pixel, and the display panel further includes a plurality of reset signal lines configured to transmit a reset signal to the at least some sub-pixels. The extending length of the reset signal line for transmitting the reset signal for the first color sub-pixel in the second direction is D1, the extending length of the reset signal line for transmitting the reset signal for the second color sub-pixel in the second direction is D2, and the extending length of the reset signal line for transmitting the reset signal for the third color sub-pixel in the second direction is D3. D3>D2, D3>D1.

20. The display panel according to claim 19, wherein: The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a red sub-pixel.

21. The display panel according to claim 19 or 20, wherein: At least part of the reset signal lines of the plurality of reset signal lines respectively include a portion extending along the first direction and a portion extending along the second direction, The first direction is different from the second direction.

22. The display panel according to claim 21, wherein: In the second direction, both sides of the electrode pattern have signal lines extending along the first direction respectively. In at least some of the sub-pixels, the signal lines extending along the first direction on both sides of the electrode pattern transmit different signals.

Images