Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component that makes it possible to suppress cracks and thereby improve reliability. A multilayer ceramic capacitor 10 comprises: a first main surface-side outer layer section 20a formed from a plurality of ceramic layers 14 positioned between a first main surface 12a and an inner layer section 18 on the first main surface 12a side; and a second main surface-side outer layer section 20b formed from a plurality of ceramic layers 14 positioned between a second main surface 12b and the inner layer section 18 on the second main surface 12b side. The first main surface-side outer layer section 20a and the second main surface-side outer layer section 20b have a first region 40a, a second region 40b, and a third region 40c in this order from the first main surface 12a and the second main surface 12b toward the inner layer section. When the average particle size D50 values of the grains of the ceramic constituting the ceramic layers 14 positioned in each of the first region 40a, the second region 40b, and the third region 40c are denoted as A1, B1, and C1, the relationship therebetween is C1 < A1 < B1.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, the trend toward miniaturization of electronic devices has led to demands for smaller and larger-capacity multilayer ceramic electronic components used in such electronic devices. This has led to demands for thinner ceramic layers and internal electrode layers, necessitating the use of more laminated layers. To achieve thinner ceramic layers and higher capacitance, it is generally considered to use finer ceramic powders or to increase the thickness of the inner layer portions, which are non-capacitance-forming portions, by reducing the thickness of the outer layer portions. However, adopting such a configuration can sometimes result in a decrease in the moisture resistance reliability of the multilayer ceramic electronic component.

[0003] Therefore, Patent Document 1 (JP-A-2005-102663) proposes a technology for improving moisture-resistant reliability in a multilayer ceramic electronic component having an active layer (capacitor-forming portion) and a cover layer (capacitor-non-forming portion) disposed on the active layer by adjusting the average grain size of the ceramic grains constituting the cover layer. Specifically, Patent Document 1 divides the cover layer into three regions: a first layer region farthest from the active layer, a third layer region closest to the active layer, and a second layer region between the first and third layer regions. The average grain size of the ceramic grains in the first layer region is adjusted so that it is greater than the average grain size of the ceramic grains in the second layer region and greater than the average grain size of the ceramic grains in the third layer region. In other words, the average grain size of the ceramic grains is adjusted to decrease from the outermost surface of the cover layer (outer layer portion) toward the active layer (inner layer portion).

[0004] JP 2014-22721 A

[0005] However, the inventors have newly discovered that the configuration of Patent Document 1 has the following problems.

[0006] In the configuration of Patent Document 1, the average particle size of the ceramic grains is large at the outermost surface of the outer layer portion. As a result, the outermost surface of the outer layer portion becomes coarse and is prone to forming irregularities. When irregularities are formed at the outermost surface of the outer layer portion, stress is concentrated at the irregularities when an external impact is applied to the multilayer ceramic electronic component, making cracks more likely to occur.

[0007] For example, if an electronic device incorporating a ceramic electronic component is dropped, the impact may cause stress to be applied to the multilayer ceramic electronic component. Furthermore, if a mounting substrate on which the multilayer ceramic electronic component is mounted undergoes thermal expansion and contraction due to a thermal cycle, bending stress may be generated in the mounting substrate, and this bending stress may be applied to the multilayer ceramic electronic component. Such stress tends to concentrate in the uneven portions formed on the outermost surfaces of the outer layer portions, which can easily cause cracks to form in the multilayer ceramic electronic component, starting from these uneven portions.

[0008] In addition, in the case of the configuration of Patent Document 1, the average grain size of the ceramic grains decreases from the outer layer portion to the inner layer portion, and therefore the number of grain boundaries between the ceramic grains increases toward the inner layer portion. As the number of grain boundaries increases, the number of escape routes for cracks increases.

[0009] If the number of escape routes for cracks increases, for example, stress on the multilayer ceramic electronic component due to dropping of the electronic device or bending stress on the multilayer ceramic electronic component due to thermal cycles, as described above, may extend to the inner layer portion, which is the capacitance forming portion, and cracks may easily occur in the inner layer portion, which may lead to short circuit defects.

[0010] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic electronic component that can suppress cracks and improve reliability.

[0011] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of laminated ceramic layers and a plurality of internal electrode layers arranged on the plurality of ceramic layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode electrically connected to a first internal electrode layer exposed at the first end surface among the plurality of internal electrode layers and arranged on the first end surface; and a second external electrode electrically connected to a second internal electrode layer exposed at the second end surface among the plurality of internal electrode layers and arranged on the second end surface, wherein the laminate includes, in the height direction, an internal electrode layer located closest to the first main surface among the plurality of internal electrode layers to an internal electrode layer located closest to the second main surface among the plurality of internal electrode layers. the ceramic ...

[0012] In the multilayer ceramic electronic component according to the present invention, the first main surface side outer layer portion and the second main surface side outer layer portion can suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portions, and improve high-temperature reliability.

[0013] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress cracks and improve reliability.

[0014] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0015] 1 is an external perspective view showing an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention. 1 is a cross-sectional view taken along line II-II of FIG. 1. 2 is a cross-sectional view taken along line III-III of FIG. 1. 3 is a cross-sectional view taken along line IV-IV of FIG. 2. 4 is a cross-sectional view taken along line V-V of FIG. 2. 5 is an enlarged schematic view taken along line A of FIG. 2. 6 is an enlarged schematic view showing a ceramic grain distribution in A of FIG. 2. 7 is an enlarged schematic view taken along line B of FIG. 3. (a) is a cross-sectional view taken along line II-II of FIG. 1 showing a structure in which counter electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into two, (b) is a cross-sectional view taken along line II-II of FIG. 1 showing a structure in which counter electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into three, and (c) is a cross-sectional view taken along line II-II of FIG. 1 showing a structure in which counter electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into four.

[0016] <Embodiments> 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component according to an embodiment of the present invention.

[0017] Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 2.

[0018] As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0019] (1) Laminate The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. The laminate 12 further has a first main surface 12a and a second main surface 12b facing in a height direction (stacking direction) x, a first side surface 12c and a second side surface 12d facing in a width direction y perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f facing in a length direction z perpendicular to the height direction x and the width direction y. The corners and ridges of the laminate 12 are rounded. Note that a corner refers to a portion where three adjacent surfaces of the laminate intersect, and a ridge refers to a portion where two adjacent surfaces of the laminate intersect. Furthermore, unevenness may be formed on part or all of the first principal surface 12 a, the second principal surface 12 b, the first side surface 12 c, the second side surface 12 d, and the first end surface 12 e, the second end surface 12 f. The ceramic layers 14 and the internal electrode layers 16 are stacked in the height direction x.

[0020] (1-1) Inner Layer Portion The laminate 12 has an inner layer portion 18 composed of one or more ceramic layers 14 and a plurality of internal electrode layers 16 disposed thereon. The internal electrode layers 16 have a first internal electrode layer 16a extended to the first end face 12e and a second internal electrode layer 16b extended to the second end face 12f, and in the inner layer portion 18, the plurality of first internal electrode layers 16a and second internal electrode layers 16b face each other with the ceramic layer 14 interposed therebetween.

[0021] (1-2) Outer Layer Portion The laminate 12 has an outer layer portion surrounding the inner layer portion 18. The outer layer portion has a first main surface side outer layer portion 20a located on the first main surface 12a side, a second main surface side outer layer portion 20b located on the second main surface 12b side, a first side surface side outer layer portion 22a located on the first side surface 12c side, a second side surface side outer layer portion 22b located on the second side surface 12d side, a first end surface side outer layer portion 24a located on the first end surface 12e side, and a second end surface side outer layer portion 24b located on the second end surface 12f side. The outer layer portion will be described later.

[0022] (1-3) Dimensions of the Laminate, Ceramic Material, Thickness of Ceramic Layer, etc. The dimensions of the laminate 12 are not particularly limited, but it is preferable that the dimension in the length direction z is 0.39 mm or more and 3.30 mm or less, the dimension in the height direction x is 0.21 mm or more and 2.70 mm or less, and the dimension in the width direction y is 0.21 mm or more and 2.70 mm or less.

[0023] The ceramic layer 14 can be formed, for example, from a dielectric material. Examples of such dielectric materials include dielectric ceramics having a perovskite structure and a perovskite-type compound containing, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the main component. When the dielectric material is the main component, a secondary component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, may be added in a smaller amount than the main component, depending on the desired characteristics of the laminate 12. Furthermore, at least one of silicon, magnesium, ba, and manganese may be added as an additive to these main components. The additive exists between the ceramic particles.

[0024] When a piezoelectric ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials. Furthermore, when a semiconductor ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as a thermistor. Specific examples of semiconductor ceramic materials include spinel ceramic materials. Furthermore, when a magnetic ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as an inductor. Furthermore, when functioning as an inductor, the internal electrode layers 16 become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0025] The thickness of the ceramic layers 14 after firing is preferably 0.2 μm or more and 0.8 μm or less. The number of laminated ceramic layers 14 is preferably 15 to 1,000. More preferably, it is 0.2 μm or more and 0.55 μm or less. This allows for an increase in the number of laminated layers, contributing to higher capacity. Note that the number of ceramic layers 14 is the total number of ceramic layers 14 in the inner layer portion 18 and the first and second main surface outer layer portions 20 a and 20 b.

[0026] (1-4) Details of Outer Layer Portion The laminate 12 has a first main surface-side outer layer portion 20a located on the first main surface 12a side and formed of a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line (extension) of that outermost surface. Similarly, the laminate 12 has a second main surface-side outer layer portion 20b located on the second main surface 12b side and formed of a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line (extension) of that outermost surface.

[0027] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed from a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side. Similarly, the laminate 12 has a second side surface side outer layer portion 22b located on the second side surface 12d side and formed from a plurality of ceramic layers 14 located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side.

[0028] The laminate 12 has a first end face-side outer layer portion 24a located on the first end face 12e side and formed from a plurality of ceramic layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. Similarly, the laminate 12 has a second end face-side outer layer portion 24b located on the second end face 12f side and formed from a plurality of ceramic layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the second end face 12f side.

[0029] In each of these outer layer portions, the ceramic layer 14 does not have to be an assembly of multiple layers, and may have a single layer structure.

[0030] (1-4-1) First Main Surface Side Outer Layer Portion and Second Main Surface Side Outer Layer Portion FIG. 6 is an enlarged schematic diagram of A in FIG. 2 . FIG. 7 is an enlarged schematic diagram showing the ceramic grain distribution in A in FIG. 2 . The ceramic layers 14 constituting the outer layer portions, such as the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b, are formed of the same dielectric ceramic material as the ceramic layers 14 of the inner layer portion 18. The outer layer portions may be formed of a material different from that of the ceramic layers 14 of the inner layer portion 18. Furthermore, when the ceramic layers 14 of the outer layer portions each have a multi-layer structure, it is preferable that the segregated Si portions of the ceramic layers 14 of the outer layer portions located closest to the first internal electrode layer 16 a and the second internal electrode layer 16 b are larger than the segregated Si portions of the ceramic layers 14 of the other portions of the outer layer portions. This improves the flexural strength of the multilayer ceramic capacitor 10 from the height direction x.

[0031] The thickness t1 of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b after firing is 15 μm or more and 60 μm or less.

[0032] Furthermore, it is preferable that the thickness t1 in the height direction x of either the first main surface side outer layer portion 20a or the second main surface side outer layer portion 20b is 3% or more of the thickness in the height direction x of the laminate 12.

[0033] The first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b will be further described below.

[0034] (a) First principal surface side outer layer portion As shown in Figures 6 and 7, the first principal surface side outer layer portion 20a has, in order from the first principal surface 12a toward the inner layer portion 18, a first region 40a, a second region 40b, and a third region 40c.

[0035] [Relationship between Average Grain Sizes in Each Region] The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the first region 40a is defined as A1. The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the second region 40b is defined as B1. The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the third region 40c is defined as C1. In this case, the relationship is C1<A1<B1. Hereinafter, A1, B1, and C1 may be simply referred to as average grain sizes A1, B1, and C1, or may be simply referred to as A1, B1, and C1.

[0036] According to the above-described configuration, the first main surface side outer layer portion 20a can suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, and improve high-temperature reliability. This will be explained in detail as follows.

[0037] Since the average particle size C1 in the third region 40c is smaller than the average particle size A1 in the first region 40a and the average particle size B1 in the second region 40b, the unevenness of the outer surface of the outer layer portion, i.e., the outer surface of the laminate 12, can be reduced compared to when the average particle size A1 in the first region 40a is larger than the average particle size B1 in the second region 40b. In other words, by adjusting the average particle size A1 in the first region 40a, which is the outermost layer of the outer layer portion, so that it is not the largest among the first to third regions 40a to 40c, the unevenness of the outer surface of the outer layer portion caused by the large average particle size can be reduced. Therefore, uneven areas where stress is likely to concentrate can be reduced, which results in suppressing stress concentration and preventing cracks from occurring.

[0038] Furthermore, because the average grain size A1 in the first region 40a is smaller than the average grain size B1 in the second region 40b, the number of grain boundaries decreases from the first region 40a to the second region 40b, i.e., from the outer surface of the outer layer portion toward the inner layer portion 18. Furthermore, because the average grain size B1 in the second region 40b is the largest among the first to third regions 40a to 40c, the number of grain boundaries in the second region 40b decreases. Therefore, even if a crack occurs on the outer surface of the first region 40a or within the first region 40a, the presence of the second region 40b prevents the crack from further extending toward the third region 40c. Therefore, the crack is prevented from extending to the inner layer portion 18, improving moisture resistance reliability and preventing short-circuit defects.

[0039] Furthermore, the average particle size C1 in the third region 40c closest to the inner layer portion 18 is adjusted to be the smallest among the first to third regions 40a to 40c. This improves the smoothness of the inner surface of the outer layer portion 18-side that is in contact with the internal electrode layer 16. Furthermore, improving the smoothness of the inner surface of the outer layer portion 18-side that is in contact with the internal electrode layer 16 also improves the smoothness of the internal electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. This prevents the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion from having a thin portion. If a thin portion were to form in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, when a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration would likely occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, potentially resulting in degradation due to electrical resistance. As described above, in the present invention, it is possible to prevent the formation of thin portions in the ceramic layer 14 located in the inner layer portion closest to the outer layer portion, thereby suppressing electric field concentration and improving the reliability of the multilayer ceramic capacitor 10.

[0040] Stress may be applied to the multilayer ceramic capacitor 10 in the following cases, for example: When an electronic device on which the multilayer ceramic capacitor 10 is mounted is dropped, the impact may cause stress to be applied to the multilayer ceramic capacitor 10. Furthermore, when a mounting substrate on which the multilayer ceramic capacitor 10 is mounted thermally expands and contracts due to a thermal cycle, a flexural stress may be generated in the mounting substrate, and this flexural stress may be applied to the multilayer ceramic capacitor 10.

[0041] As shown in FIG. 7 , the ceramic grains constituting the ceramic layer 14 in the first region 40a are preferably stacked in multiple units in the height direction x. The ceramic grains constituting the ceramic layer 14 in the second region 40b are preferably stacked in multiple units in the height direction x. The ceramic grains constituting the ceramic layer 14 in the third region 40c are preferably stacked in multiple units in the height direction x. This makes it possible to further suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, and improve high-temperature reliability. That is, since the first region 40a contains multiple, relatively small grains, it is easy to reduce the unevenness on the outer surface of the laminate 12 and to suppress the occurrence of cracks. Furthermore, since the second region 40b contains multiple, relatively large grains, it is possible to secure a relatively large region with few grain boundaries, thereby suppressing the propagation of cracks into the inner layer portion 18. Furthermore, since a plurality of relatively small grains are stacked in the third region 40c, the smoothness of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16 can be improved, thereby improving the high-temperature reliability of the multilayer ceramic capacitor 10.

[0042] The method for measuring the average particle sizes A1, B1, and C1 is described below. The average particle sizes A1, B1, and C1 can be measured using a scanning electron microscope (SEM). Specifically, cross-section polishing is first performed on the multilayer ceramic capacitor 10 from the first side surface 12c or the second side surface 12d to the center of the multilayer ceramic capacitor 10 in the width direction y to expose the LT plane. Next, a field of view is set on the exposed LT plane at a magnification such that the first region 40a, the second region 40b, and the third region 40c of the first main surface-side outer layer portion 20a fit within a single field of view. Then, SEM images of the ceramic grains in the ceramic layer 14 in the first region 40a, the second region 40b, and the third region 40c are captured at an acceleration voltage of 15 kV.

[0043] Next, using image processing software, the edges of all ceramic grains in the first region 40a, second region 40b, and third region 40c are recognized and the cross-sectional area of ​​the grains is calculated. The equivalent circle diameter is calculated from this cross-sectional area to determine the grain diameter. At this time, the diameters of all ceramic grains contained within the imaged area are measured, excluding missing grains. Finally, the D50 values ​​of the first region 40a, second region 40b, and third region 40c measured in the first main surface-side outer layer portion 20a are averaged to calculate the average grain diameters A1, B1, and C1 of the first region 40a, second region 40b, and third region 40c. Note that if the average grain diameters A1, B1, and C1 can be calculated with a certain degree of precision, the diameters of only some of the grains may be measured, rather than all of the ceramic grains contained within the imaged area.

[0044] [Relationship between the thicknesses of each region in the height direction x] The thickness of the first main surface side outer layer portion 20a in the height direction x is defined as t1, and the thicknesses of each of the regions 40a-40c in the height direction x of the first main surface side outer layer portion 20a are defined as ta1, tb1, and tc1. The thickness ta1 in the height direction x of the first region 40a on the first main surface 12a side is preferably 10% to 25% of the thickness t1 in the height direction x of the first main surface side outer layer portion 20a. Furthermore, the thickness tb1 in the height direction x of the second region 40b on the first main surface 12a side is preferably 50% to 80% of the thickness t1 in the height direction x of the first main surface side outer layer portion 20a. Furthermore, it is preferable that the thickness tc1 in the height direction x of the third region 40c on the first main surface 12a side is 10% or more and 25% or less of the thickness t1 in the height direction x of the first main surface side outer layer portion 20a.

[0045] As described above, the thickness ta1 of the first region 40a on the first main surface 12a side in the height direction x is preferably 10% to 25% of the thickness t1 of the outer layer portion 20a on the first main surface side in the height direction x. This makes it possible to suppress cracks from occurring and to prevent the cracks from extending into the inner layer portion 18.

[0046] If the thickness ta1 of the first region 40a on the first principal surface 12a side in the height direction x is less than 10% of the thickness t1 of the first principal surface side outer layer portion 20a in the height direction x, the average particle size B1 of the ceramic grains in the second region 40b is the largest among the first to third regions 40a to 40c, which tends to affect the smoothness of the outer surface of the outer layer portion. As a result, the unevenness increases and the smoothness of the outer surface of the outer layer portion (the outer surface of the first region 40a) decreases, which tends to cause stress to concentrate in the uneven parts and to cause cracks due to external stress. On the other hand, if the thickness ta1 of the first region 40a on the first main surface 12a side in the height direction x exceeds 25% of the thickness t1 of the first main surface-side outer layer portion 20a in the height direction x, a crack that occurs on the outer surface of the first region 40a or within the first region 40a will extend through the first region 40a, which has a certain thickness, and the force of extension will be large, making it difficult to stop the extension of the crack in the second region 40b. In other words, the effect of the second region 40b in suppressing the extension of a crack that occurs on the outer surface of the first region 40a or within the first region 40a will be reduced, and a crack that occurs on the outer surface of the outer layer portion may extend to the first region 40a, the second region 40b, and the third region 40c of the outer layer portion, and even to the inner layer portion 18.

[0047] Furthermore, the thickness tb1 in the height direction x of the second region 40b on the first principal surface 12a side is preferably 50% to 80% of the thickness t1 in the height direction x of the outer layer portion 20a on the first principal surface side, which can prevent cracks from extending to the inner layer portion 18 and can improve the smoothness of the outer surface of the outer layer portion and the inner surface of the outer layer portion on the inner layer portion 18 side.

[0048] If the thickness tb1 of the second region 40b on the first main surface 12a side in the height direction x is less than 50% of the thickness t1 of the first main surface-side outer layer portion 20a in the height direction x, the effect of the second region 40b in suppressing the propagation of cracks that occur on the outer surface of the first region 40a and within the first region 40a will be reduced. As a result, cracks may propagate to the first region 40a, the second region 40b, and the third region 40c of the outer layer portion, and further to the inner layer portion 18. On the other hand, if the thickness tb1 in the height direction x of the second region 40b on the first principal surface 12a side exceeds 80% of the thickness t1 in the height direction x of the first principal surface side outer layer portion 20a, either the thickness ta1 or tc1 in the height direction x of the first region 40a or the third region 40c will fall below the lower limit (25% of the thickness t1 in the height direction x of the first principal surface side outer layer portion 20a). If the thickness ta1 of the first region 40a falls below the lower limit, the average particle size A1 of the ceramic grains in the first region 40a will likely affect the smoothness of the outer surface of the outer layer portion. Therefore, as the smoothness of the outer surface of the outer layer portion decreases and the unevenness increases, stress will easily concentrate in the uneven parts, making it more likely for cracks to occur due to external stress. Furthermore, when the thickness tc1 of the third region 40c is below the lower limit, the average particle size B1 of the ceramic grains in the second region 40b tends to affect the smoothness of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16. Furthermore, the tendency to affect the smoothness of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16 tends to affect the smoothness not only of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16, but also of the inner electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. Therefore, a thin portion is formed in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion. When a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may result in degradation due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced.

[0049] The thickness tc1 of the third region 40c on the first principal surface 12a side in the height direction x is preferably 10% to 25% of the thickness t1 of the outer layer portion 20a on the first principal surface side in the height direction x, which improves the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side and also prevents cracks from extending into the inner layer portion 18.

[0050] When the thickness tc1 in the height direction x of the third region 40c on the first main surface 12a side is less than 10% of the thickness in the height direction x of the first main surface side outer layer portion 20a, the average particle size B1 of the ceramic grains in the second region 40b tends to affect the smoothness of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16. Furthermore, since the smoothness of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16 tends to be affected, the smoothness of not only the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16 but also the inner electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion tends to be affected. Therefore, a thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion is formed. When a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may cause deterioration due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced. On the other hand, if the thickness tc1 of the third region 40c on the first main surface 12a side in the height direction x exceeds 25% of the thickness t1 of the first main surface-side outer layer portion 20a in the height direction x, the thickness tc1 of the third region 40c on the first main surface 12a side will be increased. Because the average grain size C1 of the ceramic grains in the third region 40c is smaller than those in the first region 40a and the second region 40b, the number of grain boundaries of the ceramic grains will increase by the amount of the increase in the thickness of the third region 40c. Therefore, cracks that occur on the outer surface of the outer layer portion and cracks that occur inside the outer layer portion tend to propagate in the third region 40 c and may propagate into the inner layer portion 18 .

[0051] The thickness t1 of the first main surface side outer layer portion 20a and the thicknesses ta1, tb1, and tc1 of each of the regions 40a to 40c are measured by capturing an SEM image in the same manner as when measuring the average particle sizes A1 to C1 of each of the regions 40a to 40c. The thickness t1 of the first main surface side outer layer portion 20a and the thicknesses ta1, tb1, and tc1 of the first region 40a, second region 40b, and third region 40c in the first main surface side outer layer portion 20a are measured from the SEM image.

[0052] [Porosity in Outer Layer Portion] The first main surface side outer layer portion 20a preferably has voids. The porosity in the first main surface side outer layer portion 20a is preferably 0.5% or more and 2.5% or less.

[0053] By setting the porosity of the first main surface side outer layer portion 20a to be 0.5% or more and 2.5% or less, it is possible to prevent water from penetrating from outside the outer layer portion through the voids, and further to prevent water from penetrating into the inner layer portion 18. Furthermore, since stress concentration in the voids can be prevented, the occurrence of cracks can be prevented, and ultimately, the propagation of cracks toward the inner layer portion 18 can be prevented.

[0054] The method for measuring the porosity is described below. Here, porosity refers to the proportion of voids in a target region. In this embodiment, the porosity of the first main surface outer layer portion 20a is measured by the following method. First, cross-section polishing is performed from the first side surface 12c or the second side surface 12d of the multilayer ceramic capacitor 10 to the center in the width direction y of the multilayer ceramic capacitor 10 to expose the LT surface. Next, the exposed LT surface is subjected to surface precision polishing using focused ion beam (FIB) processing. An SEM image of the polished cross section of the first main surface outer layer portion 20a is then captured. Subsequently, voids are identified in any five observation ranges of the SEM image by analyzing the SEM image. Each observation range is 10 μm × 10 μm. For a specific target region in each of the five observation ranges, the porosity is calculated using the following formula (1) based on the area of ​​the target region and the area of ​​the voids within the target region: The average value of the void ratios calculated at the five locations is defined as the void ratio in this embodiment. Porosity (%) = (area of ​​voids in the target region / area of ​​the target region) × 100 (1)

[0055] [Average grain size in each region] In the first main surface side outer layer portion 20a, the average grain sizes A1, B1, and C1 of the ceramic grains in the first region 40a, second region 40b, and third region 40c are preferably set as follows: 200 nm≦A1≦350 nm is preferable. 350 nm<B1≦500 nm is preferable. 100 nm≦C1≦200 nm is preferable.

[0056] By configuring as described above, it is possible to suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, improve high-temperature reliability, and the like.

[0057] If the average grain size A1 of the ceramic grains constituting the ceramic layer 14 located in the first region 40a is smaller than 200 nm, the number of grain boundaries increases too much, making cracks more likely to occur. On the other hand, if the average grain size A1 of the ceramic grains constituting the ceramic layer 14 located in the first region 40a is larger than 350 nm, the unevenness on the outer surface of the first main surface-side outer layer portion 20a becomes too large. Therefore, stress tends to concentrate in these uneven portions, making cracks more likely to occur.

[0058] Furthermore, if the average grain size B1 of the ceramic grains constituting the ceramic layer 14 located in the second region 40b is smaller than 350 nm, the number of grain boundaries increases, increasing the number of escape routes for cracks. Therefore, the effect of the second region 40b in suppressing the propagation of cracks that occur on the outer surface of the first region 40a and within the first region 40a is reduced. On the other hand, if the average grain size B1 of the ceramic grains constituting the ceramic layer 14 located in the second region 40b is larger than 500 nm, the compressive stress inside the outer layer portion acts in a direction that reduces the effect of the second region 40b, which is inside the outer layer portion, in suppressing the propagation of cracks.

[0059] Furthermore, when the average particle size C1 of the ceramic grains constituting the ceramic layer 14 located in the third region 40c is smaller than 100 nm, the number of grain boundaries in the third region 40c increases. This increases the likelihood of internal cracks occurring during the firing process in the third region 40c near the internal electrode layer 16. If an internal crack occurring in the third region 40c extends to the internal layer portion 18, a crack spanning from the outer layer portion to the internal layer portion 18 may occur, resulting in a decrease in the reliability of the multilayer ceramic capacitor 10. On the other hand, when the average particle size C1 of the ceramic grains constituting the ceramic layer 14 located in the third region 40c is larger than 200 nm, the smoothness of the inner surface of the outer layer portion in contact with the internal electrode layer 16 in the third region 40c, on the inner layer portion 18 side, may decrease. Furthermore, a decrease in the smoothness of the inner surface of the outer layer portion in contact with the internal electrode layer 16 on the inner layer portion 18 side may result in a decrease in smoothness not only of the inner surface of the outer layer portion in contact with the internal electrode layer 16 on the inner layer portion 18 side, but also of the internal electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. As a result, a thin portion is formed in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, and when a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may cause deterioration due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced.

[0060] (b) Second Principal Surface Side Outer Layer Portion [Relationship Between Average Grain Sizes in Each Region] The second principal surface side outer layer portion 20b has a configuration similar to that of the first principal surface side outer layer portion 20a. The second principal surface side outer layer portion 20b has, in order from the second principal surface 12b toward the inner layer portion 18, a first region 40a, a second region 40b, and a third region 40c. As with the first principal surface side outer layer portion 20a, the second principal surface side outer layer portion 20b also has the following relationship: average grain size C1 of ceramic grains in the third region 40c < average grain size A1 of ceramic grains in the first region 40a < average grain size B1 of ceramic grains in the second region 40b. As a result, similar to the above-described first main surface side outer layer portion 20a, the above-described second main surface side outer layer portion 20b can achieve suppression of crack occurrence, suppression of crack propagation into the inner layer portion 18, improvement of high temperature reliability, etc. The average particle sizes A1, B1, and C1 of the second main surface side outer layer portion 20b are also measured in the same manner as described above.

[0061] Furthermore, similar to the first main surface side outer layer portion 20a, it is preferable that the ceramic grains constituting the ceramic layer 14 in each of the first region 40a, the second region 40b, and the third region 40c of the second main surface side outer layer portion 20b are stacked in multiple numbers in the height direction x.

[0062] [Relationship Between Thicknesses in the Height Direction of Each Region] If the thickness of the second main surface side outer layer portion 20b in the height direction x is t1 and the thicknesses of the regions 40a-40c in the second main surface side outer layer portion 20b in the height direction x are ta1, tb1, and tc1, respectively, the relationship between the thicknesses ta1, tb1, and tc1 and the thickness t1 is the same as that of the first main surface side outer layer portion 20a. That is, the thickness ta1 in the height direction x of the first region 40a on the second main surface 12b side is preferably 10% to 25% of the thickness t1 in the height direction x of the second main surface side outer layer portion 20b. Furthermore, the thickness tb1 in the height direction x of the second region 40b on the second main surface 12b side is preferably 50% to 80% of the thickness t1 in the height direction of the second main surface side outer layer portion 20b. The thickness tc1 of the third region 40c on the second principal surface 12b side in the height direction x is preferably 10% to 25% of the thickness t1 of the second principal surface side outer layer portion 20b in the height direction x, thereby achieving the same effects as those of the first principal surface side outer layer portion 20a described above.

[0063] The thickness t1 of the second main surface side outer layer portion 20b and the thicknesses ta1, tb1, tc1 of the second main surface side outer layer portion 20b in the respective regions 40a to 40c are also measured in the same manner as described above.

[0064] The thickness t1 in the height direction x of the first main surface side outer layer portion 20a may be different from the thickness t1 in the height direction x of the second main surface side outer layer portion 20b. Furthermore, the thicknesses ta1, tb1, tc1 in the height direction x of the first region 40a, the second region 40b, and the third region 40c on the first main surface 12a side may be different from the thicknesses ta1, tb1, tc1 in the height direction x of the first region 40a, the second region 40b, and the third region 40c on the second main surface 12b side.

[0065] [Porosity in outer layer portion] The second main surface side outer layer portion 20b preferably has voids. The porosity of the second main surface side outer layer portion 20b is preferably 0.5% or more and 2.5% or less. This provides the same effects as the first main surface side outer layer portion 20a described above. The method for calculating the porosity of the second main surface side outer layer portion 20b is the same as described above. The porosities of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b do not need to be the same; the porosity of one of them may be larger or smaller.

[0066] [Average grain size in each region] In the second main surface side outer layer portion 20b, the average grain sizes A1, B1, and C1 of the ceramic grains in the first region 40a, second region 40b, and third region 40c are preferably set as follows: 200 nm≦A1≦350 nm or less is preferable. 350 nm<B1≦500 nm or less is preferable. 100 nm≦C1≦200 nm or less is preferable. This provides the same effects as those of the first main surface side outer layer portion 20a described above.

[0067] (1-4-2) First Side-Side Outer Layer Portion and Second Side-Side Outer Layer Portion FIG. 8 is an enlarged schematic view of B in FIG. 3. The ceramic layers 14 constituting the outer layer portions, such as the first side-side outer layer portion 22a and the second side-side outer layer portion 22b, are formed of the same dielectric ceramic material as the ceramic layers 14 of the inner layer portion 18. The outer layer portions may be formed of a material different from that of the ceramic layers 14 of the inner layer portion 18. Furthermore, when the ceramic layers 14 of the outer layer portions each have a multi-layer structure, it is preferable that the segregated Si portions of the ceramic layers 14 of the outer layer portions located closest to the first internal electrode layer 16a and the second internal electrode layer 16b are larger than the segregated Si portions of the ceramic layers 14 of the other portions of the outer layer portions. This improves the flexural strength of the multilayer ceramic capacitor 10 from the width direction y.

[0068] After firing, the thickness of the first side surface outer layer portion 22a and the second side surface outer layer portion 22b is 15 μm or more and 200 μm or less.

[0069] Furthermore, the thickness t2 of either the first side surface outer layer portion 22a or the second side surface outer layer portion 22b in the width direction y is preferably 3% or more of the thickness of the laminate 12 in the width direction y.

[0070] The first side surface outer layer portion 22a and the second side surface outer layer portion 22b will be further described below.

[0071] (a) First Side Outer Layer Portion As shown in FIG. 8, the first side outer layer portion 22a has, in order from the first side surface 12c toward the inner layer portion 18, a fourth region 50a, a fifth region 50b, and a sixth region 50c.

[0072] [Relationship of Average Grain Size in Each Region] The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the fourth region 50a is defined as A2. The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the fifth region 50b is defined as B2. The average grain size D50 of the ceramic grains constituting the ceramic layer 14 located in the sixth region 50c is defined as C2. In this case, the relationship is C2<A2<B2. Hereinafter, A2, B2, and C2 may be simply referred to as average grain sizes A2, B2, and C2, or may be simply referred to as A2, B2, and C2.

[0073] According to the above-described configuration, the first side surface outer layer portion 22a can suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, and improve high-temperature reliability. This will be explained in detail as follows.

[0074] Since the average particle diameter C2 in the sixth region 50c is smaller than the average particle diameter A2 in the fourth region 50a and the average particle diameter B2 in the fifth region 50b, the unevenness of the outer surface of the outer layer portion, i.e., the outer surface of the laminate 12, can be reduced compared to when the average particle diameter A2 in the fourth region 50a is larger than the average particle diameter B2 in the fifth region 50b in the fourth and fifth regions 50a and 50b. In other words, by adjusting the average particle diameter A2 in the fourth region 50a, which is the outermost layer of the outer layer portion, so that it is not the largest among the fourth to sixth regions 50a to 50c, the unevenness of the outer surface of the outer layer portion caused by the large average particle diameter can be reduced. Therefore, uneven areas where stress is likely to concentrate can be reduced, which results in suppressing stress concentration and preventing cracks.

[0075] Furthermore, because the average grain size A2 in the fourth region 50a is smaller than the average grain size B2 in the fifth region 50b, the number of grain boundaries decreases from the fourth region 50a to the fifth region 50b, i.e., from the outer surface of the outer layer portion toward the inner layer portion 18. Furthermore, because the average grain size B2 in the fifth region 50b is the largest among the fourth to sixth regions 50a to 50c, the number of grain boundaries in the fifth region 50b is the smallest. Therefore, since the number of escape routes for cracks decreases from the fourth region 50a toward the fifth region 50b, even if cracks occur on the outer surface of the fourth region 50a or within the fourth region 50a, the presence of the fifth region 50b can prevent the cracks from further extending toward the sixth region 50c. Therefore, since the cracks can be prevented from extending to the inner layer portion 18, moisture resistance reliability can be improved and short-circuit defects can be suppressed.

[0076] Furthermore, the average particle size C2 in the sixth region 50c closest to the inner layer portion is adjusted to be the smallest among the fourth to sixth regions 50a to 50c. This improves the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side in contact with the internal electrode layer 16. Furthermore, improving the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side in contact with the internal electrode layer 16 also improves the smoothness of the internal electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. This prevents the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion from having a thin thickness, thereby preventing electric field concentration in the thin thickness portion of the ceramic layer 14. As a result, the reliability of the multilayer ceramic capacitor 10 can be improved.

[0077] As with the first main surface-side outer layer portion 20a, the ceramic grains constituting the ceramic layer 14 in the fourth region 50a are preferably stacked in multiple units in the width direction y. The ceramic grains constituting the ceramic layer 14 in the fifth region 50b are preferably stacked in multiple units in the width direction y. The ceramic grains constituting the ceramic layer 14 in the sixth region 50c are preferably stacked in multiple units in the width direction y. This makes it possible to further suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, and improve high-temperature reliability. That is, since the fourth region 50a contains multiple relatively small grains, it is easy to reduce the unevenness on the outer surface of the laminate 12 and to suppress the occurrence of cracks. Furthermore, since the fifth region 50b contains multiple relatively large grains, it is possible to ensure a relatively large region with few grain boundaries, thereby suppressing the propagation of cracks into the inner layer portion 18. Furthermore, since a plurality of relatively small grains are stacked in the sixth region 50c, the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side in contact with the internal electrode layer 16 can be improved. Furthermore, the improvement in the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side in contact with the internal electrode layer 16 also makes it possible to improve the smoothness of the internal electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. This makes it possible to prevent the formation of a thin portion in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, and to prevent the electric field from concentrating in the thin portion of the ceramic layer 14. As a result, the reliability of the multilayer ceramic capacitor 10 can be improved.

[0078] The method for measuring the average grain sizes A2, B2, and C2 is described below. The average grain sizes A2, B2, and C2 can be measured using a scanning electron microscope (SEM). Specifically, cross-section polishing is first performed from the first main surface 12a or the second main surface 12b of the multilayer ceramic capacitor 10 to the center of the multilayer ceramic capacitor 10 in the height direction x to expose the WT surface. Next, a field of view is set on the exposed WT surface at a magnification such that the fourth region 50a, the fifth region 50b, and the sixth region 50c of the first side outer layer portion 22a fit within a single field of view. Then, SEM images of the ceramic grains in the ceramic layer 14 in the fourth region 50a, the fifth region 50b, and the sixth region 50c are captured at an acceleration voltage of 15 kV.

[0079] Next, image processing software was used to identify the edges of all ceramic grains in the fourth region 50a, fifth region 50b, and sixth region 50c, and calculate the cross-sectional area of ​​the grains. The equivalent circle diameter was calculated from this cross-sectional area to determine the grain diameter. At this time, the diameters of all ceramic grains contained within the imaged area were measured, excluding missing grains. Finally, the D50 values ​​measured in the second lateral outer layer portion 22b for the fourth region 50a, fifth region 50b, and sixth region 50c were averaged to calculate the average grain diameters A2, B2, and C2 for the fourth region 50a, fifth region 50b, and sixth region 50c. Note that if the average grain diameters A2, B2, and C2 can be calculated with a certain degree of precision, it is possible to measure the diameters of only some of the grains rather than all of the ceramic grains contained within the imaged area.

[0080] [Relationship of Width-Direction Thickness of Each Region] The thickness in the width direction y of the first side surface side outer layer portion 22a is defined as t2, and the thicknesses in the width direction y of the regions 50a-50c in the first side surface side outer layer portion 22a are defined as ta2, tb2, and tc2. The thickness in the width direction y of the fourth region 50a on the first side surface 12c side is preferably 10% to 25% of the thickness in the width direction y of the first side surface side outer layer portion 22a, t2. Furthermore, the thickness in the width direction y of the fifth region 50b on the first side surface 12c side is preferably 50% to 80% of the thickness in the width direction y of the first side surface side outer layer portion 22a, t2. Furthermore, the thickness in the width direction y of the sixth region 50c on the first side surface 12c side is preferably 10% to 25% of the thickness in the width direction y of the first side surface side outer layer portion 22a, t2.

[0081] As described above, the thickness ta2 in the width direction y of the fourth region 50a on the first side surface 12c side is preferably 10% to 25% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a. This can suppress the occurrence of cracks and also suppress the propagation of cracks into the inner layer portion 18.

[0082] If the thickness ta2 of the fourth region 50a on the first side surface 12c side in the width direction y is less than 10% of the thickness t2 of the first side surface side outer layer portion 22a in the width direction y, the average particle size B2 of the ceramic grains in the fifth region 50b is the largest among the fourth to sixth regions 50a to 50c, which tends to affect the smoothness of the outer surface of the outer layer portion. As a result, the outer surface of the outer layer portion (the outer surface of the fourth region 50a) becomes less smooth due to the increased irregularities, which tends to cause stress to concentrate in the irregularities and to cause cracks due to external stress. On the other hand, if the thickness ta2 in the width direction y of the fourth region 50a on the first side surface 12c side exceeds 25% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a, a crack that occurs on the outer surface of the fourth region 50a or within the fourth region 50a will extend through the fourth region 50a, which has a certain thickness, and the force of extension will be large, making it difficult to stop the extension of this crack in the fifth region 50b. In other words, the effect of the fifth region 50b in suppressing the extension of a crack that occurs on the outer surface of the fourth region 50a or within the fourth region 50a will be reduced, and a crack that occurs on the outer surface of the outer layer portion will extend to the fourth region 50a, the fifth region 50b, and the sixth region 50c of the outer layer portion, and may even extend to the inner layer portion 18.

[0083] Furthermore, the thickness tb2 in the width direction y of the fifth region 50b on the first side surface 12c side is preferably 50% to 80% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a, which can prevent cracks from extending to the inner layer portion 18 and can improve the smoothness of the outer surface of the outer layer portion and the inner surface of the outer layer portion on the inner layer portion 18 side.

[0084] If the thickness tb2 of the fifth region 50b on the first side surface 12c side in the width direction y is less than 50% of the thickness t2 of the first side surface side outer layer portion 22a in the width direction y, the effect of the fifth region 50b in suppressing the propagation of cracks that occur on the outer surface of the fourth region 50a and within the fourth region 50a is reduced. As a result, cracks may propagate to the fourth region 50a, the fifth region 50b, and the sixth region 50c of the outer layer portion, and further to the inner layer portion 18. On the other hand, if the thickness tb2 in the width direction y of the fifth region 50b on the first side surface 12c side exceeds 80% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a, either the thickness ta2 or tc2 in the width direction y of the fourth region 50a or the sixth region 50c will fall below the lower limit (25% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a). If the thickness ta2 of the fourth region 50a falls below the lower limit, the average particle size A2 of the ceramic grains in the fourth region 50a will likely affect the smoothness of the outer surface of the outer layer portion. Therefore, as the smoothness of the outer surface of the outer layer portion decreases and the unevenness increases, stress will easily concentrate in the uneven parts, making it more likely for cracks to occur due to external stress. Furthermore, when the thickness tc2 of the sixth region 50c is below the lower limit, the average particle size B2 of the ceramic grains in the fifth region 50b tends to affect the smoothness of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16. Furthermore, the tendency to affect the smoothness of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16 tends to affect the smoothness not only of the inner surface of the inner layer portion 18 of the outer layer portion in contact with the internal electrode layer 16, but also of the inner electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. Therefore, a thin portion is formed in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion. When a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may cause deterioration due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced.

[0085] The thickness tc2 in the width direction y of the sixth region 50c on the first side surface 12c side is preferably 10% to 25% of the thickness t2 in the width direction y of the first side surface side outer layer portion 22a, which improves the smoothness of the inner surface of the outer layer portion on the inner layer portion 18 side and prevents cracks from extending into the inner layer portion 18.

[0086] In addition, when the thickness tc in the width direction y of the sixth region 50c on the first side surface 12c side is less than 10% of the thickness in the width direction y of the first side surface side outer layer portion 22a, the average particle size B2 of the ceramic grains in the fifth region 50b is likely to affect the smoothness of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16. Furthermore, since the smoothness of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16 is likely to be affected, the smoothness is likely to be affected not only of the inner surface of the inner layer portion 18 side of the outer layer portion in contact with the internal electrode layer 16, but also of the inner electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. Therefore, a thin portion is formed in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, and when a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may cause deterioration due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced. On the other hand, if the thickness tc2 of the sixth region 50c on the first side surface 12c side in the width direction y exceeds 25% of the thickness t2 of the first side surface side outer layer portion 22a in the width direction y, the thickness tc2 of the sixth region 50c on the first side surface 12c side will be increased. Because the average grain size C2 of the ceramic grains in the sixth region 50c is smaller than those in the fourth region 50a and the fifth region 50b, the number of grain boundaries of the ceramic grains increases as the thickness of the sixth region 50c increases. Therefore, cracks that occur on the outer surface of the outer layer portion or inside the outer layer portion may easily propagate in the sixth region 50c, possibly extending into the inner layer portion 18.

[0087] The thickness t2 of the first side surface outer layer portion 22a and the thicknesses ta2, tb2, and tc2 of each of the regions 50a to 50c are measured by capturing an SEM image in the same manner as when measuring the average particle diameters A2 to C2 of each of the regions 50a to 50c. The thickness t2 of the first side surface outer layer portion 22a and the thicknesses ta2, tb2, and tc2 of the fourth region 50a, fifth region 50b, and sixth region 50c in the first side surface outer layer portion 22a are measured from the SEM image.

[0088] [Porosity in Outer Layer Portion] The first side surface outer layer portion 22a preferably has voids. The porosity of the first side surface outer layer portion 22a is preferably 0.5% or more and 2.5% or less.

[0089] By setting the porosity of the first side surface outer layer portion 22a to 0.5% or more and 2.5% or less, it is possible to prevent water from penetrating from outside the outer layer portion through the voids, and further to prevent water from penetrating into the inner layer portion 18. Furthermore, since stress concentration in the voids can be prevented, the occurrence of cracks can be prevented, and ultimately, the propagation of cracks toward the inner layer portion 18 can be prevented.

[0090] The method for measuring the porosity is described below. Cross-section polishing is performed from the first main surface 12a or the second main surface 12b of the multilayer ceramic capacitor 10 to the center in the height direction x of the multilayer ceramic capacitor 10 to expose the WT surface. Next, the exposed WT surface is subjected to surface precision polishing using focused ion beam (FIB) processing. An SEM image of the polished cross section of the first side surface outer layer portion 22a is then captured. The porosity is then calculated in the same manner as the porosity of the first main surface outer layer portion 20a.

[0091] [Average grain size in each region] In the first side outer layer portion 22a, the average grain sizes A2, B2, and C2 of the ceramic grains in the fourth region 50a, the fifth region 50b, and the sixth region 50c are preferably set as follows: 200 nm≦A2≦350 nm is preferable. 350 nm<B2≦500 nm is preferable. 100 nm≦C2≦200 nm is preferable.

[0092] By configuring as described above, it is possible to suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion, improve the high-temperature reliability, and the like.

[0093] If the average grain size A2 of the ceramic grains constituting the ceramic layer 14 located in the fourth region 50a is smaller than 200 nm, the number of grain boundaries increases too much, making cracks more likely to occur. On the other hand, if the average grain size A2 of the ceramic grains constituting the ceramic layer 14 located in the fourth region 50a is larger than 350 nm, the unevenness on the outer surface of the first side surface outer layer portion 22a becomes too large. Therefore, stress tends to concentrate in these uneven portions, making cracks more likely to occur.

[0094] Furthermore, if the average grain size B2 of the ceramic grains constituting the ceramic layer 14 located in the fifth region 50b is smaller than 350 nm, the number of grain boundaries increases, increasing the number of escape routes for cracks. Therefore, the effect of the fifth region 50b in suppressing the propagation of cracks that occur on the outer surface of the fourth region 50a and within the fourth region 50a is reduced. On the other hand, if the average grain size B2 of the ceramic grains constituting the ceramic layer 14 located in the fifth region 50b is larger than 500 nm, the compressive stress inside the outer layer portion acts in a direction that reduces the effect of the fifth region 50b, which is inside the outer layer portion, in suppressing the propagation of cracks.

[0095] Furthermore, when the average particle size C2 of the ceramic grains constituting the ceramic layer 14 located in the sixth region 50c is smaller than 100 nm, the number of grain boundaries in the sixth region 50c increases. This increases the occurrence of internal cracks during the firing process in the sixth region 50c close to the internal electrode layer 16. When an internal crack generated in the sixth region 50c extends to the inner layer portion 18, a crack spanning from the outer layer portion to the inner layer portion 18 occurs, which may reduce the reliability of the multilayer ceramic capacitor 10. On the other hand, when the average particle size C2 of the ceramic grains constituting the ceramic layer 14 located in the sixth region 50c is larger than 200 nm, the smoothness of the inner surface of the outer layer portion in contact with the internal electrode layer 16 in the sixth region 50c on the inner layer portion 18 side may be reduced. Furthermore, a decrease in the smoothness of the inner surface of the outer layer portion in contact with the internal electrode layer 16 on the inner layer portion 18 side may result in a decrease in smoothness not only of the inner surface of the outer layer portion in contact with the internal electrode layer 16 on the inner layer portion 18 side, but also of the internal electrode layer 16 in contact with the outer layer portion and the ceramic layer 14 in contact with the internal electrode layer 16 in contact with the outer layer portion. As a result, a thin portion is formed in the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, and when a voltage is applied to the multilayer ceramic capacitor 10, electric field concentration is likely to occur in the thin portion of the ceramic layer 14 located in the inner layer portion 18 closest to the outer layer portion, which may cause deterioration due to electrical resistance. As a result, the reliability of the multilayer ceramic capacitor 10 may be reduced.

[0096] (b) Second Side-Side Outer Layer Portion [Relationship of Average Grain Sizes in Each Region] The second side-side outer layer portion 22b has a similar configuration to the first side-side outer layer portion 22a. The second side-side outer layer portion 22b includes a fourth region 50a, a fifth region 50b, and a sixth region 50c, arranged in this order from the second side surface 12d toward the inner layer portion 18. Similarly to the first side-side outer layer portion 22a, the second side-side outer layer portion 22b also has the following relationship: average grain size C2 of ceramic grains in the sixth region 50c < average grain size A2 of ceramic grains in the fourth region 50a < average grain size B2 of ceramic grains in the fifth region 50b. As a result, similar to the first side-side outer layer portion 22a, the second side-side outer layer portion 22b can suppress crack occurrence, suppress crack propagation toward the inner layer portion 18, and improve high-temperature reliability. The average particle sizes A2, B2, and C2 of the second side surface outer layer portion 22b are also measured in the same manner as above.

[0097] Furthermore, as described above, it is possible to suppress the occurrence of cracks, suppress the propagation of cracks into the inner layer portion 18, and improve high-temperature reliability not only in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b but also in the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b. Therefore, any of the first main surface side outer layer portion 20a, the second main surface side outer layer portion 20b, the first side surface side outer layer portion 22a, and the second side surface side outer layer portion 22b can be made to face the mounting substrate during mounting, eliminating the need for direction selection.

[0098] Furthermore, in the second side outer layer portion 22b, similar to the first side outer layer portion 22a, it is preferable that the ceramic grains constituting the ceramic layer 14 in each of the fourth region 50a, the fifth region 50b, and the sixth region 50c are stacked in multiple pieces in the width direction y.

[0099] [Relationship Between Width-Direction Thicknesses of Each Region] If the thickness of the second side surface side outer layer portion 22b in the width direction y is t2 and the thicknesses of the regions 50a-50c in the second main surface side outer layer portion 20b in the width direction y are ta2, tb2, and tc2, respectively, the relationship between the thicknesses ta2, tb2, and tc2 and the thickness t2 is the same as that of the first side surface side outer layer portion 22a. That is, the thickness ta2 in the width direction y of the fourth region 50a on the second side surface 12d side is preferably 10% to 25% of the thickness t2 in the width direction y of the second side surface side outer layer portion 22b. The thickness tb2 in the width direction y of the fifth region 50b on the second side surface 12d side is preferably 50% to 80% of the thickness t2 in the width direction y of the second side surface side outer layer portion 22b. The thickness tc2 of the sixth region 50c on the second side surface 12d side in the width direction y is preferably 10% to 25% of the thickness t2 of the second side surface side outer layer portion 22b in the width direction y, thereby achieving the same effects as those of the first side surface side outer layer portion 22a described above.

[0100] The thickness t2 of the second side surface outer layer portion 22b and the thicknesses ta2, tb2, tc2 of the second side surface outer layer portion 22b in the respective regions 50a to 50c are also measured in the same manner as described above.

[0101] The thickness t2 in the width direction y of the first side surface side outer layer portion 22a may be different from the thickness t2 in the width direction y of the second side surface side outer layer portion 22b. Furthermore, the thicknesses ta2, tb2, tc2 in the width direction y of the fourth region 50a, the fifth region 50b, and the sixth region 50c on the first side surface 12c side may be different from the thicknesses ta2, tb2, tc2 in the width direction y of the fourth region 50a, the fifth region 50b, and the sixth region 50c on the second side surface 12d side.

[0102] [Porosity in outer layer portion] The second side surface side outer layer portion 22b preferably has voids. The porosity of the second side surface side outer layer portion 22b is preferably 0.5% or more and 2.5% or less. This provides the same effects as the first side surface side outer layer portion 22a described above. The method for calculating the porosity of the second side surface side outer layer portion 22b is the same as described above. Note that the porosity of the first side surface side outer layer portion 22a and the porosity of the second side surface side outer layer portion 22b do not need to be the same; the porosity of one of them may be larger or smaller.

[0103] [Average grain size in each region] In the second side surface outer layer portion 22b, the average grain sizes A2, B2, and C2 of the ceramic grains in the fourth region 50a, fifth region 50b, and sixth region 50c are preferably set as follows: 200 nm≦A2≦350 nm or less is preferable. 350 nm<B2≦500 nm or less is preferable. 100 nm≦C2≦200 nm or less is preferable. This provides the same effects as those of the first side surface outer layer portion 22a described above.

[0104] (1-5) Internal Electrode Layers The laminate 12 has, for example, a plurality of substantially rectangular first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded so as to be alternately arranged at equal intervals with the ceramic layers 14 sandwiched between them along the height direction x of the laminate 12.

[0105] 4, the first internal electrode layer 16a is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b, and a first lead electrode portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. An end of the first lead electrode portion 28a is led out to the surface of the first end face 12e and exposed from the laminate 12.

[0106] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 26a may be tapered in plan view, with a slope increasing in either direction.

[0107] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 28a may be tapered in plan view, with a slope increasing in either direction.

[0108] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first extraction electrode portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0109] 5 , the second internal electrode layer 16b is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a, and a second extraction electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. An end of the second extraction electrode portion 28b is extracted to the surface of the second end face 12f and exposed from the laminate 12.

[0110] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 26b may be tapered in plan view, with a slope increasing in either direction.

[0111] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second lead electrode portion 28b may be tapered in plan view, with a slope increasing in either direction.

[0112] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second extraction electrode portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0113] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0114] The thickness of each of the internal electrode layers 16, i.e., the first internal electrode layers 16a and the second internal electrode layers 16b, is preferably 0.2 μm or more and 2.0 μm or less. It is more preferably 0.2 μm or more and 0.5 μm or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 15 or more and 1000 or less.

[0115] Sn may also be present at the interface between the ceramic layer 14 and the internal electrode layer 16. When Sn is present, Sn may be present in the form of a layer parallel to the internal electrode layer 16, or may be scattered. Sn may also be present in the ceramic layer 14, or may be present in the form of a solid solution inside the internal electrode layer 16.

[0116] In the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b facing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0117] As shown in FIG. 9, the laminate 12 shown in FIG. 1 may have, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not extended to either the first end face 12e or the second end face 12f. The floating internal electrode layer 16c may divide the opposing electrode portion 26c into multiple portions. For example, the floating internal electrode layer 16c may have a two-part structure as shown in FIG. 9(a), a three-part structure as shown in FIG. 9(b), or a four-part structure as shown in FIG. 9(c). Needless to say, a structure with more than four parts may also be used. By dividing the opposing electrode portion 26c into multiple portions, multiple capacitor components are formed between the opposing internal electrode layers 16a, 16b, and 16c, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, thereby increasing the withstand voltage of the multilayer ceramic capacitor 10.

[0118] (2) External Electrodes As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0119] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0120] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. In this embodiment, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

[0121] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. In this embodiment, the second external electrode 30b extends from the second end face 12f and is disposed on a part of the first main face 12a, a part of the second main face 12b, and a part of the first side face 12c, and a part of the second side face 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

[0122] The external electrode 30 includes a base electrode layer 32 containing a metal component and a plating layer 34 disposed on the base electrode layer 32. The first external electrode 30a includes a first base electrode layer 32a containing a metal component and a first plating layer 34a disposed on the first base electrode layer 32a. The second external electrode 30b includes a second base electrode layer 32b containing a metal component and a second plating layer 34b disposed on the second base electrode layer 32b.

[0123] (2-1) Base electrode layer

[0124] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a portion of the first principal surface 12a, a portion of the second principal surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a. The first base electrode layer 32a is disposed only on the surface of the first end face 12e.

[0125] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b. The second base electrode layer 32b is disposed only on the surface of the second end face 12f.

[0126] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. Hereinafter, each configuration when the base electrode layer 32 is the baked layer, the conductive resin layer, or the thin film layer will be described.

[0127] (When the Base Electrode Layer Includes a Baking Layer) The baking layer includes a glass component and a metal component. The glass component of the baking layer may include an oxide containing at least one element selected from B, Si, Ba, Mg, Al, Li, etc. For example, the glass component included in the base electrode layer 32 is preferably glass containing an oxide such as silicic acid (SiO), alumina (AlO), titanium oxide (TiO), barium oxide (BaO), or zirconia (ZrO). Of these, the glass component included in the base electrode layer 32 more preferably contains an oxide containing Ba or Ti. For example, the glass component included in the base electrode layer 32 is preferably glass containing barium oxide (BaO) or titanium oxide (TiO). When the glass component included in the base electrode layer 32 is barium oxide (BaO) or titanium oxide (TiO), such glass component has few impurities and is soft.

[0128] The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer.

[0129] The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. It may be co-fired with the internal electrode layers 16 and the ceramic layers 14, or it may be baked after the internal electrode layers 16 and the ceramic layers 14 have been baked. When the baking layer is co-fired with the internal electrode layers 16 and the ceramic layers 14, it is preferable to add a ceramic component instead of a glass component to form the baking layer. The ceramic component may be the same type of ceramic material as the ceramic layer 14, or a different type of ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc. By including a glass component or a ceramic component in the baking layer, adhesion between the laminate 12 and the base electrode layer 32, which is the baking layer, can be improved. The baking layer may include both a glass component and a ceramic component.

[0130] The thickness in the length direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x connecting the first main surface 12a and the second main surface 12b of the first baked layer located on the first end face 12e (the thickness of the base electrode layer at the center of the end face) is preferably, for example, approximately 3 μm or more and 100 μm or less.

[0131] The thickness in the length direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x connecting the first main surface 12a and the second main surface 12b of the second baked layer located on the second end face 12f (the thickness of the base electrode layer at the center of the end face) is preferably, for example, approximately 3 μm or more and 100 μm or less.

[0132] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center in the length direction z connecting the first end face 12e and the second end face 12f of the first baked layer located on a part of the first main surface 12a and a part of the second main surface 12b (the thickness of the base electrode layer at the dimension e portion) is preferably, for example, approximately 3 μm or more and 70 μm or less.

[0133] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center in the length direction z connecting the first end face 12e and the second end face 12f of the second baked layer located on a part of the first main surface 12a and a part of the second main surface 12b (the thickness of the base electrode layer at the dimension e portion) is preferably, for example, approximately 3 μm or more and 70 μm or less.

[0134] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first baked layer located on a part of the first side surface 12c and a part of the second side surface 12d (the thickness of the base electrode layer at the e dimension portion) is preferably, for example, approximately 3 μm or more and 70 μm or less.

[0135] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the second baked layer located on a part of the first side surface 12c and a part of the second side surface 12d (the thickness of the base electrode layer at the e dimension portion) is preferably, for example, approximately 3 μm or more and 70 μm or less.

[0136] (When the Base Electrode Layer Includes a Conductive Resin Layer) The conductive resin layer may be multiple layers. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or the conductive resin layer may be disposed directly on the laminate 12. Further explaining the case where the conductive resin layer is disposed on the baked layer, the conductive resin layer may be disposed so as to cover all or part of the baked layer, which is the base electrode layer 32. For example, the conductive resin layer may include a first conductive resin layer and a second conductive resin layer. The first conductive resin layer is disposed so as to cover the first base electrode layer 32a, and the second conductive resin layer is disposed so as to cover the second base electrode layer 32b. Specifically, the first and second conductive resin layers are disposed on the first and second base electrode layers 32a and 32b located on the first end face 12e and the second end face 12f. Furthermore, the first and second conductive resin layers are preferably arranged so as to extend onto the first principal surface 12 a and the second principal surface 12 b, as well as the first side surface 12 c and the second side surface 12 d. However, the first and second conductive resin layers may be arranged only on the first base electrode layer 32 a and the second base electrode layer 32 b located on the first end surface 12 e and the second end surface 12 f. Note that, when the external electrode 30 has a plating layer 34, the conductive resin layer can be arranged so as to be located between the base electrode layer 32 and the plating layer 34.

[0137] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0138] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. Alternatively, a metal powder whose surface is coated with Ag can also be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. The reason for using Ag-coated metal powder is that it allows the base metal to be made inexpensive while maintaining the properties of Ag.

[0139] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0140] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol% or more and 75 vol% or less relative to the volume of the entire conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, approximately 0.3 μm or more and 10 μm or less. The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers forms an electrical path inside the conductive resin layer.

[0141] The shape of the metal contained in the conductive resin layer is not particularly limited, and spherical, flat, etc. It is preferable to use a mixture of spherical metal powder and flat metal powder as the metal contained in the conductive resin layer.

[0142] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, and adhesion. The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0143] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0144] The conductive resin layer may also include a resin layer containing conductive particles and a thermosetting resin. When forming a resin layer, the resin layer may be formed directly on the laminate 12 without forming a baked layer.

[0145] The thickness of the conductive resin layer (thickness at the thickest part) is preferably, for example, about 10 μm or more and 150 μm or less.

[0146] (When the Underlying Electrode Layer Includes a Thin Film Layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0147] (2-2) Plating Layer Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 and 4 to 6. FIG.

[0148] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be disposed so as to cover the first base electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the first plating layer 34a may be disposed only on the first base electrode layer 32a on the first end face 12e side.

[0149] The second plating layer 34b is disposed so as to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be disposed so as to cover the second base electrode layer 32b on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be disposed only on the second base electrode layer 32b on the second end face 12f side.

[0150] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0151] The plating layer 34 may be formed of multiple layers. For example, the first plating layer 34a has a two-layer structure consisting of a first lower-layer plating layer and a first upper-layer plating layer covering the first lower-layer plating layer, and the second plating layer 34b has a two-layer structure consisting of a second lower-layer plating layer and a second upper-layer plating layer covering the second lower-layer plating layer. It is preferable that the first lower-layer plating layer and the second lower-layer plating layer are Ni plating layers, and the first upper-layer plating layer and the second upper-layer plating layer are Sn plating layers.

[0152] The first and second lower plating layers made of Ni are used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The first and second upper plating layers made of Sn are used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting.

[0153] The first and second lower plating layers made of Ni are preferably 1 μm or more and 15 μm or less, and the first and second upper plating layers made of Sn are preferably 1 μm or more and 15 μm or less.

[0154] When a conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is disposed so as to cover the conductive resin layer. Even in this case, the Ni plating layer, which is the lower plating layer of the plating layer 34, prevents the conductive resin layer from being eroded by solder, and the Sn plating layer, which is the upper plating layer, improves the wettability of the solder.

[0155] The first and second external electrodes 30a, 30b may each be provided without a base electrode layer 32, with the plating layer 34 formed directly on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure in which the first end face 12e and the second end face 12f are plated to form the plating layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed by plating after a catalyst is applied to the surface of the laminate 12 as a pretreatment. Either electrolytic plating or electroless plating may be used for the plating. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferred as the plating method.

[0156] In addition, when the plating layer 34 is formed directly on the laminate 12 without providing the base electrode layer 32, the amount of reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner laminate, or into the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design freedom of the thickness of the laminate 12.

[0157] The plating layer 34 includes a lower plating layer formed on the surface of the laminate 12 and an upper plating layer formed on the surface of the lower plating layer. Each of the lower plating layer and the upper plating layer preferably includes at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating layer is preferably formed using Ni, which has solder barrier properties, and the upper plating layer is preferably formed using Sn or Au, which have good solder wettability.

[0158] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower-layer plating layer be formed using Cu, which has good bonding properties with Ni. Furthermore, the upper-layer plating layer may be formed as needed, and the first external electrode 30a and the second external electrode 30b may each be composed of only the lower-layer plating layer. Furthermore, the plating layer 34 may have the upper-layer plating layer as the outermost layer, or another plating electrode may be further formed on the surface of the upper-layer plating layer.

[0159] When the external electrode 30 is formed only with the plating layer 34 without providing the base electrode layer 32, the thickness of each plating layer 34 disposed without providing the base electrode layer 32 is preferably 1 μm or more and 15 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. The metal ratio per unit volume of the plating layer 34 is preferably 99 volume % or more.

[0160] (3) Dimensions of the Multilayer Ceramic Capacitor The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 1.8 mm, W in the width direction y is 0.1 mm to 1.0 mm, and T in the height direction x is 0.1 mm to 1.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0161] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0162] (Step 1) First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known.

[0163] (Step 2) Then, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer is formed, and a dielectric sheet on which the pattern of the second internal electrode layer is formed are prepared.

[0164] Furthermore, with regard to the dielectric sheets, outer layer dielectric sheets on which no internal electrode layer patterns are printed are also prepared.

[0165] The dielectric sheet used for the portions that will become the first main surface side outer layer portion 20a, the second main surface side outer layer portion 20b, the first side surface side outer layer portion 22a, and the second side surface side outer layer portion 22b contains a dielectric sheet with adjusted amounts of Mn, Mg, and Si. By adjusting the amounts of Mn, Mg, and Si, it is possible to control the average grain size D50 values ​​A1, B1, and C1 of the ceramic grains that constitute the ceramic layers in the first region 40a, the second region 40b, and the third region 40c of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b. Similarly, by adjusting the amounts of Mn, Mg, and Si, it is possible to control the average grain size D50 values ​​A2, B2, and C2 of the ceramic grains that constitute the ceramic layers in the fourth region 50a, the fifth region 50b, and the sixth region 50c of the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b.

[0166] Furthermore, in the firing step (step 6) described below, by appropriately controlling the movement of the liquid phase in the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b while causing grain growth, it is possible to achieve a desired particle size distribution for the average particle size D50 values ​​A1, B1, and C1 of the ceramic grains constituting the ceramic layers in the first region 40 a, the second region 40 b, and the third region 40 c. By using a similar method, it is possible to achieve a desired particle size distribution for the average particle size D50 values ​​A2, B2, and C2 of the ceramic grains constituting the ceramic layers in the fourth region 50 a, the fifth region 50 b, and the sixth region 50 c of the first side surface side outer layer portion 22 a and the second side surface side outer layer portion 22 b.

[0167] (Step 3) Subsequently, a predetermined number of dielectric sheets for outer layers, on which no pattern of internal electrode layers is printed, are laminated to form a portion that will become the first main surface side outer layer portion 20a on the first main surface 12a side. Then, a dielectric sheet on which the pattern of the first internal electrode layer is printed and a dielectric sheet on which the pattern of the second internal electrode layer is printed are sequentially laminated on the portion that will become the first main surface side outer layer portion 20a, to form a portion that will become the internal layer portion 18. A predetermined number of dielectric sheets for outer layers, on which no pattern of internal electrode layers is printed, are laminated on the portion that will become the internal layer portion 18, to form a portion that will become the second main surface side outer layer portion 20b on the second main surface 12b side.

[0168] Here, the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b may be formed by stacking a plurality of ceramic layers, each including a portion that will become the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b, or may be formed by a method of being attached to the side surface of the laminate 12. In the case of being attached to the side surface of the laminate 12, a portion of the first main surface side outer layer portion 20a and a portion of the second main surface side outer layer portion 20b that are in contact with the first side surface side outer layer portion 22a, and a portion of the first main surface side outer layer portion 20a and a portion of the second main surface side outer layer portion 20b that are in contact with the second side surface side outer layer portion 22b are also formed by a method of being attached to the side surface of the laminate 12. In this way, a laminate sheet is formed.

[0169] (Step 4) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0170] (Step 5) The laminated block is then cut to a predetermined size to obtain laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0171] (Step 6) Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the ceramic layers, which are dielectrics, and the internal electrode layers, but is preferably 900°C or higher and 1400°C or lower.

[0172] (Step 7) Next, a conductive paste for external electrodes is applied to both end faces 12e, 12f, etc. of the laminate 12 to form the base electrode layer 32. The manufacturing process will be described below for each of the cases where the base electrode layer 32 is a baked layer, a conductive resin layer, and a thin film layer.

[0173] (When the base electrode layer is a baked layer) When the base electrode layer 32 is a baked layer, a conductive paste that will become the base electrode layer 32 is applied to the first end face 12e and the second end face 12f of the laminate 12. The conductive paste containing a glass component and a metal is applied by a method such as dipping or screen printing, and then a baking process is performed to form the base electrode layer 32. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0174] The baking layer may contain a ceramic component instead of a glass component, or may contain both. The ceramic component is preferably, for example, the same type of ceramic material as the laminate. When the baking layer contains a ceramic component, it is preferable to apply a conductive paste to the laminated chip before firing, and then simultaneously bake (fire) the laminated chip before firing and the conductive paste applied to the laminated chip before firing to form a laminate with a baked layer. The baking temperature (firing temperature) at this time is preferably 700 ° C or higher and 1400 ° C or lower.

[0175] (When the base electrode layer is a conductive resin layer) When the base electrode layer 32 is a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baking layer or the laminate 12, and heat treatment is performed at a temperature of 250°C to 550°C to thermally cure the resin, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0176] (When the base electrode layer is a thin film layer) When the base electrode layer 32 is a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as a sputtering method or a vapor deposition method. The base electrode layer 32 formed as a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0177] (When forming a plating layer directly on the laminate without providing a base electrode layer) A plating layer 34 may be provided on the exposed portions of the internal electrode layers 16 of the laminate 12 without providing a base electrode layer 32. In this case, the plating layer 34 can be formed by the following method. A plating process is performed on the first end face 12e and the second end face 12f of the laminate 12 to form a base plating film on the exposed portions of the internal electrode layers 16. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. Furthermore, if necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0178] (Step 8) Next, the plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. In this case, the plating layer 34 is formed on the surface of the base electrode layer 32 after the base electrode layer 32 is formed. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method.

[0179] When forming a conductive resin layer on the base electrode layer 32, a conductive resin paste containing a resin component and a metal component is prepared, and the conductive resin paste is applied onto the base electrode layer 32 by a dipping method. Thereafter, the plating layer 34 is formed on the conductive resin layer.

[0180] In the manner described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

[0181] 3. Experimental Examples Various multilayer ceramic capacitor samples were fabricated as multilayer ceramic electronic components according to the manufacturing method described above. Deflection tests, humidity reliability tests, and high-temperature reliability tests were conducted to evaluate the various multilayer ceramic capacitors. As examples, multilayer ceramic capacitors were prepared in which the average grain size C1 of the ceramic grains constituting the ceramic layer located in the third region was smaller than the average grain size A1 of the ceramic grains constituting the ceramic layer located in the first region and the average grain size B1 of the ceramic grains constituting the ceramic layer located in the second region. Additionally, various multilayer ceramic capacitors were prepared as Comparative Examples 1 to 5, in which the relationships between the average grain sizes A1, B1, and C1 differed from those of the present invention. Except for the relationship between the average grain sizes, the multilayer ceramic capacitors of Comparative Examples 1 to 5 were designed similarly to the examples.

[0182] A. Preparation of Samples (a) Specifications of Samples in Examples Multilayer ceramic capacitors with the following specifications were prepared as examples.

[0183] Dimensions of the multilayer ceramic capacitor (design values): L x W x T = 1.0 mm x 0.5 mm x 0.5 mm. Main material of the ceramic layer: BaTiO3. Capacitance: 22 nF. Rated voltage: 4 V. Material of the internal electrode layer: Ni.

[0184] Specifications of the first main surface side outer layer portion and the second main surface side outer layer portion They were prepared so that the relationship of average grain size C1 of the ceramic grains constituting the ceramic layer located in the third region < average grain size A1 of the ceramic grains constituting the ceramic layer located in the first region < average grain size B1 of the ceramic grains constituting the ceramic layer located in the second region was satisfied. Specifically, A1, B1, and C1 are as follows: A1 = 250 nm B1 = 380 nm C1 = 180 nm Thickness of the first main surface side outer layer portion and the second main surface side outer layer portion: 45 μm

[0185] - Thickness of the first region: 9 μm The first region was formed from the outermost surface of each of the first and second main surface side outer layer portions, extending 20% ​​(within 22.5%) toward the inner layer portion with respect to the thickness of each of the first and second main surface side outer layer portions. - Thickness of the second region: 27 μm The second region was formed to be 60% thicker than the thickness of each of the first and second main surface side outer layer portions. - Thickness of the third region: 9 μm The third region was formed from the interface between the inner layer portion and the first main surface side outer layer portion and the interface between the inner layer portion and the second main surface side outer layer portion, extending 20% ​​(within 22.5%) away from the inner layer portion with respect to the thickness of each of the first and second main surface side outer layer portions. Porosity in the outer layer portion on the first principal surface side: 1% (in the range of 0.5% to 2.5%); Porosity in the outer layer portion on the second principal surface side: 1% (in the range of 0.5% to 2.5%).

[0186] ◎ Specifications of the external electrode layer Specifications of the base electrode layer Base electrode layer: Baked layer containing a metal component and a glass component Metal component: Cu Thickness of the base electrode layer Thickness of the base electrode layer at the center in the height direction of the base electrode layer located on the first end face and the second end face (thickness at the center of the end face): 20 μm Thickness of the base electrode layer at the center in the length direction of the base electrode layer located on the first main face and the second main face, the first side face and the second side face (thickness at the center of dimension e): 0.25 μm

[0187] ◎ Specifications of the plating layer - Formed in a two-layer structure, with a Ni plating layer formed on a base electrode layer and a Sn plating layer formed on the Ni plating layer. - Ni plating layer thickness: Thickness of the Ni plating layer at the height center of the Ni plating layer located on the first end face and the second end face (thickness at the end face center): 4 μm Thickness of the Ni plating layer at the length center of the Ni plating layer located on the first main face and the second main face, the first side face and the second side face (thickness at the e dimension center): 4 μm - Sn plating layer thickness: Thickness of the Sn plating layer at the height center of the Sn plating layer located on the first end face and the second end face (thickness at the end face center): 4 μm Thickness of the Sn plating layer at the length center of the Sn plating layer located on the first main face and the second main face, the first side face and the second side face (thickness at the e dimension center): 4 μm

[0188] (b) Specifications of the sample of Comparative Example 1 For Comparative Example 1, a sample was prepared in which the relationship C1<B1<A1 was satisfied. Specifically, A1, B1, and C1 were as follows. The other configurations were the same as those of the example. A1=380 nm B1=230 nm C1=180 nm

[0189] (c) Specifications of the sample of Comparative Example 2 For Comparative Example 2, a sample was prepared that had the relationship A1<B1<C1. Specifically, A1, B1, and C1 were as follows. The other configurations were the same as those of the example. A1=170 nm B1=250 nm C1=330 nm

[0190] (d) Specifications of the sample of Comparative Example 3 For Comparative Example 3, a sample was prepared in which the relationship B1<A1<C1 was satisfied. Specifically, A1, B1, and C1 were as follows. The other configurations were the same as those of the example. A1=260 nm B1=180 nm C1=330 nm

[0191] (e) Specifications of the sample of Comparative Example 4 For Comparative Example 4, a sample was prepared in which the relationship A1<C1<B1 was satisfied. Specifically, A1, B1, and C1 were as follows. The other configurations were the same as those of the example. A1=180 nm B1=380 nm C1=240 nm

[0192] (f) Specifications of the sample of Comparative Example 5 For Comparative Example 5, a sample was prepared in which the relationship B1<C1<A1 was satisfied. Specifically, A1, B1, and C1 were as follows. The other configurations were the same as those of the example. A1=380 nm B1=180 nm C1=250 nm

[0193] B. Sample Evaluation (a) Evaluation Based on the Presence or Absence of Cracks in a Deflection Test The presence or absence of cracks in a deflection test was confirmed as follows. First, the prepared multilayer ceramic capacitor was mounted on a 1.6 mm thick mounting substrate using solder paste. Then, mechanical stress was applied by bending the substrate from the backside of the substrate, on which the multilayer ceramic capacitor was not mounted, using a push rod with a curvature radius of 5 mm. The bending amount was 4 mm and the substrate was deflected for 20 seconds. After the substrate was bent and deflected, the multilayer ceramic capacitor was removed from the mounting substrate, and the cross section was polished to observe the presence or absence of cracks. Cracks were observed by starting polishing from the first or second side of the multilayer ceramic capacitor and observing the LT cross section immediately after exposing the internal electrode layers, and by starting polishing from the first or second side of the multilayer ceramic capacitor and polishing to a position 1 / 2 of the way in the width direction y connecting the first and second side. The number of cracks confirmed to have occurred in the deflection test was counted. For each of the Examples and Comparative Examples 1 to 5, 50 samples were prepared and tested.

[0194] (b) Evaluation by Moisture Resistance Reliability Test The moisture resistance reliability test was conducted for each sample using the following method. First, each sample was mounted on a wiring board using eutectic solder. Next, the insulation resistance value of each sample was measured. Next, the wiring board was placed in a high-temperature, high-humidity chamber, and a direct current of 4 V was applied between a pair of external electrodes of each sample under an environment of 40°C and 90% RH for 500 hours. Next, the insulation resistance value of each sample after the moisture resistance reliability test was measured. Then, for each sample, an insulation resistance value of 0.1 MΩ or more after the moisture resistance reliability test was judged as "pass," and an insulation resistance value of less than 0.1 MΩ was judged as "fail." The moisture resistance reliability test was conducted using 50 samples prepared for each example and comparative examples 1 to 5. The number of samples that failed was counted as the number of reductions in insulation resistance (IR) during the moisture resistance reliability test.

[0195] (c) Evaluation by High-Temperature Reliability Test The high-temperature reliability was evaluated for each sample using the following method. First, each sample was mounted on a wiring board using eutectic solder. The insulation resistance value of each sample was then measured. The wiring board was then placed in a high-temperature chamber, and a direct current of 4 V was applied between a pair of external electrodes of each sample in an 85°C environment for 1000 hours. The insulation resistance value of each sample after the high-temperature reliability test was then measured. For each sample, an insulation resistance value of 0.1 MΩ or greater after the high-temperature reliability test was evaluated as "pass," and an insulation resistance value of less than 0.1 MΩ was evaluated as "fail." The high-temperature reliability test was conducted on 50 samples prepared for each of the example and comparative examples 1 to 5. The number of samples that failed was counted as the number of reductions in insulation resistance (IR) during the high-temperature reliability test.

[0196] Table 1 shows the results of the deflection test, humidity resistance reliability test, and high temperature reliability test for the example and comparative examples 1 to 5.

[0197]

[0198] C. Experimental Results There are six magnitude relationships between A1, B1, and C1, and in Comparative Examples 1 to 5, experiments were conducted with magnitude relationships between A1, B1, and C1 other than C1<A1<B1 in the Examples. Referring to Table 1, in the Examples, the number of cracks generated in the deflection test, the number of IR decreases in the humidity reliability test, and the number of IR decreases in the high-temperature reliability test were all 0 / 50. On the other hand, in Comparative Examples 1 to 5, at least one of the number of cracks generated in the deflection test, the number of IR decreases in the humidity reliability test, and the number of IR decreases in the high-temperature reliability test exceeded 0 / 50. From the above, it was found that by controlling the relationship C1<A1<B1 in the Examples, it is possible to suppress crack generation, improve humidity resistance reliability, improve high-temperature reliability, etc.

[0199] Further investigation is as follows. In the examples, the average grain size C1 is the smallest among A1, B1, and C1, and A1 < B1 in the first and second regions. In the examples, there were no samples in which cracks occurred in the deflection test, and there were no samples in which the moisture resistance reliability was reduced in the moisture resistance reliability test. On the other hand, in comparative example 1, like the examples, the average grain size C1 is the smallest among A1, B1, and C1, but unlike the examples, A1 > B1 in the first and second regions. In comparative example 1, there were samples in which cracks occurred in the deflection test, and there were samples in which the moisture resistance reliability was reduced in the moisture resistance reliability test.

[0200] These experimental results suggest that when A1<B1 in the first and second regions, as in the examples, the unevenness of the outer surface of the outer layer portion, i.e., the outer surface of the laminate, can be reduced compared to when A1>B1 in the first and second regions. In other words, by adjusting the average grain size A1 in the first region, which is the outermost layer of the outer layer portion, so that it is not the largest among the first to third regions, the unevenness of the outer surface of the outer layer portion caused by a large average grain size can be reduced. This reduces the number of uneven areas where stress is likely to concentrate, thereby suppressing stress concentration and crack occurrence. Furthermore, because A1<B1, the number of grain boundaries decreases from the first region to the second region, i.e., from the outer surface of the outer layer portion to the inner layer portion. Furthermore, because the average grain size B1 in the second region is the largest among the first to third regions, the number of grain boundaries is the smallest in the second region. Therefore, the number of escape routes for cracks decreases as they move from the first region to the second region, so even if a crack occurs on the outer surface of the first region or within the first region, the presence of the second region can prevent the crack from further extending toward the third region. Therefore, since the crack can be prevented from extending into the inner layer portion, the moisture resistance reliability can be improved and short-circuit defects can be suppressed. Therefore, since A1 < B1 in the first region and the second region, it was found that it is possible to suppress crack occurrence and improve moisture resistance reliability.

[0201] Furthermore, in the Examples, the average grain size C1 is smallest in the third region among the first to third regions. Also, in Comparative Example 1, the average grain size C1 is smallest in the third region among the first to third regions. On the other hand, in Comparative Examples 2 to 5, the average grain size C1 is not smallest in the third region among the first to third regions. That is, in Comparative Examples 2 and 3, the average grain size C1 is largest in the third region among the first to third regions. In Comparative Examples 4 and 5, the average grain size C1 in the third region among the first to third regions is the middle. In the Examples, no samples exhibited reduced high-temperature reliability in the high-temperature reliability test. Similarly, in Comparative Example 1, no samples exhibited reduced high-temperature reliability in the high-temperature reliability test. On the other hand, in Comparative Examples 2 to 5, there were samples exhibiting reduced high-temperature reliability in the high-temperature reliability test.

[0202] These experimental results suggest that adjusting the average grain size C1 in the third region closest to the inner layer portion to be the smallest among the first to third regions, as in the example, can improve the smoothness of the inner surface of the outer layer portion on the inner layer portion side in contact with the internal electrode layer. Therefore, thickness variation can be suppressed throughout the entire outer layer portion, including the first to third regions. This means that the formation of thin portions in the outer layer portion is suppressed. Therefore, the high-temperature reliability of the multilayer ceramic electronic component can be improved. This is also evident from the fact that no samples exhibited reduced high-temperature reliability, even in Comparative Example 1, in which the average grain size C1 in the third region closest to the inner layer portion was adjusted to be the smallest among the first to third regions.

[0203] As described above, adjusting the average particle size A1 in the first region can reduce the unevenness of the outer surface of the outer layer portion, thereby suppressing thickness variations throughout the outer layer portion. Furthermore, because thin portions of the outer layer portion are less likely to be formed, it is expected that chipping and cracking, which tend to occur in such portions, can also be suppressed. This can prevent water and other contaminants from penetrating from the outside of the outer layer portion, potentially improving the moisture resistance reliability of the multilayer ceramic capacitor.

[0204] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0205] <Modification 1> In the above embodiment, the average grain size of the ceramic grains in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b is defined, and the average grain size of the ceramic grains in the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b is also defined. However, the average grain size of the ceramic grains in the first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b does not have to have the relationship as in the above embodiment. However, it is preferable to define the average grain size of the ceramic grains in the first main surface side outer layer portion 20a, the second main surface side outer layer portion 20b, the first side surface side outer layer portion 22a, and the second side surface side outer layer portion 22b that are not covered by the external electrode 30, as in the above embodiment, because this can suppress the occurrence of cracks, etc.

[0206] In the above embodiment, the relationship between the average grain sizes of the grains in each region is defined in all of the first main surface side outer layer portion 20 a, the second main surface side outer layer portion 20 b, the first side surface side outer layer portion 22 a, and the second side surface side outer layer portion 22 b. However, the relationship between the average grain sizes of the grains in each region in at least one of the first main surface side outer layer portion 20 a, the second main surface side outer layer portion 20 b, the first side surface side outer layer portion 22 a, and the second side surface side outer layer portion 22 b may be defined as in the above embodiment.

[0207] <Modification 2> In the above embodiment, a two-terminal multilayer ceramic capacitor having two terminals, a first external electrode 30a and a second external electrode 30b, has been described as a multilayer ceramic electronic component. However, the present invention may also be applied to a three-terminal multilayer ceramic capacitor. The three-terminal multilayer ceramic capacitor includes the same laminate 12 and first to fourth external electrodes as in the above embodiment. The internal electrode layers 16 include a first internal electrode layer extending to the first end face 12e and the second end face 12f, and a second internal electrode layer extending to the first side face 12c and the second side face 12d. A first external electrode is disposed on the first end face 12e of the laminate 12. The first external electrode is electrically connected to the first internal electrode layer exposed at the first end face 12e of the laminate 12. A second external electrode is disposed on the second end face 12f of the laminate 12. The second external electrode is electrically connected to the first internal electrode layer exposed at the second end face 12f of the laminate 12. A third external electrode is disposed on the first side face 12c of the laminate 12. The third external electrode is electrically connected to the second internal electrode layer exposed at the first side face 12c of the laminate 12. A fourth external electrode is disposed on the second side face 12d of the laminate 12. The fourth external electrode is electrically connected to the second internal electrode layer exposed at the second side face 12d of the laminate 12.

[0208] <1> A multilayer ceramic electronic component including a laminate including a plurality of stacked ceramic layers and a plurality of internal electrode layers arranged on the plurality of ceramic layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end faces opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode electrically connected to a first internal electrode layer of the plurality of internal electrode layers exposed at the first end face and arranged on the first end face; and a second external electrode electrically connected to a second internal electrode layer of the plurality of internal electrode layers exposed at the second end face and arranged on the second end face, wherein the laminate comprises: the ceramic ... a multilayer ceramic electronic component, wherein when an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the first region is A1, an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the second region is B1, and an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the third region is C1, the relationship C1<A1<B1 holds.

[0209] <2> The thickness in the height direction of the first region on the first main surface side is 10% to 25% of the thickness in the height direction of the first main surface side outer layer portion, The thickness in the height direction of the second region on the first main surface side is 50% to 80% of the thickness in the height direction of the first main surface side outer layer portion, The thickness in the height direction of the third region on the first main surface side is 10% to 25% of the thickness in the height direction of the first main surface side outer layer portion, The thickness in the height direction of the first region on the second main surface side is 10% to 25% of the thickness in the height direction of the second main surface side outer layer portion, The thickness in the height direction of the second region on the second main surface side is 50% to 80% of the thickness in the height direction of the second main surface side outer layer portion, <1> The multilayer ceramic electronic component according to <1>, wherein the thickness in the height direction of the third region on the second main surface side is 10% to 25% of the thickness in the height direction of the outer layer portion on the second main surface side.

[0210] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the first main surface side outer layer portion and the second main surface side outer layer portion have voids, and the porosity of the first main surface side outer layer portion and the porosity of the second main surface side outer layer portion are each 0.5% or more and 2.5% or less.

[0211] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein A1, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the first region, is 200 nm≦A1≦350 nm or less; B1, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the second region, is 350 nm<B1≦500 nm or less; and C1, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the third region, is 100 nm≦C1≦200 nm or less.

[0212] <5> The laminate has: a first side surface side outer layer portion located on the first side surface side and formed from the plurality of ceramic layers located between the first side surface and an outermost surface of the inner layer portion on the first side surface side; and a second side surface side outer layer portion located on the second side surface side and formed from the plurality of ceramic layers located between the second side surface and an outermost surface of the inner layer portion on the second side surface side, wherein the first side surface side outer layer portion and the second side surface side outer layer portion have a fourth region, a fifth region, and a sixth region in this order from the first side surface and the second side surface toward the inner layer portion, and wherein when an average grain size D50 value of ceramic grains constituting the ceramic layer located in the fourth region is A2, an average grain size D50 value of ceramic grains constituting the ceramic layer located in the fifth region is B2, and an average grain size D50 value of ceramic grains constituting the ceramic layer located in the sixth region is C2, a relationship of C2<A2<B2 is satisfied.

[0213] <6> The widthwise thickness of the fourth region on the first side surface side is 10% to 25% of the widthwise thickness of the first side surface side outer layer portion, The widthwise thickness of the fifth region on the first side surface side is 50% to 80% of the widthwise thickness of the first side surface side outer layer portion, The widthwise thickness of the sixth region on the first side surface side is 10% to 25% of the widthwise thickness of the first side surface side outer layer portion, The widthwise thickness of the fourth region on the second side surface side is 10% to 25% of the widthwise thickness of the second side surface side outer layer portion, The widthwise thickness of the fifth region on the second side surface side is 50% to 80% of the widthwise thickness of the second side surface side outer layer portion, <5> The multilayer ceramic electronic component according to <5>, wherein the thickness in the width direction of the sixth region on the second side surface side is 10% to 25% of the thickness in the width direction of the outer layer portion on the second side surface side.

[0214] <7> The multilayer ceramic electronic component according to <5> or <6>, wherein the first side surface side outer layer portion and the second side surface side outer layer portion have voids, and the porosity of the first side surface side outer layer portion and the porosity of the second side surface side outer layer portion are 0.5% or more and 2.5% or less.

[0215] <8> The multilayer ceramic electronic component according to any one of <5> to <7>, wherein A2, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the fourth region, is 200 nm≦A2≦350 nm or less; B2, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the fifth region, is 350 nm<B2≦500 nm or less; and C2, which is an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the sixth region, is 100 nm≦C2≦200 nm or less.

[0216] REFERENCE SIGNS LIST 10: Multilayer ceramic capacitor 12: Laminate 12a: First main surface 12b: Second main surface 12c: First side surface 12d: Second side surface 12e: First end surface 12f: Second end surface 14: Ceramic layer 16: Internal electrode layer 16a, 16b: First and second internal electrode layers 18: Internal layer portion 20a: First main surface side outer layer portion 20b: Second main surface side outer layer portion 22a: First side surface side outer layer portion 22b: Second side surface side outer layer portion 24a: First end surface side outer layer portion 24b: Second end surface side outer layer portion 26a, 26b: First and second opposing electrode portions 28a, 28b: First and second extraction electrode portions 30 : External electrode 30a, 30b: First and second external electrode 32: Base electrode layer 32a, 32b: First and second base electrode layer 34: Plating layer 34a, 34b: First and second plating layer 40a-40c: First to third regions 50a-50c: Fourth to sixth regions A1, B1, C1: Average particle size A2, B2, C2: Average particle size t1, t2: Thickness ta1, tb1, tc1: Thickness ta2, tb2, tc2: Thickness x: Height direction y: Width direction z: Length direction

Claims

1. A laminate including a plurality of stacked ceramic layers and a plurality of internal electrode layers arranged on the plurality of ceramic layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode electrically connected to a first internal electrode layer of the plurality of internal electrode layers exposed at the first end surface and arranged on the first end surface; and a second external electrode electrically connected to a second internal electrode layer of the plurality of internal electrode layers exposed at the second end surface and arranged on the second end surface, wherein the laminate comprises the inner layer portion includes, in the height direction, an inner electrode layer among the plurality of inner electrode layers that is located closest to the first main surface side to an inner electrode layer among the plurality of inner electrode layers that is located closest to the second main surface side; a first main surface side outer layer portion that is located on the first main surface side and is formed of the plurality of ceramic layers that are located between the first main surface and an outermost surface of the inner layer portion on the first main surface side and an extension of the outermost surface; and a second main surface side outer layer portion that is located on the second main surface side and is formed of a plurality of ceramic layers that are located between the second main surface and an outermost surface of the inner layer portion on the second main surface side and an extension of the outermost surface, the first main surface side outer layer portion and the second main surface side outer layer portion have a first region, a second region and a third region in this order from the first main surface and the second main surface toward the inner layer portion, A multilayer ceramic electronic component, wherein when an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the first region is A1, an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the second region is B1, and an average grain size D50 value of the ceramic grains constituting the ceramic layer located in the third region is C1, the relationship C1<A1<B1 is satisfied.

2. The height direction thickness of the first region on the first main surface side is 10% or more and 25% or less of the height direction thickness of the first main surface side outer layer portion, the height direction thickness of the second region on the first main surface side is 50% or more and 80% or less of the height direction thickness of the first main surface side outer layer portion, the height direction thickness of the third region on the first main surface side is 10% or more and 25% or less of the height direction thickness of the first main surface side outer layer portion, the height direction thickness of the first region on the second main surface side is 10% or more and 25% or less of the height direction thickness of the second main surface side outer layer portion, and the height direction thickness of the second region on the second main surface side is 50% or more and 80% or less of the height direction thickness of the second main surface side outer layer portion, 2. The multilayer ceramic electronic component according to claim 1, wherein a thickness in the height direction of the third region on the second main surface side is 10% to 25% of a thickness in the height direction of the outer layer portion on the second main surface side.

3. A multilayer ceramic electronic component as described in claim 1 or 2, wherein the first main surface side outer layer portion and the second main surface side outer layer portion have voids, and the porosity of the first main surface side outer layer portion and the porosity of the second main surface side outer layer portion are each 0.5% or more and 2.5% or less.

4. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the average grain size D50 value A1 of the ceramic grains constituting the ceramic layer located in the first region is 200 nm≦A1≦350 nm or less, the average grain size D50 value B1 of the ceramic grains constituting the ceramic layer located in the second region is 350 nm<B1≦500 nm or less, and the average grain size D50 value C1 of the ceramic grains constituting the ceramic layer located in the third region is 100 nm≦C1≦200 nm or less.

5. The multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the laminate has: a first side surface side outer layer portion located on the first side surface side and formed from the plurality of ceramic layers located between the first side surface and an outermost surface of the inner layer portion on the first side surface side; and a second side surface side outer layer portion located on the second side surface side and formed from the plurality of ceramic layers located between the second side surface and an outermost surface of the inner layer portion on the second side surface side, wherein the first side surface side outer layer portion and the second side surface side outer layer portion have, in this order from the first side surface and the second side surface toward the inner layer portion, a fourth region, a fifth region and a sixth region, wherein when the average grain size D50 value of the ceramic grains constituting the ceramic layer located in the fourth region is A2, the average grain size D50 value of the ceramic grains constituting the ceramic layer located in the fifth region is B2, and the average grain size D50 value of the ceramic grains constituting the ceramic layer located in the sixth region is C2, a relationship of C2<A2<B2 is satisfied.

6. The width direction thickness of the fourth region on the first side surface side is 10% or more and 25% or less of the width direction thickness of the first side surface side outer layer portion, the width direction thickness of the fifth region on the first side surface side is 50% or more and 80% or less of the width direction thickness of the first side surface side outer layer portion, the width direction thickness of the sixth region on the first side surface side is 10% or more and 25% or less of the width direction thickness of the first side surface side outer layer portion, the width direction thickness of the fourth region on the second side surface side is 10% or more and 25% or less of the width direction thickness of the second side surface side outer layer portion, and the width direction thickness of the fifth region on the second side surface side is 50% or more and 80% or less of the width direction thickness of the second side surface side outer layer portion, 6. The multilayer ceramic electronic component according to claim 5, wherein a thickness in the width direction of the sixth region on the second side surface is 10% to 25% of a thickness in the width direction of the outer layer portion on the second side surface.

7. A multilayer ceramic electronic component as described in claim 5 or 6, wherein the first side surface outer layer portion and the second side surface outer layer portion have voids, and the porosity of the first side surface outer layer portion and the porosity of the second side surface outer layer portion are 0.5% or more and 2.5% or less.

8. A multilayer ceramic electronic component according to any one of claims 5 to 7, wherein the average grain size D50 A2 of the ceramic grains constituting the ceramic layer located in the fourth region is 200 nm≦A2≦350 nm or less, the average grain size D50 B2 of the ceramic grains constituting the ceramic layer located in the fifth region is 350 nm<B2≦500 nm or less, and the average grain size D50 C2 of the ceramic grains constituting the ceramic layer located in the sixth region is 100 nm≦C2≦200 nm or less.

Images