Chip multilayer ceramic capacitor and preparation method and application thereof

Abstract

The invention discloses a chip multilayer ceramic capacitor and a preparation method and application thereof. The chip multilayer ceramic capacitor comprises a ceramic sintered body. The ceramic sintered body comprises an inner electrode layer and a dielectric layer which are alternately stacked, and the dielectric layer contains double-shell-layer coated barium titanate-based ceramic crystal grains; the double-shell-layer coated barium titanate-based ceramic crystal grain sequentially comprises an inner core, an inner shell layer and an outer shell layer from inside to outside, the ratio of the area of the inner shell layer to the area of the inner core is 0.1-0.4; the ratio of the area of the shell layer to the area of the inner core is 0.3-0.7; the double-shell coated barium titanate-based ceramic crystal grains contain BaTiO3, R2O3, MgO, M1, M2 and (Ca (1-x-y) BaxSry) ZrO3. The chip multilayer ceramic capacitor provided by the invention has the excellent performances of high capacity, high voltage resistance, high dielectric temperature characteristic and the like.

Description

Technical Field

[0001] The invention belongs to the field of capacitors, and in particular relates to a chip-type multilayer ceramic capacitor and a preparation method and application thereof. Background Art

[0002] As one of the representatives of ceramic electronic components, multilayer ceramic capacitors (MLCCs) are widely used in various electronic devices due to their high reliability and low cost. Especially for thin and small electronic devices, multilayer ceramic capacitors need to develop in the direction of smaller size, higher capacity, higher performance and thinner layers to meet the increasingly advanced usage requirements.

[0003] At present, the dielectric materials used to manufacture this type of small-size, large-capacity MLCC are mainly BaTiO3 compounds. BaTiO3 materials (BT for short) have excellent ferroelectric, piezoelectric and dielectric properties. BaTiO3 materials are tetragonal ferroelectric phases at room temperature, and undergo ferroelectric-paraelectric phase transition at around 120°C, which causes the dielectric properties of the material to change dramatically at high temperatures, limiting its scope of application. At present, in order to improve the dielectric properties of BaTiO3 at high temperatures, the existing technology generally forms a microstructure with uneven composition during the sintering process by adding solute elements such as rare earth elements. Its typical feature is the core / shell structure, that is, a two-phase grain consisting of a core phase in the center and a shell phase around the core. Compared with the core phase, the main difference of the shell phase is that the chemical composition of the shell phase contains a high concentration of rare earth elements. After the core / shell structure is formed, the temperature characteristics of the dielectric properties of the BaTiO3 material are improved, so that the prepared MLCC has a longer service life. However, the main phase of the core / shell two-phase grains is BaTiO3, which has a large polarization characteristic. The breakdown field strength of the material is low and the voltage resistance is poor, which makes it difficult to meet the needs of high-capacity and high-voltage products. Summary of the invention

[0004] In order to overcome the problems existing in the prior art, one of the objectives of the present invention is to provide a chip-type multilayer ceramic capacitor.

[0005] A second object of the present invention is to provide a method for preparing a chip-type multilayer ceramic capacitor.

[0006] A third object of the present invention is to provide application of the above-mentioned chip-type multilayer ceramic capacitor in electronic products.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] The first aspect of the present invention provides a chip-type multilayer ceramic capacitor, comprising a ceramic sintered body; the ceramic sintered body comprises inner electrode layers and dielectric layers alternately stacked, the dielectric layer contains double-shell-coated barium titanate-based ceramic grains; the double-shell-coated barium titanate-based ceramic grains sequentially comprise an inner core, an inner shell layer and an outer shell layer from the inside to the outside; the ratio of the area of ​​the inner shell layer to the area of ​​the inner core is 0.1 to 0.4; the ratio of the area of ​​the outer shell layer to the area of ​​the inner core is 0.3 to 0.7;

[0009] The double-shell coated barium titanate-based ceramic grains contain BaTiO3, R2O3, MgO, M1, M2, (Ca (1-x-y) Ba x Sr y )ZrO3,

[0010] Among them, (Ca (1-x-y) Ba x Sr y )ZrO3, 0≤x≤1, 0≤y≤1;

[0011] M1 is a compound selected from at least one of Mn, Fe, Co, Cr, Ni, Mo, W, V, and Zn;

[0012] M2 is a compound selected from at least one of Si, Al, B and Li;

[0013] R is at least one selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y;

[0014] The inner core contains BaTiO3; the inner shell contains BaTiO3 and R2O3; the outer shell contains R2O3 and (Ca (1-x-y) Ba x Sr y )ZrO3.

[0015] During the research and development, the inventor tried to use a single layer of barium titanate-based ceramic material or a composition of (Ba 1-x-y Ca x Sr y )m(Ti 1-p Zr p )O3 is used as the raw material for preparing the dielectric layer. However, when the raw material for preparing the dielectric layer is a single-layer coated barium titanate-based ceramic material, the grains in the dielectric layer of the obtained MLCC product are single-layer coated barium titanate-based ceramic grains. At this time, the voltage resistance of the MLCC product is low, that is, the voltage range of the product is reduced. When the raw material for preparing the dielectric layer is directly (Ba 1-x- y Ca x Sry )m(Ti 1-p Zr p )O3 material or when Mg is not added to the original coating material, rare earth elements, (Ca (1-x-y) Ba x Sr y )ZrO3 and other solid dissolution, and finally form a full solid solution structure with BaTiO3, that is, a chemically uniform phase, which leads to the deterioration of the material's dielectric temperature characteristics, voltage resistance and other properties, and thus cannot meet the use requirements of high-capacity and high-voltage MLCC. Based on this, the inventor continued to develop and improve and found that: if the grains of the dielectric layer in the MLCC product are double-shell coated barium titanate-based ceramic grains, the barium titanate with ferroelectric properties is used as the core, which has a high dielectric constant and can provide high capacity for MLCC products. The barium titanate doped with R2O3 is used as the inner shell layer, which can provide a longer service life for MLCC products. The (Ca) doped with R2O3 (1-x-y) Ba x Sr y )ZrO3 as the outer shell layer significantly improves the voltage resistance of MLCC products, so that MLCC products have high capacity, high voltage resistance and long service life.

[0016] In the present invention, the ratio of the area of ​​the inner shell layer (i.e. S2) to the area of ​​the inner core (i.e. S1) (i.e. S2 / S1) is 0.1-0.4, for example, the area ratio of the two can be selected from 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4; further preferably, the ratio of the area of ​​the inner shell layer to the area of ​​the inner core is 0.15-0.3. When S2 / S1 is too small (for example, less than 0.1), the rare earth element R is not dissolved deeply in BaTiO3 (i.e. BT), the inner shell layer is thin, and the proportion of rare ferroelectric domain phase is small, resulting in the deterioration of the dielectric performance temperature characteristics of the dielectric layer and the reduction of the service life of the MLCC product; when S2 / S1 is too large (for example, greater than 0.4), the rare earth element R is too dissolved, the inner core phase becomes smaller, resulting in a decrease in the dielectric constant of the MLCC product;

[0017] In the present invention, the ratio of the area of ​​the outer shell layer (i.e. S3) to the area of ​​the inner core (i.e. S1) (i.e. S3 / S1) is 0.3-0.7, for example, the area ratio of the two can be selected from 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7; further preferably, the ratio of the area of ​​the outer shell layer to the area of ​​the inner core is 0.4-0.6. When S3 / S1 is too small (e.g., less than 0.3), the thickness of the outer shell layer is thin, and the increase in the activation energy of oxygen vacancy migration is small, resulting in a lower voltage withstand capability (i.e., breakdown field strength) of the MLCC product; when S3 / S1 is too large (e.g., greater than 0.7), the proportion of the outer shell layer is too high, and the dielectric constant of the outer shell layer material is low, resulting in a lower dielectric constant of the MLCC product and a lower product capacity.

[0018] Preferably, in the double-shell coated barium titanate-based ceramic grains, the inner core contains BaTiO3, MgO, M1, and M2; the inner shell contains BaTiO3, R2O3, MgO, M1, and M2; and the outer shell contains (Ca (1-x-y) Ba x Sr y )ZrO3, R2O3, MgO, M1, M2.

[0019] Preferably, in the dielectric layer, based on the molar percentage of BaTiO3 being 100%, the molar percentage of MgO is 0.5-10%, the molar percentage of M1 is 0.1-5%, the molar percentage of M2 is 0.1-10%, (Ca (1-x-y) Ba x Sr y )The molar percentage of ZrO3 is 0.5-15%, and the molar percentage of R2O3 is 0.1-5%.

[0020] In the present invention, the molar percentage of MgO is 0.5-10%. For example, the molar percentage of MgO can be selected from 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, 10%. More preferably, the molar percentage of MgO is 1-6%. In the present invention, MgO can prevent (Ca (1-x-y) Ba x Sr y)ZrO3 diffuses into the core and dissolves in BaTiO3, avoiding the formation of a uniform compound of the (CaBaSr)(TiZr)O3 system, and failing to form an outer shell. When the MgO content is too high (for example, greater than 10%), the solid solution inhibition effect on rare earth elements is enhanced, resulting in low element solid solubility, thinner inner shell layer, deterioration of MLCC product dielectric temperature characteristics, and reliability degradation; when the MgO content is too low (for example, less than 0.5%), the solid solution inhibition effect on rare earth elements is weakened, resulting in excessive thickness of the inner shell layer, partial solid solution of the outer shell material in BT, and reduction of the core phase, which ultimately leads to deterioration of the dielectric constant, withstand voltage and other performance of the MLCC product.

[0021] In the present invention, the (Ca (1-x-y) Ba x Sr y ) The molar percentage of ZrO3 is 0.5 to 15%. For example, the (Ca (1-x-y) Ba x Sr y )The mole percentage of ZrO3 can be selected from 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, 10%, 10.5%, 11%, 11.5%, 12%, 12.5%, 13%, 13.5%, 14%, 14.5%, 15%; further preferably, the (Ca (1-x-y) Ba x Sr y )ZrO3 has a molar percentage of 1 to 10%. In the present invention, when (Ca (1-x-y) Ba x Sr y When the content of ZrO3 is too high (for example, more than 15%), the outer shell layer is thicker, and the outer shell layer is mainly composed of (Ca (1-x-y) Ba x Sr y )ZrO3 material, its dielectric constant is low, resulting in a decrease in the dielectric constant of the final MLCC product and too low capacity; when (Ca (1-x-y) Ba x Sr y ) When the ZrO3 content is too low (for example, less than 0.5%), the thickness of the outer shell layer is thin, resulting in a weakening of the voltage resistance of the dielectric layer and a reduction in the breakdown field strength of the MLCC product.

[0022] In the present invention, (Ca (1-x-y) Ba x Sr y)ZrO3, 0≤x≤1, 0≤y≤1; for example, x can be selected from 0, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.12, 0.14, 0.16, 0.18, 0.2, 0.22, 0.24, 0.26, 0.28, 0.3, 0.32, 0.34, 0.36, 0.38, 0.4, 0.42, 0.44, 0.46, 0.48, 0.5, 0.52, 0.54, 0.56, 0.58, 0.6, 0.62, 0.64, 0.66, 0.68, 0.7, 0.72, 0.74, 0.76, 0.78, 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, 0.92, 0.94, 0 .96, 0.98, 1; y can be selected from 0, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.12, 0.14, 0.16, 0.18, 0.2, 0.22, 0.24, 0.26, 0.28, 0.3, 0.32, 0.34, 0.36, 0.38, 0.4, 0. 42, 0.44, 0.46, 0.48, 0.5, 0.52, 0.54, 0.56, 0.58, 0.6, 0.62, 0.64, 0.66, 0.68, 0.7, 0.72, 0.74, 0.76, 0.78, 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, 0.92, 0.94, 0.96, 0.98, 1. Further preferably, the (Ca (1-x-y) Ba x Sr y )ZrO3 is selected from (Ca 0.5 Ba 0.2 Sr 0.3 )ZrO3、(Ca 0.1 Ba 0.1 Sr 0.8 )ZrO3、(Ca 0.1 Ba 0.2 Sr 0.7 )ZrO3、(Ca 0.3 Ba 0.3 Sr 0.4 )ZrO3、(Ca 0.1 Ba 0.4 Sr 0.5 )ZrO3、(Ca 0.2 Ba 0.5 Sr 0.3 )ZrO3、(Ca 0.2 Ba 0.6 Sr 0.2 )ZrO3、(Ca 0.1Ba 0.6 Sr 0.3 )ZrO3、(Ca 0.2 Ba 0.7 Sr 0.1 )ZrO3、(Ca 0.1 Ba 0.8 Sr 0.1 )ZrO3、(Ca 0.05 Ba 0.9 Sr 0.05 )ZrO3、(Ca 0.7 Ba 0.2 Sr 0.1 )ZrO3、(Ca 0.8 Ba 0.1 Sr 0.1 )ZrO3、(Ca 0.9 Ba 0.05 Sr 0.05 )ZrO3 or (Ca 0.05 Ba 0.05 Sr 0.9 )ZrO3, CaZrO3, SrZrO3, BaZrO3, (Ca 0.5 Ba 0.5 )ZrO3 or (Ca 0.5 Sr 0.5 )ZrO3. The above (Ca (1-x-y) Ba x Sr y )ZrO3 has high breakdown field strength and highly stable dielectric-temperature characteristics, which can increase the activation energy of oxygen vacancy migration in the dielectric layer, thereby reducing the capacitance change rate of MLCC at different temperatures and extending its service life.

[0023] In the present invention, the molar percentage of R2O3 is 0.1-5%. For example, the molar percentage of R2O3 can be selected from 0.1%, 0.2%, 0.4%, 0.6%, 0.8%, 1%, 1.2%, 1.4%, 1.6%, 1.8%, 2%, 2.2%, 2.4%, 2.6%, 2.8%, 3%, 3.2%, 3.4%, 3.6%, 3.8%, 4%, 4.2%, 4.4%, 4.6%, 4.8%, and 5%. In the present invention, when the content of R2O3 is too much (for example, greater than 5%), after the MLCC product is sintered, the rare earth element R is too much solid solution, the inner shell area becomes thicker, and the proportion of the inner core becomes smaller, resulting in a decrease in the dielectric constant of the MLCC product at room temperature, which cannot meet the requirements of high capacity; when the content of R2O3 is too little (for example, less than 0.1%), the inner shell layer is difficult to form, and the temperature characteristics of the dielectric properties of the double-shell coated barium titanate-based ceramic grains deteriorate, the insulation resistance of the MLCC product deteriorates at high temperatures, and the service life is shortened.

[0024] In the present invention, the molar percentage of M1 is 0.1-5%. For example, the molar percentage of M1 can be selected from 0.1%, 0.2%, 0.4%, 0.6%, 0.8%, 1%, 1.2%, 1.4%, 1.6%, 1.8%, 2%, 2.2%, 2.4%, 2.6%, 2.8%, 3%, 3.2%, 3.4%, 3.6%, 3.8%, 4%, 4.2%, 4.4%, 4.6%, 4.8%, 5%. In the present invention, when the content of M1 is too much (for example, greater than 5%), semiconductivity is likely to occur, the insulation resistance of the dielectric layer is reduced, and the service life and breakdown field strength of the MLCC product are reduced; when the content of M1 is too little (for example, less than 0.1%), the anti-reduction performance is reduced, resulting in Ti 4+ After being reduced, the high-temperature and high-voltage insulation resistance performance of the dielectric layer deteriorates significantly, resulting in a reduction in the service life of MLCC products.

[0025] In the present invention, the molar percentage of M2 is 0.1-10%, for example, the molar percentage of M2 can be selected from 0.1%, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, 10%. In the present invention, when the content of M2 is too much (for example, greater than 10%), there is too much sintering liquid phase, the grains are easy to grow, and the life characteristics of the MLCC product are significantly deteriorated; when the content of M2 is too little (for example, less than 0.1%), the sintering property decreases, a higher temperature sintering is required, the insulation resistance of the dielectric layer is low, and the service life of the MLCC product is reduced.

[0026] Preferably, the barium titanate is tetragonal barium titanate.

[0027] Preferably, the ceramic sintered body further comprises a cover plate, the cover plate is made of the same material as the dielectric layer, and the cover plate is arranged on the surface of the inner electrode layer exposed in the ceramic sintered body.

[0028] Preferably, the chip-type multilayer ceramic capacitor further includes external electrodes, which are respectively disposed on both ends of the ceramic sintered body and are electrically connected to the internal electrode layer.

[0029] Preferably, a plating layer is provided on the surface of the outer electrode layer.

[0030] Preferably, the plating layer includes a first plating layer disposed on the surface of the outer electrode and a second plating layer disposed on the surface of the first plating layer.

[0031] The second aspect of the present invention provides a method for preparing the chip-type multilayer ceramic capacitor described in the first aspect of the present invention, which is prepared by method one or method two;

[0032] The method 1 comprises the following steps:

[0033] a1: adding magnesium salt, M1 salt and M2 salt to a suspension of barium titanate, mixing and drying, and then pre-calcining to obtain a core material coated with an inner shell layer;

[0034] a2: The core material coated with the inner shell layer, (Ca (1-x-y) Ba x Sr y ) ZrO3 and R2O3 are mixed and ground, and then calcined to obtain a double-shell coated barium titanate-based ceramic material;

[0035] a3: The double-shell coated barium titanate-based ceramic material is used to prepare a chip-type multilayer ceramic capacitor.

[0036] The second method comprises the following steps:

[0037] b1: R compound, Mg compound, M1 compound, M2 compound, (Ca (1-x-y) Ba x Sr y )ZrO3 or (Ca (1-x-y) Ba x Sr y ) Mixing and grinding the raw material for preparing ZrO3 and barium titanate powder to obtain the raw material for preparing the dielectric layer;

[0038] b2: using the raw materials for preparing the dielectric layer to prepare a chip-type multilayer ceramic capacitor.

[0039] Preferably, the preparation method of the barium titanate suspension is: mixing barium titanate powder with at least one solvent selected from water, ethanol, and glacial acetic acid, and grinding to obtain the suspension.

[0040] Preferably, in the method one and / or the method two, the barium titanate is prepared by a method selected from a solid phase method, a co-precipitation method, a hydrothermal method or an oxalate method.

[0041] Preferably, the magnesium salt is selected from at least one of magnesium nitrate, magnesium carbonate and magnesium acetate.

[0042] Preferably, the salt of M1 is selected from at least one of the nitrate of M1, the carbonate of M1 and the acetate of M1.

[0043] Preferably, the salt of M2 is selected from at least one of the nitrate of M2, the carbonate of M2 and the acetate of M2.

[0044] Preferably, the drying temperature in the method one is 100-300°C, for example, it can be selected from 100°C, 120°C, 140°C, 160°C, 180°C, 200°C, 220°C, 240°C, 260°C, 280°C, and 300°C.

[0045] Preferably, the drying time in the method 1 is 2 to 10 hours, for example, it can be selected from 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 7 hours, 8 hours, 9 hours, and 10 hours.

[0046] Preferably, the pre-firing temperature in the method one is 400-800°C, for example, can be selected from 400°C, 420°C, 440°C, 460°C, 480°C, 500°C, 520°C, 540°C, 560°C, 580°C, 600°C, 620°C, 640°C, 660°C, 680°C, 700°C, 720°C, 740°C, 760°C, 780°C, and 800°C.

[0047] Preferably, the pre-burning time in the method one is 0.5 to 3 h, for example, can be selected from 0.5 h, 0.8 h, 1 h, 1.2 h, 1.5 h, 1.8 h, 2 h, 2.2 h, 2.5 h, 2.8 h, and 3 h.

[0048] Preferably, the calcination temperature in the method one is 500-1000°C, for example, can be selected from 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C.

[0049] Preferably, the calcination time in the method one is 1 to 4 h, for example, can be selected from 1 h, 1.2 h, 1.5 h, 1.8 h, 2 h, 2.2 h, 2.5 h, 2.8 h, 3 h, 3.2 h, 3.5 h, 3.8 h, and 4 h.

[0050] Preferably, in the method 1, a wet crushing and drying step is provided between the mixing and grinding step and the calcining step.

[0051] Preferably, in the wet crushing and drying steps, the wet crushing time is 4 to 12 hours, for example, it can be selected from 4 hours, 5 hours, 6 hours, 7 hours, 8 hours, 9 hours, 10 hours, 11 hours, and 12 hours.

[0052] Preferably, in the wet pulverizing and drying step, the drying temperature is 100-400°C, for example, can be selected from 100°C, 200°C, 300°C, 400°C.

[0053] Preferably, in the wet crushing and drying step, the drying time is 150 to 300 min, for example, can be selected from 150 min, 170 min, 190 min, 200 min, 220 min, 240 min, 260 min, 280 min, 300 min.

[0054] Preferably, the compound of R is at least one selected from the group consisting of an oxide of R, a nitride of R, a nitrate of R, an acetate of R, and a carbonate of R.

[0055] Preferably, the Mg compound is selected from at least one of magnesium oxide, magnesium nitride, magnesium nitrate, magnesium acetate and magnesium carbonate.

[0056] Preferably, the compound of M1 is selected from at least one of the oxide of M1, the nitride of M1, the nitrate of M1, the acetate of M1, and the carbonate of M1.

[0057] Preferably, the compound of M2 is selected from at least one of an oxide of M2, a nitride of M2, a nitrate of M2, an acetate of M2, and a carbonate of M2.

[0058] Preferably, the (Ca (1-x-y) Ba x Sr y )The raw materials for preparing ZrO3 include Ca compounds, Ba compounds, Sr compounds and Zr compounds.

[0059] Preferably, the Ca compound is selected from at least one of calcium oxide, calcium nitride, calcium carbonate, calcium nitrate and calcium acetate.

[0060] Preferably, the Ba compound is selected from at least one of barium oxide, barium nitride, barium carbonate, barium nitrate and barium acetate.

[0061] Preferably, the Sr compound is selected from at least one of strontium oxide, strontium nitride, strontium carbonate, strontium nitrate and strontium acetate.

[0062] Preferably, the Zr compound is selected from at least one of zirconium oxide, zirconium nitride, zirconium carbonate, zirconium nitrate and zirconium acetate.

[0063] Preferably, in the method 1, step a3 comprises the following steps:

[0064] a31: forming a film of a ceramic slurry containing the double-shell-coated barium titanate-based ceramic material to obtain a ceramic dielectric layer green sheet;

[0065] a32: forming a conductive film on the ceramic dielectric layer green sheet to obtain a ceramic dielectric layer green sheet with an internal electrode layer;

[0066] a33: stacking the ceramic dielectric layer green sheet and the ceramic dielectric layer green sheet with the inner electrode layer, heat treating them, and then sintering them to obtain a ceramic sintered body;

[0067] a34: External electrodes are formed at both ends of the ceramic sintered body to obtain the chip-type multilayer ceramic capacitor.

[0068] Preferably, in step a31, the ceramic slurry contains a double-shell coated barium titanate-based ceramic material, a binder and an organic solvent; further preferably, the ceramic slurry contains a double-shell coated barium titanate-based ceramic material, a binder and an organic solvent in a mass ratio of 100:(7-10):(40-60).

[0069] Preferably, step b2 in the method 2 comprises the following steps:

[0070] b21: forming a film of a ceramic slurry containing the raw materials for preparing the dielectric layer to obtain a ceramic dielectric layer green sheet;

[0071] b22: forming a conductive film on the ceramic dielectric layer green sheet to obtain a ceramic dielectric layer green sheet with an internal electrode layer;

[0072] b23: stacking the ceramic dielectric layer green sheet and the ceramic dielectric layer green sheet with the inner electrode layer, heat treating them, and then sintering them to obtain a ceramic sintered body;

[0073] b24: External electrodes are formed at both ends of the ceramic sintered body to obtain the chip-type multilayer ceramic capacitor.

[0074] Preferably, in step b21, the ceramic slurry contains the raw materials for preparing the dielectric layer, a binder and an organic solvent; further preferably, the ceramic slurry contains the raw materials for preparing the dielectric layer, a binder and an organic solvent in a mass ratio of 100:(7-10):(40-60).

[0075] Preferably, in step a31 and / or step b21, the ceramic slurry is formed into a film by any method selected from the group consisting of a lip coating method and a doctor blade method.

[0076] Preferably, in step a33 and / or step b23, the heat treatment temperature is 250-350°C.

[0077] Preferably, in step a33 and / or step b23, the sintering atmosphere is a strongly reducing atmosphere; further preferably, in step a33 and / or step b23, the sintering atmosphere is a strongly reducing atmosphere in which the volume ratio of hydrogen to nitrogen is (0.1-2):100.

[0078] Preferably, in step a33 and / or step b23, the sintering temperature is 1100-1300°C.

[0079] Preferably, in step a33 and / or step b23, the sintering time is 2 to 4 hours.

[0080] Preferably, in step a34 and / or step b24, the step of forming external electrodes at both ends of the ceramic sintered body is: coating the external electrode slurry on both ends of the ceramic sintered body respectively, and then baking at a temperature of 600-900° C. for 2-4 hours.

[0081] The third aspect of the present invention provides the use of the chip-type multilayer ceramic capacitor described in the first aspect of the present invention in an electronic product.

[0082] The beneficial effects of the present invention are as follows: the grains in the dielectric layer of the chip-type multilayer ceramic capacitor of the present invention are of a double shell / core three-phase structure, wherein the core is a barium titanate ferroelectric phase with a high dielectric constant, providing high capacity for MLCC products, the inner shell is a highly rare earth-doped barium titanate pseudo-cubic phase, the lattice is distorted, the high-temperature dielectric properties of the material are improved, and a longer service life is provided for MLCC products, and the outer shell is (Ca (1-x-y) Ba x Sr y )The paraelectric phase of the ZrO3 matrix has a high activation energy for oxygen vacancy migration, providing MLCC products with higher voltage resistance; ultimately, the MLCC products with this structure have excellent properties such as high capacity, high voltage resistance, and high dielectric temperature characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 This is the TEM-EDS image of the chip-type multilayer ceramic capacitor in Example 1.

[0084] Figure 2 This is the TEM-EDS image of the chip-type multilayer ceramic capacitor in Comparative Example 3. DETAILED DESCRIPTION

[0085] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be pointed out that if there are processes that are not particularly described in detail below, they can be implemented or understood by those skilled in the art with reference to the prior art. The reagents or instruments used without indicating the manufacturer are all conventional products that can be purchased commercially. The present invention uses ICP, XRF and other detection means to detect the elemental composition and content of the sintered products in the following embodiments and comparative examples, and uses TEM to test the core-double-shell structure of the sintered products in the embodiments and comparative examples.

[0086] Example 1

[0087] This example provides a chip-type multilayer ceramic capacitor, which includes a ceramic sintered body, a cover plate, an external electrode and a plating layer. The ceramic sintered body includes inner electrode layers and dielectric layers alternately stacked, and the number of the inner electrode layers and the dielectric layers is greater than two. In order to avoid the inner electrode layer from being exposed, a cover plate is arranged on the exposed inner electrode layer in the ceramic sintered body. The material of the cover plate is the same as that of the dielectric layer. An external electrode is respectively arranged at both ends of the ceramic sintered body, and the external electrode is electrically connected to the inner electrode layer close to the side of the external electrode. A plating layer is arranged on the surface of the external electrode.

[0088] The plated layer is a first plated film and a second plated film which are stacked.

[0089] In this example, the dielectric layer includes double-shell coated barium titanate-based ceramic grains, and the double-shell coated barium titanate-based ceramic grains include a core, an inner shell and an outer shell; the core material is BaTiO3, MgO, MnO2 (i.e., M1), SiO2 (i.e., M2), the inner shell material is BaTiO3, Dy2O3 (i.e., R2O3), MgO, MnO2, SiO2, and the outer shell material is (Ca 0.5 Ba 0.2 Sr 0.3 )ZrO3, Dy2O3, MgO, MnO2, SiO2.

[0090] The area of ​​the inner core is S1, the area of ​​the inner shell is S2, and the area of ​​the outer shell is S3. S2:S1=0.2, S3:S1=0.5, as shown in Table 1.

[0091] In the double-shell coated barium titanate-based ceramic grains, the molar percentage of BaTiO3 is 100%, the molar percentage of MgO is 4%, the molar percentage of MnO2 (i.e., M1) is 1%, the molar percentage of SiO2 (i.e., M2) is 4%, the molar percentage of Dy2O3 is 3%, (Ca 0.5 Ba 0.2 Sr 0.3 )The molar percentage of ZrO3 is 6%, as shown in Table 2.

[0092] The chip-type multilayer ceramic capacitor in this example is manufactured by a manufacturing method comprising the following steps:

[0093] 1. Preparation of double-shell coated barium titanate-based ceramic materials:

[0094] 1) Place BaTiO3 powder in pure water, stir, grind and disperse to obtain a suspension;

[0095] 2) Based on the molar percentage of BaTiO3 being 100 mol%, 4 mol% of magnesium acetate, 1 mol% of manganese acetate and 4 mol% of silicon acetate are added to the above suspension solution, stirred and dispersed to obtain a mixed solution containing the core and inner shell materials;

[0096] 3) drying and pre-calcining the mixed solution obtained in step 2) to obtain a ceramic powder with an inner shell layer covering the inner core; the drying temperature is 200° C., the drying time is 6 h, the pre-calcining temperature is 600° C., and the pre-calcining time is 2 h, to obtain a ceramic powder with an inner shell layer;

[0097] 4) Based on 100 mol% of BaTiO3, 6 mol% (Ca 0.5 Ba 0.2 Sr 0.3 ) ZrO3 and 3 mol% Dy2O3 powders are mixed with the ceramic powder with an inner shell layer obtained in step 3), wet-milled for 6 hours, dried at 200°C for 200 minutes, and calcined at 750°C for 2 hours to obtain a double-shell coated barium titanate-based ceramic material.

[0098] 2. Preparation of chip-type multilayer ceramic capacitors:

[0099] 1) The double-shell coated barium titanate-based ceramic material, polyvinyl butyral (PVB), and ethanol prepared by the above method are put into a sand mill in a mass ratio of 100:10:50 and wet mixed to prepare a ceramic slurry, and the ceramic slurry is formed by a scraper method to prepare a ceramic dielectric layer green sheet.

[0100] 2) Prepare a conductive paste for internal electrodes mainly composed of a base metal material such as Ni, and screen print the conductive paste for internal electrodes on a ceramic dielectric layer green sheet to form a conductive film of a predetermined pattern on the surface of the ceramic dielectric layer green sheet.

[0101] 3) Multiple ceramic dielectric layer green sheets with conductive films formed thereon are stacked in a given direction, and ceramic dielectric layer green sheets without conductive films formed thereon are arranged on the top layer as a cover sheet, and the sheets are pressed and bonded, and cut into a given size to produce a ceramic sintered body. The ceramic sintered body is then heat treated at 300°C in an air atmosphere to burn and remove the binder, and then sintered at 1200°C for 2 hours in a strong reducing atmosphere consisting of a gas with a H2:N2 ratio of 0.005:1 to obtain a ceramic sintered body.

[0102] 4) Applying conductive paste for external electrodes to both end surfaces of the ceramic sintered body, and baking the paste at 750°C for 2 hours to form external electrodes. In addition, although there is no particular limitation on the conductive material contained in the conductive paste for external electrodes, from the perspective of cost reduction, it is preferred to use Ag, Cu, or a material containing an alloy thereof as a main component.

[0103] Alternatively, as a method of forming the external electrodes, a conductive paste for external electrodes may be applied to both end surfaces of the ceramic laminate and then fired simultaneously with the ceramic sintered body.

[0104] 5) Finally, electrolytic plating is performed to form a first plating film composed of Ni, Cu, Ni-Cu alloy, etc. on the surface of the external electrode, and then a second plating film composed of solder, tin, etc. is formed on the surface of the first plating film to obtain the chip-type multilayer ceramic capacitor in this example.

[0105] Example 2

[0106] The difference between the chip-type multilayer ceramic capacitor in this example and the embodiment 1 is that: in the double-shell coated barium titanate-based ceramic grains in the dielectric layer, S2:S1=0.1, the molar percentage of MgO is 6%, the molar percentage of Dy2O3 is 0.5%, (Ca 0.5 Ba 0.2 Sr 0.3 )The molar percentage of ZrO3 is 7%, as shown in Table 1 and Table 2.

[0107] The chip-type multilayer ceramic capacitor in this example is manufactured by a manufacturing method comprising the following steps:

[0108] 1. Raw materials for preparing the dielectric layer:

[0109] Based on the molar percentage of BaTiO3 being 100mol%, 6mol% MgO, 1mol% MnO2, 4mol% SiO2, 0.5mol% Dy2O3, 7mol% (Ca 0.5 Ba 0.2 Sr 0.3 )ZrO3 and BaTiO3 powders are mixed, and water in an amount equal to that of the BaTiO3 powder is added, the mixture is wet-ground, and dried at 150° C. for 4 h to obtain a raw material for preparing a dielectric layer.

[0110] 2. Preparation of chip-type multilayer ceramic capacitors:

[0111] 1) The raw material for preparing the dielectric layer obtained by the above method, polyvinyl butyral (PVB), and ethanol are put into a sand mill in a mass ratio of 100:10:50 and wet mixed to prepare a ceramic slurry, and the ceramic slurry is formed by a scraper method to prepare a ceramic dielectric layer green sheet.

[0112] 2) Prepare a conductive paste for internal electrodes mainly composed of a base metal material such as Ni, and screen print the conductive paste for internal electrodes on a ceramic dielectric layer green sheet to form a conductive film of a predetermined pattern on the surface of the ceramic dielectric layer green sheet.

[0113] 3) Multiple ceramic dielectric layer green sheets with conductive films formed thereon are stacked in a given direction, and ceramic dielectric layer green sheets without conductive films formed thereon are arranged on the top layer as a cover sheet, and the sheets are pressed and bonded, and cut into a given size to produce a ceramic sintered body. The ceramic sintered body is then heat treated at 300°C in an air atmosphere to burn and remove the binder, and then sintered at 1200°C for 2 hours in a strong reducing atmosphere consisting of a gas with a H2:N2 ratio of 0.005:1 to obtain a ceramic sintered body.

[0114] 4) Applying conductive paste for external electrodes to both end surfaces of the ceramic sintered body, and baking the paste at 750°C for 2 hours to form external electrodes. In addition, although there is no particular limitation on the conductive material contained in the conductive paste for external electrodes, from the perspective of cost reduction, it is preferred to use Ag, Cu, or a material containing an alloy thereof as a main component.

[0115] Alternatively, as a method of forming the external electrodes, a conductive paste for external electrodes may be applied to both end surfaces of the ceramic laminate and then fired simultaneously with the ceramic sintered body.

[0116] 5) Finally, electrolytic plating is performed to form a first plating film composed of Ni, Cu, Ni-Cu alloy, etc. on the surface of the external electrode, and then a second plating film composed of solder, tin, etc. is formed on the surface of the first plating film to obtain the chip-type multilayer ceramic capacitor in this example.

[0117] Embodiments 3 to 9

[0118] The differences between the chip-type multilayer ceramic capacitors in Examples 3 to 9 and Example 1 are shown in Tables 1 and 2, respectively.

[0119] Comparative Examples 1 to 8

[0120] The differences between the chip-type multilayer ceramic capacitors in Comparative Examples 1 to 8 and Example 1 are shown in Table 1 and Table 2, respectively.

[0121] Table 1 Relationship between the areas of the core, inner shell and outer shell

[0122] serial number <![CDATA[S2:S1]]> <![CDATA[S3:S1]]> Example 1 0.2 0.5 Example 2 0.1 0.5 Example 3 0.15 0.5 Example 4 0.3 0.5 Example 5 0.4 0.5 Example 6 0.2 0.3 Example 7 0.2 0.4 Example 8 0.2 0.6 Example 9 0.2 0.7 Comparative Example 1 0.0 0.5 Comparative Example 2 0.5 0.5 Comparative Example 3 0.2 0.0 Comparative Example 4 0.2 0.8 Comparative Example 5 0.5 0.8 Comparative Example 6 0.05 0.1 Comparative Example 7 0.05 0.8 Comparative Example 8 0.5 0.1

[0123] Table 2 Formula of double-shell coated barium titanate-based ceramic grains

[0124]

[0125]

[0126] Performance Testing

[0127] The samples prepared in Example 1 and Comparative Example 3 were subjected to EDS spectrum analysis using a transmission electron microscope to confirm the element distribution of each grain. The specific test results are as follows: Figure 1 and Figure 2 As shown. Figure 1 and Figure 2 It can be seen that the rare earth Dy elements all form a shell structure, and the Mg and Mn elements are basically evenly distributed; the Ca, Sr and Zr elements of each grain in Example 1 overlap and are wrapped in the outer layer of Ba and Ti elements, which can be seen to form a (Ca (1-x-y) Ba x Sr y ) The double-shell grain structure of ZrO3 is shown in Figure 3, while in Comparative Example 3, the elements Ca, Sr, Zr, Ba, Ti, etc. are basically evenly distributed. Except for the Sr and Mg precipitation phases, no Ca, Sr, and Zr shells are found, that is, no double-shell encapsulated grains are formed.

[0128] The dielectric constant, breakdown field strength, accelerated life and TCC performance of the chip-type multilayer ceramic capacitors in Examples 1 to 9 and Comparative Examples 1 to 8 were tested respectively. The specific test conditions, standards and requirements are shown in Table 3 below.

[0129] Table 3 Test items, test conditions, requirements and standards

[0130]

[0131] The various performance data measured according to the test conditions recorded in Table 3 above are shown in Table 4 below.

[0132] Table 4 Performance data of chip multilayer ceramic capacitors

[0133]

[0134]

[0135] As can be seen from Table 4, compared with Comparative Examples 1 to 8, Examples 1 to 9 of the present invention optimize the amount of each material in the double-shell coated barium titanate-based ceramic grains and optimize the area ratio between the inner core, the inner shell layer, and the outer shell layer, so that the chip-type multilayer ceramic capacitor has a higher dielectric constant and breakdown field strength, the dielectric constant is ≥2500, the breakdown field strength is ≥40V / μm, the average failure time of 50% is ≥3h, and the TCC is within ±15%, which meets the use requirements of high-capacity and high-voltage chip-type multilayer ceramic capacitors. The specific analysis is as follows:

[0136] By comparing Examples 1 to 5, Comparative Examples 1 to 2, and Comparative Example 7, it can be seen that when the S2 / S1 value is increased, the accelerated life performance of the chip-type multilayer ceramic capacitor product is improved, but the product dielectric constant decreases. This is because the inner shell phase (i.e., the inner shell layer) becomes thicker, the lattice distortion increases, and the high-temperature dielectric performance of the product is improved. However, the thickening of the inner shell phase means that the core phase becomes smaller, and the contribution to the capacity of the product is reduced, resulting in a decrease in the product dielectric constant;

[0137] By comparing Examples 6 to 8, Comparative Examples 3 to 4, and Comparative Example 8, it can be seen that when the S3 / S1 value increases, the breakdown field strength of the chip-type multilayer ceramic capacitor product is higher, but the dielectric constant decreases. This is because the shell phase (i.e., the shell layer) is a paraelectric phase material, and its dielectric constant is lower, which reduces the dielectric constant of the product.

[0138] In Comparative Example 5, the values ​​of S2 / S1 and S3 / S1 are both too high, the shell phase accounts for a high proportion, and the core phase is small, resulting in a reduced capacity of the chip-type multilayer ceramic capacitor product and a small dielectric constant;

[0139] In Comparative Example 6, the S2 / S1 and S3 / S1 values ​​are both too small, the proportion of the inner shell phase is small, the rare earth elements are not sufficiently dissolved, and the stability of the high-temperature dielectric properties decreases, resulting in a decrease in the life performance of the multilayer ceramic capacitor product and a deterioration in the temperature coefficient. At the same time, the outer shell phase is relatively thin, and the voltage resistance of the multilayer ceramic capacitor product is less improved, resulting in a decrease in the breakdown field strength of the product.

[0140] After testing, when (Ca (1-x-y) Ba x Sr y )ZrO3 can obtain the same results as (Ca) when x and y are any values ​​within the range of 0≤x≤1 and 0≤y≤1. 0.5 Ba 0.2 Sr 0.3 )ZrO3 has a technical effect basically equivalent to that of MnO2. When M1 is any element among Fe, Co, Cr, Ni, Mo, W, V, and Zn, a technical effect basically equivalent to that of MnO2 can be achieved. When M2 is any element among Al, B, and Li, a technical effect basically equivalent to that of SiO2 can be achieved. When R is any element among La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, Lu, and Y, a technical effect basically equivalent to that of Dy2O3 can be achieved.

[0141] In summary, the grains in the dielectric layer of the chip-type multilayer ceramic capacitor of the present invention are of a double shell / core three-phase structure, wherein the core is a barium titanate ferroelectric phase with a high dielectric constant, providing high capacity for MLCC products, the inner shell is a highly rare earth-doped barium titanate pseudo-cubic phase, the lattice is distorted, the high-temperature dielectric properties of the material are improved, and a longer service life is provided for MLCC products, and the outer shell is (Ca(1-x-y) Ba x Sr y )The paraelectric phase of the ZrO3 matrix has a high activation energy for oxygen vacancy migration, providing MLCC products with higher voltage resistance; ultimately, the MLCC products with this structure have excellent properties such as high capacity, high voltage resistance, and high dielectric temperature characteristics.

[0142] The above is a detailed description of the embodiments of the present invention, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

Claims

1. A chip-type multilayer ceramic capacitor, comprising a ceramic sintered body; the ceramic sintered body comprises inner electrode layers and dielectric layers alternately stacked, characterized in that: The dielectric layer contains double-shell-coated barium titanate-based ceramic grains; the double-shell-coated barium titanate-based ceramic grains include an inner core, an inner shell layer and an outer shell layer from the inside to the outside; the ratio of the area of ​​the inner shell layer to the area of ​​the inner core is 0.1 to 0.4; the ratio of the area of ​​the outer shell layer to the area of ​​the inner core is 0.3 to 0.7; The double-shell coated barium titanate-based ceramic grains contain BaTiO3, R2O3, MgO, M1, M2, (Ca (1-x-y) Ba x Sr y )ZrO3, Among them, (Ca (1-x-y) Ba x Sr y )ZrO3, 0≤x≤1, 0≤y≤1; M1 is a compound selected from at least one of Mn, Fe, Co, Cr, Ni, Mo, W, V, and Zn; M2 is a compound selected from at least one of Si, Al, B and Li; R is at least one selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y; The inner core contains BaTiO3; the inner shell contains BaTiO3 and R2O3; the outer shell contains R2O3 and (Ca (1-x-y) Ba x Sr y )ZrO3.

2. The multilayer ceramic capacitor according to claim 1, wherein: In the double-shell coated barium titanate-based ceramic grains, the inner core contains BaTiO3, MgO, M1, and M2; the inner shell contains BaTiO3, R2O3, MgO, M1, and M2; the outer shell contains (Ca (1-x-y) Ba x Sr y )ZrO3, R2O3, MgO, M1, M2.

3. The multilayer ceramic capacitor according to claim 1, wherein: In the dielectric layer, based on the molar percentage of BaTiO3 being 100%, the molar percentage of MgO is 0.5-10%, the molar percentage of M1 is 0.1-5%, the molar percentage of M2 is 0.1-10%, (Ca (1-x-y) Ba x Sr y )The molar percentage of ZrO3 is 0.5-15%, and the molar percentage of R2O3 is 0.1-5%.

4. The multilayer ceramic capacitor according to claim 3, wherein: The molar percentage of MgO is 1-6%; And / or, the (Ca (1-x-y) Ba x Sr y )The molar percentage of ZrO3 is 1 to 10%.

5. The multilayer ceramic capacitor according to claim 1, wherein: The ratio of the area of ​​the inner shell to the area of ​​the inner core is 0.15 to 0.3; and / or, The ratio of the area of ​​the outer shell layer to the area of ​​the inner core is 0.4 to 0.

6.

6. The multilayer ceramic capacitor according to claim 1, wherein: The ceramic sintered body also includes a cover plate, which is made of the same material as the dielectric layer and is arranged on the surface of the inner electrode layer exposed in the ceramic sintered body.

7. The multilayer ceramic capacitor according to claim 1, wherein: The chip-type multilayer ceramic capacitor further includes external electrodes, which are respectively disposed on both ends of the ceramic sintered body and are electrically connected to the internal electrode layer.

8. The method for preparing a chip-type multilayer ceramic capacitor according to any one of claims 1 to 7, characterized in that: Prepared by method 1 or method 2; The method 1 comprises the following steps: a1: adding magnesium salt, M1 salt and M2 salt to a suspension of barium titanate, mixing and drying, and then pre-calcining to obtain a core material coated with an inner shell layer; a2: The core material coated with the inner shell layer, (Ca (1-x-y) Ba x Sr y ) ZrO3 and R2O3 are mixed and ground, and then calcined to obtain a double-shell coated barium titanate-based ceramic material; a3: using the double-shell coated barium titanate-based ceramic material to prepare a chip-type multilayer ceramic capacitor; The second method comprises the following steps: b1: R compound, Mg compound, M1 compound, M2 compound, (Ca (1-x-y) Ba x Sr y )ZrO3 or (Ca (1-x-y) Ba x Sr y ) Mixing and grinding the raw material for preparing ZrO3 and barium titanate powder to obtain the raw material for preparing the dielectric layer; b2: using the raw materials for preparing the dielectric layer to prepare a chip-type multilayer ceramic capacitor.

9. The method for preparing a chip-type multilayer ceramic capacitor according to claim 8, characterized in that: The drying temperature in the method 1 is 100-300°C; And / or, the drying time in the method 1 is 2 to 10 hours; And / or, the pre-firing temperature in the method 1 is 400-800°C; And / or, the pre-burning time in the method 1 is 0.5 to 3 hours; And / or, the calcination temperature in the method 1 is 500-1000°C; And / or, the calcination time in the method 1 is 1 to 4 hours; And / or, in the method 1, a wet crushing and drying step is further provided between the mixing and grinding step and the calcining step.

10. Use of the chip-type multilayer ceramic capacitor according to any one of claims 1 to 7 in electronic products.

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