Preparation method for coplanar waveguide circuit, chip substrate and chip

Abstract

The present application discloses a preparation method for a coplanar waveguide circuit, a chip substrate and a chip, and relates to the technical field of quantum technology. The method comprises: forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate (610); forming at least one second through hole on the substrate (620); etching the first material layer to remove a portion corresponding to the conductor pattern of a first coplanar waveguide circuit in order to obtain an etched first material layer (630); etching the second material layer to remove a portion corresponding to the conductor pattern of a second coplanar waveguide circuit in order to obtain an etched second material layer (640); depositing a conductor material (650); and removing the etched first material layer and the etched second material layer to obtain a substrate with coplanar waveguide circuits (660). The present method improves the efficiency of preparation of coplanar waveguide circuits.

Description

Preparation method of coplanar waveguide circuit, chip substrate and chip

[0001] This application claims priority to Chinese patent application No. 202310674216.5 filed on June 7, 2023, entitled “Method for preparing coplanar waveguide circuit, chip substrate and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of quantum technology, and in particular to a method for preparing a coplanar waveguide circuit, a chip substrate, and a chip. Background Art

[0003] Superconducting quantum chips have attracted widespread attention due to their scalability to large numbers of qubits. Qubits, like classical bits, are the smallest unit of computer operation. The greater the number of bits, the greater the computer's performance. Superconducting qubits require corresponding control wires and superconducting resonant cavities to operate in conjunction. These control wires and superconducting resonant cavities are essentially coplanar waveguide circuits.

[0004] In current chip structures, coplanar waveguide circuits are distributed on one side of the substrate, limiting the number of coplanar waveguide circuits that can be mounted on a single chip. Therefore, consideration is being given to evolving chip structures from single-sided circuits to double-sided circuits, or even stacking multiple chips (multi-layer stacks). Double-sided and multi-layer stacked quantum chips rely on vias to connect the coplanar waveguide circuits on the upper and lower surfaces of the substrate.

[0005] Further research is needed on the preparation method of double-sided coplanar waveguide circuits.

[0006] Summary of the Invention

[0007] The present invention provides a method for manufacturing a coplanar waveguide circuit, a chip substrate, and a chip, which can improve the efficiency of manufacturing the coplanar waveguide circuit. The technical solution is as follows:

[0008] According to one aspect of an embodiment of the present application, a method for preparing a coplanar waveguide circuit is provided, the method comprising:

[0009] forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate;

[0010] Based on the at least one first through hole on the first material layer, etching the substrate to form at least one second through hole on the substrate, wherein the second material layer is used as a stop layer for etching the substrate;

[0011] Etching the first material layer to remove a portion corresponding to the conductor pattern of the first coplanar waveguide circuit to obtain an etched first material layer;

[0012] Etching the second material layer to remove a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer;

[0013] Depositing a conductor material on the first side of the substrate with the etched first material layer, the second side of the substrate with the etched second material layer, and the at least one second through hole on the substrate;

[0014] The etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit, wherein the first coplanar waveguide circuit is formed on the first surface, the second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through the conductor material at the at least one second through hole.

[0015] According to one aspect of an embodiment of the present application, a chip substrate is provided, on which a coplanar waveguide circuit is provided. The coplanar waveguide circuit is prepared using the above-mentioned method for preparing a coplanar waveguide circuit.

[0016] According to one aspect of an embodiment of the present application, a chip is provided, wherein a coplanar waveguide circuit is provided on a substrate of the chip, and the coplanar waveguide circuit is prepared using the above-mentioned method for preparing a coplanar waveguide circuit.

[0017] According to one aspect of an embodiment of the present application, a computer device is provided, wherein the computer device is used to prepare the above-mentioned method for preparing a coplanar waveguide circuit.

[0018] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned method for preparing a coplanar waveguide circuit.

[0019] According to one aspect of an embodiment of the present application, a computer program product is provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the above-described method for fabricating a coplanar waveguide circuit.

[0020] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0021] On the one hand, the technical solution proposed in the embodiments of the present application solves the problem of preparing double-sided coplanar waveguide circuits. On the other hand, when preparing the coplanar waveguide circuit, the embodiments of the present application first etch the areas where the conductor material needs to be deposited, and then deposit the conductor material, so that the circuits on both sides of the substrate can be formed at one time, simplifying the preparation process and improving preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of a coplanar waveguide circuit provided by one embodiment of the present application;

[0023] FIG2 is a schematic diagram of a deep hole preparation method in the related art;

[0024] FIG3 is a front side circuit preparation method in the related art;

[0025] FIG4 is a method for preparing a back side circuit in the related art;

[0026] FIG5 is a schematic diagram of the edge glue effect in the related art;

[0027] FIG6 is a flow chart of a method for preparing a coplanar waveguide circuit according to an embodiment of the present application;

[0028] FIG7 is a block diagram of a method for manufacturing a coplanar waveguide circuit according to an embodiment of the present application;

[0029] FIG8 is a schematic diagram of a method for preparing a coplanar waveguide circuit according to an embodiment of the present application;

[0030] FIG9 is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0032] Cloud technology refers to a hosting technology that unifies hardware, software, network and other resources within a wide area network or local area network to achieve data computing, storage, processing and sharing.

[0033] Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, and application technology based on the cloud computing business model. It can form a resource pool for on-demand, flexible and convenient use. Cloud computing technology will become a key support. Backend services for technical network systems, such as video websites, image websites, and more portals, require extensive computing and storage resources. With the rapid development and application of the internet industry, every item will likely have its own unique identification, requiring transmission to backend systems for logical processing. Different levels of data will be processed separately, and data from various industries will require strong system support, which can be achieved through cloud computing.

[0034] Cloud technology involves fundamental technologies such as cloud computing, cloud storage, databases, and big data. Cloud applications based on cloud technology include medical cloud, cloud IoT, cloud security, cloud calling, private cloud, public cloud, hybrid cloud, cloud gaming, cloud education, cloud conferencing, cloud social networking, and artificial intelligence cloud services. With the development of cloud technology and its application in various fields, more and more cloud applications will emerge.

[0035] Generally speaking, a system built based on cloud technology includes a server and a terminal. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, etc., but is not limited to this. The terminal and the server can be directly or indirectly connected by wired or wireless communication, which is not limited in this application.

[0036] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is considered a quantum computer. The main characteristics of quantum computers include high speed, strong information processing capabilities, and a wide range of applications. Compared to classical computers, the greater the amount of information they can process, the more advantageous it is for quantum computers to perform calculations, and the greater the accuracy of these calculations.

[0037] Quantum chips are the core components of quantum computers. Quantum chips integrate quantum circuits onto a substrate, thereby carrying the function of quantum information processing. Drawing inspiration from the development of traditional computers, after overcoming technical bottlenecks, quantum computer research must move towards integration to achieve commercialization and industrial upgrading. Superconducting systems, semiconductor quantum dot systems, micro-nanophotonic systems, and even atomic and ion systems are all aiming for chip integration. From a development perspective, superconducting quantum chip systems are technologically ahead of other physical systems. Traditional semiconductor quantum dot systems are also a target of research, as the traditional semiconductor industry is already well-developed. For example, if semiconductor quantum chips surpass the threshold for fault-tolerant quantum computing in terms of decoherence time and control accuracy, they have the potential to integrate existing achievements of the traditional semiconductor industry and reduce development costs.

[0038] Given the advantages of quantum computers, quantum computers can be used in future cloud-based systems to perform some processing and calculations to provide better services.

[0039] The present invention provides a method for fabricating a coplanar waveguide circuit, a chip substrate, and a chip. The coplanar waveguide circuit fabricated using the methods provided in the present invention can be used on the substrate of a quantum chip, thereby producing a chip substrate and quantum chip of higher quality. The following describes the technical solution of the present invention through several embodiments.

[0040] Before introducing the technical solutions of this application, some of the terms involved in this application are explained. The following related explanations can be combined with the technical solutions of the embodiments of this application as optional solutions, and they all fall within the scope of protection of the embodiments of this application. The embodiments of this application include at least part of the following contents.

[0041] Coplanar waveguide circuit: consists of a central conductor and semi-infinite ground planes on both sides.

[0042] Hard mask: Photoresist is usually used to define the graphic shape as a mask for etching the underlying circuit. Materials such as SiO2 can also be used as a graphic definition layer to etch the underlying circuit. In this case, the SiO2 layer is called a hard mask.

[0043] Deep silicon via (TSV): A small hole of a certain depth is etched on the silicon wafer through an etching process.

[0044] Lift off: The process in which the underlying dielectric is dissolved in a solution and the film layer above the dielectric is also removed from the substrate.

[0045] Step coverage: When a thin film is grown on the sidewall of a deep hole, the ratio of the thickness of the film at the bottom of the deep hole to the thickness of the film at the hole opening is used.

[0046] The ratio of depth to width: the ratio of the depth and width of a deep hole.

[0047] Superconducting: Below a certain characteristic temperature, the resistance of the material suddenly drops to 0, and it has complete anti-magnetism.

[0048] Superconducting circuits: Circuit structures made of superconducting materials in superconducting quantum chips.

[0049] Ion milling: Bombarding the surface of a material with an ion beam in a certain direction to remove the oxide layer on the surface of the material.

[0050] In situ: Multiple steps are performed in a single vacuum chamber or multiple interconnected vacuum chambers without being exposed to the atmosphere.

[0051] Parasitic junction: A non-target Josephson junction caused by chip manufacturing process, usually caused by manufacturing process defects.

[0052] Before explaining the embodiments of the present application, a coplanar waveguide circuit and a method for preparing the coplanar waveguide circuit in the related art are first explained.

[0053] Please refer to Figure 1, which shows a schematic diagram of a coplanar waveguide circuit. Sub-figure (a) of Figure 1 shows a three-dimensional view of the coplanar waveguide circuit. On one surface of a substrate 30 (the surface of the substrate 30 shown facing upward in the figure), there is a central conductor 20 and two conductor planes 10 on either side. The central conductor 20 and the two conductor planes 10 form a coplanar waveguide circuit. Sub-figure (b) of Figure 1 shows a top view of a possible coplanar waveguide circuit. The central conductor 50 and the two conductor planes 40 form a coplanar waveguide circuit. In some embodiments, the two conductor planes can also be referred to as semi-infinite ground planes. In some embodiments, the central conductor is separated from the conductor planes, and microwave signals propagate in the central conductor. In some embodiments, a superconducting thin film (such as titanium nitride TiN) is used as the central conductor and ground plane. The superconducting thin film between the central conductor and the ground is removed through photolithography and etching processes to form the superconducting circuit. As the number of qubits increases, the number of coplanar waveguide circuits required also increases exponentially, making the wiring of multi-qubit superconducting quantum chips a major challenge. In current chip structures, the coplanar waveguide circuits are distributed on one side of the substrate, limiting the number of coplanar waveguide circuits that can be mounted on a single chip. Therefore, the issue of limited coplanar waveguide circuits on a single chip can be addressed by evolving the chip structure from single-sided circuits to double-sided circuits, or even stacking multiple chips (multi-layer stacking). Alternatively, double-sided circuits rely on vias to connect the coplanar waveguide circuits on the upper and lower surfaces of the substrate. In multi-layer stacked quantum chips, solder joints can be used to connect the coplanar waveguide circuits between different chips.

[0054] Prior to the present examples, there was no technical solution for fabricating superconducting quantum chips that involved first creating TiN vias and then forming coplanar waveguide circuits. The prior art approach involved first creating blind vias in a silicon substrate, then fabricating the front-side circuits. Thinning and polishing the backside of the silicon substrate exposed the vias, and finally fabricating the backside circuits. The following examples describe this fabrication approach in detail. For ease of presentation, the process flow is presented using side cross-sectional views.

[0055] Please refer to Figure 2, which shows a schematic diagram of a deep hole preparation method in the related art. Prepare a silicon wafer substrate 200 with a thickness of 500um, and spin-coat a thick photoresist, as shown in Figure (1) in Figure 2. In some embodiments, the photoresist is AZ4620, the spin-coating parameters are 1000rpm, and the spin-coating is 40s to obtain a photoresist layer 210, as shown in Figure (2) in Figure 2. Optionally, the thickness of the photoresist layer 210 is 13um AZ4620. In some embodiments, after spin-coating the photoresist, a UV exposure device is used to expose the small hole portion to be exposed. Optionally, a mask plate 220 is covered above the photoresist layer 210, and the photoresist layer 210 is exposed through the mask plate 220, as shown in Figure (3) in Figure 2. The exposed photoresist layer is developed so that the exposed small hole area 230 exposes the silicon substrate, as shown in Figure (4) in Figure 2. In some embodiments, the small hole diameter is 10um. Through deep silicon etching equipment, C4F8 gas and SF6 gas are circulated and alternately introduced into the cavity to etch deep holes 240 with a depth greater than 200 μm, as shown in Figure 2 (5). The C4F8 acts as a passivation agent, preventing the portion of the deep hole near the surface from being further etched by the SF6 etching gas, thereby forming a deep hole with steep sidewalls. SF6 gas can chemically react with silicon to etch small holes of a certain depth.

[0056] In some embodiments, the pattern needs to be defined by a photomask (also called a mask) in the photolithography process. The photomask has a shape that controls whether light can pass through or not, so that the photoresist at the corresponding position is exposed or not, and then the pattern corresponding to the photomask can be obtained by developing. Optionally, the properties of the photoresist in the exposed area change and become soluble in a developer. Therefore, after photolithography development, a pinhole area can be exposed on the silicon substrate. Further, a deep silicon etching device is used to perform deep silicon etching on the pinhole area to obtain a deep hole.

[0057] Please refer to FIG3 , which shows a schematic diagram of a front-side circuit preparation method in the related art.

[0058] After the deep hole (blind hole) is prepared in the embodiment of Figure 2, the remaining photoresist is removed with a degumming solution to obtain a silicon substrate with a blind hole, as shown in Figure (1) in Figure 3. A TiN film 300 is grown on the front surface of the silicon wafer and the side wall of the deep hole by an atomic layer deposition (ALD) device, as shown in Figure (2) in Figure 3. The atomic layer deposition method is selected because atomic layer deposition has a high step coverage rate and can grow a thin film at the bottom and side wall of the deep hole, which is suitable for high aspect ratio structures. In some embodiments, the atomic layer deposition growth mode is plasma enhanced atomic layer deposition (PEALD). In this growth mode, the film growth is directional, and the TiN film 310 is mainly formed on the front surface of the substrate and the side wall of the deep hole, as shown in Figure (3) in Figure 3. Since plasma enhanced atomic layer deposition is directional and is deposited from the front of the substrate toward the back of the substrate when preparing the front circuit, it is difficult to deposit on the back of the substrate. And because the back of the substrate may be blocked (there is a chassis supporting the substrate), it is difficult for TiN to grow on it. In some embodiments, the precursor sources for atomic layer deposition are TiCl4 and NH3. At a growth temperature of 450°C, TiCl4 gas and NH3 plasma are cyclically introduced alternately. After each introduction of the precursor source, N2 is purged to remove excess precursor source. By utilizing the self-limiting nature of the precursor source (no more adhesion growth after a full layer is covered) and the chemical reaction of TiCl4 and NH3, a 100nm thick TiN superconducting film can be grown. Then, a layer of photoresist is spin-coated on the front side of the substrate to obtain a photoresist layer 310. In some embodiments, the photoresist includes but is not limited to s1805 and AZ6112, and the photoresist thickness can be selected to be 1um. The front coplanar waveguide circuit is exposed using a UV exposure device. Optionally, a mask plate 320 is covered on top of the photoresist layer 310, as shown in Figure (4) in Figure 3, and the photoresist layer 310 is photoetched through the mask plate 320 to obtain an exposed photoresist layer 330. The exposed photoresist layer 330 is then developed, and the front TiN 340 to be etched is exposed, as shown in Figure (5) in Figure 3. In some embodiments, after exposure, the mask plate is removed and then developed. The photoresist at the position corresponding to the mask opening is removed by the developer to form a pattern with the same shape as the mask opening. The exposed front TiN 340 is then etched by a dry etching device to form a front coplanar waveguide circuit, as shown in Figure (6) in Figure 3. In some embodiments, the dry etching scheme is to use BCl3 and Cl2 as etching gases to etch TiN.

[0059] Please refer to FIG4 , which shows a schematic diagram of a method for preparing a back side circuit in the related art.

[0060] The substrate 400 with the front circuit prepared is thinned and polished from the back to a thickness of 200um by a thinning machine and a polishing machine, so that a through hole 410 is exposed on the back of the substrate, as shown in Figure (1) in Figure 4. Next, a superconducting film needs to be deposited on the back of the silicon substrate to prepare the back coplanar waveguide circuit. Since the TiN in the deep hole has been exposed to the atmosphere when it is taken out of the atomic layer deposition equipment, an oxide layer will be formed on the surface. The non-superconducting contact will affect the transmission properties of the coplanar waveguide circuit. Therefore, before evaporating the back superconducting film, the oxidized TiN in the through hole 410 needs to be removed by ion milling, as shown in Figure (2) in Figure 4. In some embodiments, the substrate is bombarded with 7sccm of Ar ions for 5 minutes in a 1E-4torr vacuum environment. Then, a 100nm thick superconducting film 420 is grown in situ, as shown in Figure (3) in Figure 4. The superconducting film can be a superconducting metal such as TiN or Al, and the growth method can be electron beam evaporation, magnetron sputtering, etc. Since the TiN oxide layer at the deep hole connection has been removed and the back superconducting film is grown in situ, the two can form a good superconducting contact. After the back film is plated, the substrate is removed and a layer of photoresist is spin-coated on the back to obtain a photoresist layer 430, as shown in Figure (4) in Figure 4. Similarly, the optional photoresists include s1805, AZ6112, etc., and the photoresist thickness can be selected to be 1um. The back coplanar waveguide circuit is exposed using a UV exposure device, as shown in Figure (5) in Figure 4. Optionally, a mask plate 440 is covered on the top of the photoresist layer 430, and the photoresist layer 430 is photoetched through the mask plate 440 to obtain the exposed photoresist layer 450. The exposed photoresist layer 450 is then developed, and the back superconducting film 460 to be etched is exposed, as shown in Figure 4 (6). The exposed back superconducting film 460 is then etched away by dry etching or wet etching (depending on the back superconducting film material, as shown in Figure 4 (7). If the back superconducting film material is TiN, BCl3 and Cl2 can be used to dry etch TiN; if the back superconducting film material is Al, Al etching solution can be used to etch the back circuit), forming a back coplanar waveguide circuit. Finally, the degumming solution is used to remove the glue, and the front and back coplanar waveguide circuits can be obtained, as shown in Figure 4 (8). The circuits on the front and back sides of the substrate are electrically connected through deep holes.

[0061] The preparation of double-sided TiN coplanar waveguide circuits in the above-mentioned related technologies has the following difficulties:

[0062] 1. The process sequence is fixed, and deep holes need to be prepared first, and then the front and back coplanar waveguide circuits are prepared. Superconducting thin films need to be evaporated on the sidewalls of the through-holes to achieve connectivity between the circuits on the front and back sides of the chip. Since the through-holes on the chip have a high aspect ratio (hole depth: hole diameter = 200um: 10um = 20:1), atomic layer deposition is required to achieve thin film growth with high step coverage. If the front and back circuits are prepared first, and then deep hole etching and filling are performed, the previously prepared front and back coplanar waveguide circuits need to be protected when the deep holes are filled (usually with photoresist). The substrate temperature required for atomic layer deposition to grow TiN is generally very high (>300°C), and photoresist can hardly withstand high temperatures. Therefore, deep holes need to be prepared and filled before the front and back circuits can be prepared. The photoresist-based stripping process is also difficult to use with the atomic layer deposition coating process.

[0063] 2. Based on difficulty 1, the front and back circuits need to be prepared after the thin film is evaporated on the side walls of the through-hole. Otherwise, the prepared circuit structure will be difficult to be protected by photoresist during the atomic layer deposition coating step. When preparing the front and back side circuits, due to the presence of holes, after spin coating the photoresist, there will be areas at the edges of the holes that are not covered by the photoresist (or the photoresist is uneven). As shown in sub-figure (a) of Figure 5, there is uneven photoresist at the edges of the six holes in sub-figure (a), and the position of the photoresist at the edges of the holes is related to the height of the subsequent etching, which leads to the failure of the subsequent etching steps (as shown in sub-figure (b) of Figure 5, 500 is the TiN film, 520 is the small hole, there is a circle of brighter parts around the small hole, and 510 is the exposed substrate. This part should originally be the TiN film retained, so that the two adjacent small holes can be connected through the TiN film, but due to the edge glue effect caused by the small hole, there is an area around the small hole that is not covered by the photoresist. Therefore, in the process of etching the coplanar waveguide circuit, there is a circle of etched area around the small hole, resulting in the two adjacent small holes that should be connected to each other cannot be connected). The edge glue effect is particularly significant in the case of through-holes, because during the process of spin-coating photoresist, the vacuum adsorption of the base will cause the photoresist to be adsorbed to the other side of the substrate along the through-hole, exacerbating the unevenness of the photoresist. In some embodiments, when spin-coating photoresist, the glue is dripped onto the substrate, and the substrate is adsorbed on the suction cup by vacuum, and the suction cup is connected to the motor and can rotate at high speed. Generally, the substrate is flat and the photoresist is relatively uniform. However, due to the presence of small holes, it is difficult to obtain uniform photoresist by spin coating in engineering. The photoresist at the edge of the hole will be thicker than the photoresist in other areas due to surface tension. During photolithography, the gap between the mask and the photoresist surface is very small. The photoresist at the edge of the hole can easily stick to the mask and be torn off. After exposure, there will be an area at the edge of the hole that is not covered by photoresist.

[0064] 3. When preparing the back-side circuit, due to the presence of through-holes, the efficiency of vacuum adsorption during the glue spreading process will be weakened, increasing the risk of the substrate being thrown out and broken.

[0065] 4. When preparing the backside pattern, the frontside pattern needs to be protected (Figure 4 shows the case where the frontside pattern is not protected). This also requires that the frontside pattern not be damaged during the coating, development, and etching processes. This places greater restrictions on the selection of frontside and backside superconducting film materials and processing technology.

[0066] 5. The solution using the above-mentioned related technologies requires coating both the front and back sides separately. When coating the back side, in order to ensure good superconducting contact between the back film and the through-hole sidewall film, the through-hole sidewall film needs to be ion milled in situ before the back coating to remove the oxide layer of the through-hole sidewall film. This requires the coating equipment itself to have an ion milling function, and because the hole has a high aspect ratio, it is difficult to ensure that all oxide layers in the through-hole sidewall are completely removed. If there is an oxide layer that has not been completely etched between the back-plated layer and the through-hole sidewall film layer, a parasitic junction will exist, thereby affecting the performance of the quantum chip.

[0067] 6. Based on difficulty 5, ion milling before back-side coating will indiscriminately bombard the back-side substrate with ions, which may cause the atomic arrangement at the entire back-side substrate interface to be destroyed, affecting chip performance.

[0068] The technical solution provided by the embodiments of this application achieves film coverage of the front, back, and sidewalls of the through-holes in a single coating, naturally forming an ideal superconducting contact. This eliminates the need for ion milling and does not damage the substrate, effectively reducing process steps and making the coating equipment more user-friendly. Therefore, the technical solution provided by the embodiments of this application improves the efficiency of fabricating through-hole coplanar waveguide circuits.

[0069] Please refer to Figure 6, which shows a flow chart of a method for preparing a coplanar waveguide circuit according to an embodiment of the present application. The execution body of each step of the method can be a coplanar waveguide circuit preparation device. The method can include at least one of the following steps (610-660):

[0070] In step 610 , a first material layer is formed on a first surface of a substrate, and a second material layer is formed on a second surface of the substrate.

[0071] The substrate in the embodiments of the present application is the substrate of the coplanar waveguide circuit, which can also be considered as the substrate of the chip. The specific material of the substrate is not limited in this application. In some embodiments, the substrate is an insulating material. Optionally, the substrate is made of silicon, in which case the substrate is also referred to as a silicon substrate.

[0072] In some embodiments, the shape of the substrate surface is circular. Optionally, the two planes with the largest areas in the substrate are respectively used as the front and back (reverse) sides of the substrate. Optionally, the front and back sides of the substrate are two opposite sides. In some embodiments, the front and back sides of the substrate are the same in area.

[0073] In some embodiments, the first side of the substrate and the second side of the substrate are two opposing sides of the substrate. In some embodiments, the first side of the substrate is the front side of the substrate, and the second side of the substrate is the back side of the substrate. In some embodiments, the second side of the substrate is the front side of the substrate, or the first side of the substrate is the back side of the substrate. This application is not limited to this.

[0074] In some embodiments, the first material layer is a hard mask layer. Optionally, the first material layer is used to expose the first through hole and the conductor pattern of the first coplanar waveguide circuit on the substrate. In some embodiments, the first material layer is also a non-conductive material. Optionally, the first material layer is SiO2.

[0075] In some embodiments, the second material layer is a hard mask layer. Optionally, the second material layer is used to expose a conductor pattern of the second coplanar waveguide circuit on the substrate. Optionally, the second material layer is SiO2.

[0076] The embodiments of the present application do not limit the method of forming the first material layer and the second material layer on the substrate. The method of forming the material layer includes but is not limited to oxidation, electroplating, covering, etc.

[0077] In some embodiments, a first material layer including a first through-hole is directly formed on the first surface of the substrate, and a portion of the substrate may be exposed based on the first through-hole.

[0078] In some embodiments, a photoresist layer is formed on the first surface of the substrate. A mask is placed over the photoresist layer to shield portions other than a through-hole region where at least one first through-hole is located. The photoresist layer is photolithographically processed through the mask to obtain an exposed photoresist layer. The exposed photoresist layer is then developed to expose the through-hole region on the first surface of the substrate. A first material layer is formed on the other regions of the first surface of the substrate except the through-hole region to obtain a first material layer including the first through-hole.

[0079] In some embodiments, after forming a first material layer on the first surface of the substrate, at least one first through hole is formed in the first material layer, and a portion of the substrate may be exposed based on the first through hole.

[0080] In some embodiments, a first through-hole refers to a hole punched through the first material layer, the hole extending through the first material layer. The embodiments of the present application do not limit the method for forming the first through-hole in the first material layer. Optionally, the first through-hole is formed in the first material layer using a drilling device. Optionally, the first through-hole is formed in the first material layer using a photolithography development method. Optionally, a through-hole mold is attached to the first material layer and removed, thereby forming at least one first through-hole in the first material layer.

[0081] Step 620 , etching the substrate based on the at least one first through hole on the first material layer to form at least one second through hole on the substrate, wherein the second material layer is used as a stop layer for etching the substrate.

[0082] In some embodiments, after forming at least one first through hole in the first material layer to expose the substrate, the substrate is etched at the exposed position. Optionally, the substrate is etched through to form at least one second through hole.

[0083] In some embodiments, a through-hole etching device is used to etch a substrate based on at least one first through-hole in a first material layer, thereby forming at least one second through-hole in the substrate. Optionally, the through-hole etching device stops etching upon detecting the second material layer on the second side of the substrate. The through-hole etching device is a device used to etch through-holes. Any device that can be used to etch through-holes is included within the scope of protection of the embodiments of this application.

[0084] In some embodiments, the first through hole and the second through hole have the same or different diameters. Optionally, the first through hole and the second through hole have the same diameter, and the centerline of the first through hole and the centerline of the second through hole are aligned. Optionally, the first through hole and the second through hole are adjacent. This application does not limit the specific location and size of the first through hole and the second through hole.

[0085] The etching in the embodiments of the present application may be chemical etching or physical etching, which is not limited in the present application.

[0086] In the embodiments of the present application, a second material layer is used as a stop layer for deep hole etching (through hole etching), which can effectively protect the support plate (understood as the device that supports the silicon substrate) below the substrate from damage, thereby reducing the production cost. In addition, because the second material layer is used as the stop layer, the through hole can be directly etched in one step, without the need for thinning and polishing the back surface to obtain a through hole that completely penetrates the substrate as in the related art. Therefore, the technical solution provided by the embodiments of the present application can achieve one-time production of the through hole, reducing the production cost, reducing the number of production steps, and improving the production efficiency.

[0087] Step 630 , etching the first material layer to remove a portion corresponding to the conductor pattern of the first coplanar waveguide circuit, thereby obtaining an etched first material layer.

[0088] Unlike the related art method of first coating a metal film and then etching away the areas where the metal film is not needed, the embodiments of the present application etch away the areas where the conductive material is to be plated. Specifically, the first material layer is etched away, and the first material layer is etched away at all locations on the first surface of the substrate corresponding to the areas where the conductive material is to be plated. In other words, the first material layer after etching corresponds to locations on the substrate where the conductive material is not to be plated.

[0089] In some embodiments, the first coplanar waveguide circuit represents a circuit to be laid out on the first surface of the substrate. Optionally, the circuit on the first surface of the substrate is composed of a plurality of coplanar waveguide circuits. Optionally, the plurality of coplanar waveguide circuits constitute the above-mentioned first coplanar waveguide circuit. Of course, in addition to circuits such as coplanar waveguide circuits, other circuits designed on the substrate can also be prepared using the technical solutions provided in the embodiments of the present application, and the present application does not limit this. Optionally, the conductor pattern of the first coplanar waveguide circuit refers to the area on the first surface of the substrate where the conductor corresponding to the circuit to be laid out is located. The first material layer after etching is obtained by etching away the portion corresponding to the conductor pattern of the first coplanar waveguide circuit in the first material layer. That is, the substrate area exposed by the etched first material layer is the area for plating the conductor material.

[0090] Likewise, the etching here may be physical etching or chemical etching, which is not limited in this application.

[0091] In some embodiments, the second through-hole is located at the center conductor of the coplanar waveguide circuit. Optionally, the second through-hole can also be located at the ground planes on both sides of the center conductor of the coplanar waveguide circuit. Optionally, the center conductor of the coplanar waveguide circuit of the front circuit is connected to the center conductor of the coplanar waveguide circuit on the back side through the second through-hole. Optionally, the center conductor of the coplanar waveguide circuit of the front circuit is connected to the center conductor of the coplanar waveguide circuit on the back side through the second through-hole, and the ground planes on both sides of the center conductor of the coplanar waveguide circuit of the front circuit are connected to the ground planes on both sides of the center conductor of the coplanar waveguide circuit on the back side through the second through-hole, and after the conductor material is deposited, the connection between the front and back circuits is achieved.

[0092] Step 640 , etching the second material layer to remove a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer.

[0093] In some embodiments, the second material layer is etched to remove all locations on the second surface of the substrate corresponding to locations where the conductive material is to be plated. That is, the locations on the substrate where the second material layer is etched correspond to locations where the conductive material is not to be plated.

[0094] In some embodiments, the second coplanar waveguide circuit represents a circuit to be laid out on the second surface of the substrate. Optionally, the circuit on the second surface of the substrate is composed of a plurality of coplanar waveguide circuits. Optionally, the plurality of coplanar waveguide circuits constitute the above-mentioned second coplanar waveguide circuit. Of course, in addition to circuits such as coplanar waveguide circuits, other circuits designed on the substrate can also be prepared using the technical solutions provided in the embodiments of the present application, and the present application does not limit this. Optionally, the conductor pattern of the second coplanar waveguide circuit refers to the area where the conductor corresponding to the circuit to be laid out on the second surface of the substrate is located. The etched second material layer is obtained by etching away the portion corresponding to the conductor pattern of the second coplanar waveguide circuit in the second material layer. That is, the substrate area exposed by the etched second material layer is the area for plating the conductor material. Optionally, the circuit laid out on the front and the circuit laid out on the back can be the same or different.

[0095] Likewise, the etching here may be physical etching or chemical etching, which is not limited in this application.

[0096] Step 650 : depositing a conductor material on the first side of the substrate with the etched first material layer, the second side of the substrate with the etched second material layer, and at least one second through hole on the substrate.

[0097] In the embodiment of the present application, a conductor material is deposited on the first surface of the substrate with the etched first material layer and the second surface with the etched second material layer, as well as at least one second through hole on the substrate, so that while the front and back circuits are prepared at one time, the circuits on the front and back sides of the substrate are connected through the conductor material at the second through hole. This is different from the preparation method of the coplanar waveguide circuit in the related art. In the related art, the front circuit and the unopened through hole are first plated with a metal film, and the front metal film is etched to obtain the front circuit. The back side is then thinned and polished to open the hole. At this time, an ion milling process is required to remove the layer on the surface of the metal film, and then the metal film is plated on the back side again. That is, in the related art, not only is it necessary to plate the metal film twice, but also at least one ion milling process is required. Therefore, the preparation process of the related art is relatively complicated. The technical solution provided in the embodiment of the present application directly deposits the conductor material once, without the need for two film plating processes, and therefore no ion milling process is required. Similarly, the preparation steps are reduced and the preparation efficiency is improved.

[0098] Conductor material refers to the material required for circuit layout. The present embodiments do not limit the specific material of the conductor material; any material that can ensure the normal operation of the circuit is included within the scope of protection of the present embodiments. In other embodiments, semiconductor materials can also be used as deposition objects for circuit preparation. In some embodiments, the conductor material is titanium nitride.

[0099] In some embodiments, depositing the conductive material can be understood as plating the conductive material on the first surface having the etched first material layer, the second surface having the etched second material layer, and at least one second through hole on the substrate. The embodiments of the present application do not limit the specific method of depositing the conductive material or the method of plating the conductive material.

[0100] In some embodiments, a conductive material is deposited on a sidewall / inner wall of the at least one second through-hole on the substrate.

[0101] Step 660: Remove the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit, wherein a first coplanar waveguide circuit is formed on the first surface, a second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through the conductor material at at least one second through hole.

[0102] In some embodiments, after depositing the conductor material, after removing the etched first material layer and the etched second material layer, the substrate and the conductor material deposited on the first side, the second side and the second through hole of the substrate are retained, that is, a substrate with front and back side circuits is obtained, and the front and back side circuits are connected. Optionally, the etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit.

[0103] In some embodiments, after the conductor material is deposited, the etched first material layer and the etched second material layer can be considered impurities that need to be removed. After all impurities on the substrate surface are removed, a substrate with a coplanar waveguide circuit is obtained. After the conductor material is deposited, the etched first material layer is removed, leaving the substrate, the first surface of the substrate, and the conductor material deposited at the second through-hole, thereby forming a first coplanar waveguide circuit on the first surface of the substrate. Furthermore, after the conductor material is deposited, the etched second material layer is removed, leaving the substrate, the second surface of the substrate, and the conductor material deposited at the second through-hole, thereby forming a second coplanar waveguide circuit on the second surface of the substrate. Because the first coplanar waveguide circuit and the second coplanar waveguide circuit are connected, a substrate with a coplanar waveguide circuit is obtained.

[0104] The embodiments of this application do not limit the method for removing impurities. Impurities can be removed chemically or physically. All combinations of impurity removal methods used in circuit fabrication with other steps of this solution should be included in the scope of protection of the embodiments of this application.

[0105] The technical solution provided in the embodiment of the present application, when preparing a coplanar waveguide circuit, first etches the area where the conductor material needs to be deposited, and then deposits the conductor material, so that the circuits on both sides of the substrate can be formed at one time, which greatly simplifies the preparation process.

[0106] The following are specific examples of steps 610 to 660. It should be noted that all steps mentioned in the embodiments of the present application can be freely combined to form new embodiments. All possible embodiments formed by combinations also fall within the scope of protection of the present application, and the present application does not limit the combination method.

[0107] In some embodiments, the above step 610 also includes the following step 611 or step 612.

[0108] In step 611 , the first surface of the substrate is oxidized to form a first material layer, and the second surface of the substrate is oxidized to form a second material layer.

[0109] In some embodiments, the substrate is a silicon substrate, and the first surface of the substrate is oxidized to obtain silicon dioxide. In this case, the first material layer is a silicon dioxide layer. In some embodiments, the oxidation is performed by thermal oxidation.

[0110] In some embodiments, the substrate is a silicon substrate, and the second surface of the substrate is oxidized to obtain silicon dioxide. In this case, the second material layer is a silicon dioxide layer. In some embodiments, the oxidation process is thermal oxidation.

[0111] In some embodiments, thermal oxidation is performed simultaneously on the first and second surfaces of the substrate to form the first material layer and the second material layer. Optionally, due to the non-directional nature of thermal oxidation, the first material layer and the second material layer can be formed by thermally oxidizing the substrate once, without the need for two oxidations.

[0112] In step 612 , a first material is plated on the first surface of the substrate to form a first material layer, and a second material is plated on the second surface of the substrate to form a second material layer.

[0113] In some embodiments, the substrate is a silicon substrate, and the first material layer is a silicon dioxide layer. Silicon dioxide is directly deposited on the first surface of the silicon substrate to obtain the silicon dioxide layer. In some embodiments, silicon dioxide is deposited on the first surface of the silicon substrate using chemical vapor deposition (CVD) to obtain the silicon dioxide layer.

[0114] In some embodiments, the substrate is a silicon substrate, and the second material layer is a silicon dioxide layer. Silicon dioxide is directly plated onto the second surface of the silicon substrate to form the silicon dioxide layer. In some embodiments, silicon dioxide is plated onto the second surface of the silicon substrate using CVD evaporation to form the silicon dioxide layer. Electroplating is a simple and easy method for forming the material layer, which can improve the efficiency of forming the material layer.

[0115] Alternatively, the first surface of the substrate may be oxidized to form a first material layer, and the second surface of the substrate may be plated with a second material to form a second material layer. Alternatively, the first surface of the substrate may be plated with the first material to form a first material layer, and the second surface of the substrate may be oxidized to form a second material layer.

[0116] The following is a specific example of forming at least one first through hole in the first material layer after forming the first material layer on the first surface of the substrate. In some embodiments, forming at least one first through hole in the first material layer includes at least one of the following steps S1 to S5.

[0117] Step S1: forming a first photoresist layer on the first material layer.

[0118] In some embodiments, a photoresist is applied to the first material layer. The present embodiment of the present application does not limit the method for forming the first photoresist layer on the first material layer. Alternatively, the first photoresist layer is formed on the first material layer by spin coating the photoresist. Alternatively, the first photoresist layer is formed on the first material layer by spray coating the photoresist. Alternatively, the first photoresist layer is formed on the first material layer by thick coating the photoresist.

[0119] The embodiments of the present application do not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the first photoresist layer. Optionally, the type of photoresist includes but is not limited to S1805 and AZ6112. In addition, the thickness of the first photoresist layer is also not limited in this application. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000 rpm for 30 seconds, which results in a 6.3 μm thick first photoresist layer.

[0120] Step S2: Covering the first photoresist layer with a first mask plate, wherein the first mask plate is used to shield other parts except the through-hole region where the at least one first through-hole is located.

[0121] In some embodiments, the first mask is used to block all portions of the substrate except for the through-hole region where the at least one first through-hole is located. Optionally, the first mask is a mask that removes at least one circular hole. Optionally, only the region of the first mask containing at least one of the circular holes is transparent. Optionally, the first mask is pre-prepared and corresponds to the location of the second through-hole to be etched on the substrate.

[0122] Step S3 , performing photolithography on the first photoresist layer through a first mask to obtain an exposed first photoresist layer.

[0123] In some embodiments, ultraviolet light is transmitted through a first mask and the first photoresist layer is photolithographically processed. Alternatively, ultraviolet light is transmitted through a transparent first mask and irradiates the first photoresist layer. The ultraviolet light irradiates the first photoresist layer, causing a chemical reaction. In other words, the exposed first photoresist layer includes unexposed photoresist and exposed photoresist. The exposed photoresist is the photoresist in the area where the first through hole is located.

[0124] Step S4 , developing the exposed first photoresist layer to expose the first through-hole region on the first material layer.

[0125] In some embodiments, the exposed first photoresist layer is developed with a developer. Optionally, the exposed photoresist dissolves in the developer, exposing the through-hole region on the first material layer.

[0126] Step S5 , etching the exposed through-hole region on the first material layer using a first etching gas to form at least one first through-hole on the first material layer.

[0127] The first etching gas is a gas used to etch the first material layer. Optionally, the first etching gas and the first material layer undergo a chemical reaction, thereby achieving etching. In some embodiments, the first etching gas is CF4. In some embodiments, a dry etching device is used to etch the exposed through-hole region of the first material layer, thereby forming at least one first through-hole in the first material layer.

[0128] In some embodiments, step S5 further includes removing the remaining first photoresist layer.

[0129] Through the above steps, the exposed through-hole area on the first material layer is etched to form a first through-hole on the first material layer, exposing part of the substrate, so that the formation of the first through-hole is more accurate, thereby improving the precision of the preparation process.

[0130] In some embodiments, the above step 620 further includes at least one of the following steps 621 to 622.

[0131] Step 621 , etching the through-hole region on the first surface of the substrate using a second etching gas, where the through-hole region refers to a region exposed by at least one first through-hole on the first material layer.

[0132] In some embodiments, the second etching gas is a gas used to etch the substrate. Optionally, the second etching gas and the substrate undergo a chemical reaction to achieve etching. In some embodiments, the second etching gas is SF6 gas.

[0133] Step 622: When the second material layer is detected, the etching is stopped to form at least one second through hole on the substrate.

[0134] In some embodiments, in addition to the second etching gas, a protective gas is also used to protect other parts of the substrate from being etched. Optionally, the protective gas is C4F8. In some embodiments, a deep silicon etching device is used to etch a high-resistance silicon base (substrate) to form a small hole with a high aspect ratio. C4F8 plays a passivation role, so that the part of the deep hole close to the surface is protected from further etching by the SF6 etching gas to form a deep hole with steep side walls. SF6 gas can react chemically with silicon to etch a small hole of a certain depth. Specifically, C4F8 gas and SF6 gas are circulated and alternately introduced into the cavity until the equipment detects that the small hole passes through the entire substrate, that is, the deep silicon etching equipment is equipped with white light detection, which can detect the change of the depth of the small hole over time. When the second material layer on the second side is etched, the etching rate is significantly reduced, and the hole depth changes significantly, and etching is stopped at this time.

[0135] In some embodiments, the above step 630 further includes at least one of the following steps 631 to 635 .

[0136] Step 631: forming a second photoresist layer on the first material layer.

[0137] In some embodiments, a photoresist is applied to the first material layer. The present invention does not limit the method for forming the second photoresist layer on the first material layer. Alternatively, the second photoresist layer may be formed on the first material layer by spin coating the photoresist. Alternatively, the second photoresist layer may be formed on the first material layer by spray coating the photoresist. Alternatively, the second photoresist layer may be formed on the first material layer by thick coating the photoresist.

[0138] The embodiments of the present application do not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the second photoresist layer. Optionally, the type of photoresist includes but is not limited to S1805 and AZ6112. In addition, the thickness of the second photoresist layer is also not limited. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000 rpm for 30 seconds, which results in a 6.3 μm thick second photoresist layer.

[0139] Step 632: Cover the second photoresist layer with a second mask, where the second mask is used to block portions other than portions corresponding to the conductor pattern of the first coplanar waveguide circuit.

[0140] In some embodiments, the second mask is used to block all portions of the substrate except for portions corresponding to the conductor pattern of the first coplanar waveguide circuit. Alternatively, the second mask is configured to remove portions corresponding to the conductor pattern of the first coplanar waveguide circuit. Alternatively, the second mask allows light to pass only through portions corresponding to the conductor pattern of the first coplanar waveguide circuit. Alternatively, the second mask is pre-prepared and corresponds to locations on the substrate where the conductor material is to be deposited.

[0141] Step 633 , performing photolithography on the second photoresist layer through a second mask to obtain an exposed second photoresist layer.

[0142] In some embodiments, ultraviolet light is transmitted through a second mask and the second photoresist layer is photolithographically processed. Alternatively, ultraviolet light is transmitted through a transparent second mask and irradiates the second photoresist layer. The ultraviolet light irradiates the second photoresist layer, causing a chemical reaction. In other words, the exposed second photoresist layer includes unexposed photoresist and exposed photoresist. The exposed photoresist is the portion corresponding to the conductor pattern of the first coplanar waveguide circuit.

[0143] Step 634 , developing the exposed second photoresist layer to expose an area corresponding to the conductor pattern of the first coplanar waveguide circuit on the first material layer.

[0144] In some embodiments, the exposed second photoresist layer is developed with a developer. Optionally, the exposed photoresist dissolves in the developer, exposing an area corresponding to the conductor pattern of the first coplanar waveguide circuit on the first material layer.

[0145] Step 635 , using a third etching gas to etch the exposed area of ​​the first material layer corresponding to the conductor pattern of the first coplanar waveguide circuit to obtain an etched first material layer.

[0146] The third etching gas is used to etch the first material layer. Optionally, the third etching gas reacts chemically with the first material layer to achieve etching. In some embodiments, the third etching gas is CF4. In some embodiments, a dry etching device is used to etch the area of ​​the first material layer corresponding to the exposed conductor pattern of the first coplanar waveguide circuit, thereby exposing the conductor pattern of the first coplanar waveguide circuit on the first material layer.

[0147] In some embodiments, step 635 further includes removing the remaining second photoresist layer.

[0148] The technical solution provided by the embodiment of the present application solves the problem in the related art of reduced vacuum adsorption efficiency during the glue spreading process due to through holes.

[0149] In some embodiments, the above step 640 further includes at least one of the following steps 641 to 645 .

[0150] Step 641: forming a third photoresist layer on the second material layer.

[0151] In some embodiments, a photoresist is applied to the second material layer. The present invention does not limit the method for forming the third photoresist layer on the second material layer. Alternatively, the third photoresist layer may be formed on the second material layer by spin coating the photoresist. Alternatively, the third photoresist layer may be formed on the second material layer by spray coating the photoresist. Alternatively, the third photoresist layer may be formed on the second material layer by thick coating the photoresist.

[0152] The embodiments of the present application do not limit the specific type of photoresist. Optionally, any type of photoresist can be used to form the third photoresist layer. Optionally, the type of photoresist includes but is not limited to s1805 and AZ6112. In addition, the thickness of the third photoresist layer is also not limited. In some embodiments, the photoresist is AZ6130, and a possible spin coating parameter is 1000 rpm for 30 seconds, which results in a 6.3 μm thick third photoresist layer.

[0153] Step 642: Cover the third photoresist layer with a third mask, where the third mask is used to block portions other than portions corresponding to the conductor pattern of the second coplanar waveguide circuit.

[0154] In some embodiments, the third mask is used to block all portions of the substrate except for portions corresponding to the conductor pattern of the second coplanar waveguide circuit. Alternatively, the third mask is configured to remove portions corresponding to the conductor pattern of the second coplanar waveguide circuit. Alternatively, the third mask allows light to pass only through portions corresponding to the conductor pattern of the second coplanar waveguide circuit. Alternatively, the third mask is pre-prepared and corresponds to locations on the substrate where the conductor material is to be deposited.

[0155] Step 643 , performing photolithography on the third photoresist layer through a third mask to obtain an exposed third photoresist layer.

[0156] In some embodiments, ultraviolet light is transmitted through a third mask to perform photolithography on the third photoresist layer. Alternatively, ultraviolet light is transmitted through a transparent third mask to illuminate the third photoresist layer. The ultraviolet light irradiates the third photoresist layer, causing a chemical reaction. In other words, the exposed third photoresist layer includes unexposed photoresist and exposed photoresist. The exposed photoresist is the portion corresponding to the conductor pattern of the second coplanar waveguide circuit.

[0157] Step 644 , developing the exposed third photoresist layer to expose an area corresponding to the conductor pattern of the second coplanar waveguide circuit on the second material layer.

[0158] In some embodiments, the exposed third photoresist layer is developed with a developer. Optionally, the exposed photoresist dissolves in the developer, exposing an area corresponding to the conductor pattern of the second coplanar waveguide circuit on the second material layer.

[0159] Step 645 , using a fourth etching gas to etch the exposed area of ​​the second material layer corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer.

[0160] The fourth etching gas is used to etch the second material layer. Optionally, the fourth etching gas reacts chemically with the second material layer to achieve etching. In some embodiments, the fourth etching gas is CF4. In some embodiments, a dry etching device is used to etch the area of ​​the second material layer corresponding to the exposed conductor pattern of the second coplanar waveguide circuit, thereby exposing the conductor pattern of the second coplanar waveguide circuit on the second material layer.

[0161] In some embodiments, step 645 further includes removing the remaining third photoresist layer.

[0162] In some embodiments, the photoresist types and thicknesses of the first photoresist layer, the second photoresist layer, and the third photoresist layer may be the same or different, which is not limited in this application.

[0163] In some embodiments, when the front and back side circuits are different, the second mask plate and the third mask plate are also different. In some embodiments, when the front and back side circuits are the same, the second mask plate and the third mask plate are also the same.

[0164] In some embodiments, when the first material layer and the second material layer are made of the same material, the first etching gas, the third etching gas, and the fourth etching gas may be the same or different. When the first material layer and the second material layer are made of the same material, the first etching gas, the third etching gas, and the fourth etching gas may be the same or different. Of course, the second etching gas is different from the first etching gas, the third etching gas, and the fourth etching gas.

[0165] The technical solution provided in this embodiment utilizes SiO2 instead of photoresist for TiN stripping to form coplanar waveguide circuits. Compared to etching methods, this effectively avoids etching failures caused by the edge bead effect of the vias. Furthermore, the front and back coplanar waveguide circuits can be formed in one step, significantly reducing the number of process steps and eliminating the need for special protection of the front pattern.

[0166] In some embodiments, the above step 650 also includes the following step 651.

[0167] In step 651 , a conductor material is deposited on the first surface of the substrate with the etched first material layer, the second surface of the substrate with the etched second material layer, and at least one second through hole on the substrate by thermal atomic layer deposition.

[0168] In some embodiments, thermal atomic layer deposition is non-directional, which is different from the plasma atomic deposition in related technologies. Thermal atomic layer deposition is used to deposit conductor material on the surface of a substrate with an etched first material layer and an etched second material layer, as well as at least one second through hole on the substrate, which can achieve better deposition results.

[0169] In some embodiments, the conductor material is titanium nitride. Alternatively, a 100 nm thick TiN film is deposited at 450°C using alternating purges of TiCl4 and NH3. Because thermal atomic layer deposition (TALD) offers extremely high step coverage, TiN is deposited on the second through-hole and on areas on the front and back surfaces of the substrate not covered by SiO2.

[0170] In some embodiments, thermal atomic layer deposition is used to deposit a conductor material on a sidewall / inner wall of the at least one second through hole on the substrate.

[0171] In some embodiments, the above step 660 also includes the following step 661.

[0172] In step 661 , a detergent is used to remove the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit.

[0173] The embodiment of the present application does not limit the specific specifications of the detergent. Any detergent that can react with the first material layer and the second material layer and does not react with the substrate and the conductor material can be used to perform step 661.

[0174] In other embodiments, a detergent and ultrasound are used to remove the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit. The detergent is used to remove the etched first material layer and the etched second material layer, and the ultrasound is used to remove the conductor material deposited on the etched first material layer and the etched second material layer.

[0175] In some embodiments, the substrate is a silicon substrate, the first material layer and the second material layer are silicon dioxide, and the cleaning agent is hydrofluoric acid. Alternatively, the substrate is removed and placed sideways on a cleaning basket. SiO2 is removed using diluted hydrofluoric acid (5% concentration), while TiN on the SiO2 surface is simultaneously stripped using high-power ultrasound (300W, 45kHz). Under the high ultrasonic power, TiN on the SiO2 sidewalls also falls off, forming coplanar waveguide circuits on both the front and back surfaces.

[0176] The technical solution provided in the embodiment of the present application utilizes the characteristics of SiO2 being resistant to high temperatures (can withstand temperatures above 1000°C) and being soluble in hydrofluoric acid, and TiN being resistant to hydrofluoric acid, to combine the atomic layer deposition high-temperature coating method with the stripping process to obtain a one-time formed front and back coplanar waveguide circuit.

[0177] Please refer to FIG7 , which shows a block diagram of a method for manufacturing a coplanar waveguide circuit according to an embodiment of the present application;

[0178] As shown in 700 of Figure 7 , a 5µm thick SiO2 layer is first deposited on each of the top and bottom surfaces of a 200µm high-resistivity silicon substrate using thermal oxidation or chemical vapor deposition. A photoresist is then spin-coated on the front surface and the hole shape is defined using photolithography. The hole diameter can be set to 10µm. HMDS treatment can be used between the SiO2 and the photoresist to improve adhesion. A possible photoresist is AZ6130, and a possible spin-coating parameter is 1000rpm for 30s, resulting in a 6.3µm thick photoresist. The exposed SiO2 is then etched using a dry etcher to form a hard mask for the deep silicon vias (TSVs). CF4 can be used as a gas for etching the SiO2. Using the deep silicon etcher, the high-resistivity silicon substrate is etched to form a small hole with a high aspect ratio. C4F8 and SF6 gases are alternately introduced into the chamber until the equipment detects that the hole has penetrated the entire substrate. The SiO2 on the back of the substrate acts as a stop layer during deep silicon etching, allowing through-holes to be directly formed through deep silicon etching without the need for subsequent thinning and polishing processes. After deep silicon etching forms the deep holes, photoresist is spin-coated on the front side. At this time, due to the edge bead effect of the small holes, there is an area around the small holes that is not covered by the photoresist. Through front-side photolithography, the area to be ultimately coated with the film (including the area around the small holes that is not covered by the photoresist) is exposed to expose the SiO2, and then the exposed SiO2 is etched away using dry etching. A gas that can be used to etch SiO2 can be CF4. The substrate is then turned backside up and photoresist is spin-coated on the back side. Since there is a flat surface of SiO2 on the back side, the spin-coated photoresist is not affected by the small holes. The SiO2 and photoresist can be treated with HMDS (hexamethyldisilane) to increase adhesion. By performing photolithography on the back of the substrate, the area to be coated is exposed to expose the SiO2, and then dry etching is used to clean the exposed SiO2. A gas that can be used to etch SiO2 is CF4. The photoresist on both sides is removed through a degumming process. An optional solution is to soak the substrate in Remover PG degumming solution at 80°C for 8 hours, then rinse and dry it with IPA. The substrate is then placed in a thermal atomic layer deposition (TALD) device, and a 100nm TiN film is formed at 450°C using alternating purges of TiCl4 and NH3. Because TAD has extremely high step coverage, TiN is evaporated on the through-holes and areas on the front and back surfaces of the substrate that are not covered by SiO2. Finally, the substrate is taken out and placed sideways on a cleaning basket. SiO2 is removed by diluted hydrofluoric acid (5% concentration), and high-power ultrasound (300W, 45kHz) is used to peel off the TiN on the SiO2 surface. Under high ultrasonic power, the TiN on the side wall of SiO2 also falls off, and coplanar waveguide circuits are formed on both the front and back surfaces at the same time.

[0179] The technical solution provided in the embodiment of the present application integrates the hard mask function of SiO2, the deep silicon via stop layer function and the stripping function, thereby improving the efficiency of material use and substantially reducing the number of process steps. The stripping process is used instead of etching to effectively avoid the problem of etching failure caused by the edge glue effect of the hole. The front and back graphic structures are formed in one step, avoiding the need to consider protecting the other side graphic from damage when preparing the front and back graphics one by one. There is no need for ion milling process, which reduces the complexity of the process and has more relaxed equipment requirements.

[0180] Please refer to FIG8 , which shows a schematic diagram of a method for preparing a coplanar waveguide circuit provided in one embodiment of the present application.

[0181] As shown in FIG8 , a first material layer 810 is formed on the first surface of a substrate 800, and a second material layer 820 is formed on the second surface of the substrate 800. A first photoresist layer 830 is formed on the first material layer 810, and a first mask plate 840 is passed through the first photoresist layer to obtain an exposed first photoresist layer. The exposed first photoresist layer is then developed to expose at least one area corresponding to a first through hole on the first photo material layer. The first material layer is etched using a first etching gas, as shown in FIG8 (5). The through hole area exposed on the first material layer is then etched using a second etching gas to form at least one second through hole, as shown in FIG8 (6). A second photoresist layer 850 is formed on the first material layer. A second mask plate 860 is then covered on the second photoresist layer. After photolithography and development again, FIG8 (8) is obtained. The first material layer is etched using a third etching gas to obtain an etched first material layer, as shown in FIG8 (9). Similarly, for the second side (i.e., the back side) of the substrate, a third photoresist layer 870 is formed on the second material layer, and a third mask plate 880 is covered on the third photoresist layer 870. After photolithography and development again, Figure (11) of Figure 8 is obtained. The second material layer is etched with a fourth etching gas to obtain the etched second material layer, as shown in Figure (12) of Figure 8. After cleaning and degumming, a conductor material 890 is deposited on the substrate, as shown in Figure (14) of Figure 8. Finally, a detergent is used to clean the impurities on the surface to obtain the completed coplanar waveguide circuit.

[0182] In an exemplary embodiment, a chip substrate is further provided. The chip substrate has a coplanar waveguide circuit thereon. The coplanar waveguide circuit is prepared using the above-mentioned method for preparing the coplanar waveguide circuit.

[0183] In an exemplary embodiment, a chip is further provided. The substrate of the chip has a coplanar waveguide circuit thereon. The coplanar waveguide circuit is manufactured using the above-mentioned method for manufacturing the coplanar waveguide circuit.

[0184] In an exemplary embodiment, the chip is a quantum chip.

[0185] FIG9 shows a structural block diagram of a computer device provided by another exemplary embodiment of the present application.

[0186] Typically, the computer device 900 includes a processor 901 and a memory 902 .

[0187] The processor 901 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 901 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), or PLA (Programmable Logic Array). The processor 901 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 901 may be integrated with a GPU, which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 901 may also include an AI processor for processing computing operations related to machine learning.

[0188] Memory 902 may include one or more computer-readable storage media, which may be tangible and non-transitory. Memory 902 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in memory 902 stores a computer program, which is loaded and executed by processor 901 to implement the above-mentioned method for preparing a coplanar waveguide circuit. In some embodiments, the computer device is a device for preparing a coplanar waveguide circuit, and is a device for preparing a coplanar waveguide circuit.

[0189] Those skilled in the art will appreciate that the structure shown in FIG. 9 does not limit the computer device 900 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0190] In an exemplary embodiment, a computer-readable storage medium is further provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the computer program implements the above-mentioned method for preparing a coplanar waveguide circuit. Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives) or an optical disk, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0191] In an exemplary embodiment, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the method for fabricating a coplanar waveguide circuit.

[0192] It should be noted that the collection and processing of relevant data in this application should be strictly in accordance with the requirements of relevant national laws and regulations when applied in practice, and the informed consent or separate consent of the personal information subject should be obtained. Subsequent data use and processing should be carried out within the scope of authorization of laws and regulations and the personal information subject.

[0193] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application do not limit this.

[0194] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for preparing a coplanar waveguide circuit, the method comprising: forming a first material layer on a first surface of a substrate, and forming a second material layer on a second surface of the substrate; Based on the at least one first through hole on the first material layer, etching the substrate to form at least one second through hole on the substrate, wherein the second material layer is used as a stop layer for etching the substrate; Etching the first material layer to remove a portion corresponding to the conductor pattern of the first coplanar waveguide circuit to obtain an etched first material layer; Etching the second material layer to remove a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain an etched second material layer; Depositing a conductor material on the first side of the substrate with the etched first material layer, the second side of the substrate with the etched second material layer, and the at least one second through hole on the substrate; The etched first material layer and the etched second material layer are removed to obtain a substrate with a coplanar waveguide circuit, wherein the first coplanar waveguide circuit is formed on the first surface, the second coplanar waveguide circuit is formed on the second surface, and the first coplanar waveguide circuit and the second coplanar waveguide circuit are electrically connected through the conductor material at the at least one second through hole.

2. The method according to claim 1, wherein: The forming of a first material layer on a first surface of a substrate and the forming of a second material layer on a second surface of the substrate include: Performing oxidation treatment on the first surface of the substrate to form the first material layer, and performing oxidation treatment on the second surface of the substrate to form the second material layer; or, A first material is plated on the first surface of the substrate to form the first material layer, and a second material is plated on the second surface of the substrate to form the second material layer.

3. The method according to claim 1 or 2, wherein: After forming the first material layer on the first surface of the substrate, the method further includes: forming a first photoresist layer on the first material layer; Covering the first photoresist layer with a first mask plate, wherein the first mask plate is used to cover other parts except the through hole region where the at least one first through hole is located; Performing photolithography on the first photoresist layer through the first mask plate to obtain an exposed first photoresist layer; Developing the exposed first photoresist layer to expose the through hole area on the first material layer; The exposed through-hole region on the first material layer is etched using a first etching gas to form the at least one first through-hole on the first material layer.

4. The method according to any one of claims 1 to 3, wherein: The etching of the substrate based on the at least one first through hole on the first material layer to form at least one second through hole on the substrate comprises: Using a second etching gas to etch a through-hole region on the first surface of the substrate, wherein the through-hole region refers to a region exposed by the at least one first through-hole on the first material layer; When the second material layer is detected, etching is stopped to form the at least one second through hole on the substrate.

5. The method according to any one of claims 1 to 4, wherein: The etching of the first material layer to remove a portion corresponding to the conductor pattern of the first coplanar waveguide circuit to obtain the etched first material layer includes: forming a second photoresist layer on the first material layer; A second mask is covered on the second photoresist layer, and the second mask is used to block the first coplanar wave other parts of the conductive path other than the parts corresponding to the conductor pattern; Performing photolithography on the second photoresist layer through the second mask plate to obtain an exposed second photoresist layer; Developing the exposed second photoresist layer to expose an area corresponding to the conductor pattern of the first coplanar waveguide circuit on the first material layer; The exposed area of ​​the first material layer corresponding to the conductor pattern of the first coplanar waveguide circuit is etched using a third etching gas to obtain the etched first material layer.

6. The method according to any one of claims 1 to 5, wherein: The etching of the second material layer to remove a portion corresponding to the conductor pattern of the second coplanar waveguide circuit to obtain the etched second material layer includes: forming a third photoresist layer on the second material layer; Covering the third photoresist layer with a third mask plate, wherein the third mask plate is used to shield other parts except the part corresponding to the conductor pattern of the second coplanar waveguide circuit; Performing photolithography on the third photoresist layer through the third mask plate to obtain an exposed third photoresist layer; developing the exposed third photoresist layer to expose an area corresponding to the conductor pattern of the second coplanar waveguide circuit on the second material layer; The exposed area of ​​the second material layer corresponding to the conductor pattern of the second coplanar waveguide circuit is etched using a fourth etching gas to obtain the etched second material layer.

7. The method according to any one of claims 1 to 6, wherein: Depositing a conductor material on the first surface of the substrate with the etched first material layer, the second surface of the substrate with the etched second material layer, and the at least one second through hole on the substrate comprises: The conductor material is deposited on the first surface of the substrate with the etched first material layer, the second surface of the substrate with the etched second material layer, and the at least one second through hole on the substrate by thermal atomic layer deposition.

8. The method according to any one of claims 1 to 7, wherein: The removing of the etched first material layer and the etched second material layer to obtain a substrate with a coplanar waveguide circuit comprises: The etched first material layer and the etched second material layer are removed by using a detergent to obtain a substrate with a coplanar waveguide circuit.

9. The method according to any one of claims 1 to 8, wherein: The substrate is a silicon substrate, the first material layer is silicon dioxide, and the second material layer is silicon dioxide.

10. The method according to any one of claims 1 to 9, wherein: The conductor material is titanium nitride.

11. A chip substrate having a coplanar waveguide circuit thereon, wherein the coplanar waveguide circuit is prepared by the method according to any one of claims 1 to 10.

12. A chip, wherein a coplanar waveguide circuit is provided on a substrate of the chip, wherein the coplanar waveguide circuit is prepared by the method according to any one of claims 1 to 10.

13. The chip according to claim 12, wherein: The chip is a quantum chip.

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