Method for improving wire sawing data consistency of large wafer

Abstract

A method for improving the wire sawing data consistency of a large wafer, comprising: adjusting an initial test angle β so that the initial test angle β is equal to the included angle α between a saw mark direction and a Notch, and then using thickness contour test data in a sawing direction to perform thickness gradient calculation to represent the influence of sawing on the morphology of a silicon wafer. According to the method, by adjusting a test path to be consistent with a sawing direction, the problem of wire sawing data consistency is solved, and process adjustment and processing parameter optimization are facilitated, thereby solving the problem of a test method being unable to provide a wire sawing direction as an initial position to obtain consistency test data for process commissioning research and development requirements is solved.

Description

A method for improving data consistency in wire sawing of large silicon wafers

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 16, 2023, with application number 202310713301.8, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to a test method for improving the consistency of wire-cutting data of large silicon wafers, which mainly includes adjusting the starting position of the silicon wafer data test after wire-cutting by using the cutting angle as a reference angle, thereby obtaining the consistency data of the test data with the cutting direction as the initial angle, and then calculating the thickness steepness of the cutting direction to characterize the impact of the cutting on the silicon wafer morphology. Background Art

[0003] With the increasing performance requirements of semiconductor components and the gradual improvement of manufacturing processes, the requirements for silicon wafer flatness are also becoming increasingly stringent. How to characterize silicon wafer flatness and related parameters during the production process is of great significance to silicon wafer production.

[0004] The method of non-contact testing of silicon wafers is widely adopted because of its advantages of not damaging the surface of the silicon wafer, easy to use, and fast testing speed. Among them, the electronic capacitance method for measuring thickness is a common technology. The principle of this method is to assume that the silicon wafer is an ideal uniform dielectric, that is, the dielectric constant of the measured silicon wafer and the entire area of ​​the silicon wafer are the same or similar. Figure 1 is a schematic diagram of the principle of measuring thickness by capacitance. As shown in Figure 1, Probe A and Probe B are capacitance sensor probes; s is the probe area; D is the distance between probes A and B, which is a fixed value; a is the distance between probe A and the surface of the silicon wafer; b is the distance between probe B and the surface of the silicon wafer; during the equipment debugging process, it is also necessary to ensure that a and b are as equal as possible to ensure the accuracy of the measurement results; t is the thickness of the silicon wafer. During the test, the silicon wafer is placed between probe A and probe B. Assuming that the dielectric constant of the silicon wafer is ε, the dielectric constant of air is ε0, when there is no silicon wafer, the capacitance is C0, and when the silicon wafer is placed between probe A and probe B, the capacitance is C

[0005] When an AC high-frequency signal is input between the upper and lower capacitor probes, a high-frequency electric field is generated, and current flows through the capacitor, forming a standard linear circuit within the device, which can measure the change in current. Assuming that the current value when there is no silicon wafer is I0, when testing the silicon wafer, the current is I, the AC voltage is U, and the frequency is f, then: I0=U·2πf·C0 (3) I=U·2πf·C (4)

[0006] It can be deduced that,

[0007] Equation 5 shows that when D and ε are constant, the thickness of the silicon wafer is determined by the current flowing through it. Solving this equation yields the thickness at that point. By moving the wafer, the thickness at other locations can be determined.

[0008] When testing using line scan, the post-cut flatness test uses the notch as the initial position. Because there's no correlation between the cutting direction and the notch position, the impact of the cutting direction on the process parameters of interest cannot be reflected. Furthermore, cutting significantly impacts the flatness data of the silicon wafer. Therefore, reasonable and consistent testing and characterization of post-cut wafer flatness data is extremely important.

[0009] Summary of the Invention

[0010] In order to improve the consistency test problem of large silicon wafer wire cutting data, better solve the problem that conventional flatness testing cannot characterize the cutting direction deviation during production, and optimize process parameters, this application is completed in the following way.

[0011] A method for changing the initial test position is proposed. By adjusting the test path to align with the cutting direction, the consistency issue of wire cutting data is resolved, facilitating process adjustments and optimizing processing parameters. As shown in Figure 2, when the test path is as shown, the cutting direction is not completely consistent with the notch direction (see Figure 3). This will result in a situation in which the test data and the cutting direction are not correlated in the actual test results. When the angle between the line trace direction and the notch is α, and the starting angle of the silicon wafer test is β, β is adjusted to make α = β. In the actual test results, the test pattern remains consistent with the cutting direction, and the consistency of the test data is greatly improved.

[0012] Take the thickness profile test data in the cutting direction, see Figure 5, and calculate the thickness steepness as follows:

[0013] Where Space represents the sampling length, that is, the thickness steepness is calculated within the length range, Thk (x) is a function of the thickness of the silicon wafer at position x and position x.

[0014] The value range of Space is 5~10mm. Select the appropriate Space value and perform Thk on the symmetrical position in the cutting direction. dq calculate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1. Schematic diagram of thickness measurement using capacitance method;

[0016] Figure 2. Schematic diagram of the flatness test pattern after cutting;

[0017] Figure 3. Schematic diagram of the line mark and Notch position;

[0018] Figure 4. Schematic diagram of the improved line mark and notch position;

[0019] Figure 5. Schematic diagram of thickness steepness calculation;

[0020] Figure 6. Examples of thickness profiles and thickness steepness of two silicon wafers. DETAILED DESCRIPTION

[0021] Example

[0022] Select two different silicon wafers to ensure that their thickness, curvature, warpage and other parameters are relatively close. Adjust the angle between the line mark direction and the notch to α. When testing the starting angle β of the silicon wafer, adjust β so that α=β. Then take the thickness profile test data in the cutting direction and calculate the thickness steepness as follows:

[0023] Where Space represents the sampling length, that is, the thickness steepness is calculated within the length range, Thk (x) The thickness of the silicon wafer at position x is a function of position x. Take Space as 6mm and perform Thk on the symmetrical positions of -146mm, -75mm, 0mm, 75mm, and 146mm in the cutting direction. dq Calculation. Analysis shows that under conventional flatness test conditions, there is no obvious difference between the two silicon wafers. After calculating the data using the test method of this application, it can be seen that the silicon wafer has a greater steepness at the start and end of the cutting, and the steepness gradually decreases near the radius to the center. In addition, during the two cutting processes, the maximum steepness data was obtained at the start and end of the cutting, respectively. Analysis of the -150mm to -75mm data found that wafer 2 (wafer2) has a higher steepness and faster changes. The process can be compared based on the difference in steepness data to improve the similarities and differences of the two cutting processes and ensure process stability.

Claims

1. A method for improving the consistency test of large silicon wafer wire cutting data, taking the angle between the cutting mark and the notch as α, the starting angle of the silicon wafer test as β, and adjusting β so that α=β.

2. The method according to claim 1, further comprising: The thickness steepness is calculated along the cutting direction test data to characterize the effect of cutting on the silicon wafer morphology. The thickness profile test data along the cutting direction is taken and the calculation formula is as follows:

3. The method according to claim 2, wherein: Space represents the sampling length, that is, the thickness steepness is calculated within the length range, and Thk(x) is the thickness of the silicon wafer at position x.

4. The method according to claim 3, wherein: The value of Space is between 5mm and 10mm.

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