Semiconductor device and manufacturing method therefor

Abstract

Provided in the present disclosure are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, wherein a device region of the substrate comprises a first sub-region and a second sub-region, a first isolation sub-structure located in the first sub-region comprises a first dielectric layer that fills up a first sub-trench, and a second isolation sub-structure located in the second sub-region comprises a first dielectric layer and a first isolation layer that sequentially cover the side wall and the bottom of a second sub-trench, and a second dielectric layer that fills up the second sub-trench; removing part of the first dielectric layer and part of the second dielectric layer from the second sub-trench, so as to expose at least part of the side wall of the first isolation layer; and removing from the second sub-trench part of the first isolation layer that is exposed.

Description

Semiconductor device and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310713541.8, application date June 14, 2023, and invention name “A semiconductor device and its manufacturing method”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The storage cell of dynamic random access memory (DRAM) includes a transistor and a capacitor (1 transistor 1 capacitor, 1T1C). The gate of the transistor is connected to the word line, the source of the transistor is connected to the bit line, and the drain of the transistor is connected to the capacitor.

[0005] Currently, there are still challenges in improving DRAM to enhance its performance.

[0006] Summary of the Invention

[0007] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0008] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0009] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0010] A substrate is provided, comprising a device region and a peripheral region, wherein the device region comprises a first sub-region and a second sub-region, wherein the second sub-region is located between the first sub-region and the peripheral region; the substrate of the device region comprises a plurality of first isolation structures extending along a first direction and a plurality of second isolation structures extending along a second direction, wherein the first isolation structures and the second isolation structures jointly isolate a plurality of active pillars; the first isolation structure comprises a first sub-isolation structure located in the first sub-region and a second sub-isolation structure located in the second sub-region, wherein the first sub-isolation structure comprises a first dielectric layer filling a first sub-trench, and the second sub-isolation structure comprises a first dielectric layer sequentially covering a sidewall and a bottom of the second sub-trench, a first isolation layer, and a second dielectric layer filling the second sub-trench; wherein the first direction and the second direction are both parallel to the substrate and intersect with the first direction;

[0011] removing a portion of the first dielectric layer in the first sub-trench and a portion of the first dielectric layer and the second dielectric layer in the second sub-trench to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively;

[0012] A portion of the first isolation layer exposed in the second sub-trench is removed.

[0013] In some embodiments, the second isolation structure includes a third sub-isolation structure located in the first sub-region and a fourth sub-isolation structure located in the second sub-region, the third sub-isolation structure includes a third dielectric layer filling the third sub-trench, and the fourth sub-isolation structure includes a third dielectric layer sequentially covering the sidewalls and bottom of the fourth sub-trench, a second isolation layer, and a fourth dielectric layer filling the fourth sub-trench;

[0014] Before removing a portion of the first dielectric layer in the first sub-trench and a portion of the first dielectric layer and the second dielectric layer in the second sub-trench, the manufacturing method further includes:

[0015] forming a third isolation layer, wherein the third isolation layer covers the first isolation structure and the second isolation structure of the device region;

[0016] A portion of the third isolation layer is removed to retain the third isolation layer covering the fourth dielectric layer in the fourth sub-trench.

[0017] In some embodiments, while removing a portion of the first dielectric layer in the first sub-trench and a portion of the first dielectric layer and the second dielectric layer in the second sub-trench, the manufacturing method further includes:

[0018] A portion of the third dielectric layer in the third sub-trench and a portion of the third dielectric layer in the fourth sub-trench are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the second isolation layer.

[0019] In some embodiments, after removing a portion of the third dielectric layer in the third sub-trench and a portion of the third dielectric layer in the fourth sub-trench, the manufacturing method further includes:

[0020] removing the third isolation layer covering the fourth dielectric layer in the fourth sub-trench;

[0021] A portion of the fourth dielectric layer in the fourth sub-trench is removed; wherein a surface of the fourth dielectric layer in the fourth sub-trench is higher than a surface of the third dielectric layer.

[0022] In some embodiments, while removing the portion of the first isolation layer exposed in the second sub-trench, the manufacturing method further includes:

[0023] A portion of the second isolation layer exposed in the fourth sub-trench is removed.

[0024] In some embodiments, the active pillar includes a first end and a second end oppositely disposed along a third direction and a channel region between the first end and the second end; the third direction is perpendicular to the substrate;

[0025] After removing the portion of the first isolation layer exposed in the second sub-trench, the manufacturing method further includes:

[0026] A plurality of word line structures extending along the second direction are formed; the word line structures cover the channel regions of the active pillars located in the same row.

[0027] In some embodiments, the first sub-groove and the second sub-groove together form a first groove, and the third sub-groove and the fourth sub-groove together form a second groove;

[0028] The forming of a plurality of word line structures extending along the second direction includes:

[0029] forming a gate dielectric layer covering at least the channel region of the active pillar in the first trench and the second trench;

[0030] A gate conductive layer covering at least a portion of the gate dielectric layer is formed in the first trench and the second trench; the gate conductive layer encapsulates the channel region of the active pillars located in the same row, and the gate conductive layers in the first sub-trench and the second sub-trench are electrically connected; wherein the gate dielectric layer and the gate conductive layer together form a word line structure.

[0031] In some embodiments, forming a gate conductive layer in the first trench and the second trench to at least partially cover the gate dielectric layer includes:

[0032] forming a conductive material layer, wherein the conductive material layer fills the first trench and the second trench;

[0033] removing the conductive material layer covering the second end of the active pillar;

[0034] forming a fourth isolation layer, wherein the fourth isolation layer fills the first trench and the second trench;

[0035] Sequentially etching the fourth isolation layer and the conductive material layer in the second trench to form a word line trench and a gate conductive layer; wherein the word line trench extends along the second direction; the gate conductive layer in the second sub-trench is in direct contact with the gate dielectric layer; and the gate conductive layer in the fourth sub-trench is in direct contact with the fourth dielectric layer;

[0036] An isolation material is filled in the word line isolation groove to form a word line isolation structure.

[0037] In some embodiments, after removing the portion of the first isolation layer exposed in the second sub-trench, the manufacturing method further includes:

[0038] forming a plurality of bit line structures extending along the first direction; the bit line structures sequentially connecting the first ends of the active pillars located in the same column;

[0039] A plurality of storage capacitors are formed; the first electrodes of the storage capacitors are connected to the second ends of the active pillars, and the second electrodes of the storage capacitors are connected to a common end.

[0040] In some embodiments, providing a substrate includes:

[0041] Etching the substrate to form a first trench in the device region and a third trench in the peripheral region; the first trench and the third trench both extend along the first direction; the first trench includes a first sub-trench located in the first sub-region and a second sub-trench located in the second sub-region;

[0042] forming a first dielectric layer, wherein the first dielectric layer covers the sidewalls and bottoms of the second sub-trench and the third trench, and the first dielectric layer fills the first sub-trench to form a first sub-isolation structure;

[0043] forming a first isolation layer, wherein the first isolation layer covers the first dielectric layer;

[0044] A second dielectric layer is formed, and the second dielectric layer fills the second sub-trench and the third trench to form a second sub-isolation structure and a third isolation structure, respectively.

[0045] In some embodiments, providing a substrate further comprises:

[0046] Etching the substrate, the first dielectric layer, and the second dielectric layer to form a second trench in the device region, wherein the second trench further extends into the third trench in the peripheral region; the second trench extends along the second direction; and the second trench includes a third sub-trench located in the first sub-region and a fourth sub-trench located in the second sub-region;

[0047] forming a third dielectric layer, wherein the third dielectric layer covers the sidewalls and the bottom of the fourth sub-trench and the third dielectric layer fills the third sub-trench to form a third sub-isolation structure;

[0048] forming a second isolation layer, wherein the second isolation layer covers the third dielectric layer;

[0049] A fourth dielectric layer is formed, wherein the fourth dielectric layer fills the fourth sub-trench to form a fourth sub-isolation structure.

[0050] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, comprising:

[0051] a substrate comprising a device region and a peripheral region, wherein the device region comprises a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the peripheral region;

[0052] The substrate of the device region includes a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, wherein the first trenches and the second trenches together isolate a plurality of active pillars; the active pillars include a first end and a second end oppositely disposed along a third direction, and a channel region located between the first end and the second end; the first trenches include a first sub-trench located in the first sub-region and a second sub-trench located in the second sub-region; wherein the first direction and the second direction are both parallel to the substrate and intersect with each other, and the third direction is perpendicular to the substrate;

[0053] A plurality of word line structures extending along the second direction are located in the first trench and the second trench; the word line structures cover the channel regions of the active pillars located in the same row; wherein the word line structure in the first sub-trench is electrically connected to the word line structure in the second sub-trench.

[0054] In some embodiments, the semiconductor device further comprises:

[0055] a fourth isolation layer extending along the second direction and located in the first trench and the second trench; the fourth isolation layer covers the second ends of the active pillars located in the same row;

[0056] A plurality of word line isolation structures extending along the second direction are located between adjacent word line structures and adjacent fourth isolation layers.

[0057] In some embodiments, the word line structure includes:

[0058] a gate dielectric layer, covering at least the channel region of the active pillar;

[0059] A gate conductive layer is located on the surface of the gate dielectric layer and covers the channel region of the active pillars located in the same row; wherein the gate conductive layer in the first sub-trench is electrically connected to the gate conductive layer in the second sub-trench, and the gate conductive layer in the second sub-trench is in direct contact with the gate dielectric layer.

[0060] In some embodiments, the semiconductor device further comprises:

[0061] a first dielectric layer located in the first sub-trench and the second sub-trench, wherein the first dielectric layer is located between the first ends of adjacent active pillars and covers the sidewalls and bottom of the second sub-trench;

[0062] a first isolation layer of the first dielectric layer covering the sidewalls and bottom of the second sub-trench;

[0063] A second dielectric layer is located in the second sub-trench, and the second dielectric layer is located below the gate conductive layer.

[0064] In some embodiments, the second trench includes a third sub-trench located in the first sub-region and a fourth sub-trench located in the second sub-region; and the semiconductor device further includes:

[0065] a third dielectric layer located in the third sub-trench and the fourth sub-trench, wherein the third dielectric layer is located between the first ends of adjacent active pillars and covers the sidewalls and bottom of the fourth sub-trench;

[0066] a second isolation layer of the third dielectric layer covering the bottom of the fourth sub-trench;

[0067] A fourth dielectric layer is located in the fourth sub-trench, and a sidewall of the fourth dielectric layer is in direct contact with the gate conductive layer and the fourth isolation layer.

[0068] In some embodiments, the semiconductor device further comprises:

[0069] a third isolation structure located in the peripheral region and extending along the first direction, the third isolation structure comprising a first portion and a second portion, wherein a portion of the second trench extending into the third isolation structure is the second portion;

[0070] The first portion includes a first dielectric layer, a first isolation layer, and a second dielectric layer covering the first isolation layer in sequence;

[0071] The second portion includes a third dielectric layer and a second isolation layer sequentially covering the second trench and extending to at least a portion of the sidewall and bottom of the third isolation structure, and a fourth dielectric layer filling the second trench and extending to the third isolation structure.

[0072] In some embodiments, the semiconductor device further comprises:

[0073] extending a plurality of bit line structures along the first direction, wherein the bit line structures sequentially connect the first ends of the active pillars located in the same column;

[0074] A plurality of storage capacitors; a first electrode of the storage capacitor is connected to the second end of the active pillar, and a second electrode of the storage capacitor is connected to a common end.

[0075] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a portion of the first dielectric layer within the first sub-trench and a portion of the first dielectric layer within the second sub-trench are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively. The portion of the first isolation layer exposed within the second sub-trench is removed. Thus, during the subsequent formation of a wordline structure, the wordline structures within the first sub-trench and the second sub-trench can be electrically connected. Specifically, the wordline structure located in the first sub-region and used to connect the gates of memory cells in the same row can be electrically connected to the end of the wordline structure located in the second sub-region. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] FIG1 is a schematic top view of a semiconductor device according to some examples;

[0077] FIG2 is a schematic cross-sectional view of a semiconductor device according to some examples;

[0078] FIG3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0079] FIG4 is a schematic top view of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0080] 5A to 5O are schematic cross-sectional views of a semiconductor device during the manufacturing process according to an embodiment of the present disclosure;

[0081] FIG6 is a schematic top view of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0082] FIG7 is a schematic cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0083] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0084] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0085] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0086] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0087] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0088] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0089] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0090] Before introducing the embodiments of the present disclosure, we first define three directions that may be used to describe the structure of the embodiments of the present disclosure. These three directions may include the X direction, the Y direction, and the Z direction. The X direction and the Y direction are both parallel to the substrate and intersect with each other. The Z direction is perpendicular to the substrate. In the embodiments of the present disclosure, the memory cells may be arranged in an array along the X direction and the Y direction. The X direction may also be referred to as the row direction, and the Y direction may also be referred to as the column direction.

[0091] It should be noted that a first direction, a second direction and a third direction may be defined. In the embodiment of the present disclosure, the first direction is defined as the Y direction, the second direction is defined as the X direction, and the third direction is defined as the Z direction.

[0092] Referring to Figures 1 and 2, Figure 1 is a schematic top view of a semiconductor device provided in some examples, and Figure 2 is a schematic cross-sectional view of a semiconductor device provided in some examples. As shown in Figures 1 and 2, a substrate 100 includes a device region 102 and a peripheral region 104. The peripheral region 104 can be arranged around the device region 102. A memory cell array is provided in the device region 102, and the memory cell array includes a plurality of memory cells arranged in an array along the X and Y directions. The peripheral region 104 includes a peripheral circuit, which can be used to control the memory cell array. The device region 102 includes a first sub-region 106 (as shown by the dotted box in Figure 1) and a second sub-region 108 (as shown by the dashed box in Figure 1). The second sub-region 108 is located between the first sub-region 106 and the peripheral region 104. More specifically, the first sub-region 106 includes a plurality of active pillars 110 arranged in an array along the X and Y directions. Each active pillar includes a first end and a second end opposite each other along the Z direction, and a channel region located between the first and second ends. The drain of a transistor can be, for example, the first end of the active pillar, the source of a transistor can be, for example, the second end of the active pillar, and the gate of the transistor can surround the channel region of the active pillar. The first ends of active pillars in the same column (i.e., arranged along the Y direction) can be connected to the same bit line (BL), which can extend from the first sub-region to the second sub-region along the Y direction. The gates outside the channel regions of active pillars in the same row (i.e., arranged along the X direction) can be connected to the same word line (WL), which can extend from the first sub-region to the second sub-region along the X direction. In other words, no memory cells are located in the second sub-region 108, which includes bit line ends and word line ends.

[0093] Figure 2 illustrates schematic cross-sectional views along the aa, bb, cc, dd, and ee directions in Figure 1 , wherein the cross-sectional views along the aa and bb directions each illustrate schematic cross-sectional views of the first and second sub-regions of the device region along the Y direction; the cross-sectional views along the cc and dd directions each illustrate schematic cross-sectional views of the first and second sub-regions of the device region along the X direction; and the cross-sectional view along the ee direction illustrates schematic cross-sectional views of the peripheral region along the X direction. Figures 1 and 2 illustrate a vertical channel transistor (VGT), which has a gate-all-around (GAA) structure.

[0094] As shown in the cc direction cross-sectional structural diagram in FIG2 , the substrate 100 of the device region 102 includes a first trench 112 extending along the Y direction, and the first trench 112 includes a first sub-trench 114 located in the first sub-region 106 and a second sub-trench 116 located in the second sub-region 108; the word line structure in the first sub-trench 114 and the word line structure in the second sub-trench 116 may be isolated by a first silicon nitride pillar 124 (as shown in the dotted circle in FIG2 ), that is, the word line structure located in the first sub-region 106 for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region 108 may not be electrically connected, and there is a risk of high resistance at the end of the word line structure (WL End High Resistance) and a potential risk of word line structure disconnection (WL Open). As shown in the schematic cross-sectional structure diagram along the aa direction in FIG2 , the substrate 100 of the device region 102 further includes a second trench 118 extending along the X direction. The second trench 118 includes a third sub-trench 120 located in the first sub-region 106 and a fourth sub-trench 122 located in the second sub-region 108. The second silicon nitride pillar 126 in the fourth sub-trench 122 (as shown in the dotted circle in FIG2 ) may cause contamination to the bit line structure formed in subsequent processes (SIN Pollution Risk).

[0095] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0096] Referring to FIG3 , FIG3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG3 , an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0097] Step S301: providing a substrate, the substrate comprising a device region and a peripheral region, the device region comprising a first sub-region and a second sub-region, the second sub-region being located between the first sub-region and the peripheral region; the substrate in the device region comprising a plurality of first isolation structures extending along a first direction and a plurality of second isolation structures extending along a second direction, the first isolation structures and the second isolation structures jointly isolating a plurality of active pillars; the first isolation structure comprising a first sub-isolation structure located in the first sub-region and a second sub-isolation structure located in the second sub-region, the first sub-isolation structure comprising a first dielectric layer filling a first sub-trench, the second sub-isolation structure comprising a first dielectric layer sequentially covering a sidewall and a bottom of the second sub-trench, a first isolation layer, and a second dielectric layer filling the second sub-trench; wherein the first direction and the second direction are both parallel to the substrate and intersect with the first direction;

[0098] Step S302: removing a portion of the first dielectric layer in the first sub-trench and a portion of the first dielectric layer and the second dielectric layer in the second sub-trench to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively;

[0099] Step S303: removing the portion of the first isolation layer exposed in the second sub-trench.

[0100] In the embodiment of the present disclosure, part of the first dielectric layer in the first sub-trench and part of the first dielectric layer and the second dielectric layer in the second sub-trench are removed to expose at least part of the sidewall of the active pillar and at least part of the sidewall of the first isolation layer, respectively; the part of the first isolation layer exposed in the second sub-trench is removed; in this way, in the subsequent process of forming the word line structure, the word line structures in the first sub-trench and the second sub-trench can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.

[0101] Referring to Figures 4 and 5A to 5O, Figure 4 is a schematic diagram of the top view structure of the semiconductor device provided in an embodiment of the present disclosure, and Figures 5A to 5O are schematic diagrams of the cross-sectional structure during the manufacturing process of the semiconductor device provided in an embodiment of the present disclosure, which describe in detail the manufacturing method of the semiconductor device provided in an embodiment of the present disclosure.

[0102] It should be noted that Figures 5A to 5O all illustrate schematic cross-sectional structural diagrams along the aa direction, bb direction, cc direction, dd direction and ee direction in Figure 4, wherein the schematic cross-sectional structural diagrams along the aa direction and the bb direction both illustrate schematic cross-sectional structural diagrams of the first sub-region 206 and the second sub-region 208 of the device region 202 along the Y direction; the schematic cross-sectional structural diagrams along the cc direction and the dd direction both illustrate schematic cross-sectional structural diagrams of the first sub-region 206 and the second sub-region 208 of the device region 202 along the X direction; and the schematic cross-sectional structural diagram along the ee direction illustrates a schematic cross-sectional structural diagram of the peripheral region 204 along the X direction.

[0103] In the embodiment of the present disclosure, step S301 includes:

[0104] The substrate 200 is etched to form a first trench 212 in the device region 202 and a third trench 218 in the peripheral region 204; the first trench 212 and the third trench 218 both extend along a first direction; the first trench 212 includes a first sub-trench 214 located in the first sub-region 206 and a second sub-trench 216 located in the second sub-region 208;

[0105] forming a first dielectric layer 220 , wherein the first dielectric layer 220 covers the sidewalls and bottoms of the second sub-trench 216 and the third trench 218 , and the first dielectric layer 220 fills the first sub-trench 214 to form a first sub-isolation structure 228 ;

[0106] forming a first isolation layer 222 , wherein the first isolation layer 222 covers the first dielectric layer 220 ;

[0107] A second dielectric layer 224 is formed to fill the second sub-trench 216 and the third trench 218 to form a second sub-isolation structure 230 and a third isolation structure 232 , respectively.

[0108] As shown in Figures 4 and 5A, substrate 200 includes a device region (Core) 202 and a peripheral region (Periphery) 204. Periphery 204 can be disposed around device region 202. Device region 202 includes a first sub-region 206 (indicated by the dashed-line box in Figure 4) and a second sub-region 208 (indicated by the dotted-line box in Figure 4). Second sub-region 208 is located between first sub-region 206 and peripheral region 204. First sub-region 206 includes a memory cell array, i.e., a plurality of memory cells arranged in an array along the X and Y directions. No memory cells are disposed in the second sub-region. Second sub-region 208 includes bitline structure terminals and wordline structure terminals. Peripheral region 204 includes peripheral circuitry. Here, a bitline structure terminal is referred to as a bitline terminal, and a wordline structure terminal is referred to as a wordline terminal.

[0109] In some embodiments, the substrate may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc. The disclosed embodiments do not specifically limit the material of the substrate.

[0110] As shown in Figure 5A, the substrate 200 is etched to form a first trench 212 in the device area 202 and a third trench 218 in the peripheral area 204; wherein the first trench 212 includes a first sub-trench 214 located in the first sub-area 206 and a second sub-trench 216 located in the second sub-area 208; the first sub-trench 214, the second sub-trench 216 and the third trench 218 all extend along the Y direction.

[0111] Here, the number of first sub-trenches in the first sub-region can be, for example, multiple, and the first sub-trench is used to isolate active pillars in different columns; the number of second sub-trenches in the second sub-region can be, for example, one or two. In a specific example, the second sub-trench in the second sub-region can be between the first sub-trench in the first sub-region and the third trench in the peripheral region. The second sub-trench can be located on one side of the first sub-region, or on two opposite sides of the first sub-region.

[0112] Here, the first trench can be formed in the device region and the third trench can be formed in the peripheral region simultaneously in the same etching process. The heights of the first sub-trench, the second sub-trench, and the third trench along the Z direction are substantially the same. The width of the first sub-trench along the X direction is smaller than the width of the second sub-trench along the X direction, and the width of the first sub-trench along the X direction is smaller than the width of the third trench along the X direction.

[0113] As shown in FIG5A , a first dielectric layer 220 is formed in the first sub-trench 214, the second sub-trench 216, and the third trench 218. Here, since the first sub-trench 214, the second sub-trench 216, and the third trench 218 have different sizes, the first dielectric layer 220 may completely fill the first sub-trench 214 to form the first sub-isolation structure, while the first dielectric layer 220 only covers the sidewalls and bottoms of the second sub-trench 216 and the third trench 218.

[0114] For example, the process of forming the first dielectric layer in the first sub-trench can be performed using the following method: for example, forming a first dielectric material layer in the first sub-trench, the first dielectric material layer covering the substrate surface; performing a planarization process on the first dielectric material layer, removing a portion of the first dielectric material layer to expose the substrate surface, so that the remaining surface of the first dielectric material layer is substantially flush with the substrate surface, and the remaining first dielectric material layer serves as the first dielectric layer. For another example, forming the first dielectric layer in the first sub-trench, the first dielectric layer covering the substrate surface. In this manner, a portion of the first dielectric layer can be removed again in a subsequent process to expose the substrate surface.

[0115] In a specific example, the planarization process includes but is not limited to a chemical mechanical polishing (CMP) process.

[0116] It should be noted that "substantially flush" means that the height difference between the substrate surface and the first dielectric layer surface along the Z direction is less than a preset value, that is, the height difference between the substrate surface and the first dielectric layer surface along the Z direction meets the required process tolerance range. In one specific example, the height difference between the substrate surface and the first dielectric layer surface along the Z direction is 0.

[0117] In some embodiments, the process of forming the first dielectric layer includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0118] In some embodiments, the material of the first dielectric layer may include but is not limited to silicon dioxide.

[0119] As shown in Figure 5A, a first isolation layer 222 is formed in the second sub-trench 216 and the third trench 218, and the first isolation layer 222 covers the first dielectric layer 220; a second dielectric layer 224 is formed in the second sub-trench 216 and the third trench 218, and the second dielectric layer 224 fills the second sub-trench 216 and the third trench 218 to form a second sub-isolation structure 230 and a third isolation structure 232, respectively; wherein the first sub-isolation structure 228 and the second sub-isolation structure 230 together form the first isolation structure 226.

[0120] In some embodiments, the process of forming the first isolation layer and the second dielectric layer includes, but is not limited to, CVD, PVD, and ALD, or any combination thereof.

[0121] In some embodiments, the material of the first isolation layer may include but is not limited to silicon nitride; the material of the second dielectric layer may include but is not limited to silicon dioxide.

[0122] In the embodiment of the present disclosure, step S301 further includes:

[0123] The substrate 200, the first dielectric layer 220, and the second dielectric layer 224 are etched to form a second trench 234 in the device region 202. The second trench 234 also extends into the third trench 218 in the peripheral region 204. The second trench 234 extends along the second direction. The second trench 234 includes a third sub-trench 236 located in the first sub-region 206 and a fourth sub-trench 238 located in the second sub-region 208.

[0124] forming a third dielectric layer 240 , where the third dielectric layer 240 covers the sidewalls and the bottom of the fourth sub-trench 238 , and the third dielectric layer 240 fills the third sub-trench 236 to form a third sub-isolation structure 248 ;

[0125] forming a second isolation layer 242 , wherein the second isolation layer 242 covers the third dielectric layer 240 ;

[0126] A fourth dielectric layer 244 is formed to fill the fourth sub-trench 238 to form a fourth sub-isolation structure 250 .

[0127] As shown in FIG5A , the substrate 200, the first dielectric layer 220, and the second dielectric layer 224 are etched to form a second trench 234 in the device region 202. The second trench 234 may extend into the third trench 218 in the peripheral region 204. The second trench 234 includes a third sub-trench 236 located in the first sub-region 206 and a fourth sub-trench 238 located in the second sub-region 208. Both the third sub-trench 236 and the fourth sub-trench 238 extend along the X-direction.

[0128] Here, based on the third trench already being filled to form a third isolation structure, the third isolation structure includes a first dielectric layer and a first isolation layer sequentially covering the sidewalls and bottom of the third trench, and a second dielectric layer completely filling the third trench. During the etching process to form the second trench, a portion of the second dielectric layer within the third trench may be removed, meaning that the second trench may extend into the third trench. The third and fourth sub-trenches included in the second trench may both extend into the third trench along the X-direction.

[0129] Here, the number of third sub-trenches in the first sub-region can be, for example, multiple, and the third sub-trench is used to isolate active pillars in different rows; the number of fourth sub-trenches in the second sub-region can be, for example, one or two. In a specific example, the fourth sub-trench in the second sub-region can be between the third sub-trench in the first sub-region and the third trench in the peripheral region, the fourth sub-trench can be located on one side of the first sub-region, or the fourth sub-trench can be located on two opposite sides of the first sub-region.

[0130] Here, the heights of the third sub-groove and the fourth sub-groove along the Z direction are substantially the same, and the width of the third sub-groove along the Y direction is smaller than the width of the fourth sub-groove along the Y direction. In a specific example, the height of the second groove along the Z direction is smaller than the height of the first groove along the Z direction.

[0131] 5B , a third dielectric layer 240 is formed in the third sub-trench 236 and the fourth sub-trench 238. Since the third sub-trench 236 and the fourth sub-trench 238 have different sizes, the third dielectric layer 240 may completely fill the third sub-trench 236 to form the third sub-isolation structure 248, while the third dielectric layer 240 only covers the sidewalls and bottom of the fourth sub-trench 238.

[0132] For example, a third dielectric layer is formed in the third sub-trench, and the third dielectric layer may cover the substrate surface. In this way, a portion of the third dielectric layer may be removed in a subsequent process to expose the substrate surface.

[0133] In some embodiments, the material of the third dielectric layer may include but is not limited to silicon dioxide.

[0134] As shown in Figure 5B, a second isolation layer 242 is formed, and the second isolation layer 242 can cover the third dielectric layer 240 located on the surface of the substrate 200 and the surface of the third dielectric layer 240 located in the fourth sub-groove 238; a fourth dielectric layer 244 is formed in the fourth sub-groove 238, and the fourth dielectric layer 244 can cover the second isolation layer 242 located on the surface of the substrate 200 and the second isolation layer 242 located in the fourth sub-groove 238; wherein the fourth dielectric layer 244 can fill the fourth sub-groove 238.

[0135] Here, the second isolation layer covers the device area and the peripheral area. Of course, the second isolation layer covers the surface of the first dielectric layer in the first sub-trench in the first sub-area, the surface of the second dielectric layer in the second sub-trench in the second sub-area, and the surface of the second dielectric layer in the third trench in the peripheral area. Of course, the fourth dielectric layer also covers the surface of the second isolation layer in the device area and the peripheral area.

[0136] In some embodiments, the process of forming the third dielectric layer, the second isolation layer, and the fourth dielectric layer includes, but is not limited to, CVD, PVD, and ALD, or any combination thereof.

[0137] In some embodiments, the material of the second isolation layer may include but is not limited to silicon nitride; the material of the fourth dielectric layer may include but is not limited to silicon dioxide.

[0138] In some embodiments, the materials of the first isolation layer and the second isolation layer may be the same or different.

[0139] In some embodiments, the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer may be the same or different.

[0140] As shown in Figures 5B and 5C, the fourth dielectric layer 244 can be planarized to expose the surface of the second isolation layer 242 located in the device area 202 and the peripheral area 204; the exposed second isolation layer 242 can also be etched back to expose the first dielectric layer 220 in the first sub-trench 214, the second dielectric layer 224 in the second sub-trench 216, the third dielectric layer 240 in the third sub-trench 236, and the fourth dielectric layer 244 in the fourth sub-trench 238.

[0141] Here, the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure. The third sub-isolation structure includes a third dielectric layer filling the third sub-trench. The fourth sub-isolation structure includes a third dielectric layer covering the sidewall and bottom of the fourth sub-trench in sequence, a second isolation layer, and a fourth dielectric layer filling the fourth sub-trench.

[0142] Here, the first and second sub-isolation structures extending along the Y direction, as well as the third and fourth sub-isolation structures extending along the X direction, isolate the device region of the substrate into a plurality of active pillars arranged in an array along the X and Y directions. More specifically, the first sub-isolation structure extending along the Y direction and the third sub-isolation structure extending along the X direction isolate the first sub-region of the substrate into a plurality of active pillars arranged in an array. Each active pillar includes a first end and a second end oppositely disposed along the Z direction, and a channel region located therebetween. The drain of a transistor can, for example, be the first end of the active pillar, the source of a transistor can, for example, be the second end of the active pillar, and the gate of the transistor can surround the channel region of the active pillar. The drains of multiple transistors in the same column (i.e., arranged along the Y direction) can be connected to the same bitline structure, the end of which is located within the second sub-region. The gates of multiple transistors in the same row (i.e., arranged along the X direction) can be connected to the same wordline structure, the end of which is located within the second sub-region.

[0143] Here, the third isolation structure extending along the Y direction isolates the peripheral region of the substrate into a plurality of active regions, which can be used to form transistors of the peripheral circuit later.

[0144] It should be noted that the first isolation layer covering the sidewalls and bottom of the second sub-trench and the first isolation layer covering the sidewalls and bottom of the third trench are masked by the second dielectric layer and are not exposed, and the second isolation layer covering the sidewalls and bottom of the fourth sub-trench is masked by the fourth dielectric layer and is not exposed. Therefore, it is difficult to remove these masked and unexposed first isolation layers or second isolation layers during etching back.

[0145] In the embodiment of the present disclosure, before step S302, the manufacturing method further includes:

[0146] forming a third isolation layer 252 , where the third isolation layer 252 covers the first isolation structure 226 and the second isolation structure 246 of the device region 202 ;

[0147] A portion of the third isolation layer 252 is removed to retain the third isolation layer 252 covering the fourth dielectric layer 244 in the fourth sub-trench 238 .

[0148] As shown in Figure 5D, a third isolation layer 252 is formed, and the third isolation layer 252 covers the device area 202 and the peripheral area 204; more specifically, the third isolation layer 252 covers the surface of the first isolation structure 226 (i.e., the first sub-isolation structure 228 and the second sub-isolation structure 230) located in the device area 202, the surface of the second isolation structure 246 (i.e., the third sub-isolation structure 248 and the fourth sub-isolation structure 250), and the surface of the third isolation structure 232 located in the peripheral area 204.

[0149] In some embodiments, the process of forming the third isolation layer includes, but is not limited to, CVD, PVD, and ALD, or any combination thereof.

[0150] In some embodiments, the material of the third isolation layer includes but is not limited to silicon nitride.

[0151] As shown in FIG5E , a photoresist layer 254 is formed on the third isolation layer 252. The photoresist layer 254 covers the third isolation layer 252 in the peripheral region 204 and the fourth dielectric layer 244 in the fourth sub-trench 238 in the second sub-region 208. In other words, the orthographic projection of the third isolation structure 232 on the XY plane is within the range of the orthographic projection of the photoresist layer 254 on the XY plane, and the orthographic projection of the fourth dielectric layer 244 of the fourth sub-isolation structure 250 on the XY plane is within the range of the orthographic projection of the photoresist layer 254 on the XY plane.

[0152] As shown in FIG. 5E and FIG. 5F , the portion of the third isolation layer 252 not covered by the photoresist layer 254 is removed using the photoresist layer 254 as a mask to retain the portion of the third isolation layer 252 covered by the photoresist layer 254 ; the photoresist layer 254 is removed.

[0153] Illustratively, the photoresist layer may be removed using an ashing process.

[0154] 5F shows that the third isolation layer 252 covering the peripheral region 204 and the fourth dielectric layer 244 in the fourth sub-trench 238 of the second sub-region 208 are still retained. Thus, during subsequent processes, the third isolation layer can protect the third isolation structure in the peripheral region and the fourth dielectric layer in the fourth sub-trench of the second sub-region from damage.

[0155] In the embodiment of the present disclosure, at the same time as step S302, the manufacturing method further includes:

[0156] Portions of the third dielectric layer 240 in the third sub-trench 236 and the fourth sub-trench 238 are removed to expose at least portions of sidewalls of the active pillar 210 and at least portions of sidewalls of the second isolation layer 242 .

[0157] As shown in FIG5G , while removing a portion of the first dielectric layer 220 in the first sub-trench 214 and a portion of the first dielectric layer 220 and the second dielectric layer 224 in the second sub-trench 216, a portion of the third dielectric layer 240 in the third sub-trench 236 and a portion of the third dielectric layer 240 in the fourth sub-trench 238 are removed; wherein, the portion of the first dielectric layer 220 in the first sub-trench 214 is removed to expose the sidewall of the active pillar 210 parallel to the Y direction, the portion of the first dielectric layer 220 and the second dielectric layer 224 in the second sub-trench 216 is removed to expose the sidewall of the active pillar 210 parallel to the Y direction and the two sidewalls of the first isolation layer 222 parallel to the Y direction, and the portion of the third sub-trench 236 is removed. A portion of the third dielectric layer 240 in the fourth sub-trench 238 is removed to expose the sidewall of the active pillar 210 parallel to the X direction, and a portion of the third dielectric layer 240 in the fourth sub-trench 238 is removed to expose the sidewall of the active pillar 210 parallel to the X direction and a sidewall of the second isolation layer 242 of the device region 202 parallel to the X direction.

[0158] Here, the active pillar extends along the Z direction and may have two sidewalls parallel to the X direction and two sidewalls parallel to the Y direction. Removing the first dielectric layer, the second dielectric layer, and the third dielectric layer may expose the four sidewalls of the active pillar. Of course, the substrate surface, that is, the top surface of the active pillar, may also be exposed.

[0159] It should be noted that the height h0 of the exposed sidewall of the active pillar along the Z direction is less than the height h1 of the first trench along the Z direction, and the height h0 of the exposed sidewall of the active pillar along the Z direction is less than the height h2 of the second trench along the Z direction. The portion of the sidewall of the active pillar parallel to the Y direction is still covered by the first dielectric layer, and the portion of the sidewall of the active pillar parallel to the X direction is still covered by the third dielectric layer. As shown in the cross-sectional structural schematic diagram along the cc direction in Figure 5G, the height of the portion of the active pillar whose sidewall is covered by the first dielectric layer along the Z direction is (h1-h0); as shown in the cross-sectional structural schematic diagram along the aa direction in Figure 5G, the height of the portion of the active pillar whose sidewall is covered by the third dielectric layer along the Z direction is (h2-h0).

[0160] It should be noted that the two side walls of the exposed first isolation layer are parallel to the Y direction, and the two side walls of the unexposed first isolation layer are parallel to the Y direction and are in direct contact with the first dielectric layer and the second dielectric layer respectively. The surfaces of the first dielectric layer and the second dielectric layer in the second sub-groove are substantially flush, that is, the heights of the two side walls of the exposed first isolation layer along the Z direction are substantially the same. Of course, the height d1 of the side wall of the exposed first isolation layer along the Z direction is less than the height h1 of the second sub-groove along the Z direction. More specifically, the height d1 of the side wall of the exposed first isolation layer along the Z direction is substantially the same as the height h0 of the side wall of the exposed active column along the Z direction.

[0161] It should be noted that "substantially the same" means that the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction is less than a preset value. In other words, the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction meets the required process tolerance range. In one specific example, the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction is 0.

[0162] In the embodiment of the present disclosure, after removing a portion of the third dielectric layer 240 in the third sub-trench 236 and a portion of the third dielectric layer 240 in the fourth sub-trench 238 , the manufacturing method further includes:

[0163] removing the third isolation layer 252 covering the fourth dielectric layer 244 in the fourth sub-trench 238 ;

[0164] A portion of the fourth dielectric layer 244 in the fourth sub-trench 238 is removed; wherein the surface of the fourth dielectric layer 244 in the fourth sub-trench 238 is higher than the surface of the third dielectric layer 240 .

[0165] Still as shown in FIG5G , while removing the third isolation layer 252 covering the fourth dielectric layer 244 in the fourth sub-trench 238, the third isolation layer 252 covering the peripheral region 204 is also removed, thereby exposing the fourth dielectric layer 244 in the fourth sub-trench 238 and the second dielectric layer 224 in the third trench 218, respectively. A portion of the fourth dielectric layer 244 in the fourth sub-trench 238 is removed to expose the other sidewall of the second isolation layer 242 in the device region 202 parallel to the X direction. Finally, a portion of the second dielectric layer 224, a portion of the third dielectric layer 240, and a portion of the fourth dielectric layer 244 in the peripheral region 204 are removed to expose the surface of the substrate 200 and the two sidewalls of the second isolation layer 242 in the peripheral region 204 parallel to the Y direction.

[0166] It should be noted that, for the second sub-region of the device region, the exposed sidewalls of the second isolation layer parallel to the X-direction are in direct contact with the third and fourth dielectric layers, respectively. Of course, the height of the exposed sidewalls of the second isolation layer along the Z-direction is less than the height h2 of the fourth sub-trench along the Z-direction. The surface of the fourth dielectric layer in the fourth sub-trench is higher than the surface of the third dielectric layer; that is, the two sidewalls of the exposed second isolation layer have different heights along the Z-direction. More specifically, the height d2 of the exposed sidewall of the second isolation layer near the third dielectric layer along the Z-direction is greater than the height d3 of the exposed sidewall of the second isolation layer near the fourth dielectric layer along the Z-direction. In other words, the surfaces of the first and second dielectric layers in the second sub-trench and the third dielectric layer in the fourth sub-trench are substantially flush, and the surfaces of the first and second dielectric layers in the second sub-trench and the third dielectric layer in the fourth sub-trench are lower than the surface of the fourth dielectric layer in the fourth sub-trench. In one specific example, the surface of the fourth dielectric layer in the fourth sub-trench is substantially flush with the top surface of the active pillar.

[0167] It should be noted that, in the peripheral region, the exposed sidewalls of the second isolation layer are parallel to the Y direction, and the unexposed sidewalls of the second isolation layer are directly in contact with the third dielectric layer and the fourth dielectric layer, respectively. The surfaces of the third and fourth dielectric layers within the second trench within the third isolation structure extending into the peripheral region are substantially flush, that is, the height d4 of the two sidewalls of the exposed second isolation layer along the Z direction is substantially the same.

[0168] In the embodiment of the present disclosure, while removing the portion of the first isolation layer 222 exposed in the second sub-trench 216 , the manufacturing method further includes:

[0169] The portion of the second isolation layer 242 exposed in the fourth sub-trench 238 is removed.

[0170] As shown in FIG5H , the portion of the first isolation layer 222 exposed in the second sub-trench 216 is removed, as is the portion of the second isolation layer 242 exposed in the fourth sub-trench 238, and the portion of the second isolation layer 242 exposed in the third trench 218. As a result, the surfaces of the first dielectric layer 220, the first isolation layer 222, and the second dielectric layer 224 in the second sub-trench 216 are substantially flush; the remaining second isolation layer 242 in the fourth sub-trench 238 is completely covered by the fourth dielectric layer 244; and the surfaces of the third dielectric layer 240, the second isolation layer 242, and the fourth dielectric layer 244 extending from the second trench 234 to the third trench 218 are substantially flush.

[0171] In some embodiments, the process of removing the first isolation layer and the second isolation layer includes dry etching, wet etching, or a combination thereof. The embodiments of the present disclosure have no particular limitation on the process of removing the first isolation layer and the second isolation layer.

[0172] In the embodiment of the present disclosure, after removing the portion of the first isolation layer 222 exposed in the second sub-trench 216 , the manufacturing method further includes:

[0173] A plurality of word line structures 272 extending along the second direction are formed; the word line structures 272 cover the channel regions 266 of the active pillars 210 located in the same row.

[0174] In the embodiment of the present disclosure, the first sub-groove 214 and the second sub-groove 216 together form the first groove 212 , and the third sub-groove 236 and the fourth sub-groove 238 together form the second groove 234 ;

[0175] A plurality of word line structures 272 extending along the second direction are formed, including:

[0176] A gate dielectric layer 256 is formed in the first trench 212 and the second trench 234 to cover at least the channel region 266 of the active pillar 210 ;

[0177] A gate conductive layer 270 covering at least a portion of the gate dielectric layer 256 is formed in the first trench 212 and the second trench 234; the gate conductive layer 270 encapsulates the channel region 266 of the active pillars 210 located in the same row, and the gate conductive layers 270 in the first sub-trench 214 and the second sub-trench 216 are electrically connected; wherein the gate dielectric layer 256 and the gate conductive layer 270 together form a word line structure 272.

[0178] As shown in FIG. 5I , a gate dielectric layer 256 is formed in the first trench 212 and the second trench 234 to cover the four exposed sidewalls of the active pillar 210 . The gate dielectric layer 256 may also cover the top surface of the active pillar 210 .

[0179] In some embodiments, the gate dielectric layer may be formed by processes including, but not limited to, CVD, PVD, and ALD, or any combination thereof. In other embodiments, the gate dielectric layer may be formed using an in-situ oxidation process, for example, by oxidizing the exposed sidewalls and top surfaces of the active pillars to form the gate dielectric layer.

[0180] In some embodiments, the material of the gate dielectric layer includes but is not limited to silicon dioxide.

[0181] As shown in FIG5J , a conductive material layer 258 is formed, covering the device region 202 and the peripheral region 204. As previously described, the surfaces of the first dielectric layer 220, the second dielectric layer 224, and the third dielectric layer 240 are substantially flush, and the surfaces of the first dielectric layer 220, the second dielectric layer 224, and the third dielectric layer 240 are lower than the surface of the fourth dielectric layer 244. Therefore, the conductive material layer 258 can completely fill the first sub-trench 214, the third sub-trench 236, and the fourth sub-trench 238, but does not completely fill the second sub-trench 216.

[0182] In some embodiments, the process of forming the conductive material layer includes, but is not limited to, CVD, PVD, and ALD, or any combination thereof.

[0183] In some embodiments, the material of the conductive material layer includes but is not limited to titanium nitride or a metal material, such as metal tungsten.

[0184] In the embodiment of the present disclosure, a gate conductive layer 270 covering at least a portion of the gate dielectric layer 256 is formed in the first trench 212 and the second trench 234, including:

[0185] forming a conductive material layer 258 , wherein the conductive material layer 258 fills the first trench 212 and the second trench 234 ;

[0186] removing the conductive material layer 258 covering the second end 264 of the active pillar;

[0187] forming a fourth isolation layer 268 , wherein the fourth isolation layer 268 fills the first trench 212 and the second trench 234 ;

[0188] The fourth isolation layer 268 and the conductive material layer 258 in the second trench 234 are sequentially etched to form a word line trench and a gate conductive layer 270 . The word line trench extends along the second direction. The gate conductive layer 270 in the second sub-trench 216 is in direct contact with the gate dielectric layer 256 . The gate conductive layer 270 in the fourth sub-trench 238 is in direct contact with the fourth dielectric layer 244 .

[0189] An isolation material is filled in the word line trench to form a word line isolation structure 274 .

[0190] 5K , an insulating layer 260 is formed, covering the device region 202 and the peripheral region 204. As previously described, the conductive material layer 258 fills the first sub-trench 214, the third sub-trench 236, and the fourth sub-trench 238, but does not fill the second sub-trench 216. Therefore, the insulating layer 260 may fill the second sub-trench 216.

[0191] In some embodiments, the process of forming the insulating layer includes, but is not limited to, ALD.

[0192] In some embodiments, the material of the insulating layer includes but is not limited to silicon dioxide.

[0193] As shown in FIG. 5L , the insulating layer 260 may be planarized to expose the conductive material layer 258 .

[0194] In some embodiments, the planarization process may include, but is not limited to, CMP.

[0195] As shown in FIG5M , a portion of the conductive material layer 258 is etched away to expose the second end 264 of the active pillar, and the remaining conductive material layer 258 covers the channel region 266 of the active pillar. Here, the gate dielectric layer 256 located on the top surface of the active pillar 210 can also be removed, leaving only the gate dielectric layer 256 covering the sidewalls of the active pillar 210. That is, the gate dielectric layer 256 can cover the channel region 266 and the second end 264 of the active pillar 210.

[0196] It should be noted that the surfaces of the remaining conductive material layers in the first and second sub-grooves are basically flush, and part of the remaining conductive material layer in the second sub-grooves is covered with an insulating layer; the surfaces of the remaining conductive material layers in the third and fourth sub-grooves are basically flush.

[0197] As shown in Figure 5N, a fourth isolation layer 268 is formed in the first trench 212 and the second trench 234, and the fourth isolation layer 268 covers the surface of the remaining conductive material layer 258 located in the first sub-trench 214, the second sub-trench 216, the third sub-trench 236 and the fourth sub-trench 238; wherein the fourth isolation layer 268 fills the first sub-trench 214, the second sub-trench 216, the third sub-trench 236 and the fourth sub-trench 238.

[0198] Exemplarily, a fourth isolation material layer is formed in the first trench and the second trench, and the fourth isolation material layer may cover the top surface of the active pillar; the fourth isolation material layer is planarized or etched back to remove a portion of the fourth isolation material layer to expose the top surface of the active pillar, so that the remaining surface of the fourth isolation material layer is basically flush with the top surface of the active pillar, and the remaining fourth isolation material layer is used as the fourth isolation layer.

[0199] In some embodiments, the process of forming the fourth isolation layer includes, but is not limited to, CVD, PVD, and ALD, or any combination thereof.

[0200] In some embodiments, the material of the fourth isolation layer includes but is not limited to silicon nitride.

[0201] Still as shown in FIG. 5N and FIG. 5O , the fourth isolation layer 268 and the remaining conductive material layer 258 in the second trench 234 may be etched in sequence to form a word line trench and a gate conductive layer 270 ; wherein the word line trench extends along the X direction; and an isolation material may be filled in the word line trench to form a word line isolation structure 274 .

[0202] Here, the purpose of forming the word line isolation structure is to isolate different word line structures.

[0203] Here, the gate conductive layer of the word line structure may be a composite conductive layer, for example, the gate conductive layer may include titanium nitride and metal tungsten. The embodiment of the present disclosure has no particular limitation on the number of layers and materials of the gate conductive layer.

[0204] In the disclosed embodiment, the wordline structure extending along the X-direction includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers the channel regions of the active pillars located in the same row, and the gate conductive layer covers the gate dielectric layer of the channel regions of the active pillars located in the same row. The gate conductive layer and the gate dielectric layer in the second sub-trench are in direct contact, that is, the gate conductive layer in the second sub-trench is not isolated by the first isolation layer. Thus, the gate conductive layer in the first sub-trench is electrically connected to the gate conductive layer in the second sub-trench. In other words, the ends of the wordline structure in the first sub-region and the wordline structure in the second sub-region can be electrically connected, eliminating the risk of wordline structure disconnection.

[0205] In the embodiment of the present disclosure, different word line structures are isolated by the word line isolation structure, and the gate conductive layer in the fourth sub-trench is in direct contact with the fourth dielectric layer, that is, the gate conductive layer in the fourth sub-trench is not in contact with the second isolation layer; in this way, the second isolation layer in the fourth sub-trench is buried under the fourth dielectric layer, which can prevent the second isolation layer exposed in the fourth sub-trench from contaminating the subsequently formed bit line structure.

[0206] In the embodiment of the present disclosure, after removing the portion of the first isolation layer 222 exposed in the second sub-trench 216 , the manufacturing method further includes:

[0207] A plurality of bit line structures 276 extending along a first direction are formed; the bit line structures 276 sequentially connect the first ends 262 of the active pillars 210 located in the same column;

[0208] A plurality of storage capacitors are formed; a first electrode of the storage capacitor is connected to the second end 264 of the active pillar, and a second electrode of the storage capacitor is connected to the common end.

[0209] Here, a bit line structure extending along the Y direction can also be formed, which connects the first ends of the active pillars in the same column in sequence; the first electrode of the storage capacitor is connected to the second end of the active pillar, and the second electrode of the storage capacitor is connected to the common end.

[0210] It should be noted that in the embodiment of the present disclosure, the first end of the active column can be, for example, a source, and the second end of the active column can be, for example, a drain; or, the first end of the active column can be, for example, a drain, and the second end of the active column can be, for example, a source.

[0211] In the disclosed embodiment, portions of the first dielectric layer within the first sub-trench and portions of the first dielectric layer and the second dielectric layer within the second sub-trench are removed to expose at least portions of the sidewalls of the active pillar and portions of the sidewalls of the first isolation layer, respectively. Portions of the first isolation layer exposed within the second sub-trench are removed. Thus, during the formation of the wordline structure, the wordline structures within the first sub-trench and the second sub-trench can be electrically connected, i.e., the wordline structure located in the first sub-region for connecting the gates of the memory cells in the same row and the end of the wordline structure located in the second sub-region can be electrically connected. Furthermore, while removing the portion of the first isolation layer exposed within the second sub-trench, the portion of the second isolation layer exposed within the fourth sub-trench can also be removed to prevent the exposed second isolation layer from contaminating the subsequently formed bitline structure.

[0212] Referring to Figures 6 and 7, Figure 6 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present disclosure, and Figure 7 is a schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure. As shown in Figures 6 and 7, an embodiment of the present disclosure provides a semiconductor device, which includes:

[0213] The substrate 200 includes a device region 202 and a peripheral region 204 . The device region 202 includes a first sub-region 206 and a second sub-region 208 . The second sub-region 208 is located between the first sub-region 206 and the peripheral region 204 .

[0214] The substrate 200 of the device region 202 includes a plurality of first trenches 212 extending along a first direction and a plurality of second trenches 234 extending along a second direction. The first trenches 212 and the second trenches 234 together isolate a plurality of active pillars 210. The active pillars 210 include first and second ends 262 and 264 oppositely disposed along a third direction, and a channel region 266 located between the first and second ends 262 and 264. The first trenches 212 include a first sub-trench 214 located in the first sub-region 206 and a second sub-trench 216 located in the second sub-region 208. The first and second directions are both parallel to the substrate 200 and intersect with each other, and the third direction is perpendicular to the substrate 200.

[0215] A plurality of word line structures 272 extending along the second direction are located in the first trench 212 and the second trench 234 ; the word line structures 272 cover the channel regions 266 of the active pillars located in the same row; wherein the word line structures 272 in the first sub-trench 214 and the word line structures 272 in the second sub-trench 216 are electrically connected.

[0216] The dashed box in the cross-sectional structural diagram along the cc direction in FIG. 7 illustrates the active pillar 210 . The active pillar 210 includes a first end 262 and a second end 264 that are oppositely arranged along the Z direction, and a channel region 266 located between the first end 262 and the second end 264 .

[0217] In the embodiment of the present disclosure, the word line structures in the first sub-trench and the second sub-trench can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.

[0218] In the embodiment of the present disclosure, the semiconductor device further includes:

[0219] The fourth isolation layer 268 extending along the second direction is located in the first trench 212 and the second trench 234 ; the fourth isolation layer 268 covers the second ends 264 of the active pillars 210 located in the same row;

[0220] A plurality of word line isolation structures 274 extending along the second direction are located between adjacent word line structures 272 and adjacent fourth isolation layers 268 .

[0221] Here, the word line isolation structure 274 extends along the X direction, a portion of the word line isolation structure 274 is located between adjacent word line structures 272 , and a portion of the word line isolation structure 274 is located between adjacent fourth isolation layers 268 .

[0222] In the embodiment of the present disclosure, the word line structure 272 includes: a gate dielectric layer 256 , at least covering the channel region 266 of the active pillar 210 ;

[0223] The gate conductive layer 270 is located on the surface of the gate dielectric layer 256 and covers the channel region 266 of the active pillars 210 located in the same row; wherein, the gate conductive layer 270 in the first sub-trench 214 and the second sub-trench 216 are electrically connected, and the gate conductive layer 270 in the second sub-trench 216 is in direct contact with the gate dielectric layer 256.

[0224] In the embodiment of the present disclosure, the semiconductor device further includes:

[0225] a first dielectric layer 220 located in the first sub-trench 214 and the second sub-trench 216 , wherein the first dielectric layer 220 is located between the first ends 262 of adjacent active pillars 210 and covers the sidewalls and bottom of the second sub-trench 216 ;

[0226] a first isolation layer 222 of the first dielectric layer 220 covering the sidewalls and the bottom of the second sub-trench 216;

[0227] The second dielectric layer 224 is located in the second sub-trench 216 , and the second dielectric layer 224 is located below the gate conductive layer 270 .

[0228] Here, the surfaces of the first dielectric layer 220, the first isolation layer 222, and the second dielectric layer 224 in the second sub-trench 216 are substantially flush; the first dielectric layer 220 covers the bottom and a portion of the sidewalls of the second sub-trench 216, the first isolation layer 222 covers the first dielectric layer 220, and the second dielectric layer 224 covers the first isolation layer 222; the gate conductive layer 270 in the second sub-trench 216 is located above the first dielectric layer 220, the first isolation layer 222, and the second dielectric layer 224; and the fourth isolation layer 268 and the insulating layer 260 are also located in the second sub-trench 216, and the fourth isolation layer 268 and the insulating layer 260 are located above the gate conductive layer 270.

[0229] In other words, the top surface of the second dielectric layer 224 is in direct contact with the gate conductive layer 270. The orthographic projections of the first dielectric layer 220, the first isolation layer 222, and the second dielectric layer 224 in the second sub-trench 216 on the XY plane are located within the orthographic projection of the gate conductive layer in the second sub-trench 216 on the XY plane.

[0230] In the embodiment of the present disclosure, the second trench 234 includes a third sub-trench 236 located in the first sub-region 206 and a fourth sub-trench 238 located in the second sub-region 208 ; the semiconductor device further includes:

[0231] a third dielectric layer 240 located in the third sub-trench 236 and the fourth sub-trench 238 , wherein the third dielectric layer 240 is located between the first ends 262 of adjacent active pillars 210 and covers the sidewalls and bottom of the fourth sub-trench 238 ;

[0232] a second isolation layer 242 of the third dielectric layer 240 covering the bottom of the fourth sub-trench 238;

[0233] The fourth dielectric layer 244 is located in the fourth sub-trench 238 , and the sidewalls of the fourth dielectric layer 244 are in direct contact with the gate conductive layer 270 and the fourth isolation layer 268 .

[0234] Here, the third dielectric layer 240 covers the bottom and a portion of the sidewalls of the fourth sub-trench 238, the second isolation layer 242 covers a portion of the third dielectric layer 240, and the fourth dielectric layer 244 covers the second isolation layer 242. That is, the orthographic projection of the second isolation layer 242 on the XY plane is within the orthographic projection of the fourth dielectric layer 244 on the XY plane. The gate conductive layer 270 is located above the third dielectric layer 240, and the fourth isolation layer 268 is located above the gate conductive layer 270; the surfaces of the fourth isolation layer 268 and the fourth dielectric layer 244 are substantially flush.

[0235] In other words, the sidewalls of the fourth dielectric layer 244 parallel to the X direction are in direct contact with the gate conductive layer 270. The orthographic projections of the second isolation layer 242 and the fourth dielectric layer 244 in the fourth sub-trench 238 on the XY plane are outside the orthographic projection of the gate conductive layer in the second sub-trench 216 on the XY plane.

[0236] In the embodiment of the present disclosure, the semiconductor device further includes:

[0237] A third isolation structure 232 located in the peripheral region 204 and extending along the first direction, the third isolation structure 232 includes a first portion 278 and a second portion 280 , and the portion of the second trench 234 extending into the third isolation structure 232 is the second portion 280 ;

[0238] The first portion 278 (as shown by the dashed box in the cross-sectional structural diagram along the ee direction in FIG7 ) includes a first dielectric layer 220 , a first isolation layer 222 , and a second dielectric layer 224 covering the first isolation layer 222 , which sequentially cover the sidewalls and bottom of the third trench 218 .

[0239] The second portion 280 (as shown by the dotted box in the cross-sectional structural diagram in the ee direction in FIG7 ) includes a third dielectric layer 240 and a second isolation layer 242 that sequentially cover the second trench 234 and extend to at least a portion of the sidewalls and bottom of the third isolation structure 232, and a fourth dielectric layer 244 that fills the second trench 234 and extends to a portion of the third isolation structure 232.

[0240] In the embodiment of the present disclosure, the semiconductor device further includes:

[0241] A plurality of bit line structures 276 are extended along a first direction, and the bit line structures 276 sequentially connect the first ends 262 of the active pillars 210 located in the same column;

[0242] a plurality of storage capacitors; a first electrode of the storage capacitor is connected to the second end 264 of the active pillar 210, and a second electrode of the storage capacitor is connected to the common end.

[0243] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a portion of the first dielectric layer within the first sub-trench and a portion of the first dielectric layer within the second sub-trench are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively. The portion of the first isolation layer exposed within the second sub-trench is removed. Thus, during the subsequent formation of a wordline structure, the wordline structures within the first sub-trench and the second sub-trench can be electrically connected. Specifically, the wordline structure located in the first sub-region and used to connect the gates of memory cells in the same row can be electrically connected to the end of the wordline structure located in the second sub-region.

[0244] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0245] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure. Industrial Applicability

[0246] In the embodiment of the present disclosure, part of the first dielectric layer in the first sub-trench and part of the first dielectric layer and the second dielectric layer in the second sub-trench are removed to expose at least part of the sidewall of the active pillar and at least part of the sidewall of the first isolation layer, respectively; the part of the first isolation layer exposed in the second sub-trench is removed; in this way, in the subsequent process of forming the word line structure, the word line structures in the first sub-trench and the second sub-trench can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A substrate (100) is provided, wherein the substrate (100) comprises a device region (102) and a peripheral region (104), wherein the device region (102) comprises a first sub-region (106) and a second sub-region (108), wherein the second sub-region (108) is located between the first sub-region (106) and the peripheral region (104); the substrate (100) of the device region (102) comprises a plurality of first isolation structures (226) extending along a first direction and a plurality of second isolation structures (246) extending along a second direction, wherein the first isolation structures (226) and the second isolation structures (246) jointly isolate a plurality of active pillars (110); and the first isolation structures (2 26) comprises a first sub-isolation structure (228) located in the first sub-region (106) and a second sub-isolation structure (230) located in the second sub-region (208), wherein the first sub-isolation structure (228) comprises a first dielectric layer (220) filling up the first sub-groove (214), and the second sub-isolation structure (230) comprises a first dielectric layer (220) sequentially covering the sidewall and bottom of the second sub-groove (216), a first isolation layer (222), and a second dielectric layer (224) filling up the second sub-groove (216); wherein the first direction and the second direction are both parallel to the substrate (100) and the first direction and the second direction intersect; Removing a portion of the first dielectric layer (214) in the first sub-groove (214) and a portion of the first dielectric layer (214) and the second dielectric layer (224) in the second sub-groove (216) to expose at least a portion of the sidewall of the active pillar (110) and at least a portion of the sidewall of the first isolation layer (222), respectively; The portion of the first isolation layer (222) exposed in the second sub-trench (216) is removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The second isolation structure (246) comprises a third sub-isolation structure (248) located in the first sub-region (206) and a fourth sub-isolation structure (250) located in the second sub-region (208), wherein the third sub-isolation structure (248) comprises a third dielectric layer (240) filling up the third sub-trench (236), and the fourth sub-isolation structure (250) comprises a third dielectric layer (240) sequentially covering the sidewall and bottom of the fourth sub-trench (238), a second isolation layer (242), and a fourth dielectric layer (244) filling up the fourth sub-trench (238); Before removing a portion of the first dielectric layer (220) in the first sub-groove (214) and a portion of the first dielectric layer (220) and the second dielectric layer (224) in the second sub-groove (216), the manufacturing method further comprises: forming a third isolation layer (252), wherein the third isolation layer (252) covers the first isolation structure (226) and the second isolation structure (246) of the device region (102); A portion of the third isolation layer (252) is removed to retain the third isolation layer (252) covering the fourth dielectric layer (244) in the fourth sub-trench (238).

3. The method for manufacturing a semiconductor device according to claim 2, wherein: While removing a portion of the first dielectric layer (220) in the first sub-groove (214) and a portion of the first dielectric layer (220) and the second dielectric layer (224) in the second sub-groove (216), the manufacturing method further comprises: A portion of the third dielectric layer (240) in the third sub-trench (236) and a portion of the third dielectric layer (240) in the fourth sub-trench (238) are removed to expose at least a portion of the sidewall of the active pillar (110) and at least a portion of the sidewall of the second isolation layer (242).

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After removing a portion of the third dielectric layer (240) in the third sub-groove (236) and a portion of the third dielectric layer (240) in the fourth sub-groove (238), the manufacturing method further comprises: removing the third isolation layer (252) covering the fourth dielectric layer (244) in the fourth sub-groove (238); A portion of the fourth dielectric layer (244) in the fourth sub-groove (238) is removed; wherein the surface of the fourth dielectric layer (244) in the fourth sub-groove (238) is higher than the surface of the third dielectric layer (240).

5. The method for manufacturing a semiconductor device according to claim 4, wherein: While removing the portion of the first isolation layer (222) exposed in the second sub-groove (216), the manufacturing method further comprises: The portion of the second isolation layer (242) exposed in the fourth sub-trench (238) is removed.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The active pillar (210) comprises a first end (262) and a second end (264) arranged opposite to each other along a third direction, and a channel region (266) located between the first end (262) and the second end (264); the third direction is perpendicular to the substrate (100); After removing the portion of the first isolation layer (222) exposed in the second sub-groove (216), the manufacturing method further comprises: A plurality of word line structures (272) extending along the second direction are formed; the word line structures (272) cover the channel regions (266) of the active pillars (210) located in the same row.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first sub-groove (114) and the second sub-groove (116) together form a first groove (112), and the third sub-groove (120) and the fourth sub-groove (122) together form a second groove (118); The forming of a plurality of word line structures (272) extending along the second direction comprises: A gate dielectric layer (256) is formed in the first trench (112) and the second trench (118) to at least cover the channel region (266) of the active pillar (210); A gate conductive layer (270) is formed in the first trench (112) and the second trench (118) to cover at least a portion of the gate dielectric layer (256); the gate conductive layer (270) covers the channel region (266) of the active pillars (210) located in the same row, and the gate conductive layers in the first sub-trench (114) and the second sub-trench (116) are electrically connected; wherein the gate dielectric layer (256) and the gate conductive layer (270) together form a word line structure (272).

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming a gate conductive layer (270) in the first trench (112) and the second trench (118) to cover at least a portion of the gate dielectric layer (256) comprises: forming a conductive material layer (258), wherein the conductive material layer (258) fills the first trench (112) and the second trench (118); removing the conductive material layer (258) covering the second end (264) of the active pillar (210); forming a fourth isolation layer (268), wherein the fourth isolation layer (268) fills the first trench (212) and the second trench (234); The fourth isolation layer (268) and the conductive material layer (258) in the second trench (234) are sequentially etched to form a word line trench and a gate conductive layer (270); wherein the word line trench extends along the second direction; the gate conductive layer (270) in the second sub-trench (216) is in direct contact with the gate dielectric layer (256); and the gate conductive layer (270) in the fourth sub-trench (238) is in direct contact with the fourth dielectric layer (244); An isolation material is filled in the word line isolation trench to form a word line isolation structure (274).

9. The method for manufacturing a semiconductor device according to any one of claims 6 to 8, wherein: After removing the portion of the first isolation layer (222) exposed in the second sub-groove (216), the manufacturing method further comprises: A plurality of bit line structures (276) extending along the first direction are formed; the bit line structures (276) sequentially connect the first ends (262) of the active pillars (210) located in the same column; A plurality of storage capacitors are formed; a first electrode of the storage capacitor is connected to the second end (264) of the active column (210), and a second electrode of the storage capacitor is connected to a common end.

10. The method for manufacturing a semiconductor device according to any one of claims 2 to 9, wherein: The providing of a substrate (200) comprises: The substrate (200) is etched to form a first trench (212) in the device region (202) and a third trench (218) in the peripheral region (204); the first trench (212) and the third trench (218) both extend along the first direction; the first trench (212) includes a first sub-trench (214) located in the first sub-region (206) and a second sub-trench (216) located in the second sub-region (208); forming a first dielectric layer (220), wherein the first dielectric layer (220) covers the sidewalls and bottom of the second sub-trench (216) and the third trench (218), and the first dielectric layer (220) fills the first sub-trench (214) to form a first sub-isolation structure (228); forming a first isolation layer (222), wherein the first isolation layer (222) covers the first dielectric layer (220); A second dielectric layer (224) is formed, and the second dielectric layer (224) fills the second sub-trench (216) and the third trench (218) to form a second sub-isolation structure (230) and a third isolation structure (232) respectively.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The providing of a substrate (200) further comprises: The substrate (200), the first dielectric layer (220) and the second dielectric layer (224) are etched to form a second trench (234) in the device region (202), wherein the second trench (234) further extends into the third trench (218) in the peripheral region (204); the second trench (234) extends along the second direction; the second trench (234) includes a third sub-trench (236) located in the first sub-region (206) and a fourth sub-trench (238) located in the second sub-region (208); forming a third dielectric layer (240), wherein the third dielectric layer (240) covers the sidewalls and the bottom of the fourth sub-trench (238), and the third dielectric layer (240) fills the third sub-trench (236) to form a third sub-isolation structure (248); forming a second isolation layer (242), wherein the second isolation layer (242) covers the third dielectric layer (240); A fourth dielectric layer (244) is formed, and the fourth dielectric layer (244) fills the fourth sub-trench (238) to form a fourth sub-isolation structure (250).

12. A semiconductor device, comprising: A substrate (200); the substrate (200) comprises a device region (202) and a peripheral region (204); the device region (202) comprises a first sub-region (206) and a second sub-region (208); the second sub-region (208) is located between the first sub-region (206) and the peripheral region (204); The substrate (200) of the device region (202) comprises a plurality of first trenches (212) extending along a first direction and a plurality of second trenches (234) extending along a second direction, wherein the first trenches (212) and the second trenches (234) together isolate a plurality of active pillars (210); the active pillars (210) comprise a first end (262) and a second end (264) arranged opposite to each other along a third direction, and a channel region (266) located between the first end (262) and the second end (264); the first trench (212) comprises a first sub-trench (214) located in the first sub-region (206) and a second sub-trench (216) located in the second sub-region (208); wherein the first direction and the second direction are both parallel to the substrate (200) and the first direction and the second direction intersect, and the third direction is perpendicular to the substrate (200); A plurality of word line structures (272) extending along the second direction are located in the first trench (212) and the second trench (234); the word line structures (272) cover the channel regions (266) of the active pillars (210) located in the same row; wherein the first sub-trench (214) The word line structure (272) in the second sub-trench (216) is electrically connected to the word line structure (272) in the second sub-trench (216).

13. The semiconductor device according to claim 12, wherein: The semiconductor device further comprises: A fourth isolation layer (268) extending along the second direction and located in the first trench (212) and the second trench (234); the fourth isolation layer (268) covers the second ends (264) of the active pillars (210) located in the same row; A plurality of word line isolation structures (274) extending along the second direction are located between adjacent word line structures (272) and adjacent fourth isolation layers (268).

14. The semiconductor device according to claim 13, wherein: The word line structure (272) comprises: A gate dielectric layer (256) at least covers the channel region (266) of the active column (210); A gate conductive layer (270) is located on the surface of the gate dielectric layer (256) and covers the channel region (266) of the active pillars (210) located in the same row; wherein the gate conductive layer (270) in the first sub-groove (214) and the second sub-groove (216) are electrically connected, and the gate conductive layer (270) in the second sub-groove (216) is in direct contact with the gate dielectric layer (256).

15. The semiconductor device according to claim 14, wherein: The semiconductor device further comprises: A first dielectric layer (220) located in the first sub-groove (214) and the second sub-groove (216), wherein the first dielectric layer (220) is located between first ends (262) of adjacent active pillars (210) and the first dielectric layer (220) covers the sidewall and bottom of the second sub-groove (216); a first isolation layer (222) of the first dielectric layer (220) covering the sidewalls and bottom of the second sub-groove (216); A second dielectric layer (224) is located in the second sub-groove (216), and the second dielectric layer (224) is located below the gate conductive layer.

16. The semiconductor device according to claim 14 or 15, wherein: The second trench (234) includes a third sub-trench (236) located in the first sub-region (206) and a fourth sub-trench (238) located in the second sub-region (208); the semiconductor device further includes: A third dielectric layer (240) located in the third sub-groove (236) and the fourth sub-groove (238), wherein the third dielectric layer (240) is located between the first ends (262) of the adjacent active pillars (210) and covers the sidewall and bottom of the fourth sub-groove (238); a second isolation layer (242) of the third dielectric layer (240) covering the bottom of the fourth sub-groove (238); A fourth dielectric layer (244) is located in the fourth sub-trench (238), and a sidewall of the fourth dielectric layer (244) is in direct contact with the gate conductive layer (270) and the fourth isolation layer (268).

17. The semiconductor device according to claim 16, wherein: The semiconductor device further comprises: a third isolation structure (232) located in the peripheral region (204) and extending along the first direction, the third isolation structure (232) comprising a first portion and a second portion, the portion of the second trench (234) extending into the third isolation structure (232) being the second portion; The first part includes a first dielectric layer (220) sequentially covering the sidewall and bottom of the third trench (218), a first isolation layer (222), and a second dielectric layer (224) covering the first isolation layer (222); The second portion includes a third dielectric layer (240) and a second isolation layer (242) which sequentially cover the second trench (234) and extend to at least a portion of the sidewall and bottom of the third isolation structure (232), and a fourth dielectric layer (244) which fills the second trench (234) and extends to a portion of the third isolation structure (232).

18. The semiconductor device according to any one of claims 12 to 17, wherein: The semiconductor device further comprises: A plurality of bit line structures (276) are extended along the first direction, wherein the bit line structures (276) sequentially connect the first ends (262) of the active pillars (210) located in the same column; A plurality of storage capacitors; a first electrode of the storage capacitor is connected to the second end (264) of the active column (210), and a second electrode of the storage capacitor is connected to a common end.

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