Firmware upgrading method and apparatus, BMC chip, server and medium

Abstract

The present application relates to the technical field of computers. Disclosed are a firmware upgrading method and apparatus, a BMC chip, a server and a medium. The method comprises: powering on a coprocessor, loading same with a coprocessor system, and initializing inter-core communication with a main processor; powering on the main processor and loading same with a main processor system, and releasing a bus control right by means of loading a bus driver; the main processor sending a bus control right release message to the coprocessor; in response to the bus control right release message, the coprocessor taking over the bus control right; the main processor sending new firmware and a firmware upgrading message to the coprocessor; and, in response to the firmware upgrading message, the coprocessor writing the new firmware into a corresponding server hardware module by means of a bus, so as to upgrade firmware of the server hardware module.

Description

Firmware upgrade method, device, BMC chip, server and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310694567.2, and entitled “A firmware upgrade method, device, BMC chip, server and medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to a firmware upgrade method, device, BMC chip, server and medium. Background Art

[0004] The Baseboard Management Controller (BMC) is a controller chip that manages device information, monitors status, remotely controls, and maintains servers. With the continuous upgrading of BMCs, the new generation of BMC chips, AST2600, has significantly improved performance compared to the previous generation, providing the possibility for server motherboards to achieve more functions. The AST2600 chip provides three ARM (Advanced RISC Machines) processors, which is two more processors than the previous generation, specifically including two Cortex A7 main processors and one Cortex M3 coprocessor. At present, BMC chips with multiple processors like this upgrade the relevant firmware of the server through the main processor (such as Cortex A7), and the coprocessor (such as Cortex M3) is in an idle state. The inventors realized that the effective use of coprocessors has always been a problem, which makes the main processor heavy and the overall performance of the BMC chip low.

[0005] Summary of the Invention

[0006] According to various embodiments disclosed in the present application, in a first aspect, a firmware upgrade method is provided, which is applied to a coprocessor, and the method includes: powering on and loading the coprocessor system, and establishing inter-core communication with the main processor; receiving a bus control release message sent by the main processor, the bus control release message being a notification message sent by the main processor after the main processor is powered on and loaded with the main processor system, and releasing the bus control right by loading the bus driver; taking over the bus control right in response to the bus control release message; receiving new firmware and a firmware upgrade message sent by the main processor; and writing the new firmware into the corresponding server hardware module through the bus in response to the firmware upgrade message to upgrade the firmware of the server hardware module.

[0007] According to various embodiments disclosed in the present application, in a second aspect, a firmware upgrade method is provided, which is applied to a main processor, and the method includes: powering on and loading the main processor system, and releasing bus control rights by loading a bus driver; when the coprocessor is powered on and loads the coprocessor system and completes the establishment of inter-core communication with the main processor, sending a bus control rights release message to the coprocessor, so that the coprocessor responds to the bus control rights release message and takes over the bus control rights; sending new firmware and a firmware upgrade message to the coprocessor, so that the coprocessor responds to the firmware upgrade message and writes the new firmware to the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

[0008] According to various embodiments disclosed in the present application, in a third aspect, a firmware upgrade method is provided, the method comprising: the coprocessor is powered on to load the coprocessor system and establish inter-core communication with the main processor; the main processor is powered on to load the main processor system and releases bus control rights by loading the bus driver; when the coprocessor is powered on to load the coprocessor system and establishes inter-core communication with the main processor, the main processor sends a bus control rights release message to the coprocessor; the coprocessor receives the bus control rights release message sent by the main processor; the coprocessor takes over the bus control rights in response to the bus control rights release message; the main processor sends new firmware and a firmware upgrade message to the coprocessor; the coprocessor receives the new firmware and the firmware upgrade message sent by the main processor; the coprocessor responds to the firmware upgrade message and writes the new firmware into the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

[0009] According to the various embodiments disclosed in the present application, in a fourth aspect, a firmware upgrade device is provided, which is applied to a coprocessor, and the device includes: an initialization module for powering on and loading the coprocessor system, and initializing inter-core communication with the main processor; a control right message receiving module for receiving a bus control right release message sent by the main processor, the bus control right release message is a notification message sent by the main processor after the main processor is powered on and loaded with the main processor system, and the bus control right is released by loading the bus driver; a control right takeover module for taking over the bus control right in response to the bus control right release message; a firmware receiving module for receiving new firmware and firmware upgrade messages sent by the main processor; a firmware upgrade module for writing the new firmware to the corresponding server hardware module through the bus in response to the firmware upgrade message, so as to upgrade the firmware of the server hardware module.

[0010] According to the various embodiments disclosed in the present application, in a fifth aspect, a firmware upgrade device is provided, which is applied to a main processor, and the device includes: a control right release module, which is used to power on and load the main processor system, and release the bus control right by loading the bus driver; a control right message sending module, which is used to send a bus control right release message to the coprocessor when the coprocessor is powered on to load the coprocessor system and initialize the inter-core communication with the main processor, so that the coprocessor responds to the bus control right release message and takes over the bus control right; a firmware sending module, which is used to send new firmware and a firmware upgrade message to the coprocessor, so that the coprocessor responds to the firmware upgrade message and writes the new firmware to the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

[0011] According to various embodiments disclosed in the present application, in a sixth aspect, a BMC chip is provided, comprising: a coprocessor, a main processor, and a memory, wherein the memory is communicatively connected to the coprocessor and the main processor, respectively, and computer instructions are stored in the memory. The coprocessor executes the computer instructions to thereby execute the method of the above-mentioned first aspect or any corresponding embodiment thereof, and the main processor executes the computer instructions to thereby execute the method of the above-mentioned second aspect or any corresponding embodiment thereof.

[0012] According to various embodiments disclosed in the present application, in a seventh aspect, a computer-readable storage medium is provided, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the method of the above-mentioned first aspect, second aspect or any corresponding embodiment thereof.

[0013] According to various embodiments disclosed in the present application, in an eighth aspect, a server is provided, comprising a server motherboard and a BMC chip, wherein the BMC chip is communicatively connected to each hardware module on the server motherboard, and the BMC chip stores computer instructions, and the BMC chip executes the computer instructions to cause the BMC chip to execute the method of the first aspect, the second aspect, or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] FIG1 is a schematic diagram of a first interactive process of a firmware upgrade method according to one or more embodiments of the present application;

[0016] FIG2 is a schematic diagram of a second interactive process of a firmware upgrade method according to one or more embodiments of the present application;

[0017] FIG3 is a schematic diagram of a third interactive process of a firmware upgrade method according to one or more embodiments of the present application;

[0018] FIG4 is a schematic diagram of a fourth interactive process of a firmware upgrade method according to one or more embodiments of the present application;

[0019] FIG5 is a schematic diagram of a fifth interactive flow of a firmware upgrade method according to one or more embodiments of the present application;

[0020] FIG6 is a schematic diagram of a sixth interactive flow of a firmware upgrade method according to one or more embodiments of the present application;

[0021] FIG7 is a schematic structural diagram of a firmware upgrade device according to one or more embodiments of the present application;

[0022] FIG8 is a structural diagram of a firmware upgrade device according to one or more embodiments of the present application;

[0023] FIG9 is a schematic diagram of the hardware structure of a BMC chip according to one or more embodiments of the present application;

[0024] FIG10 is a schematic diagram of the hardware structure of a server according to one or more embodiments of the present application;

[0025] FIG11 is a flow chart of a firmware upgrade method applied to a coprocessor according to one or more embodiments of the present application;

[0026] FIG12 is a flowchart of a firmware upgrade method applied to a main processor according to one or more embodiments of the present application;

[0027] FIG13 is a schematic diagram of the structure of a non-volatile computer-readable storage medium according to one or more embodiments of the present application. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0029] The new generation BMC chip, the AST2600, offers three ARM processors, two more than the previous generation. These include two Cortex A7 main processors and one Cortex M3 coprocessor. In the future, multi-processor BMC chips are expected to become mainstream. Currently, server firmware upgrades for multi-processor BMC chips like these are performed by the main processor, leaving the coprocessor idle. For example, in the AST2600, the main Cortex A7 processor runs the Linux operating system, while the coprocessor, the Cortex M3, lacks any operating system and only assists the main processor in performing simple computations. When the firmware of a server hardware module needs to be upgraded, the Cortex A7 responds to the upgrade request and writes the new firmware to the corresponding server hardware module via the bus, thereby completing the upgrade. Therefore, effectively utilizing the coprocessor has always been a challenge. Coprocessor resources are underutilized, leaving the main processor performing the majority of tasks, including small tasks like firmware upgrades. This burdens the main processor and reduces the overall performance of the BMC chip. In order to improve the overall performance of the BMC chip, this application provides the following solution.

[0030] According to an embodiment of the present application, an embodiment of a firmware upgrade method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0031] In this embodiment, a firmware upgrade method is provided, which can be used for the above-mentioned BMC chip. FIG1 is a flowchart of a firmware upgrade method according to an embodiment of the present application. As shown in FIG1 , FIG11 and FIG12 , steps S101 to S105 are applied to the coprocessor, and steps S111 to S113 are applied to the main processor. The process specifically includes the following steps:

[0032] Step S101: Power on and load the coprocessor system, and establish inter-core communication with the main processor;

[0033] Step S111, power on and load the main processor system, and release bus control by loading the bus driver;

[0034] Step S112: When the coprocessor is powered on and the coprocessor system is loaded and inter-core communication with the main processor is established, a bus control right release message is sent to the coprocessor;

[0035] Step S102, receiving a bus control right release message sent by the main processor;

[0036] Step S103, taking over the bus control right in response to the bus control right release message;

[0037] Step S113, sending new firmware and firmware upgrade message to the coprocessor;

[0038] Step S104, receiving new firmware and firmware upgrade message sent by the main processor;

[0039] Step S105 , in response to the firmware upgrade message, writing the new firmware into the corresponding server hardware module via the bus to upgrade the firmware of the server hardware module.

[0040] Specifically, in order to improve the utilization rate of the BMC chip and thus realize a coprocessor-based firmware upgrade solution, the present embodiment pre-deploys a coprocessor operating system in the coprocessor. Among them, the system kernel of the coprocessor operating system is not specifically limited, and includes but is not limited to the Windows kernel, the Linux kernel, the iOS kernel, etc. In a specific embodiment, the embodiment of the present application adopts a real-time operating system (RTOS). RTOS is an operating system that can accept and process external events or data at a fast enough speed when they are generated, and the results of its processing can control the production process or respond quickly to the processing system within a specified time, dispatch all available resources to complete real-time tasks, and control all real-time tasks to run in a coordinated and consistent manner. Thanks to the advantages of the real-time operating system being free, lightweight and low-power, it is more compatible with the lower performance of the coprocessor, making the RTOS run more smoothly on the coprocessor, and providing a more reliable solution for the effective use of coprocessors such as Cortex M3. In addition, thanks to the advantages of the real-time operating system being small in size and fast in startup, the operating system of the coprocessor can be powered on and started earlier than the operating system of the main processor. In subsequent steps, the coprocessor can prioritize initializing inter-core communication, and when the inter-core communication initialization is completed, the main processor can just execute the task of switching bus control, thereby improving the collaborative working efficiency of the main processor and the coprocessor.

[0041] After the coprocessor is powered on to start the system, the coprocessor is made to actively initialize inter-core communication with the main processor, so that the main processor and the coprocessor can exchange data. The means of initializing inter-core communication can be based on Mailbox to directly create a communication channel between the main processor and the coprocessor, similar to the main processor and the coprocessor both having a mailbox for receiving messages, and both parties sending emails to each other to achieve communication; in addition, the main processor and the coprocessor can also complete large data communication in a shared memory manner through a predefined protocol. When the main processor is powered on to start the system, the bus driver pre-installed in the main processor system is used to make the main processor release the bus control right, where the bus includes but is not limited to I 2 C bus, SCI bus, SPI bus. In one or more embodiments, when the BMC chip is AST2600, the bus refers to I 2 C bus, but with the development of BMC chip technology, new multi-core BMC chips in the future will also be able to communicate with server hardware modules through other types of buses, so other types of buses should also fall within the scope of protection of this application, and this application does not specifically limit the specific bus type. Afterwards, the main processor sends a bus control release message to the coprocessor through the inter-core communication mechanism between the coprocessor and the main processor, so that the coprocessor knows that the main processor is no longer communicating with the server hardware module, so that it can take over the bus control in time and communicate with the server hardware module. Then, when the main processor receives a firmware upgrade task, the main processor can send the received new firmware to the coprocessor, so that the coprocessor that has taken over the bus control right can execute the firmware upgrade, which provides a new direction for the coprocessor to share the main core task, completes the firmware upgrade task with a dual-system architecture, shares the task of the main processor, reduces the main processor overhead, and improves the overall performance of the BMC.

[0042] In some alternative embodiments, when the bus is I 2 When the bus is C, the above step S103 includes:

[0043] Step a1: Enable the server hardware module by configuring the system control unit register. 2 C bus;

[0044] Step a2: Configure the server hardware module 2 C related registers to obtain the I 2 C bus control.

[0045] Specifically, in one or more embodiments, I 2 C bus controls the server hardware module. Based on this, this embodiment enables the main processor to connect one I / O port of the server hardware module to the main processor after startup. 2C bus is directly disabled, thereby releasing the control right of the bus, and the coprocessor needs to re-control the I 2 C bus configuration, thereby passing the I 2 C bus accesses the server hardware module. Before configuration, the pins of the server hardware module are simple input and output interfaces. This interface can multiplex multiple functions. Initially, it is used to input and output some general level signals and does not have I 2 The communication function of the I C bus is completed through the System Control Units (SCU) register on the BMC side. 2 C bus function multiplexing configuration, so that the server hardware module pin is set to I through register configuration 2 C function. After successful setting, 2 C registers are configured, such as the bus communication frequency, communication address, etc., to complete the I 2 C bus debugging. After successful configuration, the coprocessor can be used to debug the I 2 C bus and server hardware modules to exchange data, thus realizing the I 2 C bus control is switched between the main processor and the coprocessor.

[0046] In some optional implementations, the above step S101 includes:

[0047] Step a1: configuring a shared memory and an interrupt signal format. The shared memory is used by the main processor and the coprocessor to read and write data together. The interrupt signal format is used by the main processor and the coprocessor to send interrupt signals of corresponding formats to each other to notify the other party to read data from the shared memory.

[0048] Step a2: Set the interrupt enable to enable the interrupt.

[0049] Specifically, the present application uses an interface protocol to enable the coprocessor to initialize inter-core communication. The coprocessor needs to configure the interrupt signal format, which is configured the same in the coprocessor system and the main processor system. For example, assume that the XXXX1 signal represents the task of releasing bus control, and the XXXX2 signal represents the task of firmware transmission. The coprocessor also divides an independent storage space in the BMC's memory module as shared memory. The shared memory is used for the main processor and the coprocessor to read and write data together. The shared memory facilitates the stable transmission of firmware that occupies a certain storage space between the two cores. Both the main processor and the coprocessor use the preset inter-core communication driver function to write data to the shared memory in accordance with the specified data format through the interface protocol, and use the preset inter-core communication driver function to read data from the shared memory in accordance with the specified data format. Compared with the method of using only the signal mechanism to complete communication between the two cores, as the system becomes more complex and the amount of code gradually increases, data communication without protocol brings great problems to programming and understanding, reducing the scalability of the system. In the embodiment of the present application, when initializing inter-core communication, the dual-core communication can adopt the same communication protocol as the system peripherals, so that the protocol parsing inter-core communication driver function can be reused, while also improving portability. In addition, the applicable communication protocol can be defined according to actual needs, or the general communication protocol can be appropriately modified to be more suitable for data communication with large amounts of shared memory. The software encapsulation of the communication interface usually defines data sending functions, data receiving functions, protocol parsing functions, etc. The principle is that the interface should be as simple as possible to minimize the coupling between the two cores and improve the stability and reliability of firmware transmission.

[0050] In some optional implementations, as shown in FIG2 , the above step S102 includes step S201 and step S202, and the above step S112 includes step S211 and step S212. The specific steps are as follows:

[0051] Step S211, storing the bus control right release message into the shared memory through the preset inter-core communication driver function;

[0052] Step S212, sending a first interrupt signal to the coprocessor;

[0053] Step S201, receiving a first interrupt signal sent by a main processor;

[0054] Step S202 : In response to the first interrupt signal, a bus control right release message is read from the shared memory through a preset inter-core communication driver function.

[0055] Specifically, in this embodiment, bus control release messages are transmitted through an inter-core interrupt mechanism and shared memory, ensuring stable transmission of bus control release messages. Furthermore, the coprocessor is informed promptly by the received bus control release message that the main processor system has released bus control, allowing it to immediately take over bus control and subsequently communicate with the server hardware module via the bus to control firmware upgrades for the server hardware module, thereby improving coprocessor utilization and enhancing the overall performance of the BMC.

[0056] In some optional embodiments, as shown in FIG3 , a front-end interface is deployed in the main processor system, and the front-end interface is used for the client to remotely access the main processor system. The above step S113 includes steps S311 to S314, and the above step S104 includes steps S301 and S302. The specific steps are as follows:

[0057] Step S311, receiving the new firmware uploaded by the client through the front-end interface;

[0058] Step S312, verifying the new firmware;

[0059] Step S313: The firmware upgrade message and the verified new firmware are stored in the shared memory through the inter-core communication driver function;

[0060] Step S314, sending a second interrupt signal to the coprocessor;

[0061] Step S301, receiving a second interrupt signal sent by the main processor;

[0062] Step S302 : In response to the second interrupt signal, new firmware and firmware upgrade information are read from the shared memory through a preset inter-core communication driver function.

[0063] Specifically, in this embodiment, a front-end interface is also deployed in the main processor system. The user can enter a predetermined URL through a browser on any computer device, log in to the front-end interface in the form of a UI, and select the new firmware locally stored on the computer device through the front-end interface. Click Upload to remotely upload the new firmware to the main processor, so that the main processor receives the firmware upgrade task, thereby improving the flexibility of the firmware upgrade. Afterwards, considering that the new firmware uploaded by the user through the computer device is often in a compressed package format, the main processor also needs to verify the new firmware, remove specific fields in the package format, and restore the new firmware file to the original format type of the firmware. Then, the main processor stably transmits the new firmware to the coprocessor through the second interrupt signal and shared memory according to the received firmware upgrade task. Under the condition that the coprocessor takes over the bus control, the coprocessor uses the bus to write the new firmware to the server hardware module, overwriting the old firmware, thereby realizing the firmware upgrade task based on the coprocessor, improving the utilization rate of the coprocessor, and improving the overall performance of the BMC.

[0064] In some optional implementations, as shown in FIG4 , before step S113, the method provided in the embodiment of the present application further includes steps S401 to S403 and steps S411 to S413, wherein steps S401 to S403 are applied to the coprocessor, and steps S411 to S413 are applied to the main processor. The specific steps are as follows:

[0065] Step S401, reading old firmware information from the server hardware module to be upgraded via the bus;

[0066] Step S402, writing the old firmware information into the shared memory through a preset inter-core communication driver function;

[0067] Step S403: Send a third interrupt signal to the main processor.

[0068] Step S411, receiving a third interrupt signal sent by the coprocessor;

[0069] Step S412, in response to the third interrupt signal, reading old firmware information from the shared memory through the inter-core communication driver function;

[0070] Step S413: Save the old firmware information in a database associated with the main processor system.

[0071] Specifically, in this embodiment, after the coprocessor takes over the bus control right to access the server hardware module, it also reads the installed old firmware information from the server hardware module to be upgraded, and similarly transmits the old firmware information to the main processor through interrupt signals and shared memory. The main processor saves the received old firmware information in a database associated with the main processor system. For example, the Cortex A7 uses the Linux system, and the redis database is mounted under its system, so that the old firmware information is stored in the redis database. The stored firmware information includes but is not limited to the firmware version number, firmware name, and firmware size. In this way, the historical firmware versions and upgrade records of the server hardware module can be archived, which is convenient for users to flexibly retrieve when tracing problems later. In addition, after the update, it is also possible to verify whether the upgrade is successful based on the old firmware information stored in the redis database, thereby further improving the reliability of the firmware upgrade.

[0072] In some optional embodiments, as shown in FIG5 , a firmware upgrade method provided by the present application further includes steps S501 to S503 and steps S511 to S513, wherein steps S501 to S503 are applied to the coprocessor, and steps S511 to S513 are applied to the main processor. The specific steps are as follows:

[0073] Step S501, when the firmware upgrade of the server hardware module is completed, the current firmware information is read from the server hardware module via the bus;

[0074] Step S502: Write the upgrade completion message and current firmware information to the shared memory through the inter-core communication driver function;

[0075] Step S503, sending a fourth interrupt signal to the main processor;

[0076] Step S511, receiving a fourth interrupt signal sent by the coprocessor;

[0077] Step S512, in response to the fourth interrupt signal, reading the upgrade completion message and current firmware information from the shared memory through a preset inter-core communication driver function;

[0078] Step S513 , in response to the upgrade completion message, the current firmware information is compared with the old firmware information stored in the database, and whether the upgrade is successful is determined based on the comparison result.

[0079] Specifically, this embodiment is based on the old firmware information stored in the above-mentioned main processor system database. Whenever the new firmware upgrade is completed, the coprocessor also reads the current firmware information of the server hardware module after the upgrade, and sends the current firmware information to the main processor, so that the main processor compares the current firmware information with the old firmware information before the upgrade in the database, so as to determine whether the upgrade is successful based on the comparison result. When the firmware information comparison is inconsistent, it indicates that the firmware upgrade of the server hardware module is successful. When the firmware information comparison is consistent, it indicates that the upgrade has failed and needs to be re-upgraded, thereby further improving the stability and reliability of the firmware upgrade.

[0080] In some optional implementations, the present application provides a firmware upgrade method, further comprising the following steps:

[0081] Step b1, receiving a request for viewing update history sent by the client through the front-end interface;

[0082] Step b2: In response to the update history viewing request, the historical firmware information stored in the database is displayed in the front-end interface in chronological order, so that the client can view the historical firmware information by accessing the front-end interface.

[0083] Specifically, the embodiment of the present application can also display the historical firmware information stored in the database in chronological order in the front-end interface according to the customer's request to view the update history, so that the user can remotely access the front-end interface through a computer device to view the historical firmware information, thereby achieving the effect of remotely troubleshooting problems anytime and anywhere, and solving the problem of untimely troubleshooting of problems in different locations.

[0084] To facilitate understanding of the solution of the present application, as shown in FIG6 , in one or more embodiments, the server hardware module requiring firmware upgrade is a power supply unit (PSU), and the BMC chip uses AST2600. Therefore, the specific steps of the technical solution provided by the present application are as follows:

[0085] 1) After the BMC is powered on, the Cortex A7 loads the bootrom, thereby loading the Linux system. At the same time, the Cortex M3 loads the RTOS. The RTOS completes the startup first. After the startup is completed, the Cortex M3 initializes inter-core communication and creates related tasks.

[0086] 2) After the Linux system is loaded, start loading I 2 C bus driver, during this process, the Linux side needs to release the I2C bus where the PSU is located. 2 C bus control, and call the inter-core communication driver function to notify the RTOS side that I 2 C driver loading;

[0087] 3) After receiving the message, the RTOS side initializes the I 2 C bus (enables the PSU's I 2 C bus and configure the PSU's I 2 C related registers), obtain the PSU's I 2 C bus control;

[0088] 4) RTOS side calls I 2 The C driver function reads the old firmware information of the PSU and puts it into the shared memory. The Linux side reads the old firmware information of the PSU from the shared memory and stores it in the Redis database. When the Linux side needs PSU related information, it can read it from the Redis database.

[0089] 5) The Linux side receives the PSU upgrade task through the BMC front-end interface and obtains the new firmware. After completing the firmware verification process before the PSU upgrade, the Linux side transfers the new firmware to the shared memory and notifies the RTOS side to start executing the PSU upgrade task.

[0090] 6) RTOS reads the new firmware from the shared memory and calls I 2 C driver function operates PSU device to upgrade firmware;

[0091] 7) After the PSU upgrade task is successful, the RTOS side calls the inter-core communication driver function to notify the Linux side that the task is completed, and at the same time calls I 2 The C driver function reads the current firmware information such as the current PSU version and the current firmware information, and puts the current firmware information into the shared memory;

[0092] 8) After the Linux side obtains the upgrade success status, it reads the current firmware information from the shared memory and puts it into the Redis database. At the same time, it reads the old firmware information in the Redis database to perform a content check and analyze whether the new firmware information is different from the old firmware information. If the two firmware information are different, it is determined that the PSU upgrade is successful.

[0093] This embodiment also provides a firmware upgrade device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0094] This embodiment provides a firmware upgrade device, as shown in FIG7 , which is applied to a coprocessor and includes:

[0095] The initialization module 701 is used to power on and load the coprocessor system and establish inter-core communication with the main processor.

[0096] The control right message receiving module 702 is used to receive a bus control right release message sent by the main processor. The bus control right release message is a notification message sent by the main processor after the main processor is powered on and loads the main processor system and releases the bus control right by loading the bus driver.

[0097] The control right taking over module 703 is configured to take over the bus control right in response to the bus control right release message.

[0098] The firmware receiving module 704 is configured to receive new firmware and firmware upgrade messages sent by the main processor.

[0099] The firmware upgrade module 705 is configured to write the new firmware into the corresponding server hardware module via the bus in response to the firmware upgrade message, so as to upgrade the firmware of the server hardware module.

[0100] This embodiment provides a firmware upgrade device, as shown in FIG8 , which is applied to a main processor and includes:

[0101] The control right releasing module 801 is used to power on and load the main processor system, and release the bus control right by loading the bus driver.

[0102] The control right message sending module 802 is used to send a bus control right release message to the coprocessor when the coprocessor is powered on to load the coprocessor system and complete the inter-core communication with the main processor, so that the coprocessor responds to the bus control right release message and takes over the bus control right.

[0103] The firmware sending module 803 is used to send new firmware and a firmware upgrade message to the coprocessor, so that the coprocessor responds to the firmware upgrade message and writes the new firmware into the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

[0104] The further functional description of each of the above modules and units is the same as that of the corresponding method embodiments above and will not be repeated here.

[0105] A firmware upgrade device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0106] An embodiment of the present application further provides a BMC chip having a firmware upgrade device as shown in FIG. 7 and FIG. 8 .

[0107] Please refer to Figure 9, which is a schematic diagram of the structure of a BMC chip 60 provided in an optional embodiment of the present application. As shown in Figure 9, the BMC chip 60 includes: one or more main processors 10, one or more coprocessors 30, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used with multiple memories and multiple storage devices. Similarly, multiple computer devices can be connected, with each device providing some of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 9 uses a main processor 10 and a coprocessor 30 as an example.

[0108] The main processor 10 may be a central processing unit, a network processor, or a combination thereof. The main processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0109] The coprocessor 30 may be a central processing unit, a network processor, or a combination thereof. The coprocessor 30 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general purpose array logic (GAL), or any combination thereof.

[0110] The memory 20 stores instructions that can be executed by at least one main processor 10 and the coprocessor 30, so as to enable the at least one processor 10 and the coprocessor 30 to implement the method shown in the above embodiment.

[0111] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0112] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0113] The computer device further includes a communication interface 40 for the computer device to communicate with other devices or a communication network.

[0114] Please refer to Figure 10, which is a server provided by an optional embodiment of the present application, including a server motherboard 50 and a BMC chip 60. The BMC chip 60 is communicatively connected to each hardware module on the server motherboard. The BMC chip 60 provides basic hardware management functions for the server motherboard 50, such as monitoring the temperature, fan speed, power status, etc. of the server motherboard 50. The BMC also provides a remote management function, allowing administrators to remotely manage the server through the network, including powering on and off the server motherboard 50, restarting, configuring BIOS, etc. The BMC chip 60 is tightly integrated with some hardware modules (such as sensors) on the server motherboard, and can sense hardware status changes in a timely manner and report to the administrator. In addition, the BMC chip 60 also usually has its own IP address and network interface, and can be managed and monitored independently of the server operating system through the network. In short, the BMC chip 60 is an important part of server management. It can provide rich hardware management and remote management functions to help administrators manage servers more efficiently.

[0115] Referring to Figure 13, an embodiment of the present application further provides a non-volatile computer-readable storage medium 1301. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as computer-readable instructions 1302 that can be recorded on a storage medium, or downloaded via a network and originally stored in a remote storage medium or a non-transitory machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer-readable instructions. When the software or computer-readable instructions are accessed and executed by the computer, processor, or hardware, the method shown in the above embodiment is implemented.

[0116] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A firmware upgrade method, characterized in that: Applied to a coprocessor, the method comprises: Power on and load the coprocessor system, and establish inter-core communication with the main processor; Receiving a bus control right release message sent by a main processor, wherein the bus control right release message is a notification message sent by the main processor after the main processor is powered on to load the main processor system and releases the bus control right by loading the bus driver; In response to the bus control right release message, taking over the bus control right; Receive new firmware and firmware upgrade messages sent by the main processor; and In response to the firmware upgrade message, the new firmware is written into the corresponding server hardware module through a bus to upgrade the firmware of the server hardware module.

2. The method according to claim 1, characterized in that The coprocessor establishes inter-core communication with the main processor through initialization, including: Configuring a shared memory and an interrupt signal format, wherein the shared memory is used by the main processor and the coprocessor to read and write data together, and the interrupt signal format is used by the main processor and the coprocessor to send interrupt signals of corresponding formats to each other to notify the other party to read data from the shared memory; and Set the interrupt enable to turn on the interrupt.

3. The method according to claim 2, characterized in that The receiving a bus control right release message sent by the main processor comprises: receiving a first interrupt signal sent by the main processor, wherein the first interrupt signal is an interrupt signal sent by the main processor after storing the bus control right release message in the shared memory through a preset inter-core communication driver function; and In response to the first interrupt signal, the bus control right release message is read from the shared memory through a preset inter-core communication driver function.

4. The method according to claim 2, characterized in that: The receiving of new firmware and firmware upgrade message sent by the main processor includes: receiving a second interrupt signal sent by the main processor, wherein the second interrupt signal is an interrupt signal sent by the main processor after storing the new firmware and the firmware upgrade message in the shared memory through a preset inter-core communication driver function; and In response to the second interrupt signal, the new firmware and the firmware upgrade message are read from the shared memory through a preset inter-core communication driver function.

5. The method according to claim 2, characterized in that: Before receiving the new firmware and firmware upgrade message sent by the main processor, the method further includes: Reading old firmware information from the server hardware module to be upgraded through the bus; Writing the old firmware information into the shared memory through a preset inter-core communication driver function; and A third interrupt signal is sent to the main processor, so that the main processor responds to the third interrupt signal, reads the old firmware information from the shared memory through a preset inter-core communication driver function, and saves the old firmware information in a database associated with the main processor system.

6. The method according to claim 5, characterized in that The method further comprises: When the firmware upgrade of the server hardware module is completed, reading the current firmware information from the server hardware module via the bus; Writing an upgrade completion message and the current firmware information to the shared memory through the inter-core communication driver function; and A fourth interrupt signal is sent to the main processor, so that the main processor responds to the fourth interrupt signal, reads the upgrade completion message and the current firmware information from the shared memory through a preset inter-core communication driver function, and makes the main processor respond to the upgrade completion message, compares the current firmware information with the old firmware information stored in the database, and determines whether the upgrade is successful based on the comparison result.

7. The method according to claim 1, characterized in that The coprocessor system is a real-time operating system.

8. The method according to claim 1, characterized in that The bus is I 2 C bus, taking over bus control rights, including: By configuring the system control unit register to enable the I 2 C bus; and Configure the server hardware module 2 C related registers, obtain the I 2 C bus control.

9. A firmware upgrade method, characterized in that: Applied to a main processor, the method comprises: Power on and load the main processor system, and release bus control by loading the bus driver; When the coprocessor is powered on and the coprocessor system is loaded and the inter-core communication with the main processor is established, a bus control right release message is sent to the coprocessor, so that the coprocessor responds to the bus control right release message and takes over the bus Control; and The new firmware and the firmware upgrade message are sent to the coprocessor, so that the coprocessor responds to the firmware upgrade message and writes the new firmware into the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

10. The method according to claim 9, characterized in that The coprocessor establishes inter-core communication with the main processor by initialization, including: the coprocessor initializes the inter-core communication with the main processor by configuring shared memory and interrupt signal format, and setting interrupt enable, the shared memory is used for the main processor and the coprocessor to read and write data together, and the interrupt signal format is used for the main processor and the coprocessor to send interrupt signals of corresponding formats to each other to notify the other party to read data from the shared memory; and The sending of a bus control right release message to the coprocessor comprises: storing the bus control right release message into the shared memory through a preset inter-core communication driver function; and A first interrupt signal is sent to the coprocessor, so that the coprocessor responds to the first interrupt signal and reads the bus control right release message from the shared memory through a preset inter-core communication driver function.

11. The method according to claim 10, characterized in that A front-end interface is deployed in the main processor system, and the front-end interface is used for a client to remotely access the main processor system. The sending of new firmware and firmware upgrade messages to the coprocessor includes: Receiving new firmware uploaded by the client through the front-end interface; Verifying the new firmware; storing the firmware upgrade message and the verified new firmware into the shared memory through the inter-core communication driver function; and A second interrupt signal is sent to the coprocessor, so that the coprocessor responds to the second interrupt signal and reads the new firmware and the firmware upgrade message from the shared memory through the inter-core communication driver function.

12. The method according to claim 10, characterized in that Before sending the new firmware and the firmware upgrade message to the coprocessor, the method further includes: receiving a third interrupt signal sent by the coprocessor, wherein the third interrupt signal is an interrupt signal sent by the coprocessor after the coprocessor reads old firmware information from the server hardware module to be upgraded through the bus and writes the old firmware information into the shared memory through a preset inter-core communication driver function; In response to the third interrupt signal, the inter-core communication driver function reads the Old firmware information; and The old firmware information is stored in a database associated with the main processor system.

13. The method according to claim 12, characterized in that The method further comprises: receiving a fourth interrupt signal sent by the coprocessor, wherein the fourth interrupt signal is an interrupt signal sent after the coprocessor reads the current firmware information from the server hardware module through the bus and writes the upgrade completion message and the current firmware information to the shared memory through the inter-core communication driver function when the firmware upgrade of the server hardware module is completed; In response to the fourth interrupt signal, reading the upgrade completion message and the current firmware information from the shared memory through a preset inter-core communication driver function; and In response to the upgrade completion message, the current firmware information is compared with the old firmware information stored in the database, and whether the upgrade is successful is determined based on the comparison result.

14. The method according to claim 12, characterized in that A front-end interface is deployed in the main processor system, and the front-end interface is used for a client to remotely access the main processor system. The method further includes: Receiving a request for viewing update history sent by a client through the front-end interface; and In response to the update history viewing request, the historical firmware information stored in the database is displayed in the front-end interface in chronological order, so that the client can view the historical firmware information by accessing the front-end interface.

15. A firmware upgrade method, characterized in that: The method comprises: The coprocessor is powered on to load the coprocessor system and establish inter-core communication with the main processor; The main processor is powered on to load the main processor system, and releases the bus control right by loading the bus driver; When the coprocessor is powered on to load the coprocessor system and the inter-core communication with the main processor is established, the main processor sends a bus control right release message to the coprocessor; The coprocessor receives a bus control right release message sent by the main processor; The coprocessor takes over the bus control right in response to the bus control right release message; The main processor sends new firmware and firmware upgrade message to the coprocessor; The coprocessor receives new firmware and firmware upgrade messages sent by the main processor; and In response to the firmware upgrade message, the coprocessor writes the new firmware into the corresponding server hardware module through a bus to upgrade the firmware of the server hardware module.

16. The method according to claim 15, characterized in that The step of establishing inter-core communication between the coprocessor and the main processor comprises: The coprocessor is configured with a shared memory and an interrupt signal format, the shared memory is used for the main processor and the coprocessor to read and write data together, and the interrupt signal format is used for the main processor and the coprocessor to send interrupt signals of corresponding formats to each other to notify the other party to read data from the shared memory; and The coprocessor sets the interrupt enable to enable the interrupt.

17. A firmware upgrade device, characterized in that: Applied to a coprocessor, the device comprises: Initialization module, used to load the coprocessor system at power-on and establish inter-core communication with the main processor; A control right message receiving module, used to receive a bus control right release message sent by a main processor, wherein the bus control right release message is a notification message sent by the main processor after the main processor is powered on to load the main processor system and releases the bus control right by loading the bus driver; A control right taking over module, used for taking over the bus control right in response to the bus control right release message; A firmware receiving module, used for receiving new firmware and firmware upgrade messages sent by the main processor; and The firmware upgrade module is used to respond to the firmware upgrade message and write the new firmware into the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

18. A firmware upgrade device, characterized in that: Applied to a main processor, the device comprises: The control right release module is used to load the main processor system at power-on and release the bus control right by loading the bus driver; a control right message sending module, used for sending a bus control right release message to the coprocessor when the coprocessor is powered on to load the coprocessor system and establish inter-core communication with the main processor, so that the coprocessor responds to the bus control right release message and takes over the bus control right; and The firmware sending module is used to send new firmware and firmware upgrade messages to the coprocessor, so that the coprocessor responds to the firmware upgrade message and writes the new firmware into the corresponding server hardware module through the bus to upgrade the firmware of the server hardware module.

19. A BMC chip, characterized in that: include: Coprocessors, main processors and memory, The memory is respectively connected to the coprocessor and the main processor for mutual communication, the memory stores computer instructions, the coprocessor executes the method according to any one of claims 1 to 8 by executing the computer instructions, and the main processor executes the method according to claims 9 to 14 by executing the computer instructions. The method of any one of the above.

20. A server, characterized in that: The invention comprises a server mainboard and a BMC chip, wherein the BMC chip is communicatively connected with each hardware module on the server mainboard, the BMC chip stores computer instructions, and the BMC chip executes the method according to any one of claims 1 to 8 or 9 to 14 by executing the computer instructions.

21. A non-volatile computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method of any one of claims 1 to 8 or 9 to 14.

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