Photonic integrated circuit chip and silicon optical integrated platform

Abstract

Provided in the present utility model are a photonic integrated circuit chip and a silicon optical integrated platform. The utility model aims to arrange multiple layers of waveguides in an optical waveguide layer of a photonic integrated circuit chip, the multiple layers of waveguides jointly participating in the spot size conversion of light, so as to reduce the light loss in spot size conversion by a conventional edge coupler provided with a single-layer waveguide. Furthermore, in the thickness direction of a substrate layer, at least one protective layer is arranged on the surface of the side of the photonic integrated circuit chip away from the substrate layer, thereby preventing water vapor from entering silicon dioxide on a surface layer during long-term use, thereby affecting device performance. Moreover, the influence of various kinds of dirt infiltration in the packaging process can be prevented.

Description

Photonic integrated circuit chips and silicon photonic integration platforms

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 16, 2023, with application number 202321536704.1 and invention name “Photonic Integrated Circuit Chip and Silicon Photonic Integration Platform”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The utility model relates to the technical field of optical communications, and in particular to a photonic integrated circuit chip and a silicon photonic integrated platform. Background Art

[0003] In recent years, photonic integrated circuit chips have effectively reduced the cost and power consumption of optical communication modules and are a key technology for achieving optical interconnection. The mode field of a typical single-mode silicon optical waveguide is on the order of hundreds of nanometers, while the mode field diameter (MFD) of ordinary single-mode optical fibers required for coupling and alignment with photonic integrated circuit chips (such as silicon photonic chips) is 9-10μm. This significant mode field mismatch between the two makes direct coupling with the chip less tolerant and results in significant optical coupling losses. Therefore, a specific coupler is required on the photonic integrated circuit chip to achieve efficient coupling with the single-mode fiber.

[0004] Commonly used waveguide couplers include two main types: grating couplers and edge couplers. Grating couplers offer advantages such as wide alignment tolerance, ease of packaging, and on-chip testing. However, they suffer from low coupling efficiency and a narrow operating bandwidth. Edge couplers, on the other hand, offer advantages such as high coupling efficiency and a wide operating bandwidth.

[0005] Furthermore, because the photonic integrated circuit chip lacks a passivation layer, moisture can easily penetrate the silicon dioxide layer over long-term use, affecting device performance. Furthermore, the surface of the photonic integrated circuit chip is susceptible to various contaminants during process engineering, such as bumping and TSV. Utility Model Content

[0006] The purpose of the present utility model is to provide a photonic integrated circuit chip and a silicon photonic integrated platform to reduce light loss during the mode spot conversion process and improve the optical coupling efficiency between the photonic integrated circuit chip and the external optical fiber, while avoiding the effects of various dirt during the packaging process and water vapor intrusion during use.

[0007] The purpose of this utility model is achieved by the following technical solutions:

[0008] According to one aspect of the present invention, a photonic integrated circuit chip is provided, comprising: a substrate layer, a dielectric layer, and an optical waveguide layer stacked together;

[0009] The photonic integrated circuit chip includes an optical device disposed in the optical waveguide layer and a device waveguide optically connected to the optical device. The photonic integrated circuit chip has an external end face coupled to the outside world along a thickness direction perpendicular to the substrate layer.

[0010] In the thickness direction of the substrate layer, the optical waveguide layer is sequentially stacked with a first waveguide, a second waveguide, and a third waveguide:

[0011] The first waveguide is optically connected to the device waveguide, and an end of the first waveguide facing the outer end face is at a first lateral distance from the outer end face;

[0012] The second waveguide is optically coupled to the first waveguide and is spaced apart from the first waveguide in a thickness direction;

[0013] The third waveguide is optically coupled to the second waveguide and is spaced apart from the second waveguide in the thickness direction;

[0014] The first waveguide, the second waveguide, and the third waveguide all extend from the interior of the photonic integrated circuit chip to the outer end surface;

[0015] The photonic integrated circuit chip further includes at least one protective layer, which covers a surface of the photonic integrated circuit chip on a side away from the substrate layer, wherein the protective layer is made of silicon nitride.

[0016] In some embodiments, the at least one protective layer covers a surface of the optical waveguide layer on a side away from the substrate layer.

[0017] In some embodiments, a conductive circuit layer and a metal through-hole are further provided in the optical waveguide layer, and the conductive circuit layer realizes electrical connection between each conductive circuit layer or other devices through the metal through-hole; the at least one protective layer is in direct contact with the surface of the metal layer, and the at least one protective layer is provided with a first through-hole that penetrates the at least one protective layer in the thickness direction to expose the surface of the metal layer, and the first through-hole is filled with a conductive material.

[0018] Furthermore, the at least one protective layer includes a first protective layer, a second protective layer, and a dielectric layer disposed between the first protective layer and the second protective layer; wherein the dielectric layer is made of silicon oxide.

[0019] Furthermore, in the thickness direction of the substrate layer, the first waveguide and the second waveguide partially overlap in projection, so as to be coupled in an adiabatic coupling manner;

[0020] In a direction perpendicular to the thickness of the substrate layer, an extension length of the second waveguide is greater than an extension length of the third waveguide, and an end portion of the second waveguide close to the outer end surface is flush with an end portion of the third waveguide close to the outer end surface.

[0021] Furthermore, the second waveguide and the third waveguide are configured to perform spot mode conversion on the light coupled from the first waveguide and transmit it to an external optical fiber, or to perform spot mode conversion on the light input from the external optical fiber and couple the spot mode converted light to the first waveguide.

[0022] Furthermore, the first waveguide and the device waveguide are arranged in the same layer.

[0023] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

[0024] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the second waveguide is in an inverted wedge-shaped structure.

[0025] Furthermore, in a direction from the inside of the photonic integrated circuit chip to the outer end surface, the third waveguide has a constant cross-sectional width.

[0026] Furthermore, the number of the second waveguides is multiple, and the number of the third waveguides is multiple;

[0027] At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of third waveguides is arranged in multiple rows and / or multiple columns;

[0028] Wherein, at a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of third waveguides are arranged in a staggered or irregular manner.

[0029] Furthermore, from the inside of the photonic integrated circuit chip toward the outer end surface, a cross-sectional width of a portion of at least one of the plurality of second waveguides gradually becomes thinner toward the outer end surface.

[0030] Further, the first waveguide, the second waveguide and the third waveguide are silicon nitride waveguides or silicon oxynitride waveguides.

[0031] Furthermore, in the thickness direction of the substrate layer, the optical waveguide layer is further provided with:

[0032] A fourth waveguide is optically coupled to the third waveguide and spaced apart from the third waveguide in thickness, and extends from the interior of the photonic integrated circuit chip toward the outer end surface.

[0033] Furthermore, an extension length of the fourth waveguide is less than or equal to an extension length of the third waveguide, and an end portion of the fourth waveguide close to the outer end surface is flush with an end portion of the third waveguide close to the outer end surface.

[0034] Furthermore, in a direction from the inside of the photonic integrated circuit chip to the outer end surface, the fourth waveguide has a constant cross-sectional width.

[0035] Furthermore, the fourth waveguide has a constant cross-sectional width in a direction from the inner end toward the outer end of the multi-layer edge coupler.

[0036] Furthermore, the number of the second waveguides is multiple, the number of the third waveguides is multiple, and the number of the fourth waveguides is multiple;

[0037] At a cross-sectional position close to the plane where the outer end surface is located, a combination of the plurality of second waveguides, the plurality of third waveguides, and the plurality of fourth waveguides are arranged in a plurality of rows and columns;

[0038] Between adjacent rows and / or columns, the plurality of second waveguides, the plurality of third waveguides, and the plurality of fourth waveguides are arranged in a staggered or irregular manner.

[0039] Furthermore, the fourth waveguide is a silicon nitride waveguide or a silicon oxynitride waveguide.

[0040] According to another aspect of the present application, there is also provided a silicon photonic integrated platform, comprising: a photonic integrated circuit chip;

[0041] An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core;

[0042] The optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

[0043] This application employs multilayer waveguides within the optical waveguide layer of a photonic integrated circuit (PIC) chip. These multilayer waveguides participate in light spot conversion, reducing the optical loss during spot conversion in conventional edge couplers with single-layer waveguides. Furthermore, along the thickness of the substrate layer, at least one protective layer is provided on the surface of the PIC chip, distal from the substrate layer, to prevent moisture from entering the surface silicon dioxide layer during long-term use, thereby affecting device performance. This also prevents the intrusion of various contaminants during the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other implementation methods can be obtained based on these drawings without paying any creative work.

[0045] FIG1 shows a schematic structural diagram of a photonic integrated circuit chip provided in one embodiment of the present application;

[0046] FIG2A shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position A;

[0047] FIG2B shows a schematic cross-sectional view of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position B;

[0048] FIG2C shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position C;

[0049] FIG2D shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position D;

[0050] FIG2E shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position E;

[0051] FIG2F shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position F;

[0052] FIG2G shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position G;

[0053] FIG3 shows a schematic top view of the structure of a plurality of second waveguides from a cross-sectional position C to a cross-sectional position D in FIG1 ;

[0054] FIG4A shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position A;

[0055] FIG4B shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position E;

[0056] FIG4C shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG1 at a cross-sectional position G;

[0057] FIG5 shows a schematic structural diagram of a photonic integrated circuit chip provided in another embodiment of the present application;

[0058] FIG6A shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position A;

[0059] FIG6B shows a schematic cross-sectional view of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position B;

[0060] FIG6C shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position C;

[0061] FIG6D shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position D;

[0062] FIG6E shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position E;

[0063] FIG6F shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position F;

[0064] FIG7A shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position A;

[0065] FIG7B shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position C;

[0066] FIG7C shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG5 at a cross-sectional position E;

[0067] FIG8 shows a schematic structural diagram of a photonic integrated circuit chip provided in another embodiment of the present application;

[0068] FIG9 shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in FIG8 at a cross-sectional position A. FIG. DETAILED DESCRIPTION

[0069] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In addition, in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings.

[0070] In the description of the present invention, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements or an interaction relationship between two elements. The meaning of chip in this article may include bare chips. When it comes to method steps, the sequence illustrated in this article represents an exemplary scheme, but does not represent a limitation on the sequence. For ordinary technicians in this field, the specific meanings of the above terms in this utility model can be understood according to specific circumstances.

[0071] As used herein, the term "substrate" can refer to the substrate of a diced wafer or the substrate of an undiced wafer. It should be understood that the term "film" encompasses layers and, unless otherwise specified, should not be interpreted as indicating vertical or horizontal thickness. It should be noted that the thicknesses of the various material layers of the edge coupler structure shown in the figures are merely illustrative and do not represent actual thicknesses.

[0072] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods. Example

[0073] Figure 1 shows a structural schematic diagram of a photonic integrated circuit chip provided in an embodiment of the present application, Figure 2A shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position A, Figure 2B shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position B, Figure 2C shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position C, Figure 2D shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position D, Figure 2E shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position E, Figure 2F shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position F, Figure 2G shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position G, and Figure 3 shows a top-down structural schematic diagram of multiple second waveguides from cross-sectional position C to cross-sectional position D in Figure 1.

[0074] As shown in FIG. 1 and FIG. 2A to FIG. 2G , the photonic integrated circuit chip 1000 provided in the first embodiment of the present application includes: a substrate layer 601 , a dielectric layer 602 , and an optical waveguide layer 310 , which are stacked.

[0075] The photonic integrated circuit chip 1000 includes a first region 100 and a second region 200 located above the dielectric layer 602 and at least partially below the stack of optical waveguide layers 310. An optical device 101 and a device waveguide 110 optically connected to the optical device 101 are disposed within the optical waveguide layer 310 of the first region 100. An edge coupler is disposed within the optical waveguide layer 310 of the second region 200. Along a thickness direction perpendicular to the substrate layer 601, the photonic integrated circuit chip 1000 has an external end face coupled to the outside world.

[0076] In the thickness direction of the substrate layer 601, the first waveguide 201, the second waveguide 202 and the third waveguide 203 are sequentially stacked in the optical waveguide layer 310:

[0077] The first waveguide 201 is optically connected to the device waveguide 110, and an end of the first waveguide 201 facing the outer end surface is at a first lateral distance L1 from the outer end surface;

[0078] The second waveguide 202 is optically coupled to the first waveguide 201 and is spaced apart from the first waveguide 201 in the thickness direction;

[0079] The third waveguide 203 is optically coupled to the second waveguide 202 and is spaced apart from the second waveguide 202 in the thickness direction;

[0080] The first waveguide 201 , the second waveguide 202 , and the third waveguide 203 extend from the interior of the photonic integrated circuit chip 1000 to the outer end surface in their respective layers;

[0081] The photonic integrated circuit chip 1000 further includes at least one protective layer 501 , which covers a surface of the photonic integrated circuit chip 1000 away from the substrate layer 601 . The protective layer 501 is made of silicon nitride.

[0082] As can be seen from the above, the embodiments of the present application aim to reduce the optical loss of conventional single-layer waveguides during the spot conversion process by providing multiple layers of waveguides within the optical waveguide layer of a photonic integrated circuit chip (PIC). These multiple layers of waveguides jointly participate in the spot conversion of light. Furthermore, at least one protective layer is provided on the surface of the PIC chip, distal from the substrate layer, along the thickness direction of the substrate layer. This prevents moisture from entering the surface silicon dioxide layer during long-term use, thereby affecting device performance. This also prevents the intrusion of various contaminants during the packaging process.

[0083] Furthermore, at a cross-sectional position near the outer end face of the photonic integrated circuit chip, the multilayer waveguides are used together to confine the light field, thereby adjusting the mode spot size of the light field near the edge of the photonic integrated circuit chip so that it can match the mode field diameter of the external optical fiber, thereby improving the optical coupling efficiency between the photonic integrated circuit chip and the external optical fiber.

[0084] It should be noted that the mode field diameter after conversion through a single-layer waveguide is usually sensitive to the morphology or size of the single-layer waveguide itself, which can cause the actual light field mode spot size near the edge of the photonic integrated circuit chip to be too large or too small, making it difficult to adjust. However, using multiple waveguides to jointly participate in the mode spot conversion of the light field can reduce the sensitivity of the single-layer waveguide's own morphology or size to the single-layer waveguide's mode field diameter (light spot diameter) while ensuring coupling efficiency.

[0085] For example, in this embodiment, the photonic integrated circuit chip 1000 uses a top silicon layer 603 of an SOI (Silicon On Insulator) structure to fabricate the device waveguide 110. The optical device 101 includes, for example, a light absorbing layer (e.g., a germanium layer). The light absorbing layer is disposed on the side of the device waveguide 110 facing away from the substrate layer 601 in the thickness direction of the substrate layer 601.

[0086] The dielectric layer 602 is, for example, a buried silicon oxide layer.

[0087] The optical waveguide layer 310 is, for example, SiO 2 . Specifically, a SiO 2 film layer is deposited around the first waveguide 201 , the second waveguide 202 , and the third waveguide 203 to cover the first waveguide 201 , the second waveguide 202 , and the third waveguide 203 . The SiO 2 film layer also serves as a support platform for the multi-layer waveguide, so that the first waveguide 201 , the second waveguide 202 , and the third waveguide 203 all extend from the interior of the photonic integrated circuit chip 1000 toward the outer end surface.

[0088] The terms “first,” “second,” and “third” herein are intended to distinguish different objects, rather than to rank the objects or limit the number of the objects.

[0089] Furthermore, the first region 100 and the second region 200 are distributed in a flat manner on a plane perpendicular to the thickness direction of the substrate layer 601, so that light can be freely transmitted laterally between the photonic integrated circuit chip 1000 and the external optical fiber 400. At the same time, this horizontal flat layout can also make full use of the surface area of ​​the photonic integrated circuit chip 1000, thereby improving the effective utilization rate of the surface area of ​​the photonic integrated circuit chip 1000.

[0090] Illustratively, in this embodiment, the at least one protective layer 501 covers a surface of the optical waveguide layer 310 that is away from the substrate layer 601 .

[0091] By way of example, in this embodiment, a conductive circuit layer and metal vias are further provided within the optical waveguide layer 310 in the first region 100. The conductive circuit layers achieve electrical connections between each other or with other devices through the metal vias. The at least one protective layer is in direct contact with the surface of the metal layer. The at least one protective layer 501 is provided with a first via (not shown) penetrating the at least one protective layer 501 in the thickness direction to expose the surface of the metal layer. The first via (not shown) is filled with a conductive material 701. By way of example, the conductive material 701 is aluminum, which has low electrical conductivity.

[0092] Illustratively, in this embodiment, the at least one protective layer includes a first protective layer 501, a second protective layer 502, and a dielectric layer 503 stacked between the first protective layer 501 and the second protective layer 502, wherein the dielectric layer 503 is made of silicon oxide, and the dielectric layer 503 can serve as a connector between the first protective layer 501 and the second protective layer 502 to increase the overall thickness and strength.

[0093] In this embodiment, the second waveguide 202 is optically coupled with the first waveguide 201 to provide a light field transition. It also forms a multilayer waveguide with the third waveguide 203 to participate in light spot conversion, thereby reducing optical loss during the spot conversion process in conventional single-layer waveguides. Specifically, along the thickness direction of the substrate layer 601, the first waveguide 201 and the second waveguide 202 partially overlap in projection, achieving adiabatic coupling. In a direction perpendicular to the thickness of the substrate layer 601, the second waveguide 202 extends longer than the third waveguide 203, and the end of the second waveguide 202 near the outer end face is flush with the end of the third waveguide 203 near the outer end face.

[0094] For example, in this embodiment, the first waveguide 201, the second waveguide 202, and the third waveguide 203 are silicon nitride waveguides or silicon oxynitride waveguides. Since silicon generally has a higher refractive index, the actual mode size that can be achieved by a silicon waveguide is approximately 2-5 μm. However, silicon nitride or silicon oxynitride has a lower refractive index than silicon, so silicon nitride or silicon oxynitride waveguides can achieve a larger mode size than silicon waveguides. In some embodiments, to facilitate processing and manufacturing, the first waveguide 201, the second waveguide 202, and the third waveguide 203 are all made of the same material, for example, silicon nitride.

[0095] In this embodiment, the second waveguide 202 and the third waveguide 203 are configured to perform spot conversion on the light coupled from the first waveguide 201 (for example, to expand the spot size of the light) and transmit it to an external optical fiber, or to perform spot conversion on the light input from the external optical fiber (for example, to shrink the spot size of the light) and couple the spot-converted light to the first waveguide 201.

[0096] Specifically, the first waveguide 201, the second waveguide 202, and the third waveguide 203 are formed by patterning the waveguide layer in each layer; and the number of the first waveguides 201, the second waveguide 202, and the third waveguide 203 or the spacing in the thickness direction thereof is determined according to the size of the required coupled light spot diameter.

[0097] In some embodiments, the first waveguide 201 and the device waveguide 110 are disposed in the same layer.

[0098] In some embodiments, a portion of the first waveguide 201 is in a reverse wedge-shaped structure pointing from the inside of the photonic integrated circuit chip to the outer end surface, so that the light coupled from the device waveguide 110 can be gradually expanded after the mode spot conversion is performed by the first waveguide 201.

[0099] In some embodiments, a portion of the second waveguide 202 is in a reverse wedge-shaped structure pointing from the inside of the photonic integrated circuit chip to the outer end face, so that the light coupled from the first waveguide 201 can be gradually expanded after the mode spot conversion in the second waveguide 202 and match the mode spot diameter of the external optical fiber.

[0100] In some embodiments, the third waveguide 203 has a constant cross-sectional width in a direction from the inside of the photonic integrated circuit chip to the external end face, and the second waveguide 202 and the third waveguide 203 jointly confine the light field to adjust the mode spot size of the light field near the edge of the photonic integrated circuit chip 1000 so that it can match the mode field diameter of the external optical fiber, thereby improving the optical coupling efficiency between the photonic integrated circuit chip and the external optical fiber.

[0101] For example, as shown in FIG1 and FIG2A-2G, the number of the second waveguides 202 is two, and the number of the third waveguides 203 is three. At a cross-sectional position close to the plane where the outer end surface is located (for example, at cross-sectional position A), the combination of the two second waveguides 202 and the three third waveguides 203 is arranged in multiple rows and / or columns; wherein, between adjacent rows and / or columns, the two second waveguides 202 and the three third waveguides 203 are staggered or irregularly arranged.

[0102] Compared with a configuration in which the second waveguides 202 and the third waveguides 203 are aligned vertically, the staggered arrangement of the plurality of second waveguides 202 and the plurality of third waveguides 203 not only relaxes the requirements for process alignment errors between the second waveguides 202 and the third waveguides 203 , making processing and manufacturing more convenient, but also increases the alignment tolerance of the edge coupler having the multi-layer waveguides in the horizontal direction by staggering the plurality of second waveguides 202 and the plurality of third waveguides 203 between adjacent rows and / or columns.

[0103] At cross-sectional position B, the cross-sectional dimensions of the plurality of second waveguides 202 have changed compared to cross-sectional position A. At this time, the cross-sectional dimensions of the plurality of second waveguides 202 are relatively larger, while the cross-sectional dimensions of the plurality of third waveguides 203 remain unchanged, and the light field is mainly confined to the plurality of second waveguides 202.

[0104] At the cross-sectional position C, there are only the plurality of second waveguides 202 .

[0105] 3 , in some embodiments, from the inside of the photonic integrated circuit chip toward the outer end surface, a portion of the cross-sectional width of at least one second waveguide 202 among the plurality of second waveguides 202 gradually becomes thinner toward the direction close to the outer end surface.

[0106] Furthermore, from a cross-sectional position C near the end of the third waveguide 203 to a cross-sectional position D near the end of the first waveguide 201, the plurality of second waveguides 202 are configured to perform in-plane optical coupling within their planes. In the direction from the interior of the photonic integrated circuit chip toward the outer end face, two second waveguides 202 and the projected portion of a second waveguide 202 located between the two second waveguides 202 overlap, thereby coupling via adiabatic coupling. This allows light fields to be guided from the plurality of second waveguides 202 at the cross-sectional positions near the end of the third waveguide 203 to the single second waveguide 202 at the cross-sectional position near the end of the first waveguide 201; conversely, light fields can be guided from the single second waveguide 202 at the cross-sectional position near the end of the first waveguide 201 to the plurality of second waveguides 202 at the cross-sectional positions near the end of the third waveguide 203.

[0107] Specifically, from the cross-sectional position C to the cross-sectional position D, the light field is coupled from the two second waveguides 202 into one second waveguide 202 located between the two second waveguides 202 .

[0108] At cross-sectional position E, compared with cross-sectional position D, both the second waveguide 202 and the first waveguide 201 exist. Since the cross-sectional size of the second waveguide 202 is relatively large and the cross-sectional size of the first waveguide 201 is relatively small, the light field is mainly confined to the second waveguide 202.

[0109] From the cross-sectional position E to the cross-sectional position F, the cross-sectional size of the second waveguide 202 gradually decreases, while the cross-sectional size of the first waveguide 201 gradually increases, and the light field is gradually coupled from the second waveguide 202 into the first waveguide 201 .

[0110] At the cross-sectional position G, there is only the first waveguide 201 .

[0111] In some embodiments, a portion of the first waveguide 201 is in a reverse wedge-shaped structure pointing from the inside of the photonic integrated circuit chip to the outer end surface, so that the light coupled from the second waveguide 202 can be gradually shrunk after the mode spot conversion is performed by the first waveguide 201.

[0112] In some embodiments, in order to improve the optical coupling efficiency between the first waveguide 201 and the device waveguide 110 , the first waveguide 201 is epitaxially grown from the outer end surface of the photonic integrated circuit chip toward the inside into the first region 100 .

[0113] In some embodiments, the first waveguide 201 may also serve as a transmission waveguide of the device. Example

[0114] Figure 4A shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position A, Figure 4B shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position E, and Figure 4C shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 1 at cross-sectional position G.

[0115] As shown in Figures 4A-4C , at cross-sectional position A, compared to Example 1, the number of second waveguides 202 and third waveguides shown in Example 2 is greater than three, for example, four, five, or more, although this is not a limitation in this embodiment of the present application. The plurality of second waveguides 202 and the plurality of third waveguides 203 are arranged in multiple rows and / or columns; wherein, at a cross-sectional position near the plane of the outer end face, the plurality of second waveguides 202 and the plurality of third waveguides 203 are staggered or irregularly arranged between adjacent rows and / or columns.

[0116] It should be noted that the combination of the plurality of second waveguides 202 and the plurality of third waveguides 203 is irregularly arranged, and the light field corresponding to the arrangement matches the light field coupled by the external optical fiber.

[0117] From cross-sectional position A to cross-sectional position E, multiple third waveguides 203 completely convert the light field into a second waveguide 202 through an intermediate adiabatic conversion process. Then, from cross-sectional position E to cross-sectional position G, a second waveguide 202 adiabatically converts the light field into a first waveguide 201. Example

[0118] Figure 5 shows a structural schematic diagram of a photonic integrated circuit chip provided in another embodiment of the present application, Figure 6A shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position A, Figure 6B shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position B, Figure 6C shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position C, Figure 6D shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position D, Figure 6E shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position E, and Figure 6F shows a cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position F.

[0119] As shown in FIG5 and FIG6A-FIG6F, in this embodiment, compared to the first embodiment, the optical waveguide layer 310 is further provided with a fourth waveguide 204 in the thickness direction of the substrate layer 601. The fourth waveguide 204 is optically coupled with the third waveguide 203 and extends from the interior of the photonic integrated circuit chip toward the outer end surface. The extension length of the fourth waveguide 204 is less than or equal to the extension length of the third waveguide 203, and the end of the fourth waveguide 204 close to the outer end surface is flush with the end of the third waveguide close to the outer end surface.

[0120] The terms “first,” “second,” “third,” and “fourth” herein are intended to distinguish different objects, rather than to rank the objects or limit the number of the objects.

[0121] A multilayer waveguide is formed by the first waveguide, the second waveguide, the third waveguide, and the fourth waveguide. The multilayer waveguides jointly participate in the light mode spot conversion to reduce the light loss of the photonic integrated circuit chip during the mode spot conversion process. In addition, at a cross-sectional position close to the outer end face of the photonic integrated circuit chip, the second waveguide, the third waveguide, and the fourth waveguide jointly limit the light field to adjust the mode spot size of the light field close to the edge of the photonic integrated circuit chip so that it can match the mode field diameter of the external optical fiber, thereby improving the optical coupling efficiency between the photonic integrated circuit chip and the external optical fiber.

[0122] Illustratively, in this embodiment, the first waveguide 201 , the second waveguide 202 , the third waveguide 203 , and the fourth waveguide 204 are silicon nitride waveguides or silicon oxynitride waveguides.

[0123] In this embodiment, the second waveguide 202, the third waveguide 203, and the fourth waveguide 204 are configured to perform spot conversion on the light coupled from the first waveguide 201 (for example, to expand the spot size of the light) and transmit it to an external optical fiber, or to perform spot conversion on the light input from the external optical fiber (for example, to shrink the spot size of the light) and couple the spot-converted light to the first waveguide 201.

[0124] Illustratively, in this embodiment, the fourth waveguide 204 has a constant cross-sectional width in a direction from the inside of the photonic integrated circuit chip toward the outer end surface.

[0125] In some embodiments, to facilitate processing and manufacturing, the first waveguide 201, the second waveguide 202, the third waveguide 203, and the fourth waveguide 204 are all made of the same material, for example, silicon nitride.

[0126] For example, as shown in Figures 5 and 6A-6F, there are multiple second waveguides 202, for example, three or more, and there are multiple third waveguides 203, for example, three or more. At a cross-sectional position close to the plane where the outer end face is located (for example, at cross-sectional position A), the three second waveguides 202 and the three third waveguides 203 are arranged in multiple rows and / or columns. Between adjacent rows and / or columns, the three second waveguides 202 and the three third waveguides 203 are arranged in an array, and the optical field corresponding to this arrangement matches the optical field coupled from the external optical fiber.

[0127] At cross-sectional position B, the cross-sectional dimensions of the plurality of second waveguides 202 have changed compared to cross-sectional position A. At this point, the cross-sectional dimensions of the plurality of second waveguides 202 are relatively larger, while the cross-sectional dimensions of the plurality of third waveguides 203 and the plurality of fourth waveguides 204 remain unchanged. That is, in this embodiment, from the inner end toward the outer end of the multilayer edge coupler, the third waveguides 203 and the fourth waveguides 204 have a constant cross-sectional width, and the light field is primarily confined to the plurality of second waveguides 202.

[0128] At the cross-sectional position C, there are only the plurality of second waveguides 202 .

[0129] From a cross-sectional position C near the end of the third waveguide 203 to a cross-sectional position D near the end of the first waveguide 201, the plurality of second waveguides 202 are configured to be optically coupled with the first waveguide 201. Specifically, in the thickness direction of the substrate layer 601, the projections of the ends of the first waveguide 201 and the second waveguide 202 overlap so as to be coupled by adiabatic coupling.

[0130] From the cross-sectional position D to the cross-sectional position E, the cross-sectional size of the second waveguide 202 gradually decreases, while the cross-sectional size of the first waveguide 201 gradually increases, and the light field is gradually coupled from the second waveguide 202 into the first waveguide 201 .

[0131] At the cross-sectional position F, there is only the first waveguide 201 . Example

[0132] Figure 7A shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position A, Figure 7B shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position C, and Figure 7C shows another cross-sectional schematic diagram of the photonic integrated circuit chip provided in Figure 5 at cross-sectional position E.

[0133] As shown in Figures 7A to 7C, at cross-sectional position A, compared with Example 3, Example 4 shows that at a cross-sectional position close to the plane where the outer end face is located, the combination of multiple second waveguides 202 and multiple third waveguides 203 is arranged in multiple rows and / or columns; wherein, between adjacent rows and / or columns, the multiple second waveguides 202 and the multiple third waveguides 203 are staggered.

[0134] In some other embodiments, the combination of multiple second waveguides 202 and multiple third waveguides 203 can also be arranged irregularly, that is, the multiple second waveguides are arbitrarily arranged in the plane where they are located, and the multiple third waveguides are arbitrarily arranged in the plane where they are located, and the light field corresponding to the arrangement matches the light field coupled with the external optical fiber.

[0135] From cross-sectional position A to cross-sectional position C, multiple third waveguides 203 and multiple fourth waveguides 204 completely convert the light field into a second waveguide 202 through an intermediate adiabatic conversion process. Then, from cross-sectional position C to cross-sectional position E, a second waveguide 202 adiabatically converts the light field into a first waveguide 201. Example

[0136] FIG8 shows a schematic structural diagram of a photonic integrated circuit chip provided in another embodiment of the present application, and FIG9 shows a schematic cross-sectional diagram of the photonic integrated circuit chip provided in FIG8 at a cross-sectional position A. ...

[0137] As shown in FIG8 , in this embodiment, compared to the first embodiment, the at least one protective layer covers the surface of the at least one functional layer on a side facing away from the substrate layer 601 , but does not completely cover the upper portion of the second region 200 of the photonic integrated circuit chip 1000 . For example, as shown in FIG9 , at cross-sectional position A, the at least one protective layer is not provided on the side of the optical waveguide layer 310 facing away from the substrate layer 601 . This is suitable for situations where the influence of water vapor is relatively small.

[0138] Continuing to refer to Figures 1, 5, and 8, according to another aspect of the present application, a silicon photonic integration platform is further provided, comprising the photonic integrated circuit chip 1000 described in any of the aforementioned embodiments; an optical fiber 400, wherein the optical fiber 400 comprises an optical fiber core 401 and an optical fiber cladding 402 covering the optical fiber core 401; wherein the optical fiber 400 is aligned with the outer end surface of the photonic integrated circuit chip 1000 for optical coupling.

[0139] The present invention aims to reduce optical loss during the spot conversion process in conventional edge couplers with single-layer waveguides by providing multiple layers of waveguides within the optical waveguide layer of a photonic integrated circuit chip. The multiple layers of waveguides participate in the spot conversion process. Furthermore, at least one protective layer is provided on the surface of the photonic integrated circuit chip, distal from the substrate layer, along the thickness direction of the substrate layer. This prevents moisture from entering the surface silicon dioxide layer during long-term use, potentially affecting device performance. This also prevents the intrusion of various contaminants during the packaging process.

[0140] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. All equivalent changes and modifications based on the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A photonic integrated circuit chip, characterized in that: include: A substrate layer, a dielectric layer and an optical waveguide layer are stacked; The photonic integrated circuit chip comprises an optical device arranged in the optical waveguide layer and a device waveguide optically connected to the optical device, and the photonic integrated circuit chip has an external end face coupled to the outside world along a thickness direction perpendicular to the substrate layer; In the thickness direction of the substrate layer, the optical waveguide layer is sequentially stacked with a first waveguide, a second waveguide and a third waveguide: The first waveguide is optically connected to the device waveguide, and an end of the first waveguide facing the outer end surface is at a first lateral distance from the outer end surface; The second waveguide is optically coupled to the first waveguide and is spaced apart from the first waveguide in a thickness direction; The third waveguide is optically coupled to the second waveguide and is spaced apart from the second waveguide in a thickness direction; The first waveguide, the second waveguide and the third waveguide all extend from the interior of the photonic integrated circuit chip to the outer end surface; The photonic integrated circuit chip further comprises at least one protective layer, and the at least one protective layer covers a surface of the photonic integrated circuit chip on a side away from the substrate layer, wherein the material of the protective layer is silicon nitride.

2. The photonic integrated circuit chip according to claim 1, characterized in that: The at least one protective layer covers a surface of the optical waveguide layer on a side away from the substrate layer.

3. The photonic integrated circuit chip according to claim 1, characterized in that: A conductive circuit layer and a metal through hole are also provided in the optical waveguide layer, and the conductive circuit layer realizes electrical connection between each conductive circuit layer or other devices through the metal through hole; The at least one protective layer is in direct contact with the surface of the metal layer. The at least one protective layer is provided with a first through hole penetrating the at least one protective layer in the thickness direction to expose the surface of the metal layer. The first through hole is filled with a conductive material.

4. The photonic integrated circuit chip according to claim 1, characterized in that: The at least one protective layer comprises a first protective layer, a second protective layer, and a dielectric layer disposed between the first protective layer and the second protective layer; Wherein, the material of the dielectric layer is silicon oxide.

5. The photonic integrated circuit chip according to claim 1, characterized in that: In the thickness direction of the substrate layer, the first waveguide and the second waveguide partially overlap in projection so as to be coupled in an adiabatic coupling manner; In a thickness direction perpendicular to the substrate layer, an extension length of the second waveguide is greater than an extension length of the third waveguide, and an end of the second waveguide close to the outer end surface is flush with an end of the third waveguide close to the outer end surface.

6. The photonic integrated circuit chip according to claim 5, characterized in that: The second waveguide and the third waveguide are configured to perform spot-conversion on the light coupled from the first waveguide and transmit it to an external optical fiber, or to perform spot-conversion on the light input from the external optical fiber and couple the spot-converted light to the first waveguide.

7. The photonic integrated circuit chip according to claim 1, characterized in that: The first waveguide and the device waveguide are arranged in the same layer.

8. The photonic integrated circuit chip according to claim 1, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

9. The photonic integrated circuit chip according to claim 1, characterized in that: A portion of the second waveguide is in a reverse wedge-shaped structure in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface.

10. The photonic integrated circuit chip according to claim 1, characterized in that: The third waveguide has a constant cross-sectional width in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface.

11. The photonic integrated circuit chip according to claim 6, characterized in that: The number of the second waveguides is plural, and the number of the third waveguides is plural; At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of third waveguides is arranged in a plurality of rows and / or a plurality of columns; Wherein, at a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of third waveguides are arranged in a staggered manner or in an irregular arrangement.

12. The photonic integrated circuit chip according to claim 11, characterized in that: From the inside of the photonic integrated circuit chip toward the outer end surface, a cross-sectional width of a portion of at least one second waveguide among the plurality of second waveguides gradually becomes thinner toward the outer end surface.

13. The photonic integrated circuit chip according to claim 1, characterized in that: The first waveguide, the second waveguide, and the third waveguide are silicon nitride waveguides or silicon oxynitride waveguides.

14. The photonic integrated circuit chip according to claim 1, characterized in that: In the thickness direction of the substrate layer, the optical waveguide layer is further provided with: A fourth waveguide is optically coupled to the third waveguide and spaced apart from the third waveguide in thickness, and extends from the inside of the photonic integrated circuit chip toward the outer end surface.

15. The photonic integrated circuit chip according to claim 14, characterized in that: An extension length of the fourth waveguide is less than or equal to an extension length of the third waveguide, and an end portion of the fourth waveguide close to the outer end surface is flush with an end portion of the third waveguide close to the outer end surface.

16. The photonic integrated circuit chip according to claim 15, characterized in that: The fourth waveguide has a constant cross-sectional width in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface.

17. The photonic integrated circuit chip according to claim 14, characterized in that: The number of the second waveguides is plural, the number of the third waveguides is plural, and the number of the fourth waveguides is plural; At a cross-sectional position close to the plane where the outer end surface is located, a combination of a plurality of second waveguides, a plurality of third waveguides, and a plurality of fourth waveguides are arranged in a plurality of rows and columns; Between adjacent rows and / or columns, the plurality of second waveguides, the plurality of third waveguides, and the plurality of fourth waveguides are arranged in a staggered manner or in an irregular manner.

18. The photonic integrated circuit chip according to claim 14, characterized in that: The fourth waveguide is a silicon nitride waveguide or a silicon oxynitride waveguide.

19. A silicon photonic integration platform, characterized in that: A photonic integrated circuit chip comprising any one of claims 1 to 18; An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core; Wherein, the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

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