Optical chip structure and manufacturing method therefor

Abstract

The present application relates to an optical chip structure and a manufacturing method therefor. The method comprises: providing a base and a semi-finished chip, wherein the base comprises a first substrate, an isolation dielectric layer formed on the first substrate, a first semiconductor optical device, and a first waveguide, the semi-finished chip comprises a second substrate and a semi-finished thin film layer located on one side of the second substrate, the semi-finished thin film layer and the first waveguide are made of different materials, and the first substrate comprises a silicon substrate; forming a recess in the isolation dielectric layer, wherein the first waveguide is at least partially located between the recess and the first substrate; bonding the semi-finished chip in the recess by means of the semi-finished thin film layer, so that the semi-finished thin film layer is optically coupled to the first waveguide; removing the second substrate of the semi-finished chip to form a second semiconductor optical device; and carrying out metallization to form an electrode structure separately connected to the first semiconductor optical device and the second semiconductor optical device.

Description

Optical chip structure and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 12, 2023, with application number 202310691618.6 and invention name “Optical chip structure and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photonic integration technology, and in particular to an optical chip structure and a preparation method thereof. Background Art

[0003] With the development of photonic integration technology, traditional optical chip structures have the characteristics of high integration and low cost. At the same time, traditional optical chip structures can be integrated with modulators, which can complete the optical and electrical transceiver functions.

[0004] However, although the traditional optical chip structure can complete the optoelectronic transceiver function, there is a problem of high process difficulty caused by the integration of materials of different material systems during the manufacturing process. Summary of the Invention

[0005] Based on this, it is necessary to provide an optical chip structure and a preparation method thereof to address the problem of high process difficulty caused by the integration of materials of different material systems during the production process of the optical chip structure in traditional technology.

[0006] To achieve the above objectives, the present application provides a method for preparing an optical chip structure, comprising:

[0007] Providing a substrate and a semi-finished chip, wherein the substrate includes a first substrate, an isolation dielectric layer formed on the first substrate, a first semiconductor optical device, and a first waveguide; the semi-finished chip includes a second substrate and a semi-finished thin film layer located on one side of the second substrate, wherein the semi-finished thin film layer and the first waveguide are made of materials of different material systems, and the first substrate includes a silicon substrate;

[0008] forming a groove in the isolation dielectric layer, wherein the first waveguide is at least partially located between the groove and the first substrate;

[0009] Bonding the semi-finished chip into the groove via the semi-finished film layer, so that the semi-finished film layer is optically coupled to the first waveguide;

[0010] removing the second substrate of the semi-finished chip to form a second semiconductor optical device;

[0011] Metallization is performed to form electrode structures respectively connecting the first semiconductor optical device and the second semiconductor optical device.

[0012] The above-mentioned method for preparing the optical chip structure forms a groove in the isolation dielectric layer and bonds the semi-finished chip in the groove through the semi-finished thin film layer, so that the first waveguide is well integrated with the semi-finished thin film layer from different material systems, effectively reducing the process difficulty.

[0013] Furthermore, the formation of the groove facilitates light transmission between the first semiconductor optical device and the second semiconductor optical device, and also facilitates the simultaneous metallization process between multiple devices, thus saving process steps.

[0014] In one embodiment, an isolation dielectric layer with a preset thickness is provided between the bottom of the groove and the first waveguide;

[0015] The step of bonding the semi-finished chip into the groove through the semi-finished film layer so as to optically couple the semi-finished film layer with the first waveguide comprises:

[0016] The semi-finished film layer is bonded to the isolation dielectric layer.

[0017] In one embodiment, the semi-finished chip comprises a thin-film lithium niobate chip, the semi-finished thin-film layer comprises a lithium niobate thin-film layer, and the formed second semiconductor optical device comprises a lithium niobate modulator.

[0018] In one embodiment, the semi-finished chip includes a laser chip, the semi-finished thin film layer includes a Group III-V semiconductor material thin film layer, and the formed second semiconductor optical device includes a laser.

[0019] In one embodiment, removing the second substrate of the semi-finished chip to form a second semiconductor optical device includes:

[0020] removing the second substrate of the semi-finished chip;

[0021] Etching the semi-finished thin film layer to form an electrode contact area and an optical processing area;

[0022] A protective dielectric layer is filled in the groove, and the protective dielectric layer covers the second semiconductor optical device.

[0023] In one embodiment, the first waveguide includes a first sub-waveguide and a second sub-waveguide, the semi-finished chip includes a first semi-finished chip and a second semi-finished chip, the first semi-finished chip is optically coupled to the first sub-waveguide, and the second semi-finished chip is optically coupled to the second sub-waveguide.

[0024] In one embodiment, the first semi-finished chip is a thin-film lithium niobate chip, the second semi-finished chip is a laser chip, and the first semi-finished chip and the second semi-finished chip are optically connected via the first sub-waveguide and the second sub-waveguide.

[0025] In one embodiment, the first semiconductor optical device includes a waveguide layer, and the first waveguide is located in the same layer as the waveguide layer of the first semiconductor optical device.

[0026] In one embodiment, the first waveguide and the waveguide layer of the first semiconductor optical device are formed in one process flow.

[0027] The present application also provides an optical chip structure, including:

[0028] A substrate comprising a first substrate, an isolation dielectric layer located on the first substrate, a first semiconductor optical device, and a first waveguide;

[0029] a second semiconductor optical device bonded to the isolation dielectric layer on the first waveguide and optically coupled to the first waveguide, wherein the first waveguide is at least partially located between the second semiconductor optical device and the first substrate;

[0030] an electrode structure, connected to the first semiconductor optical device and the second semiconductor optical device respectively;

[0031] The first semiconductor optical device and the second semiconductor optical device are optically connected via the first waveguide.

[0032] In one embodiment, an isolation dielectric layer with a preset thickness is provided between the first waveguide and the second semiconductor optical device.

[0033] In one embodiment, it further includes:

[0034] The protective dielectric layer covers the second semiconductor optical device.

[0035] In one embodiment, the first waveguide includes a first sub-waveguide and a second sub-waveguide, the second semiconductor optical device includes a first semiconductor sub-device and a second semiconductor sub-device, the first semiconductor sub-device is optically coupled to the first sub-waveguide, and the second semiconductor sub-device is optically coupled to the second sub-waveguide.

[0036] In one embodiment, the first semiconductor sub-device is a lithium niobate modulator, the second semiconductor sub-device is a laser, and the first semiconductor sub-device and the second semiconductor sub-device are optically connected via the first sub-waveguide and the second sub-waveguide.

[0037] In one embodiment, the first semiconductor optical device is a detector, the second semiconductor optical device is a lithium niobate modulator, and the first semiconductor optical device and the second semiconductor optical device are optically connected via the first waveguide. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] FIG1 is a flow chart of a method for preparing an optical chip structure provided in one embodiment;

[0040] FIG2 is a schematic diagram of a cross-sectional structure of an optical chip provided in one embodiment;

[0041] 3 to 9 are schematic cross-sectional views of the optical chip structure obtained during the preparation process provided in one embodiment;

[0042] 10 to 20 are schematic diagrams of cross-sectional structures obtained during the preparation process of an optical chip structure provided in yet another embodiment.

[0043] Explanation of the accompanying drawings: 110 - first substrate, 120 - second substrate, 210 - isolation dielectric layer, 211 - first dielectric layer, 212 - second dielectric layer, 220 - protective dielectric layer, 221 - third dielectric layer, 222 - fourth dielectric layer, 300 - first semiconductor optical device, 310 - silicon-germanium detector, 320 - silicon-based modulator, 330 - thermo-optical modulator, 340 - passive device, 410 - first waveguide, 411 - first sub-waveguide, 412 - second sub-waveguide, 420 - waveguide layer, 510 - semi-finished thin film layer, 520 - buried oxide layer, 600 - groove, 610 - first groove, 620 - second groove, 700 - electrode structure. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0047] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0048] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0049] While embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0050] In one embodiment, referring to FIG1 , a method for preparing an optical chip structure is provided, comprising:

[0051] Step S100, providing a substrate and a semi-finished chip, wherein the substrate includes a first substrate 110, an isolation dielectric layer 210 formed on the first substrate 110, a first semiconductor optical device 300, and a first waveguide 410; the semi-finished chip includes a second substrate 120 and a semi-finished thin film layer 510 located on one side of the second substrate 120, wherein the semi-finished thin film layer 510 and the first waveguide 410 are made of materials of different material systems, and the first substrate 110 includes a silicon substrate;

[0052] Step S200 , forming a groove 600 in the isolation dielectric layer 210 , wherein the first waveguide 410 is at least partially located between the groove 600 and the first substrate 110 ;

[0053] Step S300 , bonding the semi-finished chip into the groove 600 via the semi-finished film layer 510 , so that the semi-finished film layer 510 is optically coupled to the first waveguide 410 ;

[0054] Step S400 , removing the second substrate 120 of the semi-finished chip to form a second semiconductor optical device;

[0055] Step S500 : performing metallization to form an electrode structure 700 respectively connecting the first semiconductor optical device 300 and the second semiconductor optical device.

[0056] In step S100, referring to FIG3 , the base includes a first substrate 110, an isolation dielectric layer 210 formed on the first substrate 110, a first semiconductor optical device 300, and a first waveguide 410. Specifically, the first substrate 110 may include a silicon substrate. The isolation dielectric layer 210 is formed directly on the first substrate 110, and the first semiconductor optical device 300 and the first waveguide 410 are formed within the isolation dielectric layer 210. For example, the first semiconductor optical device 300 includes a silicon-germanium detector 310 and a silicon-based modulator 320. The isolation dielectric layer 210 may be made of silicon dioxide (SiO2).

[0057] In this embodiment, when the first substrate 110 is a silicon substrate, the optical chip is a silicon photonic chip. The silicon photonic chip includes an isolation dielectric layer 210, which may include a first dielectric layer 211 and a second dielectric layer 212. The first dielectric layer 211 is formed directly on the first substrate 110, and the second dielectric layer 212 is formed on the first dielectric layer 211. The first semiconductor optical device 300 and the first waveguide 410 may both be formed within the second dielectric layer 212. The first semiconductor optical device 300 can receive external light.

[0058] The semi-finished chip includes a second substrate 120 and a semi-finished thin film layer 510 located on one side of the second substrate 120. Specifically, the second substrate 120 may include, but is not limited to, a silicon substrate. Furthermore, the second substrate 120 may also be a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. The type of the second substrate 120 does not limit the scope of protection of this application.

[0059] The semi-finished film layer 510 and the first waveguide 410 can be made of materials of different material systems. For example, when the semi-finished film layer 510 is made of lithium niobate, the first waveguide 410 can be made of silicon (Si) or silicon nitride (SiN) of the Group IV material system.

[0060] In step S200 , referring to FIG. 4 , a groove 600 is formed in the isolation dielectric layer 210 . For example, the isolation dielectric layer 210 includes a first dielectric layer 211 and a second dielectric layer 212 . The second dielectric layer 212 can be etched to form the groove 600 . The groove 600 is located in the second dielectric layer 212 .

[0061] As an example, the depth of the groove 600 may be 1.5 μm.

[0062] The first waveguide 410 is at least partially located between the groove 600 and the first substrate 110 . The length of the first waveguide 410 may be greater than the width of the groove 600 . The first waveguide 410 is located below the groove 600 and within the isolation dielectric layer 210 above the first substrate 110 .

[0063] In step S300 , referring to FIG. 5 , the semi-finished film layer 510 is in direct contact with the bottom of the groove 600 , and the semi-finished chip is bonded in the groove 600 through the semi-finished film layer 510 . At this time, the semi-finished film layer 510 can be optically coupled with the first waveguide 410 .

[0064] In step S400 , referring to FIG. 6 , the second substrate 120 of the semi-finished chip is removed to form a second semiconductor optical device.

[0065] In step S500, please refer to Figure 9, the electrode structure 700 can metallize the first semiconductor optical device 300 and the second semiconductor optical device, and the electrode structure 700 connecting the second semiconductor optical device can be formed together with the electrode structure 700 connecting the first semiconductor optical device 300. Both can be formed in the same process flow, which can effectively save process steps and improve process efficiency.

[0066] Various other devices can also be formed within the substrate, such as a thermo-optical modulator 330 and passive devices 340. The thermo-optical modulator 330 can be made of titanium nitride (TiN) or other materials, without limitation. The passive device 340 can be made of silicon nitride (SiN), and the material of the passive device 340 is also not limited and can be selected based on practical needs. The simultaneous integration of multiple devices within the optical chip increases the chip's integration density and enhances its functionality.

[0067] In this embodiment, a groove 600 is formed in the isolation dielectric layer 210, and the semi-finished chip is bonded in the groove 600 through the semi-finished thin film layer 510, so that the first waveguide 410 is well integrated with the semi-finished thin film layer 510 from different material systems, effectively reducing the process difficulty.

[0068] In addition, the formation of the groove 600 facilitates light transmission between the first semiconductor optical device 300 and the second semiconductor optical device 300. At the same time, the formation of the groove 600 also facilitates the simultaneous metallization process between multiple devices, saving process steps.

[0069] In one embodiment, referring to FIG. 5 , an isolation dielectric layer 210 of a predetermined thickness is provided between the bottom of the groove 600 and the first waveguide 410 . Step S300 involves bonding the semi-finished chip to the groove 600 via the semi-finished film layer 510 , optically coupling the semi-finished film layer 510 to the first waveguide 410 , and includes:

[0070] The semi-finished film layer 510 is bonded to the isolation dielectric layer 210 .

[0071] When etching the isolation dielectric layer 210 to form the groove 600, the bottom of the groove 600 may not contact the first waveguide 410. A gap exists between the groove 600 and the first waveguide 410, leaving a predetermined thickness of the isolation dielectric layer 210 at the bottom of the groove 600. For example, the predetermined thickness may be 80 nm. At this point, the semi-finished thin film layer 510 is bonded to the isolation dielectric layer 210.

[0072] As an example, when the isolation dielectric layer 210 includes a first dielectric layer 211 and a second dielectric layer 212 , a second dielectric layer 212 with a predetermined thickness is retained at the bottom of the groove 600 .

[0073] In this embodiment, by retaining the isolation dielectric layer 210 between the bottom of the groove 600 and the first waveguide 410 , the semi-finished film layer 510 is bonded to the isolation dielectric layer 210 , which is more conducive to optimizing device performance.

[0074] In one embodiment, step S400 removes the second substrate 120 of the semi-finished chip to form a second semiconductor optical device, including:

[0075] Step S410, removing the second substrate 120 of the semi-finished chip;

[0076] Step S420 , etching the semi-finished thin film layer 510 to form an electrode contact area and an optical processing area;

[0077] In step S430 , the groove 600 is filled with a protective dielectric layer 220 , and the protective dielectric layer 220 covers the second semiconductor optical device.

[0078] In step S410 , the second substrate 120 of the semi-finished chip is removed, and the semi-finished film layer 510 is retained.

[0079] In step S420, referring to FIG. 7 , the semi-finished thin film layer 510 is etched to form the semi-finished thin film layer 510 into a predetermined shape, thereby forming an electrode contact area and an optical processing area. The electrode contact area may be formed with an electrode structure, and the optical processing area may perform optical functions such as generating laser light or modulating or absorbing light. Specifically, dry etching may be employed, including at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP). Due to the anisotropic nature of dry etching, the semi-finished thin film layer 510 can be formed into the predetermined shape.

[0080] In step S430 , referring to FIG. 8 , the protective dielectric layer 220 is filled in the groove 600 , and the protective dielectric layer 220 covers the second semiconductor optical device.

[0081] The protective dielectric layer 220 and the isolation dielectric layer 210 can both be made of silicon dioxide (SiO 2 ). Of course, the materials of the protective dielectric layer 220 and the isolation dielectric layer 210 can also be different, which is not limited here.

[0082] After step S430, a metal stack may be formed to connect to the second semiconductor optical device. The number of metal stacks is not limited. The metal stack facilitates routing of the entire optical chip, and other components may be formed between the metal stacks.

[0083] In one embodiment, referring to FIG. 3 , a substrate and a semi-finished chip are provided. The substrate includes a first substrate 110, an isolation dielectric layer 210 formed on the first substrate 110, a first semiconductor optical device 300, and a first waveguide 410. When the semi-finished chip is a thin-film lithium niobate chip, the thin-film lithium niobate chip includes a second substrate 120 and a lithium niobate thin film layer located on one side of the second substrate 120. The lithium niobate thin film layer and the first waveguide 410 are made of materials of different material systems. When the semi-finished chip is a laser chip, the laser chip includes a second substrate 120 and a laser thin film layer 512 located on one side of the second substrate 120. The laser thin film layer 512 and the first waveguide 410 are made of materials of different material systems.

[0084] In one embodiment, referring to FIG5 , a thin-film lithium niobate chip is bonded within the groove 600 via a lithium niobate thin film layer, thereby optically coupling the lithium niobate thin film layer to the first waveguide 410. Alternatively, a laser chip is bonded within the groove 600 via a Group III-V semiconductor material thin film layer, thereby optically coupling the Group III-V semiconductor material thin film layer to the first waveguide 410.

[0085] In one embodiment, referring to Figure 6 , when the semi-finished chip is a thin-film lithium niobate chip, the second substrate 120 of the thin-film lithium niobate chip is removed, leaving the lithium niobate thin film layer. Specifically, the second substrate 120 includes a base layer and a buried oxide layer 520 (BOX). The buried oxide layer 520 (BOX) can be formed by oxygen ion implantation. The entire second substrate 120, including the base layer and buried oxide layer 520 (BOX), is removed, leaving only the lithium niobate thin film layer within the groove 600.

[0086] Alternatively, when the semi-finished chip is a laser chip, an N-type semiconductor layer and a P-type semiconductor layer are formed on the laser chip before bonding, thereby forming a semi-finished chip. This can avoid incompatibility between chips made of different material systems during the process. The second substrate 120 of the laser chip, which will become the semi-finished chip, is removed, leaving behind the Group III-V semiconductor material thin film layer. Specifically, the stacked N-type semiconductor layer, light-emitting layer, and P-type semiconductor layer remain.

[0087] In one embodiment, referring to FIG. 7, when the semi-finished chip is a thin-film lithium niobate chip, the semi-finished thin film layer is a lithium niobate thin film layer, and the lithium niobate thin film layer is etched to form an electrode contact area and an optical processing area. For example, when etching the lithium niobate thin film layer, the lithium niobate thin film layer can be etched into a preset shape of a "convex" character. At this time, partial etching of the lithium niobate thin film layer is required, that is, etching both sides of the lithium niobate thin film layer so that the height of both sides is less than the height of the middle part of the lithium niobate thin film layer, thereby forming electrode contact areas on both sides of the lithium niobate thin film layer. Making the lithium niobate thin film layer in the preset shape of a "convex" character can enable the lithium niobate modulator to obtain better performance.

[0088] Alternatively, when the semi-finished chip is a laser chip, the semi-finished thin film layer is a III-V semiconductor material thin film layer, and the III-V semiconductor material thin film layer is etched to form an electrode contact area and an optical processing area. Specifically, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor layer are etched in sequence. For example, the III-V semiconductor material thin film layer can be etched into a preset shape of a "convex" character. At this time, before bonding, the laser chip first forms an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer, thereby forming a semi-finished chip. The laser chip that has become a semi-finished chip is etched so that both sides of the P-type semiconductor and both sides of the light-emitting layer are completely etched away, while a partial thickness is retained on both sides of the N-type semiconductor layer, and only partial etching is performed.

[0089] In one embodiment, referring to FIG. 8, when the second semiconductor optical device is a lithium niobate modulator, the lithium niobate modulator is covered by a protective dielectric layer 220. Specifically, the lithium niobate modulator is covered by a third dielectric layer 221. Alternatively, when the second semiconductor optical device is a laser, the laser is covered by a protective dielectric layer 220. Specifically, the laser is covered by a fourth dielectric layer 222.

[0090] In one embodiment, referring to FIGS. 10 to 20, the first waveguide 410 includes a first sub-waveguide 411 and a second sub-waveguide 412. The semi-finished chip includes a first semi-finished chip and a second semi-finished chip. The first semi-finished chip is optically coupled to the first sub-waveguide 411, and the second semi-finished chip is optically coupled to the second sub-waveguide 412.

[0091] As an example, the first semi-finished chip can be a thin-film lithium niobate chip, and the second semi-finished chip can be a laser chip. In this case, referring to FIG11 , the groove 600 includes a first groove 610 and a second groove 620 . Referring to FIG12 , the thin-film lithium niobate chip can be bonded within the first groove 610 via a lithium niobate thin film layer. Referring to FIG13 , the laser chip can be bonded within the second groove 620 via a Group III-V semiconductor material thin film layer. The thin-film lithium niobate chip is optically coupled to the first sub-waveguide 411 , and the laser chip is optically coupled to the second sub-waveguide 412 . The thin-film lithium niobate chip and the laser chip are optically connected via the first sub-waveguide 411 and the second sub-waveguide 412 .

[0092] The second groove 620 can be formed in the isolation dielectric layer 210 simultaneously with the first groove 610. Of course, the second groove 620 can also be formed after the thin film lithium niobate chip bonding is completed. The formation time of the second groove 620 is not limited here.

[0093] Referring to Figures 12 and 13 , the thin-film lithium niobate chip can be bonded into the first groove 610 before the laser chip is bonded into the second groove 620. The thin-film lithium niobate chip substrate is then removed, filling the first groove 610. Finally, the laser chip substrate is removed.

[0094] Alternatively, the laser chip may be bonded into the second groove 620 after the thin-film lithium niobate chip is bonded into the first groove 610 .

[0095] Then, the substrate of the laser chip can be removed at the same time as the substrate of the thin-film lithium niobate chip is removed.

[0096] Traditional silicon photonic chips offer the advantages of high integration and low cost, and their onboard silicon germanium high-speed detectors perform well. However, traditional silicon photonic chips also suffer from the disadvantages of being unable to generate light and having limited modulator bandwidth. A single thin-film lithium niobate modulator, while offering the advantages of high bandwidth and low loss, cannot integrate other detectors and cannot generate light. A single laser has the advantage of being able to generate light, but suffers from poor integration and high cost. In this embodiment, a first semi-finished chip and a second semi-finished chip are simultaneously bonded within the photonic chip. The first semi-finished chip can later form the lithium niobate modulator, while the second semi-finished chip can later form the laser. The laser emits light, while the lithium niobate modulator receives and outputs the light sent by the light source. Furthermore, a first semiconductor optical device 300 is formed within the photonic chip, serving as the receiving end of the photonic chip, receiving light from the lithium niobate modulator as well as external light. Through hybrid integration, a complete silicon photonic chip is formed, with the complementary advantages of each structure within the silicon photonic chip, realizing the photoelectric transceiver function of the silicon photonic chip.

[0097] In one embodiment, the first semiconductor optical device 300 includes a waveguide layer 420 , and the first waveguide 410 is located in the same layer as the waveguide layer 420 of the first semiconductor optical device 300 .

[0098] As an example, the waveguide layer 420 of the first semiconductor optical device 300 can be formed together with the first waveguide 410, that is, both can be formed in a single process flow. For example, a waveguide material layer can be first formed on the first dielectric layer 211, and then the waveguide material layer can be etched to form the waveguide layer 420 and the first waveguide 410.

[0099] In this example, the waveguide layer 420 and the first waveguide 410 are formed in one process flow, which saves process steps and improves process efficiency.

[0100] It should be understood that although the various steps in the flowchart of FIG1 are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in FIG1 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0101] In one embodiment, referring to FIG. 2 , an optical chip structure is provided, including a substrate, a second semiconductor optical device, and an electrode structure 700 .

[0102] The base includes a first substrate 110 , an isolation dielectric layer 210 located on the first substrate 110 , a first semiconductor optical device 300 , and a first waveguide 410 .

[0103] As an example, the isolation dielectric layer 210 includes a first dielectric layer 211 and a second dielectric layer 212 . The first dielectric layer 211 is located on the first substrate 110 . The second dielectric layer 212 is located on the first substrate 110 . The first semiconductor optical device 300 and the first waveguide 410 are located in the second dielectric layer 212 .

[0104] The second semiconductor optical device is bonded to the isolation dielectric layer 210 on the first waveguide 410 and optically coupled to the first waveguide 410 . The first waveguide 410 is at least partially located between the second semiconductor optical device and the first substrate 110 .

[0105] The first semiconductor optical device 300 and the second semiconductor optical device are optically connected via a first waveguide 410 .

[0106] As an example, the first semiconductor optical device 300 may be a detector, the second semiconductor optical device may be a lithium niobate modulator, and the first semiconductor optical device 300 and the second semiconductor optical device may be optically connected via the first waveguide 410 .

[0107] As an example, the isolation dielectric layer 210 includes a first dielectric layer 211 and a second dielectric layer 212 , and the second semiconductor optical device is bonded in the second dielectric layer 212 .

[0108] The length of the first waveguide 410 may be greater than the width of the second optical device.

[0109] The electrode structure 700 is connected to the first semiconductor optical device 300 and the second semiconductor optical device respectively.

[0110] In this embodiment, the second semiconductor optical device and the first semiconductor optical device 300 are integrated together in the optical chip. The first semiconductor optical device 300 serves as the receiving end of the entire optical chip, and the second semiconductor optical device serves as the transmitting end of the entire optical chip. The transmitting end and the receiving end are integrated in a single optical chip at the same time, which can fully realize the optoelectronic transceiver function and meet the needs of the next generation of optoelectronic transceiver modules.

[0111] In one embodiment, an isolation dielectric layer 210 of a predetermined thickness is provided between the first waveguide 410 and the second semiconductor optical device. The second semiconductor optical device may not be in contact with the first waveguide 410, and an isolation dielectric layer 210 of a predetermined thickness remains between the first waveguide 410 and the second semiconductor optical device. For example, the predetermined thickness may be 80 nm.

[0112] In one embodiment, the optical chip structure further includes a protective dielectric layer 220. The protective dielectric layer 220 covers the second semiconductor optical device.

[0113] In one embodiment, the first waveguide 410 includes a first sub-waveguide 411 and a second sub-waveguide 412, and the second semiconductor optical device includes a first semiconductor sub-device and a second semiconductor sub-device. The first semiconductor sub-device is optically coupled to the first sub-waveguide 411, and the second semiconductor sub-device is optically coupled to the second sub-waveguide 412.

[0114] As an example, the first semiconductor sub-device may be a lithium niobate modulator, and the second semiconductor sub-device may be a laser. The lithium niobate modulator is optically coupled to the first sub-waveguide 411, and the laser is optically coupled to the second sub-waveguide 412. Furthermore, the lithium niobate modulator and the laser are optically connected to each other via the first sub-waveguide 411 and the second sub-waveguide 412.

[0115] In the entire optical chip, the first semiconductor sub-device can be a lithium niobate modulator, the second semiconductor sub-device can be a laser, and the first semiconductor optical device 300 can be a silicon germanium high-speed modulator. The laser emits an optical signal, the lithium niobate modulator receives the optical signal emitted by the laser, processes it and outputs it, and the silicon germanium high-speed modulator receives the optical signal from the lithium niobate modulator and the optical signal outside the optical chip.

[0116] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0117] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing an optical chip structure, characterized in that: include: Providing a substrate and a semi-finished chip, wherein the substrate comprises a first substrate, an isolation dielectric layer formed on the first substrate, a first semiconductor optical device and a first waveguide, wherein the semi-finished chip comprises a second substrate and a semi-finished thin film layer located on one side of the second substrate, wherein the semi-finished thin film layer and the first waveguide are made of materials of different material systems, and wherein the first substrate comprises a silicon substrate; forming a groove in the isolation dielectric layer, wherein the first waveguide is at least partially located between the groove and the first substrate; Bonding the semi-finished chip into the groove through the semi-finished film layer, so that the semi-finished film layer is optically coupled with the first waveguide; Removing the second substrate of the semi-finished chip to form a second semiconductor optical device; Metallization is performed to form electrode structures respectively connecting the first semiconductor optical device and the second semiconductor optical device.

2. The method for preparing an optical chip structure according to claim 1, characterized in that: The isolation dielectric layer having a preset thickness is provided between the bottom of the groove and the first waveguide; The step of bonding the semi-finished chip into the groove through the semi-finished film layer so that the semi-finished film layer is optically coupled with the first waveguide comprises: The semi-finished film layer is bonded to the isolation dielectric layer.

3. The method for preparing an optical chip structure according to claim 1, characterized in that: The semi-finished chip comprises a thin-film lithium niobate chip, the semi-finished thin-film layer comprises a lithium niobate thin-film layer, and the formed second semiconductor optical device comprises a lithium niobate modulator.

4. The method for preparing an optical chip structure according to claim 1, characterized in that: The semi-finished chip includes a laser chip, the semi-finished thin film layer includes a thin film layer of Group III-V semiconductor material, and the formed second semiconductor optical device includes a laser.

5. The method for preparing an optical chip structure according to claim 1, characterized in that: The step of removing the second substrate from the semi-finished chip to form a second semiconductor optical device comprises: removing the second substrate of the semi-finished chip; Etching the semi-finished thin film layer to form an electrode contact area and an optical processing area; A protective dielectric layer is filled in the groove, and the protective dielectric layer covers the second semiconductor optical device.

6. The method for preparing an optical chip structure according to claim 1, characterized in that: The first waveguide includes a first sub-waveguide and a second sub-waveguide, the semi-finished chip includes a first semi-finished chip and a second semi-finished chip, the first semi-finished chip is optically coupled to the first sub-waveguide, and the second semi-finished chip is optically coupled to the second sub-waveguide.

7. The method for preparing an optical chip structure according to claim 6, characterized in that: The first semi-finished chip is a thin-film lithium niobate chip, the second semi-finished chip is a laser chip, and the first semi-finished chip and the second semi-finished chip are optically connected via the first sub-waveguide and the second sub-waveguide.

8. The method for preparing an optical chip structure according to claim 1, characterized in that: The first semiconductor optical device includes a waveguide layer, and the first waveguide is located at the same layer as the waveguide layer of the first semiconductor optical device.

9. The method for preparing an optical chip structure according to claim 8, characterized in that: The first waveguide and the waveguide layer of the first semiconductor optical device are formed in one process flow.

10. An optical chip structure, characterized in that: include: A substrate, comprising a first substrate, an isolation dielectric layer located on the first substrate, a first semiconductor optical device and a first waveguide; a second semiconductor optical device bonded to the isolation dielectric layer on the first waveguide and optically coupled to the first waveguide, wherein the first waveguide is at least partially located between the second semiconductor optical device and the first substrate; an electrode structure, connected to the first semiconductor optical device and the second semiconductor optical device respectively; The first semiconductor optical device and the second semiconductor optical device are optically connected via the first waveguide.

11. The optical chip structure according to claim 10, characterized in that: An isolation dielectric layer with a preset thickness is provided between the first waveguide and the second semiconductor optical device.

12. The optical chip structure according to claim 10, characterized in that: Also includes: The protective dielectric layer covers the second semiconductor optical device.

13. The optical chip structure according to claim 10, characterized in that: The first waveguide includes a first sub-waveguide and a second sub-waveguide, the second semiconductor optical device includes a first semiconductor sub-device and a second semiconductor sub-device, the first semiconductor sub-device is optically coupled to the first sub-waveguide, and the second semiconductor sub-device is optically coupled to the second sub-waveguide.

14. The optical chip structure according to claim 13, characterized in that: The first semiconductor sub-device is a lithium niobate modulator, the second semiconductor sub-device is a laser, and the first semiconductor sub-device and the second semiconductor sub-device are optically connected via the first sub-waveguide and the second sub-waveguide.

15. The optical chip structure according to claim 10, characterized in that: The first semiconductor optical device is a detector, the second semiconductor optical device is a lithium niobate modulator, and the first semiconductor optical device and the second semiconductor optical device are optically connected via the first waveguide.

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