Method for dicing bonding wafer, and chip die

Abstract

Provided in the present application are a method for dicing a bonding wafer, and a chip die. The bonding wafer comprises a first body material layer of a first wafer, a second body material layer of a second wafer, and an intermediate layer located between the first body material layer and the second body material layer. The method comprises carrying out processing by means of a first wafer dicing process and penetrating through a first body material layer, and forming a first trench; carrying out processing, by means of a second wafer dicing process, from the bottom surface of the first trench and penetrating through an intermediate layer, and forming a second trench; and carrying out processing from the bottom surface of the second trench and penetrating through a second body material layer, and obtaining a chip die. In the technical solution of the present application, a silicon material of the first body material layer of the first wafer is removed in advance, the intermediate layer containing a functional layer of the wafer is exposed, and dicing cutting is then directly performed on the intermediate layer, thus damage to the intermediate layer, especially the functional layer, during the wafer dicing method is reduced.

Description

A method for dicing bonded wafers and a chip bare crystal

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 12, 2023, with application number 202310687695.4 and invention name “A method for dicing bonded wafers and chip bare crystals”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip packaging, and more specifically, to a method for dicing a bonded wafer and a chip bare die. Background Art

[0003] Wafer dicing refers to the process of cutting a single or multiple die from a wafer for subsequent die bonding, wire bonding, and testing. A bonded wafer is generally formed by bonding at least two wafers. For example, a bonded wafer can be formed by hybrid bonding of two wafers, wherein an intermediate layer can be provided between the bulk material layers of the two wafers. The intermediate layer can be composed of a functional layer of a wafer including metal wiring and dielectric material, and a bonding layer including bonding metal. The functional layer can include a low-k layer or an extremely low-k (ELK) layer with low dielectric strength or weak interlayer bonding.

[0004] Currently, most wafer scribing methods use direct blade scribing or laser grooving followed by blade scribing. For bonded wafers, especially hybrid-bonded wafers, direct blade scribing can cause stress in the intermediate layers, especially the functional layers of the wafer, leading to delamination or cracking, particularly the low-k layer or ELK layer. These defects are difficult to detect because they are obscured by the top wafer's bulk material layer. Laser grooving requires the removal of the top wafer's bulk material and intermediate layers. Due to the thickness of these layers, laser grooving requires greater laser grooving energy, which increases the heat-affected zone of the intermediate layers, especially the functional layers of the wafer. Furthermore, defects such as thermal damage caused by laser grooving are difficult to detect because they are obscured by the top wafer's bulk material layer.

[0005] Summary of the Invention

[0006] The present application provides a method for slicing a bonded wafer and a chip bare crystal obtained by the method. The method reduces the damage to the intermediate layer, especially the functional layer of the wafer, caused by the wafer slicing method by removing the silicon material of the slicing path of the first main material layer in advance to expose the intermediate layer, and then directly slicing and cutting the intermediate layer.

[0007] In a first aspect, a method for dicing a bonded wafer is provided, wherein the bonded wafer includes a first bulk material layer of a first wafer, a second bulk material layer of a second wafer, and an intermediate layer located between the first bulk material layer and the second bulk material layer. The method includes: processing and penetrating the first bulk material layer through a first wafer dicing process to generate a first groove; processing from the bottom surface of the first groove and penetrating the intermediate layer through a second wafer dicing process to generate a second groove; processing from the bottom surface of the second groove and penetrating the second bulk material layer to obtain a chip bare crystal.

[0008] According to the technical solution provided in the present application, the material in the scribing area of ​​the first main material layer is removed in advance to expose the intermediate layer, and then the intermediate layer is directly processed, thereby avoiding defects such as delamination and cracking of the intermediate layer, especially the functional layer of the wafer, caused by direct blade scribing, and large heat-affected zone and thermal damage of the intermediate layer, especially the functional layer of the wafer, caused by laser processing scribing.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the width of the second groove is smaller than the width of the first groove, so that the middle sublayer of the chip bare crystal includes a first portion located at the edge of the middle sublayer and not covered by the first body material sublayer of the chip bare crystal.

[0010] According to the technical solution provided in this application, the wafer scribing process for processing the intermediate layer will not affect the side wall surface of the first groove, and the defects of the intermediate layer or the intermediate sublayer on the connecting surface between the first main material layer and the intermediate layer can be directly obtained through appearance inspection.

[0011] In combination with the first aspect, in certain implementations of the first aspect, a reference cable is provided on the first part of the intermediate sublayer near the surface of the first main material sublayer, and the reference cable is used to determine the processing position of the first wafer dicing process and / or the second wafer dicing process.

[0012] According to the technical solution provided in this application, the first wafer dicing process and the second wafer dicing process can be aligned using a reference cable, the alignment is relatively accurate, and the reference cable can be used to check whether the processing position of the wafer dicing process is offset.

[0013] In combination with the first aspect, in some implementations of the first aspect, the first wafer scribing process includes a plasma etching process.

[0014] According to the technical solution provided in the present application, the end position of the first wafer scribing process can be determined by judging the rate of removing the bottom surface material of the first groove.

[0015] In combination with the first aspect, in some implementations of the first aspect, the second wafer scribing process includes a laser processing process.

[0016] According to the technical solution provided by this application, it can be ensured that all materials in the scribe line area of ​​the intermediate layer are removed and the intermediate sublayer will not crack or delaminate. In addition, since the thickness of the intermediate layer is thinner than that of the first bulk material layer, compared with the first bulk material layer and the intermediate layer with a larger total thickness processed by laser, this application uses laser to directly process the thinner intermediate layer. The power or grooving energy used by the laser grooving is smaller, and thus the heat-affected zone and the laser processing cause less thermal damage to the intermediate layer, especially the functional layer of the wafer.

[0017] In combination with the first aspect, in some implementations of the first aspect, processing from the bottom surface of the second trench and penetrating the second body material layer includes: processing from the bottom surface of the second trench to generate a third trench until penetrating the second body material layer.

[0018] In combination with the first aspect, in some implementations of the first aspect, the third wafer scribing process includes a blade cutting process.

[0019] According to the technical solution provided in this application, the dicing efficiency of the blade cutting process is faster and the cost is lower.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the width of the third groove is smaller than the width of the second groove, so that the second body material sublayer of the chip bare crystal includes a first portion located at the edge of the second body material sublayer and not covered by the middle sublayer of the chip bare crystal.

[0021] According to the technical solution provided in this application, the third wafer scribing process does not cause damage to the sidewalls of the second groove, that is, it does not cause damage to the middle sublayer, ensuring that the metal wiring and dielectric materials in the middle sublayer will not be affected.

[0022] In combination with the first aspect, in some implementations of the first aspect, the bottom surface of the first trench is a first surface connecting the intermediate layer and the first body material layer.

[0023] According to the technical solution provided in the present application, the first wafer scribing process has almost no impact on the intermediate layer, and the processing cost of the first wafer scribing process can be saved.

[0024] In combination with the first aspect, in some implementations of the first aspect, the bonded wafer is formed by hybrid bonding of a first wafer and a second wafer.

[0025] In the second aspect, a chip bare crystal is provided, comprising a first body material sublayer, an intermediate sublayer, and a second body material sublayer; the intermediate sublayer is located between the first body material sublayer and the second body material sublayer and connects the first body material sublayer and the second body material sublayer, the intermediate sublayer comprises a first part and a second part, the first part of the intermediate sublayer is located at the edge of the intermediate sublayer and is not covered by the first body material sublayer, and the second part of the intermediate sublayer is covered by the first body material sublayer.

[0026] According to the technical solution provided in the present application, defects at the connection surface between the intermediate sub-layer and the first main body material sub-layer can be effectively inspected.

[0027] In combination with the second aspect, in certain implementations of the second aspect, the side surface of the first body material sub-layer is formed by a plasma etching process.

[0028] In combination with the second aspect, in certain implementations of the second aspect, the side surface of the first portion of the intermediate sublayer is formed by a laser processing process.

[0029] In combination with the second aspect, in certain implementations of the second aspect, the second main body material sublayer includes a first part and a second part, the first part of the second main body material sublayer is located at the edge of the second main body material sublayer and is not covered by the intermediate sublayer, and the second part of the second main body material sublayer is covered by the intermediate sublayer.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the side surface of the first portion of the second body material sub-layer is formed by a blade cutting process.

[0031] In combination with the second aspect, in certain implementations of the second aspect, a reference cable is provided on the first part of the intermediate sublayer near the surface of the first main material sublayer, and the reference cable is located between the side of the first main material sublayer and the side of the first part of the intermediate sublayer.

[0032] In a third aspect, an integrated circuit chip is provided, comprising the second aspect or any possible chip bare crystal of the second aspect.

[0033] Optionally, the integrated circuit chip may be any one of a microprocessor chip, a memory chip, a sensor chip, a driver chip and a communication chip.

[0034] In a fourth aspect, an electronic device is provided, which includes the second aspect or any possible chip bare crystal of the second aspect or the integrated circuit chip of the third aspect.

[0035] Optionally, the electronic device may be an intelligent terminal device such as a mobile phone, a personal computer or an information processing center, or may be a device or server with data processing capabilities such as a cloud server, a network server, an application server or a management server. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic diagram of a wafer dicing process provided in an embodiment of the present application.

[0037] FIG2 is a schematic diagram of a bonded wafer provided in an embodiment of the present application.

[0038] FIG3 is a schematic flow chart of a wafer dicing method provided in an embodiment of the present application.

[0039] FIG4 is a flow chart of a wafer dicing method provided in an embodiment of the present application.

[0040] FIG5 is a schematic diagram of a bonded wafer including a reference cable provided in an embodiment of the present application.

[0041] FIG6 is a schematic diagram of a chip bare die provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solution in this application will be described below with reference to the accompanying drawings.

[0043] In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0044] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0045] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0046] In order to facilitate understanding of the technical solution of this application, the professional terms mentioned in this application are briefly explained below.

[0047] 1. Wafer dicing

[0048] The process of wafer dicing is to divide the entire wafer containing chips or integrated circuits into individual chip dies according to the size of the chips or integrated circuits.

[0049] Figure 1 shows a schematic diagram 100 of a wafer dicing process. Figure 1 (a) shows a wafer 110, which may include a bulk material layer such as a silicon material layer, and a functional layer including metal wiring or dielectric material. Figure 1 (b) shows a wafer 110 containing one or more integrated circuits 120. The surface of the wafer 110 is marked with dicing lanes 130 to indicate the wafer division position during the wafer dicing process. The area of ​​the dicing lanes 130 does not include the metal wiring of the integrated circuit 120, so the division position of the dicing lanes 130 will not directly cut into the circuit in the wafer. Finally, after the wafer 110 is divided, individual chip dies are formed as shown in Figure 1 (c). The chip dies 140 and 150 can be two chip dies made of different materials, using different processes or having different functions. For example, the chip dies 140 and 150 are a memory chip and a processor chip, respectively.

[0050] (d) in Figure 1 shows a schematic diagram of an integrated circuit chip including chip dies 140 and 150. The integrated chip packages the chip dies 140 and 150 together to form a three-dimensional stacked chip structure. Among them, the chip dies 140 and 150 can be regarded as top chips (top chip), and the silicon interposer 160 can be regarded as the bottom chip (bottom chip). The chip dies 140, 150 and the silicon interposer 160 can be interconnected vertically through micro-bumps 152 and through silicon vias (through silicon vias) 162. The silicon interposer 160 and the packaging substrate 170 are connected vertically through solder 172, ultimately forming a packaged integrated circuit chip including the chip dies 140 and 150.

[0051] 2. Wafer bonding

[0052] Wafer bonding involves combining two wafers of the same or different materials under certain conditions, creating a single piece by combining them through van der Waals, molecular, and even atomic forces. For ease of understanding, the resulting wafer formed by these two wafers is referred to as a "bonded wafer."

[0053] Figure 2 shows a schematic diagram of a bonded wafer comprising two wafers. Figure 2(a) shows a front view of the bonded wafer, which includes a first bulk material layer of the first wafer, a second bulk material layer of the second wafer, and an intermediate layer, wherein the intermediate layer may include a functional layer, a bonding layer, etc. of the first wafer and / or the second wafer.

[0054] (b) in Figure 2 shows a cross-sectional schematic diagram of a bonded wafer formed by a hybrid bonding method, wherein the bonded wafer includes a first bulk material layer 210 and a first functional layer 220 of a first wafer, a second functional layer 240 and a second bulk material layer 250 of a second wafer, and a bonding layer 230 between the first wafer and the second wafer. Among them, the first functional layer 220 and the second functional layer 240 include an inner metal 224 for circuit wiring, and a dielectric material (the cross-sectional shaded area of ​​the first functional layer 220 and the second functional layer 240 is shown in the figure). The bonding layer 230 may include an adhesive or bonding metal for achieving a bonding connection. For example, in the process of hybrid bonding, the bonding layer may include a bonding metal 236, such as copper. Optionally, the first functional layer 220 and / or the second functional layer 240 also include a sealing coil 218 for dividing the circuit range and sealing and protecting the circuit. Optionally, the first bulk material layer 210 may include through silicon vias 212 for forming micro bumps 152 as shown in (d) of FIG1 . In the above hybrid bonding method, the combination of the first functional layer 220, the bonding layer 230, and the second functional layer 240 may be considered as an intermediate layer between the bulk material layers of the two wafers in the bonded wafer.

[0055] The bonded wafer can also be obtained by other bonding methods. For example, the bonded wafer can be obtained by a fusing bonding method. As shown in (c) in Figure 2, during the fusing bonding process, the first bulk material layer 210 of the first wafer and the second functional layer 250 of the second wafer are bonded to each other through the bonding layer 230. At this time, the combination of the bonding layer 230 and the second functional layer 250 can be regarded as an intermediate layer located between the bulk material layers of the two wafers in the bonded wafer. In other embodiments of the present application, the intermediate layer may also not include the bonding layer 230, that is, the first bulk material layer 210 and the second functional layer 250 can be directly bonded by intermolecular forces or the like.

[0056] It is worth noting that the cross-sectional views of the bonded wafer shown in (b) and (c) of Figure 2 do not limit the structure of the bonded wafer of the present application. The present application can also use other bonding methods to obtain the bonded wafer, such as diffusion bonding.

[0057] In an embodiment of the present application, the wafer 110 shown in (a) and (b) in Figure 1 is the structure of the bonded wafer shown in Figure 2. By dicing the dicing area shown in Figure 2, one or more chip bare crystals shown in (c) in Figure 1 are finally obtained. According to the current wafer dicing method, the bonded wafer can be regarded as a three-layer structure, including a first bulk material layer of a first wafer, a second bulk material layer of a second wafer, and an intermediate layer located between the first bulk material layer and the second bulk material layer. Correspondingly, the obtained chip bare crystal includes a three-layer structure, namely, a first bulk material sublayer, a second bulk material sublayer, and an intermediate sublayer located between the first bulk material sublayer and the second bulk material sublayer. For the convenience of description, the intermediate layer composed of the functional layer and / or bonding layer is described as a whole in the following figures.

[0058] Currently, wafer scribing methods mostly use direct blade scribing or laser grooving followed by blade scribing. For example, the direct blade scribing method uses a high-speed rotating diamond blade (a blade made of diamond particles and resin, ceramic, or metal) to directly cut the scribing lines. The laser grooving followed by blade scribing method uses a laser to first process the scribing lines of the first bulk material layer and the intermediate layer. After the laser processing penetrates the first bulk material layer and the intermediate layer, the high-speed rotating diamond blade is used to cut the scribing lines of the second bulk material layer.

[0059] In the current wafer scribing method, the first bulk material layer and the intermediate layer are mostly processed by the same wafer scribing process, which increases the difficulty of processing silicon materials and dielectric materials at the same time. Moreover, in the intermediate layer, the dielectric material of the functional layer of the wafer is usually a brittle material or a material with weak interlayer bonding force such as SiO2 and SiCN. The direct blade scribing method is prone to cause defects such as delamination or cracking of the dielectric material, and fragmentation of the contact surface between the first bulk material layer and the intermediate layer. When laser processing the first bulk material layer and the intermediate layer, due to the large total thickness of the first bulk material layer and the intermediate layer, the laser processing requires a large power or slotting energy so that the laser can completely remove the material in the scribing area of ​​the first bulk material layer and the intermediate layer. Furthermore, due to the large power or energy required for laser processing, the area of ​​the heat-affected zone caused by laser processing increases, thereby causing thermal damage to the intermediate layer, especially the functional layer of the wafer.

[0060] In order to reduce the damage caused by the dicing method to the intermediate layer, especially the functional layer of the wafer, the present application shows a wafer dicing method 300, which can be applied to the dicing of the bonded wafer shown in Figure 2. Figure 3 shows a schematic flow chart of method 300, and Figure 4 shows a schematic flow chart of method 300. Method 300 includes steps 310 to 330, which first removes the silicon material of the dicing lane of the first bulk material layer to expose the intermediate layer, and then directly dicing and cutting the intermediate layer, thereby reducing the damage caused by the wafer dicing method to the intermediate layer, especially the functional layer of the wafer.

[0061] Optionally, before step 310, method 300 may further include a pre-treatment step. In an embodiment of the present application, the pre-treatment step may include a thinning process of the first body material layer, such as mechanical grinding and polishing, abrasion and other processes. The thinning process of the first body material layer can also realize the exposure of the silicon through-hole, and then the pre-treatment step may further include forming a micro-bump as shown in (d) in Figure 1 by sputtering, photolithography, electroplating and other methods. In some other embodiments of the present application, the pre-treatment step may include forming a passivation layer by chemical vapor deposition (CVD). The pre-treatment step may also include flattening the wafer surface by a chemical-mechanical planarization (CMP) process. Finally, the bonded wafer obtained after the pre-treatment step is shown in step 1 in Figure 4.

[0062] Step 310: A first trench is generated by performing a first wafer scribing process and penetrating the first body material layer.

[0063] It should be understood that, as shown in step 2 of FIG4 , the first wafer scribing process can remove material in the scribing street region of the first bulk material layer to form a first trench to expose the bulk material of the intermediate layer. This first wafer scribing process has a minimal effect on removing the intermediate layer, particularly the functional layer of the wafer, and thus does not cause defects such as delamination or cracking of the intermediate layer, particularly the functional layer of the wafer.

[0064] Optionally, the first wafer scribing process may be a process that has a good removal effect on the first bulk material layer but has no significant removal effect on the intermediate layer. For example, the first wafer scribing process may be a process in which the rate of etching the silicon material is greater than or much greater than the rate of etching the dielectric material. Furthermore, the rate of etching the first bulk material layer is greater than the rate of etching the intermediate layer, so that the end position of the first wafer scribing process can be determined by the rate of etching the bottom material of the first groove. For example, when the etching depth of the first groove changes slowly or the etching rate decreases significantly, it means that the bottom surface of the first groove is located in the intermediate layer, and the first wafer scribing process can be stopped.

[0065] Exemplarily, the first wafer scribing process may be a plasma etching process. In an embodiment of the present application, the plasma etching process is preferably plasma dry etching. For example, the plasma dry etching may be a Bosch process, that is, by alternating etching of etching gas SF6 and passivation gas C4F8. Among them, the Bosch process etches the silicon material of the first body material layer by SF6, and deposits C4F8 on the silicon surface to prevent the reaction of fluorine ions with silicon, forming periodic etching and passivation, so that each step of etching the first groove is only carried out along the depth direction of the first body material layer, and finally the sidewall of the first groove is a scallop morphology. Preferably, the surface roughness of the sidewall of the first groove is less than 5μm.

[0066] Exemplarily, the first wafer scribing process may be a solution wet etching process, for example, potassium hydroxide (KOH) solution may be used to rapidly etch the silicon material of the first bulk material layer, while KOH solution has a slow etching rate for oxides or nitrides in the intermediate layer.

[0067] Optionally, in an embodiment of the present application, the bottom surface of the first groove is preferably the surface where the intermediate layer is connected to the first bulk material layer, or in other words, the first wafer scribing process stops when processing to the intermediate layer. In this way, the first wafer scribing process has almost no impact on the intermediate layer, and the etching cost of the first wafer scribing process can be saved. In other embodiments of the present application, the first wafer scribing process can also be stopped after processing to a certain depth of the intermediate layer. In this way, it can be ensured that the silicon material of the first bulk material layer in the first groove can be completely removed.

[0068] Optionally, the sidewall angle of the first trench may be 80° to 100°, and the roughness of the sidewall may be less than 5 μm, so that the obtained chip bare die meets the process requirements of packaging.

[0069] Step 320: Using a second wafer scribing process, a second trench is generated by processing from the bottom surface of the first trench and penetrating the middle layer.

[0070] It should be understood that step 310 removes all material from the first bulk material layer in the scribe lane area, thereby exposing the intermediate layer. The second wafer scribing process can then proceed directly from the exposed surface of the intermediate layer, i.e., the bottom surface of the first groove. As shown in step 3 of FIG. 4 , the second wafer scribing process processes the bottom surface of the first groove until it penetrates the intermediate layer. The bottom surface of the second groove can be the surface where the intermediate layer connects to the second bulk material layer, or it can be on the second bulk material layer as shown in FIG. 4 .

[0071] Optionally, the second wafer scribing process may be a laser processing process, wherein the exposed middle layer material is removed by laser until the bottom surface of the laser-removed area extends to the second bulk material layer, thereby ensuring that all material in the scribing street area of ​​the middle layer is removed.

[0072] In this way, the middle sublayer of the chip bare crystal obtained after wafer dicing will not crack or delaminate. In addition, since the thickness of the middle layer may be thinner than the thickness of the first main material layer, compared with the first main material layer and the middle layer with a larger total thickness processed by laser, the present application uses laser to directly process the thinner middle layer, and the power or energy used for laser grooving is smaller, thereby reducing the thermal damage caused by the heat-affected zone and laser processing to the middle layer, especially the functional layer of the wafer.

[0073] In some other embodiments of the present application, the second wafer scribing process may also be a direct process that penetrates the intermediate layer and the second body material layer. The above situation is introduced in step 330 and will not be described in detail here.

[0074] Optionally, in an embodiment of the present application, the width of the second groove may be the same as the width of the first groove, that is, both are the width shown in the scribing area in Figure 2. However, when the width of the second groove is the same as the width of the first groove, the process of processing the second groove by the second wafer scribing process will inevitably damage the sidewall of the first groove. This will then cause the sidewall of the first groove to be uneven or damaged. In addition, the defects of the intermediate layer will not only appear on the sidewall of the second groove, but also on the connection surface between the first bulk material layer and the intermediate layer, especially the functional layer of the wafer. When the width of the second groove is the same as the width of the first groove, the first bulk material layer blocks the defects on the connection surface, making it difficult for these defects to be effectively inspected.

[0075] Optionally, to address the difficulty in effectively inspecting the aforementioned defects, as described in the third step of FIG. 4 , the width of the second trench can be smaller than that of the first trench. This allows the die's intermediate sublayer to include a first portion located at the edge of the intermediate sublayer and not covered by the first bulk material sublayer, and a second portion covered by the first bulk material sublayer. Preferably, the spacing between the top edge of the sidewall of the second trench and the bottom edge of the sidewall of the first trench on the same side is 5 to 15 μm, meaning the width of the first portion of the intermediate sublayer is 5 to 15 μm. By observing the appearance of the exposed surface of the first portion of the intermediate sublayer, for example using automated optical inspection (AOI), it is determined whether the side surfaces of the intermediate sublayer and the interface connecting the intermediate sublayer to the first bulk material sublayer are defective due to wafer scribing. Furthermore, the second wafer scribing process does not contact the sidewalls of the first trench, thereby preventing damage to the sidewalls.

[0076] Optionally, the widths of the first and second grooves can be determined using a reference cable. Figure 5 shows a schematic diagram of a bonded wafer 500 including a reference cable 510. Figure 5(a) shows a cross-sectional view of the bonded wafer 500. If the die is square as shown in Figure 1(b), the sealing coil is arranged around the square integrated circuit, and the reference cable 510 is positioned outside the sealing coil. Figure 5(b) shows a top view of the bonded wafer 500. Similar to the sealing coil arrangement, the reference cable 510 is also arranged around the square integrated circuit. As shown in Figure 5(a), the reference cable 510 is positioned between the side of the first bulk material sublayer and the side of the intermediate sublayer, or in other words, between the sidewalls of the first trench and the sidewalls of the second trench. The edge of the second portion of the reference cable 510, which is close to the intermediate sublayer, corresponds to the side of the first bulk material sublayer or the sidewall of the first trench, and the edge of the second portion, which is far from the intermediate sublayer, corresponds to the side of the intermediate sublayer or the sidewall of the second trench.

[0077] Illustratively, an embodiment of the present application shows a method for wafer dicing based on a reference cable 510 .

[0078] In step 310, the first body material layer is processed by a first wafer scribing process. When the surface of the reference cable 510 near the first body material layer is completely exposed, the first wafer scribing process is stopped. For example, if the thickness of the reference cable 510 is not taken into account, the first wafer scribing process is stopped when the surface of the reference cable 510 near the first body material layer in FIG5 is just completely exposed and the bottom edge of the sidewall of the first groove just coincides with the edge of the second portion of the reference cable 510 near the middle sublayer. For another example, the first wafer scribing process is stopped when the distance between the bottom edge of the sidewall of the first groove and the edge of the second portion of the reference cable 510 near the middle sublayer is a first distance threshold. For example, the first distance threshold can be 1 to 5 μm.

[0079] In step 320, as shown in FIG5(b), the processing starting position of the second wafer scribing process, or the processing starting point of the second trench, may be the edge of the second portion of the reference cable 510 away from the middle sublayer. In other embodiments of the present application, the processing starting position of the second wafer scribing process may also be spaced a second distance threshold from the edge of the second portion of the reference cable 510 away from the middle sublayer. For example, the second distance threshold may be 1 to 5 μm.

[0080] In this way, by referring to the position difference between the cable 510 and the bottom edge of the side wall of the first groove and the top edge of the side wall of the second groove, it can be determined whether there is a problem such as processing position deviation, over-processing or under-processing.

[0081] Step 330 : Processing from the bottom surface of the second trench and penetrating the second body material layer to obtain a chip bare die.

[0082] Optionally, the process for processing the bottom surface of the second trench may still be the second wafer scribing process, that is, the second wafer scribing process is used to process and penetrate the intermediate layer and the second body material layer.

[0083] Exemplarily, the second wafer dicing process can be a laser processing process. Since the heat-affected zone of the second main material layer caused by laser processing has little effect on the intermediate layer, especially the functional layer of the wafer, the chip bare crystal can be obtained by continuing to laser process and penetrate the second main material layer.

[0084] Optionally, the process for processing the bottom surface of the second groove can be a third wafer scribing process, in which the third wafer scribing process processes the second bulk material layer to form a third groove until the third groove penetrates the second bulk material layer. In the embodiment of the present application, the third wafer scribing process is preferably a blade dicing process with high scribing efficiency and low cost, that is, the bulk material of the second bulk material layer in the scribing street area is directly cut by diamond scribing.

[0085] Optionally, the third wafer scribing process may be the same as the first wafer scribing process mentioned above, such as a plasma dry etching process or a solution wet etching process, so as to quickly remove the material of the second body material layer.

[0086] Optionally, as shown in the fourth step in Figure 4, the width of the third groove generated by the third wafer dicing process can be smaller than the width of the second groove, so that the second body material sublayer of the chip bare crystal includes a first part located at the edge of the second body material sublayer and not covered by the intermediate sublayer, and a second part covered by the intermediate sublayer. In this way, the third wafer dicing process does not cause damage to the side walls of the second groove, that is, it does not cause damage to the side of the intermediate sublayer. For example, when the third wafer dicing process is a blade cutting process, since the blade is not in direct contact with the intermediate layer, the damage caused by the final blade cutting process will not affect the intermediate layer, especially the functional layer of the wafer.

[0087] In an embodiment of the present application, the bonded wafer includes two wafers. Optionally, in other embodiments of the present application, the bonded wafer may include more than two wafers, that is, at least three wafers and the at least three wafers are bonded one by one from top to bottom, and the body material layers of each two bonded wafers include an intermediate layer, ultimately forming a three-dimensional stacked structure. The wafer scribing method shown in the present application can also be applied to the above-mentioned embodiment, that is, before scribing the kth intermediate layer, the silicon material in the scribing road area of ​​the wafer body material layer above the kth intermediate layer is first removed, thereby exposing the kth intermediate layer. After scribing the kth intermediate layer, the silicon material in the scribing road area of ​​the wafer body material layer below the kth intermediate layer is removed, thereby exposing the k+1th intermediate layer. Until the processing passes through the wafer body material layer at the bottom of the bonded wafer, a chip bare crystal with multiple body material sublayers and multiple intermediate sublayers is obtained.

[0088] The present application pre-processes the material in the dicing area of ​​the first main material layer to expose the intermediate layer, and then directly processes the intermediate layer, thereby avoiding the defects of delamination and cracking of the intermediate layer, especially the functional layer of the wafer, caused by direct blade dicing, and large heat-affected zone and thermal damage of the intermediate layer, especially the functional layer of the wafer, caused by laser processing dicing.

[0089] Furthermore, in an embodiment of the present application, the width of the second trench formed by processing the intermediate layer is smaller than the width of the first trench formed by processing the first bulk material layer previously, so that the intermediate sub-layer includes a first portion located at the edge of the intermediate sub-layer and not covered by the first bulk material sub-layer. Thus, the second wafer scribing process for processing the intermediate layer does not affect the sidewall surface of the first trench, and defects in the intermediate layer or the intermediate sub-layer at the interface between the first bulk material layer and the intermediate layer can be directly detected through visual inspection.

[0090] Through the wafer dicing method described in this application, one or more chip bare die are ultimately obtained. Figure 6 shows a schematic structural diagram of a chip bare die 600. The chip bare die 600 includes a first bulk material sublayer 610, an intermediate sublayer 620, a second bulk material sublayer 630, and microbumps.

[0091] As shown in FIG6 , when the width of the second trench is smaller than the width of the first trench, the intermediate sub-layer 620 includes a first portion located at the edge of the intermediate sub-layer 620 and not covered by the first bulk material sub-layer 610, and a second portion covered by the first bulk material sub-layer 610. In this way, defects at the interface between the intermediate sub-layer 620 and the first bulk material sub-layer 610 can be effectively inspected.

[0092] Optionally, as shown in FIG6 , when the width of the third trench is smaller than that of the second trench, the second body material sub-layer 630 includes a first portion located at the edge of the second body material sub-layer 630 and not covered by the intermediate sub-layer 620, and a second portion covered by the intermediate sub-layer 620. In this way, the third wafer scribing process does not damage the sidewalls of the second trench, that is, it does not damage the intermediate sub-layer 620 and the functional layers therein, such as metal wiring and dielectric materials.

[0093] Optionally, as shown in FIG6 , a reference cable (not shown in FIG6 ) is provided on the first portion of the intermediate sublayer 620 near the surface of the first bulk material sublayer 610. The reference cable is located between the side surface of the first bulk material sublayer 610 and the side surface of the intermediate sublayer 620 and is used to determine the processing position of the first wafer scribing process and / or the second wafer scribing process. In this way, the first wafer scribing process and the second wafer scribing process can be aligned using the reference cable 510, and the alignment is relatively accurate. The reference cable 510 can also be used to check whether the processing position of the wafer scribing process is offset.

[0094] As shown in (d) of Figure 1 , the chip die shown in Figure 6 can be used as a chip component in an integrated circuit chip, and the integrated circuit chip can be any of a microprocessor chip, a memory chip, a sensor chip, a driver chip, and a communication chip. The chip die or integrated circuit chip shown in this application can also be set in an electronic device, such as a mobile phone, a personal computer, or an information processing center. An integrated circuit chip for implementing communication processing, storage, and expansion is set on a smart terminal device. The integrated circuit chip includes one or more chip die with the structure shown in Figure 6.

[0095] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for dicing a bonded wafer, characterized in that: The bonded wafer comprises a first bulk material layer of a first wafer, a second bulk material layer of a second wafer, and an intermediate layer between the first bulk material layer and the second bulk material layer, and the method comprises: A first trench is generated by processing through a first wafer scribing process and penetrating the first bulk material layer; Processing from the bottom surface of the first groove and penetrating the middle layer through a second wafer scribing process to generate a second groove; The second body material layer is processed from the bottom surface of the second groove to obtain a chip bare crystal.

2. The method according to claim 1, characterized in that The width of the second groove is smaller than the width of the first groove, so that the middle sublayer of the chip die includes a first portion located at an edge of the middle sublayer and not covered by the first body material sublayer of the chip die.

3. The method according to claim 2, characterized in that A reference cable is disposed on a first portion of the intermediate sublayer close to a surface of the first main body material sublayer, and the reference cable is used to determine a processing position of the first wafer dicing process and / or the second wafer dicing process.

4. The method according to any one of claims 1 to 3, characterized in that The first wafer dicing process includes a plasma etching process.

5. The method according to any one of claims 1 to 4, characterized in that The second wafer scribing process includes a laser processing process.

6. The method according to any one of claims 1 to 5, characterized in that The processing from the bottom surface of the second groove and penetrating the second body material layer comprises: A third trench is generated by processing from the bottom surface of the second trench through a third wafer scribing process until the third trench penetrates the second body material layer.

7. The method according to claim 6, characterized in that The third wafer dicing process includes a blade cutting process.

8. The method according to claim 6 or 7, characterized in that: The width of the third groove is smaller than the width of the second groove, so that the second body material sublayer of the chip die includes a first portion located at an edge of the second body material sublayer and not covered by the middle sublayer of the chip die.

9. The method according to any one of claims 1 to 8, characterized in that The bottom surface of the first groove is a first surface where the intermediate layer is connected to the first body material layer.

10. The method according to any one of claims 1 to 9, characterized in that: The bonded wafer is formed by hybrid bonding of the first wafer and the second wafer.

11. A chip bare die, characterized in that: include: a first sublayer of bulk material, an intermediate sublayer, and a second sublayer of bulk material; The intermediate sublayer is located between the first body material sublayer and the second body material sublayer and connects the first body material sublayer and the second body material sublayer, the intermediate sublayer includes a first part and a second part, the first part of the intermediate sublayer is located at the edge of the intermediate sublayer and is not covered by the first body material sublayer, and the second part of the intermediate sublayer is covered by the first body material sublayer.

12. The chip bare die according to claim 11, characterized in that: The side surface of the first body material sub-layer is formed by a plasma etching process.

13. The chip bare die according to claim 11 or 12, characterized in that: The side surface of the first part of the intermediate sub-layer is formed by a laser processing process.

14. The chip bare die according to any one of claims 11 to 13, characterized in that: The second bulk material sublayer includes a first portion and a second portion. The first portion of the second bulk material sublayer is located at the edge of the second bulk material sublayer and is not covered by the intermediate sublayer. The second portion of the second bulk material sublayer is covered by the intermediate sublayer.

15. The chip bare die according to claim 14, characterized in that: The side surface of the first portion of the second body material sub-layer is formed by a blade cutting process.

16. The chip bare die according to any one of claims 11 to 15, characterized in that: A reference cable is disposed on a surface of the first portion of the intermediate sublayer close to the first bulk material sublayer, and the reference cable is located between a side surface of the first bulk material sublayer and a side surface of the first portion of the intermediate sublayer.

17. An integrated circuit chip, characterized in that: Comprising the chip bare die as claimed in any one of claims 11 to 16.

18. An electronic device, characterized in that: It comprises the chip bare die as claimed in any one of claims 11 to 16 or the integrated circuit chip as claimed in claim 17.

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