Low flicker noise near-threshold CMOS inverter

Abstract

The design of a near-threshold inverter suppressing the flicker noise is disclosed. The inverter is operated near the threshold, and thus its operation point, determined by the connection to the near-threshold region, suppresses the flicker noise floor effectively for short-channel CMOS devices. Two variants of the connection are possible: one with the static pull-up PMOS network, and another with a static pull-down NMOS network. The part, which is chosen to be static reduces its contribution to the flicker noise more significantly.

Description

Title: Low Flicker Noise Near«Threshold CMOS InverterTECHNICAL FIELD

[0001] The disclosed invention of a low flicker noise near-threshold CMOS inverter relates to the flicker noise suppression in CMOS, and represents the CMOS structure decreasing the flicker noise in general, and to low-noise CMOS ring oscillators utilizing the disclosed low flicker noise near-threshold CMOS inverter in particular. Thus, the present invention also relates to the implementation of the CMOS inverter into control gate and ring oscillator.BACKGROUND ART

[0002] Complementary metal-oxide-semiconductor (CMOS) ring oscillators are widely used in True Random Number Generators (TRNG), Physical Unclonable Functions (PUF), or Phase Locked Loop (PLL) circuits. The ring oscillators are typically based on the CMOS inverter structure.

[0003] As a device’s size scales down, the inverter dimensions become smaller, and noise in ring oscillators becomes more important. The flicker noise is caused by impurities in the semiconductor device channel, and variations in charge trapping. The flicker noise could also be increased by semiconductor degradation caused e.g. by aging or ionizing radiation.

[0004] The flicker noise is significant, and it dominates over white (temperature) noise in lower frequencies for upstream CMOS technology nodes. Flicker noise commonly dominates over white noise up to tens of Mhz and its significance increases for recent technology nodes, as reported e.g. in the patent US10295583B2. The flicker noise in the ring oscillator translates into phase noise or jitter.

[0005] In cryptographic primitives, high entropy, and / or long-term stability is a common requirement. It is advantageous to strengthen high entropy lower amplitude noise source - represented by white noise - beside lower entropy burst noise source - represented by a flicker noise.

[0006] The standard method of flicker noise elimination is high current insertion e.g. by extending the transistor channel as reported in the document ABIDI, Assad A. Phase noise and jitter in CMOS ring oscillators. IEEE journal of solid-state circuits, 2006, 41.8: 1803-1816.

[0007] Another option used for flicker noise suppression is the connection employing the resistor degeneration effect disclosed in the patent EP2609681B1.

[0008] The flicker noise drain to source voltage and the gate bias dependence is negligible for long-channel NMOS transistors, however, the significant gate bias dependence of the flicker noise has been reported for PMOS devices, and for short- channel devices in general, as reported in the document CHANG, Jimmin; ABIDI, A. A.; VISWANATHAN, C. R. Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures. IEEE Transactions on Electron Devices, 1994, 41.11: 1965-1971.

[0009] The existing solutions used to diminish the flicker noise provide the flicker suppression for a cost of increased area and / or increased power consumption. This might be problematic, especially in low-power design.SUMMARY OF THE INVENTION

[0010] The above disadvantages are suppressed by the circuit structure that decreases the flicker noise by choosing the operating point of the CMOS inverter circuit in the near-threshold region for the switching device and near the saturation region for the static pull-up or pull-down device respectively. The operating point is chosen in such a way, that the flicker noise is decreased significantly. The choice of the operating point in the region with a low flicker level is problematic due to CMOS's complementary nature, where only PMOS or NMOS flicker noise contribution is suppressed ideally, however, the disclosed connection represents a highly efficient way to limit flicker noise contribution from both PMOS and NMOS.

[0011] The inverter circuit comprises semi-standard connections of PMOS and NMOS transistors. One of the complementary parts serves as a static pull-up or puii-down network respectively, while the other part as a dynamic switching part.

[0012] The NMOS transistor is connected by its source terminal to the inverter ground node VSS and by the drain terminal to the inverter output. The gate terminal of the NMOS transistor is the inverter input node. The PMOS transistor drain terminal is connected to the inverter output node, but its source terminal is connected to the SUB node. The PMOS gate terminal is connected to the REF node.

[0013] The SUB node voltage V(SUB) is chosen in such a way, that it is lower than circuit nominal supply voltage V(VDD), but higher than the threshold voltage of the PMOS transistor V(THP): V(VDD) » V(SUB) > V(THP).

[0014] The REF node voltage is chosen in such a way, that it is lower than the V(SUB) voltage: V(SUB) > V(REF). Typically, V(REF) ≃ 0.5 * V(SUB).

[0015] Complementary structure is also possible: The NMOS inverter is connected by its source terminal to the inverter ground node VSS and by the drain terminal to the inverter output. The gate terminal of the NMOS is connected to the REF node. The PMOS inverter drain terminal is connected to the inverter output node, its source terminal is connected to the SUB node. The PMOS gate terminal is the inverter input node.

[0016] In the complementary case, the SUB node voltage V(SUB) is chosen in such a way, that it is lower than circuit nominal supply voltage V(VDD), but higher than the threshold voltage of the PMOS transistor V(THP): V(VDD) » V(SUB) > V(THP).

[0017] The REF node voltage is chosen in such a way, that it is lower than the threshold voltage of the NMOS transistor V(THN: V(REF) < V(THN). Typically, V(REF) ≃ 0.5 * V(THN).

[0018] The advantages of the disclosed solution embodiment are, that it has a simple structure without additional components such as resistors decreasing the occupiedcircuit area, or that a high mismatch could be achieved when sizes of PMOS and NMOS transistors are chosen close to the lower technology limit.

[0019] The property of the disclosed solution embodiment is that the near-threshold operation decreases the oscillation frequency - high oscillation frequencies could not be achieved, however short rings could be used for higher frequencies leading to small area footprint, while the disadvantage of the disclosed solution embodiment is, the lower noise immunity in the near-subthreshold region.

[0020] In one embodiment of the invention, the Low Flicker Noise Near-Threshold CMOS Inverter comprises a semi-standard connections of PMOS transistor and NMOS transistor, where the NMOS transistor is connected by its source terminal S to the ground VSS node, and by its drain terminal D to the inverter output Y, while the PMOS transistor drain terminal D is connected to the inverter output Y.

[0021] It is essential that the gate terminal G of the NMOS transistor is connected to the inverter input IN, and the source terminal S of the PMOS transistor is connected to the SUB node, and the PMOS transistor gate terminal G is connected to the REF node. Alternatively, the gate terminal G of the PMOS transistor is connected to the inverter input IN node, and the source terminal S of the PMOS transistor is connected to the SUB node, and the NMOS transistor gate terminal G is connected to the REF node.

[0022] It is also possible that the inverter is configured is such a way that multiple transistors of the same type are connected in parallel or in series to the PMOS transistor or NMOS transistor, while their gate terminals G are connected to REF node and / or IN node respectively.

[0023] Furthermore, the invention also relates to a control gate comprising the CMOS inverter structure according to this invention.

[0024] Advantageously, the control gate is configured in such a way that typically two, but at least one of the gate terminals G of PMOS and NMOS transistors placed in parallel or in series to the transistors in the inverter structure are bonded togethercreating a second input of the control gate, where the control gate implements a basic logic function, typically NAND.

[0025] Furthermore, the invention relates to a ring oscillator comprising an odd number of three or more inverters according to this invention, which are connected in the ring in such a way that the output Y of one of inverters in the ring is the output of the ring oscillator OUT.

[0026] Moreover, the invention also relates to a ring oscillator comprising an even number of two or more inverters according to this invention and one control gate provided with the inverters and connected in the ring, wherein the output of one of inverters or the output of the control gate in the ring is the output of the ring oscillator OUT, and one of the control gate inputs is connected to the output of one of inverter outputs in the ring, and the second input of the control gate is the enable signa! ENA of the ring oscillator.BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The standard embodiment of the inverter-based ring oscillator is shown in Fig.1, while Fig. 2 illustrates the embodiment of the standard inverter-based ring oscillator with the incorporated control signal. Fig. 3 illustrates the structure of the CMOS inverter, while Fig. 4 discloses the principle of the disclosed solution. Fig. 5 gives an example of how the disclosed solution could be incorporated into a standard digital design. Fig. 6 describes how the operation point of CMOS devices in the disclosed inverter is limited in a particular case.

[0028] Fig. 5 illustrates, how the disclosed solution could be incorporated into a standard CMOS digital design represented by a counter 302 in the VDD domain characterized by the nominal supply voltage provided through the VDD node 102. The counter 302 is connected by its input to the output 303 of the comparator 301 in the VDD domain. The comparator 301 inputs are reference input REF 122 and inverterbased ring oscillator 120 output OUT 102 located in the SUB supply voltage domaincharacterized by a near-threshold supply voltage provided through the SUB node 121. Both supply domains have a common ground VSS node 103.

[0029] Fig. 6 describes how the limited operation point of CMOS devices in the disclosed inverter limits the flicker noise RMS in a particular realization of the disclosed inverter in the sky 130 technology.DETAILED DESCRIPTION OF THE INVENTION

[0030] The inverter-based ring oscillator 120 comprises an odd count of inverters 101 chained in the ring in a standard way, following the structure of the ring oscillator 100 or 200 in Fig. 1 , or Fig. 2 respectively, where the output of the first is connected to the input of another, and one of the inverter outputs is the output of the ring oscillator OUT node 102.

[0031] The inverter 101 is the disclosed solution shown in Fig. 4 with the operating point chosen near the threshold region compared to the standard CMOS inverter in Fig. 3. The disclosed inverter operation region reduction is shown in Fig. 6. The disclosed Inverter 101 is composed of a PMOS transistor 111 connected by its source terminal S to the SUB node 121, by its gate terminal G to the reference input REF 122, and by its drain terminal D to the inverter output Y 113, and by an NMOS transistor 112 connected by its drain terminal D to the inverter output Y 113, by its gate terminal G to the inverter input IN 114, and by its source terminal S to the ground VSS node 103-INDUSTRIAL UTILIZATION

[0032] The disclosed solution has good industrial applicability, for example, in the creation of cryptographic primitives like ring-oscillator-based random number generators (TRNGs) or physically unclonable functions (PUFs), especially in low- power application-specific integrated circuits (ASICs).

Claims

CLAIMS1. A Low Flicker Noise Near-Threshold CMOS Inverter (101) comprising a semi- standard connections of PMOS transistor (111) and NMOS transistor (112), where the NMOS transistor (112) is connected by its source terminal S to the ground VSS node (103), and by its drain terminal D to the inverter output Y (113), while the PMOS transistor (111) drain terminal D is connected to the inverter output Y (113), characterized in that the gate terminal G of the NMOS transistor (112) is connected to the inverter input IN (114), and the source terminal S of the PMOS transistor (111) is connected to the SUB node (121), and the PMOS transistor (111) gate terminal G is connected to the REF node (122), or the gate terminal G of the PMOS transistor (111) is connected to the inverter input IN node (114), and the source terminal S of the PMOS transistor (111) is connected to the SUB node (121), and the NMOS transistor (112) gate terminal G is connected to the REF node (122).

2. The inverter according to claim 1 , wherein multiple transistors of the same type are connected in parallel or in series to the PMOS transistor (111) or NMOS transistor (112), while their gate terminals G are connected to REF node (122) and / or IN node (114) respectively.

3. A control gate (201) comprising CMOS inverter according to claim 1 or 2, wherein typically two, but at least one of the gate terminals G of PMOS and NMOS transistors placed in parallel or in series to the transistors in the inverter structure are bonded together creating a second input of the control gate (201).

4. A ring oscillator (100) comprising an odd number of three or more inverters (101) according to claim 1 or 2 connected in the ring, wherein the output Y (113) of one of inverters in the ring is the output of the ring oscillator OUT (102).

5. A ring oscillator (200) comprising an even number of two or more inverters (101) and one control gate (201) according to any of claims 1 to 4 connected in the ring, wherein the output of one of inverters (101) or the output of the control gate (201) in the ring is the output of the ring oscillator OUT (102), and one of the control gate (201) inputs is connected to the output of one of inverter (101) outputs in the ring, and the second input of the control gate (201) is the enable signal ENA (202) of the ring oscillator.LIST OF REFERENCE MARKS100 - standard inverter-based ring oscillator101 - CMOS inverter circuit102 - ring oscillator OUT103 - ground VSS node111 - PMOS transistor112 - NMOS transistor113 - inverter output Y114 - inverter input IN120 - inverter-based ring oscillator employing disclosed inverters121 - SUB node122 - REF node200 - standard ring oscillator with ENA control signal201 - ring oscillator control gate202 - enable signal ENA301 - comparator in the VDD domain302 - counter in the VDD domain303 - output of the comparator

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