Clock generator system and method

Abstract

A clock generator system comprising a controller unit that includes a control interface. One or more logic modules located at various location of an integrated circuit (IC). The one or more logic modules operably connected to the controller unit. A clock generator circuit that includes a two input OR gate, including a phase lock loop (PLL) clock input and a phase lock loop (PLL) enable input operatively attached to the controller unit. A latch including a set (S) input and a reset (R) input. A first delay path including an input from the Q output of the latch, and the output of the first delay path connects to the reset (R) input. A pulse generator (PG) including an input from the Q output of the latch and an output connected to the input of a second delay path.

Description

[0001] CLOCK GENERATOR SYSTEM AND METHOD

[0002] BACKGROUND

[0003] The present disclosure, in some embodiments thereof, relates to a clock generator system and, more specifically to a choice between the generations of two or more of clock signals for data communication, but not exclusively, to data communication.

[0004] In digital circuits, the clock frequency may be a crucial factor in determining the performance of a digital system. The clock frequency is the number of clock cycles that occur in one second and it may be used to synchronize all the operations in the digital circuit. However, the clock frequency may not always constant. One of the main factors that can affect the stability of the clock frequency is voltage variations. The voltage supply to the digital circuit determines the speed at which the digital circuit operates. If the voltage supply drops, the digital circuit will slow down and if the voltage increases, the digital circuit will speed up. This relationship between voltage and clock frequency is known as the voltage-frequency relationship. Voltage variations can be caused by various factors such as changes in the temperature of the digital circuit, power supply fluctuations, or the load on the digital circuit. These variations in voltage can cause changes in the clock frequency, leading to instability in the digital circuit. In order to maintain stability, digital circuits may use voltage regulators that control the voltage supplied to the digital circuit. The voltage regulators monitor the voltage levels and adjust them as needed to maintain a stable voltage supply. The stable voltage may help to ensure that the clock frequency remains stable and the digital circuit operates at its optimal performance.

[0005] Performance criteria for how well a clock generator for a digital circuit may perform may consider parameters such as jitter, phase noise and power consumption. Jitter is a measure of the short-term variations in the clock signal, and low-jitter clock generators may be critical for applications where signal integrity is essential. In high-speed digital systems, signal edges may become increasingly distorted as jitter increases, leading to errors in data transmission. A low- jitter clock generator may ensure that the transitions of a clock signal are clean and precisely timed, reducing the probability of errors. Phase noise is a measure of the noise in the frequency domain of the clock signal, and low-phase-noise clock generators may be essential for applications such as radar, wireless communication, and high-speed analog-to-digital converters (ADCs). Phase noise can cause unwanted frequency components to appear in the spectrum of a digital system, leading to interference and distortion.

[0006] A low-phase-noise clock generator may ensure that frequency spectrum of the clock signal is free from unwanted noise, improving the performance of the digital system. Power consumption may also be a critical consideration in any electronic design, and low-power clock generators may be essential for applications where power efficiency is a primary concern. A low-power clock generator may reduce energy consumption, extend battery life, and generates less heat, which can reduce the overall power budget of the digital system. Low-power clock generation may be particularly important for portable devices, such as smartphones, tablets, and wearable devices, where battery life may be a critical factor. Consideration of parameters such as jitter, phase noise and power consumption with respect to clock generation, therefore, may enable high-speed data transfer, precise timing, and low power consumption required by digital system applications.

[0007] A clock tree is a network of clock distribution paths that delivers clock signals to the various components of a digital circuit. In digital circuits, timing may be crucial for synchronizing the various operations of the components. A clock tree may ensure that all components of the digital circuit receive the same clock signal with minimal delay and skew. The clock signal is typically generated by a primary clock source, and then propagated through a series of buffers, inverters, and other components that shape and distribute the signal throughout the circuit. The clock tree may be designed to minimize the skew between different components and to ensure that the clock signal arrives at each component with a minimum of delay. The clock tree typically consists of several levels of buffers, each of which amplifies and re-shapes the clock signal to reduce the effects of signal degradation and noise. The buffers may also help to minimize the delay and skew of the clock signal, ensuring that all components receive the same signal at approximately the same time.

[0008] SUMMARY

[0009] It is an object of the present invention to provide an apparatus, a system, a computer program product, and a method for a clock generator system and, more specifically to a choice between the generations of two or more different types of clock signals, but not exclusively, to any particular circuit or circuits generating the clock signals. A clock generator system comprising a controller unit that includes a control interface. One or more logic modules located at various location of an integrated circuit (IC). The one or more logic modules operably connected to the controller unit. A clock generator circuit that includes a two input OR gate, including a phase lock loop (PLL) clock input and a phase lock loop (PLL) enable input operatively attached to the controller unit. A latch including a set (S) input and a reset (R) input. A first delay path including an input from the Q output of the latch, and the output of the first delay path connects to the reset (R) input. A pulse generator (PG) including an input from the Q output of the latch and an output connected to the input of a second delay path. An AND gate with input from the output of the second delay path and another input from the phase lock loop clock input, and the output of the AND connects to the set (S) input.

[0010] The AND gate provides an aggregating of the output of the two input OR gate with the output of the second delay path. The Q output is configurable responsive to the aggregating to provide a generated clock pulse on the Q output responsive to allow at least one of the first, the second delay paths and the phase lock loop (PLL) clock input. Further, to apportion the generated clock pulse on the Q output to reduce the margins associated with the use of phase lock loop (PLL) clock input enabled by PLL enable input. Thereby to achieve a lower interface delay penalty of the control interface between the one or more logic modules at various locations of the integrated circuit (IC). The generated clock pulse may protect the at least one or more logic modules at various locations of the integrated circuit (IC).

[0011] A method for generating a clock pulse in a clock generator system that includes multiple clock generator circuits operably attached to one or more logic modules situated at various locations of an integrated circuit (IC). The method enables a phase lock loop (PLL) clock input to be received on the clock generator circuits. The PLL clock input is aggregated by ANDing an output of a second delay path with the PLL clock input. An input to a first delay path and an input to a pulse generator (PG) is cascaded with an input to the second delay path from the Q output of a latch. Latching on the set (S) input and the reset (R) input of the latch with the ANDing and the output of the first delay path respectively. A generated clock pulse is provided on the Q output of the latch responsive to the first, the second delay paths and / or the phase lock loop (PLL) clock input. Responsive to the generated clock pulse provided, the margins associated with the enabling use of a PLL enable input is reduced, thereby achieving a lower interface delay penalty of a control and communication interface connected between the one or more logic modules situated at various locations of the integrated circuit (IC). The generated clock pulse provided may be from voltages sensed at multiple regions the IC, and the evaluation of multiple delay paths to initiate the next cycle of the clock generator system. The initiation of the next cycle of the clock generator system may be only when the functions of all regions of the IC are correctly performed with a next clock edge of the clock pulse on the Q output. Responsive to the voltages sensed and the evaluation of multiple delay paths, voltage drops on farther away sites in the IC may be compensated by modelling clock network effects, arbitrary logic behavior of the logic modules, by utilizing the first delay path and / or the second delay path.

[0012] According to a first aspect, a clock generator circuit that includes multiple, configurable, distributed delay models located at various parts in an integrated circuit (IC). The distributed delay models may be provided from other same clock generator circuits located at various parts of the IC. The other delay models may be used under the control of a control unit to sense the process, voltage, and temperature (PVT) throughout the integrated circuit (IC).

[0013] According to a second aspect the clock generator circuit offer immediate (next cycle) response to supply perturbations and thus to have a potential to reduce required margins and improve power and performance of the IC. The delay paths of the clock generators may therefore, function as process monitors and as aging monitors.

[0014] According to a third aspect, the distribution of delay models at various locations of the IC enables power supply detection throughout the IC to capture the voltage frequency (V-F) curve and to enable the calibration of delay paths of several voltage threshold (Vt) types. The distribution of the delay models and operation of the clock generators, allows modelling of wire delays in the integrated circuit, allows compensation of the cycle period for voltage drops on farther away sites in a macro of the IC, and allows modelling of clock network effects and arbitrary logic behavior.

[0015] According to a fourth aspect, the clock generator circuit further includes, and is further configurable to provide a generated clock pulse responsive to the distributed delay models and / or a phase lock loop (PLL) clock input to the clock generator circuit. When responsive to the phase lock loop (PLL) clock input under control of the control unit, a PLL enable input is applied to the clock generator circuit, achieves a lower interface delay penalty of a communication interface connected between one or more logic modules situated at various locations of the integrated circuit (IC).

[0016] According to a fifth aspect, the PLL clock input helps to synchronize the clock signals across the one or more logic modules of the IC to ensure that all the one or more logic modules operate at the same frequency, thereby to minimize the risk of errors and data corruption.

[0017] According to a sixth aspect, the stable PLL clock input signal can be used as a reference for data transfer to help to ensure that data is transmitted accurately and efficiently between the logic modules. Thereby to improve the performance of the IC by providing a stable clock signal so that all the components of the IC operate at their optimal frequency.

[0018] According to a seventh aspect, both sides of the interface between the two rising edge to rising edge (R2R) of two delay circuits / paths, lock to the same PLL clock provided on a PLL clock input signal to the clock generator circuit. It is possible to use just a single (falling edge) flop for a one cycle delay interface instead of two. Therefore, the delay paths / circuits protect the one or more logic modules of the IC logic modules to enable a decrease in PLL supply margin, while achieving a lower interface delay penalty than may be possible with a ring oscillator (RO) only design to improve both power and interface delay performance.

[0019] The combined features described herein of a generated clock pulse responsive to the distributed delay models, and / or a phase lock loop (PLL) clock input to the clock generator circuit. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals respectively.

[0020] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0021] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the disclosure, exemplary methods and / or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

[0022] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0023] Some embodiments of the disclosure are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the disclosure. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the disclosure may be practiced.

[0024] In the drawings:

[0025] FIG. 1 shows a clock generator system, in accordance with some embodiments;

[0026] FIG. 2 A shows further details of primary / secondary clock generator circuits, in accordance with some embodiments;

[0027] FIG. 2B shows further details of a delay circuit, in accordance with some embodiments;

[0028] FIG. 3 A shows further details of a unit model 22 that may be used to implement a primary clock generator circuit, in accordance with some embodiments;

[0029] FIG. 3B shows that shows a graph of frequency versus voltage curves for three tunable or configurable delay path units, in accordance with some embodiments;

[0030] FIG. 4 shows a graph of voltage amplitude versus time for the operation of both primary and secondary clock generator circuits, in accordance with some embodiments; and

[0031] FIG. 5 shows a flowchart of a method, in accordance with some embodiments.

[0032] DETAILED DESCRIPTION

[0033] The present disclosure, in some embodiments thereof, relates to a clock generator system and, more specifically to a choice between the generations of two or more different types of clock signals, but not exclusively, to any particular circuit or circuits generating the clock signals.

[0034] Before explaining at least one embodiment of the disclosure in detail, it is to be understood that the disclosure is not necessarily limited in its application to the details of construction and the arrangement of the components and / or methods set forth in the following description and / or illustrated in the drawings and / or the Examples. The disclosure is capable of other embodiments or of being practiced or carried out in various ways. The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0035] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

[0036] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network.

[0037] The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0038] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions. The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0039] By way of introduction aspects of the disclosure below, describe a clock generator circuit that includes multiple, configurable, distributed delay models located at various parts in an integrated circuit (IC). The distributed delay models may be provided from other same clock generator circuits located at various parts of the IC. The other delay models may be used under the control of the control unit to sense the process, voltage, and temperature (PVT) throughout the integrated circuit (IC). Further, to offer immediate (next cycle) response to supply perturbations and thus to have a potential to reduce required margins and improve power and performance of the IC. The delay paths of the clock generators may therefore, function as process monitors and as aging monitors. The distribution of delay models at various locations of the IC enables power supply detection throughout the IC to capture the voltage frequency (V-F) curve and to enable the calibration of delay paths of several voltage threshold (Vt) types. The distribution of the delay models and operation of the clock generators of the above features allows modelling of wire delays in the integrated circuit, to allow compensation of the cycle period for voltage drops on farther away sites in a macro of the IC and allows modelling of clock network effects and arbitrary logic behavior.

[0040] The clock generator circuit further includes and is further configurable to provide a generated clock pulse responsive to the distributed delay models and / or a phase lock loop (PLL) clock input to the clock generator circuit. When responsive to the phase lock loop (PLL) clock input under control of the control unit, a PLL enable input is applied to the clock generator circuit to achieve a lower interface delay penalty of a communication interface connected between one or more logic modules situated at various locations of the integrated circuit (IC). The PLL clock input helps to synchronize the clock signals across the one or more logic modules of the IC to ensure that all the one or more logic modules operate at the same frequency, thereby to minimize the risk of errors and data corruption. The stable PLL clock input signal can be used as a reference for data transfer to help to ensure that data is transmitted accurately and efficiently between the logic modules. The stable PLL clock input signal further helps to improve the performance of the IC by providing a stable clock signal so that all the components of the IC operate at their optimal frequency. The combined features described herein of a generated clock pulse responsive to the distributed delay models, and / or a phase lock loop (PLL) clock input to the clock generator circuit. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals respectively.

[0041] Reference is now made to FIG. 1, which shows a clock generator system 10, in accordance with some embodiments. Clock generator system 10 may include two integrated circuits (IC), IC 5, and IC 6 or may be included on one integrated circuit. Integrated circuits 5 and 6 may be implemented as a system on a chip (SoC) that may combine many elements of a computer system into a single chip. The SoC may further include a central processing unit (CPU), system memory, peripheral controllers for USB, storage, and more advanced peripherals such as graphics processing units (GPUs), specialized neural network circuitry, radio modems (for Bluetooth™ or Wi-Fi™), and more.

[0042] Integrated circuit 6 includes a control unit 1 that may be implemented as a microcontroller, microprocessor or may be provided from a CPU. Control unit 1 connects bi-directionally to communication interface 3. Communication interface 3 operably connects to the input of IC 5 (shown by dashed line). Primary clock generator circuit 20 receives input from a phase lock loop (PLL) clock input (pll clk) and a phase lock loop (PLL) enable input (pll en). Primary clock generator circuit 20 is operatively attached to control unit 1 (shown by dashed line). The Q output of primary clock generator circuit 20 connects to the input of clock tree 2. Clock tree 2 is also operatively attached to control unit 1 and clock generator circuit 20 (shown by dashed lines). A clock tree is a network of clock distribution paths that delivers clock signals to the various components of a digital circuit. Clock tree 2 delivers clock signals to integrated circuit 5. In digital circuits, timing may be crucial for synchronizing the various operations of the components. The clock signal CP derived from the Q output of primary clock generator circuit 20 is propagated through a series of buffers, inverters, and other components (not shown) that shape and distribute the clock signal throughout clock generator system 10 described in greater detail in the descriptions that follow.

[0043] Integrated circuit 5 includes multiple logic modules 4 positioned across a layout of IC 5 in terms relative to the points of a compass North (N), South (S), East (E) and West (W). The layout being the representation of IC 5 in terms of planar geometric shapes (not shown) that correspond to the patterns of metal, oxide, or semiconductor layers that make up logic modules 4 and their electrical interconnections between each other as well as to clock tree 2, primary clock generator circuit 20, communication interface 3, and control unit 1. Logic modules 4 need not necessarily be the same as each other. Example of logic modules 4 may include memory chips, interface ICs (level shifters, serializer / de-serializer, etc.), power management ICs, programmable devices, linear integrated circuits, radio frequency circuits, data acquisition ICs including A / D converters, D / A converters, digital potentiometers, clock / timing ICs, and switched capacitor (SC) circuits. Common to each of the logic modules 4 is a secondary clock generator circuit 20 that receives input from a phase lock loop (PLL) clock input (pll clk) and a phase lock loop (PLL) enable input (pll en) supplied from the primary clock generator circuit 20 via clock tree 2.

[0044] Reference is now made to FIG. 2A, which shows further details of primary / secondary clock generator circuits 20, in accordance with some embodiments. Primary or secondary clock generator circuit 20 receives input from a phase lock loop (PLL) clock input (pll clk) and a phase lock loop (PLL) enable input (pll en) on one non-inverting input and an inverting input respectively of an OR gate G1. The output of OR gate G1 connects to a set si input of an AND gate G2. The output of AND gate G2 connects to the set (S) input of latch L4. The Q output of latch L4 connects to the input of a buffer G3, the input to a first (1) delay path formed by rising edge to a rising edge (R2R (1)) delay circuit 12, and the input to a second (2) delay path formed by an input to a pulse generator (PG) 30 cascaded with a rising edge to a rising edge (R2R (2)) delay circuit 14. The output of rising edge (R2R (2)) delay circuit 14 connects to a set sO input of an AND gate G2. The output of rising edge (R2R (1)) delay circuit 12 connects to the reset (R) input of latch L4. The output of buffer G3 provides the clock (elk) pulse generated by primary / secondary clock generator circuits 20. In general, the clock signal derived from the Q output of primary clock generator circuit 20 is responsive to the distributed delay models, and / or an enabled phase lock loop (PLL) clock input to the master clock generator circuit 20. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals respectively.

[0045] Reference is now made to FIG. 2B, which shows further details of delay circuit 12, in accordance with some embodiments. Delay circuit 12may be implemented as ring oscillators (RO) as shown, may also be used to implement delay circuit 14. Delay circuits 12 and 14 of secondary clock generators 20 may serve to function as distributed delay models located at various parts of integrated circuit (IC) 5. The delay models delay circuits 12 and 14 of secondary clock generators 20 may be used under the control of controller 1 to sense the process, voltage, and temperature (PVT) at various locations throughout IC 5.

[0046] By way of non-limiting example and for purposes of simplicity, delay circuit 12 includes a combination logic portion of four two input NAND gates and a flip-flop portion which includes four flip-flops. Any odd or even number of combinational logic gates and flip-flops may be used for the range of delay required. In the combination logic portion, input I connects to one input of NAND gate xdl3 and the other pin connects to clock CK. Output n3 of NAND gate xdl3 connects to one input of NAND gate xdl2. The other input of NAND gate xdl2 connects to configure input cfgl. The Output n2 of NAND gate xdl2 connects to one input of NAND gate xdll. The other input of NAND gate xdll connects to clock CK. The output nl of NAND gate xdll connects to one input of NAND gate xdlO. The other input of NAND gate xdO connects to configure input cfgO. The output O of NAND gate xdlO provides the output of delay circuit 12. Table T1 shows the possible inputs on each of the two inputs cfgO and cfgl of each of the four flip-flops. The fourth flip-flop has inputs a and b on two respective inputs, similarly the third flip-flop inputs c and d, similarly the second flip-flop inputs e and f and similarly the first flip-flop inputs g and h.

[0047] Included in operation of clock generator circuit 20, the output of latch L4 is inverted by buffer G3 and the output of buffer G3 is generated clock output cp supplied at Q output. Phase delay circuit 12 delays the rise of generated clock output cp to a rising edge applied to the “reset” R input of latch L4. The rise of generated clock output cp is tunable or configurable. Together with the latch L4, phase delay circuit 12 is effectively a “one shot” circuit that may only stay at a high state for a period of time. The period is determined by the process speed, voltage and temperature (PVT) characteristic as well as the configuration data of phase delay circuit 12.

[0048] Similarly, if phase delay circuit 14 is the same as phase delay circuit 12 and is controlled the same, phase delay circuit 14 delays the fall of the output of latch L4 in response to the reset R assertion by phase delay circuit 12 to a rising edge of the set S input of latch L4. Phase delay circuit 14 is therefore, another, equal delay, “one shot” circuit. The output of phase delay circuit 14 however, will only stay low for so long. The period for which the output of latch L4 stays low is determined by the delay of phase delay circuit 14. While phase delay circuits 12 and 14 are identically controlled by a controller (not shown), their delay may not be exactly equal due to supply variations throughout the cycle of operation of clock generator circuit 20 and IC 5, among other factors. The set S input of latch L4 is supplied by the output of AND gate G2.

[0049] The set S input of latch L4 in primary clock generator circuit 20 is from AND gate G2 that may ANDs other delay circuit paths from phase delay circuits of the secondary clock generator circuits 20 may also be tunable or configurable before a runtime of IC 5 and controllable at a runtime of IC 5. The phase delay circuits of secondary clock generator circuits 20 may be similar to or are the same as delay element 12. The outputs of the delay circuits of the other tunable or configurable delay paths may be applied on multiple inputs applied to an expanded AND gate G2 input (not shown). The output of latch L4 on Q output is applied to another input of AND gate G2 via pulse generator (PG) 30 cascaded with a rising edge to a rising edge (R2R (2)) delay circuit 14.. The multiple inputs are ANDed by AND gate G2, so that the output of enable circuit 18 asserts a “set” S signal to latch L4, only when all of paths supplied on the multiple inputs have switched to one. A feature of AND gate G2, therefore, is that it aggregates the multiple inputs. The aggregation of the multiple inputs enable the frequency of the clock pulse output (cp) signal to be configured by being responsive to the slowest delay path of the other delay elements supplied on inputs provided from delay circuit 14 of clock generator circuit 20.

[0050] Under the control of a controller included in IC 5, where IC 5 may be a CPU or included in the CPU. The frequency of the clock pulse output (cp) signal of clock generator circuit 20 may be reduced to cause a delay when a slower operating unit in integrated circuit (IC) 5 is turned on. The delay will grow if voltage drops, without any need for tuning of the phase delay circuits 12 and 14 or any of the phase delay paths at different location in IC 5. Yet the user and / or operating system may request a different frequency. On the other hand, the CPU macro itself may request a momentary slowdown when a slow unit is turned on. A user may alter the clock pulse output (cp) signal responsive to a request of the user. The frequency of the clock pulse output (cp) signal may be reduced when a macro of IC 5 or CPU requests for a momentary turning on of a slow operating unit in the integrated circuit 5.

[0051] In general, and according to descriptions that follow, the variations in operation of primary clock generator circuit 20 and other delay paths at various other locations in IC 5, enable the other delay paths of secondary clock generator circuits 20 to serve as sensors or monitors in IC 5. A feature of other delay paths at various other locations in IC 5 is that the other delay paths can be configured to perform a specific sensing or monitoring function under the control of control unit 1 included in IC 6.

[0052] Reference is now made to FIG. 3 A, which shows further details of a unit model 22 that may be used to implement primary clock generator circuit 20, in accordance with some embodiments. Unit model 22a or unit model 22b may be implemented as unit model 22 that may include a pulse generator circuit 30. Enable outputs enO and enl of a half splitter circuit 26 (not shown) may be applied to respective inputs of unit model 22a or unit model 22b when unit model 22a or unit model 22b are each implemented as unit model 22. Specifically, for unit model 22, pulse generator 30 includes an input connected to clock signal cp. Clock signal cp connects to the rising edge enable (En) inputs of latches LI and L2 and one input of NAND gate G9. Enable enO may be applied to the input of latch LI. The output of latch LI is connected to the input of latch L2 and a second input of NAND gate G9. The output of latch L2 is connected to the input of inverter gate 16 and the output of inverter gate 16 connects to a third input of NAND gate G9. The output of NAND gate G9 connects to the input of buffer 17 and the output of buffer gate 17 provides a pulse (pls) output that connects in parallel to the clock (elk) inputs of delay path units 34U, 34L and 34S. Tuning controls 32 from controller 214 may be provided on multiple latches L3. The multiple output of latches L3 connect to configure (cfg) input of each of the delay path units 34U, 34L and 34S. The three outputs of each delay path units 34U, 34L, and 34S connect to three respective inputs of NAND gate G10.

[0053] Reference is now made to FIG. 3B that shows a graph 200 of frequency versus voltage curves for three tunable or configurable delay path units 34U, 34L, and 34S, in accordance with some embodiments. The three tunable or configurable delay path units 34U, 34L, and 34S may be included in either unit models 22a and 22b. Three scaling curves 341, 342 and 343 are shown for respective delay path units 34S, 34L, and 34U for respective Standard Voltage Threshold (SVT), Low voltage Threshold (LVT) and Ultralow Voltage Threshold regions (ULVT). Arrows 341b, 342b, and 343b indicate a low voltage failure point, a mid-voltage failure point, and a high voltage failure point respectively. The voltage axis is marked at points 341a, 342a and 343a indicate the voltage levels of supply of a low performance power supply, a normal power supply and a high performance power supply respectively at various locations of IC 5. Prior to a runtime of IC 5, a test time enables the tuning or configuring of the three delay path units 34U, 34L and 34S. The three scaling curves 341, 342 and 343 are utilized to tune the three tunable or configurable delay path units 34U, 34L and 34S. Included in the tuning and the subsequent runtime of IC 5 delay path units 34U, 34L and 34S are utilized to provide a monitor or sensing of the frequency and power supply levels for delay path units 34U, 34L and 34S located at various locations of IC 5.

[0054] Unit models 22a and 22b each implemented as unit model 22 serve as additional cycling paths. The additional cycling paths delay a rising edge to a rising edge (R2R) of clock pulse cp. Unit models 22a and 22b delay the rising edge by each generating short negative pulse; pulse pls. Pulse pls is from each pulse generator circuit 30 included in unit model 22a and unit model 22b. The pulses pls quickly reset the outputs of the cycling paths to zero and each pulse pls then goes through tunable or configurable delay path units 34U, 34L, and 34S. Going through delay path units 34U, 34L and 34S delays the trailing edge of the pulse (pls rising) and produces a rising edge. The rising edge is tuned at the test time that represents the latency of some location of the integrated circuit (IC) 5.

[0055] At the runtime of IC 5, after tuning and Voltage threshold (Vt) gate constants derived from the test time have been loaded to controller 24, the average frequency of the clock pulse cp is monitored. The average frequency may be monitored by controller 24 counting clock pulses of clock pulse cp in a window compared with an external, slow, fixed frequency reference clock. Only one set of controls of controller 24 may be modified at a time in order to slow down a clock frequency of clock generator circuit 20 that is too high, as clock generator circuit 20 waits for the last path of either unit models 22a or 22b to rise. A criteria of slowing down a clock frequency is that at no time, may the clock period of a clock signal become shorter than what is defined by all the other paths set at the test time. The criteria will prevent the clock of a macro of IC 5IC 5 from ever running so fast as to functionally fail the macro of IC 5IC 5 or the clock of a macro of a CPU. In sum, the duration of each clock signal (cp) cycle is tunable or configurable in a unit model 22, and is process, voltage and temperature (PVT) responsive by virtue of tunable or configurable delay path units 34U, 34L and 34S in each unit model 22. The clock cycle duration is determined by the largest delay (longest) of the delay path units 34U, 34L and 34S located in various places on the clocked macro of IC 5, Where each of the delay path units 34U, 34L and 34S being influenced by the average supply voltage at its vicinity, at the time of the clock cycle.

[0056] Reference is now made to FIG. 4 that shows a graph 400 of voltage amplitude versus time for the operation of both primary and secondary clock generator circuits 20, in accordance with some embodiments. Clock generator circuit 20 further includes and is further configurable to provide a generated clock pulse responsive to the distributed delay models as described above and / or (PLL) clock input (pll clk) and a phase lock loop (PLL) enable input (pll en) input to clock generator circuit 20. When responsive to (PLL) clock input (pll clk) under control of control unit 1, PLL enable input (pll en) is applied to the clock generator circuit to achieve a lower interface delay penalty of communication interface 3 connected between one or more logic modules 4 situated at various locations of integrated circuit (IC) 5.

[0057] PLL clock input (pll clk) helps to synchronize clock signals across multiple logic modules 4 of the IC 5 to ensure that all logic modules 4 operate at the same frequency, thereby minimizing the risk of errors and data corruption of data transmitted and received between logic modules 4. Other examples of logic modules 4 include system memory, peripheral controllers for universal serial bus (USB), storage, and more advanced peripherals such as graphics processing units (GPUs), specialized neural network circuitry, radio modems (for Bluetooth™ or WiFi™), and more. The stable PLL clock input (pll clk) signal may be used as a reference for data transfer to help to ensure that data is transmitted accurately and efficiently between logic modules 4. Stable PLL clock input (pll clk) signal, further helps to improve the performance of IC 5 to provide a stable clock so that all the components of IC 5 operate at their optimal frequency. The combined features described herein of a generated clock pulse (elk) of both primary and secondary clock generator circuits 20, responsive to the distributed delay models, and / or a phase lock loop (PLL) clock input to both primary and secondary clock generator circuits 20. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals (of communication interface 3) respectively. In operation of both the primary and secondary clock generator circuits 20, the set input (S) signal to latch L4 is waiting to be set on si input of AND gate G2 by going high to a logic 1. If PLL enable input (pll en) is going low to logic zero (0), then si input of AND gate G2 will always be high so that there is no waiting for PLL clock input (pll clk) signal on the other input of OR gate Gl. However, if PLL enable input (pll en) is high, there is now a situation where there is a waiting for PLL clock input (pll clk) signal on the other input of OR gate Gl to rise high in order to set the set input (S) of latch L4.

[0058] With reference to graph 400, the top graph shows the waveform output of rising edge (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4. The top graph also includes, shows PLL clock input (pll clk) signal. The bottom graph shows the clock (elk) pulse generated by primary / secondary clock generator circuits 20 and the set (S) and reset (R) pulses. The set (S) pulses applied at times tl, t2, and t3. In the top graph at time tl it can be seen that the waveform output of rising edge (R2R (1)) has arrived earlier than the PLL clock input (pll clk) signal. The PLL clock input (pll clk) signal is shown as being very fixed and stable. At time tl a set (S) pulse is derived that causes the elk pulse generated by primary / secondary clock generator circuits 20 to rise. With the fall of (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4 is a reset pulse applied to the reset of latch L4. On the next cycle at time t2, that the PLL clock input (pll clk) signal has now arrived earlier than the waveform output of rising edge (R2R (1)) of delay circuit 12. Therefore, the set (S) pulse will be at the time of the later rise of the waveform output of rising edge (R2R (1)) of delay circuit 12. Again with the of (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4 is a reset pulse applied to the reset of latch L4. At time t3 the rising edge (R2R (1)) signal is early, the frequency output of rising edge (R2R (1)) of delay circuit 12 is increased due to increased voltage, and a waiting period is initiated until the arrival and rise of the PLL clock input (pll clk) signal in order to establish the set (S) pulse.

[0059] Therefore, as both sides of the interface between the two rising edge (R2R (2)) of delay circuit 14 and rising edge (R2R (1)) of delay circuit 12 lock to the same PLL clock provided by the PLL clock input (pll clk) signal it is possible to use just a single (falling edge) flop for a 1 cycle delay interface instead of two. Since delay paths of delay circuit 12 and delay circuit 14 cascaded with pulse generator 30 protect logic modules 4 it is possible to decrease PLL supply margin, while achieving a lower interface delay penalty than is possible with a ring oscillator (RO) only design to improve both power and interface delay performance.

[0060] Reference is now made to FIG. 5 that shows a flowchart of a method 500, in accordance with some embodiments. At step 501, phase lock loop (PLL) clock input (pll clk) signal is received on an enabled input of clock generator system 10. If PLL enable input (pll en) is going low to logic zero (0), then si input of AND gate G2 will always be high so that there is no waiting for PLL clock input (pll clk) signal on the other input of OR gate Gl. However, if PLL enable input (pll en) is high, there is now a situation where there is a waiting for PLL clock input (pll clk) signal on the other input of OR gate Gl to rise high in order to set the set input (S) of latch L4. The activation PLL enable input (pll en) is in order to enable a stable PLL clock input (pll clk) signal that may be used as a reference for data transfer to help to ensure that data is transmitted accurately and efficiently between logic modules 4. Stable PLL clock input (pll clk) signal, further helps to improve the performance of IC 5 to provide a stable clock so that all the components of IC 5 operate at their optimal frequency. The combined features described herein of a generated clock pulse (elk) of both primary and secondary clock generator circuits 20, responsive to the distributed delay models, and / or a phase lock loop (PLL) clock input to both primary and secondary clock generator circuits 20. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals (of communication interface 3) respectively.

[0061] At step 503, phase lock loop (PLL) clock input (pll clk) aggregated with the output of a second delay path formed by pulse generator circuit 30 cascaded with delay circuit 14 (R2R (2)). The aggregation of step 503 is by logically ANDing the phase lock loop (PLL) clock input (pll clk) with the second delay path by AND gate G2. In general, the second delay path receives an input from the Q output of both primary and secondary clock generator circuits 20.

[0062] At step 505, the output of the second delay path formed by pulse generator circuit 30 cascaded with delay circuit 14 (R2R (2)) and the input from the Q output of both primary and secondary clock generator circuits 20.

[0063] At step 507, latching on the set (S) input and the reset (R) input of latch L4 is performed with the ANDing and the output of the first delay path (R2R(1)) respectively, input of OR gate Gl to rise high in order to set the set input (S) of latch L4. With reference to graph 400 again, the top graph shows the waveform output of rising edge (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4. The top graph also includes, shows PLL clock input (pll clk) signal. The bottom graph shows the clock (elk) pulse generated by primary / secondary clock generator circuits 20 and the set (S) and reset (R) pulses. The set (S) pulses applied at times tl, t2, and t3. In the top graph at time tl it can be seen that the waveform output of rising edge (R2R (1)) has arrived earlier than the PLL clock input (pll clk) signal. The PLL clock input (pll clk) signal is shown as being very fixed and stable. At time tl a set (S) pulse is derived that causes the elk pulse generated by primary / secondary clock generator circuits 20 to rise. With the fall of (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4 is a reset pulse applied to the reset of latch L4. On the next cycle at time t2, that the PLL clock input (pll clk) signal has now arrived earlier than the waveform output of rising edge (R2R (1)) of delay circuit 12. Therefore, the set (S) pulse will be at the time of the later rise of the waveform output of rising edge (R2R (1)) of delay circuit 12. Again with the of (R2R (1)) of delay circuit 12 that connects to the reset (R) input of latch L4 is a reset pulse applied to the reset of latch L4. At time t3 the rising edge (R2R (1)) signal is early, the frequency output of rising edge (R2R (1)) of delay circuit 12 is increased due to increased voltage, and a waiting period is initiated until the arrival and rise of the PLL clock input (pll clk) signal in order to establish the set (S) pulse.

[0064] At step 509, a generated clock pulse on the Q output responsive to the first delay path, the second delay path or the phase lock loop (PLL) clock input (pll clk) is provided. The generated clock pulse on the Q output responsive to the first delay path and the second delay path is typically subjected prior to a runtime of IC 5, to a test time to enable the tuning or configuring of the three delay path units 34U, 34L, and 34S. The three scaling curves 341, 342 and 343 are utilized to tune the three tunable or configurable delay path units 34U, 34L, and 34S of both primary and secondary clock generator circuits 20. Included in the tuning and the subsequent runtime of IC 5 delay path units 34U, 34L, and 34S of the secondary clock generator circuits 20 are utilized to monitor, sense, and evaluate the frequency and power supply levels for delay path units 34U, 34L, and 34S located at various locations of IC 5. Whereas during the runtime of IC 5, the clock signal derived from the Q output of primary clock generator circuit 20 is propagated through a series of buffers, inverters, and other components (not shown) that shape and a distribution the clock signal throughout clock generator system 10. The distribution being further responsive to monitor or sensing and evaluating of the frequency and power supply levels for delay path units 34U, 34L and 34S located at various locations of IC 5. The distribution further initiates the next cycle of clock generator system 10 only when the functions of all regions of IC 5 are correctly performed with a next clock edge of the clock pulse on the Q output. 517. Responsive to the sensing and the evaluating, voltage drops may be compensated on farther away sites in IC 5 and to modelling of clock network effects and arbitrary logic behavior of logic modules 4 by the first delay path (R2R(1)) and the second delay path (R2R(2)).

[0065] At step 511, when responsive to (PLL) clock input (pll clk) is required for communication data transfer between logic modules 4, under control of control unit 1, PLL enable input (pll en) is applied to the clock generator circuit to achieve a lower interface delay penalty of communication interface 3 connected between one or more logic modules 4 situated at various locations of integrated circuit (IC) 5 and the phase lock loop (PLL) clock input (pll clk).

[0066] In sum, the combined features described herein of a generated clock pulse (elk) of both primary and secondary clock generator circuits 20, responsive to the distributed delay models, and / or a phase lock loop (PLL) clock input to both primary and secondary clock generator circuits 20. Provide energy efficiency, margin minimization, and / or improved synchronization / communication of data, improved performance, PLL margin minimization, reduced delay penalties on interface signals (of communication interface 3) respectively. The use of the distributed delay models allows for tuning at every cycle of a clock pulse that may provide a more dynamic approach to clock generation compared to the exclusive use of PLLs. The use of the distributed delay models allows responses to changes in supply conditions more quickly, reducing the need for large margins. The distributed delay models allows for the sensing of process, voltage, and temperature (PVT) throughout IC 5, enabling immediate response to supply perturbations in effect to minimize the need for large margins and improves the power and performance of IC 5.

[0067] Whereas the selective us of PLLs clock signals in combination with the use of the distributed delay models provides synchronized approach to clock generation by clock generation system 10 that reduces the delay penalty on interface signals. The synchronization provided by PLLs clock signals helps ensure that all components in IC 5 are operating at the same clock frequency, reducing the potential for errors or communication issues caused by out-of-sync signals. PLLs clock signals can be designed with adjustable loop bandwidth and phase margins, which can be adjusted to meet the specific synchronization requirements of different logic modules in IC 5.

[0068] The selective us of PLLs clock signals in combination with the use of the distributed delay models therefore, allows for a more fine-tuned approach to synchronization, reducing the potential for delay penalties on interface signals. Because both sides of the interface between the two rising edge (R2R (2)) of delay circuit 14 and rising edge (R2R (1)) of delay circuit 12 lock to the same PLL clock provided by the PLL clock input (pll clk) signal, it is possible to use just a single (falling edge) flop for a 1 cycle delay interface instead of two. Further, delay paths of delay circuit 12 and delay circuit 14 cascaded with pulse generator 30, protect logic modules 4, and decrease PLL supply margin, while achieving a lower interface delay penalty to improve both power and interface delay performance.

[0069] Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

[0070] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0071] As used herein the term “about” refers to ± 10 %.

[0072] The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of' and "consisting essentially of'. The phrase "consisting essentially of' means that the composition or method may include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0073] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[0074] The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features from other embodiments.

[0075] The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the disclosure may include a plurality of “optional” features unless such features conflict.

[0076] Throughout this application, various embodiments of this disclosure may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0077] Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging / ranges between” a first indicate number and a second indicate number and “ranging / ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween. It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiment of the disclosure. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

[0078] It is the intent of the applicant(s) that all publications, patents and patent applications referred to in this specification are to be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually noted when referenced that it is to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is / are hereby incorporated herein by reference in its / their entirety.

Claims

CLAIMS1. A clock generator system comprising: a controller unit, including a control interface; one or more logic modules located at various location of an integrated circuit (IC), wherein the one or more logic modules are operably connected to the controller unit; a clock generator circuit including: a two input OR gate, including a phase lock loop (PLL) clock input and a phase lock loop (PLL) enable input operatively attached to the controller unit; a latch including a set (S) input and a reset (R) input; a first delay path including an input from the Q output of the latch, wherein the output of the first delay path connects to the reset (R) input, a pulse generator (PG) including an input from the Q output of the latch and an output connected to the input of a second delay path; and an AND gate with input from the output of the a second delay path and another input from the phase lock loop clock input, wherein the output of the AND connects to the set (S) input, wherein the AND gate provides an aggregating of the output of the two input OR gate with the output of the second delay path, wherein the Q output is configurable responsive to the aggregating to: provide a generated clock pulse on the Q output responsive to allow at least one of the first, the second delay paths and the phase lock loop (PLL) clock input, and apportion the generated clock pulse on the Q output to reduce the margins associated with the use of phase lock loop (PLL) clock input enabled by PLL enable input to achieve a lower interface delay penalty of the control interface between the one or more logic modules at various locations of the integrated circuit (IC).

2. The clock generator system of claim 1, wherein generated clock pulse protects the at least one or more logic modules at various locations of the integrated circuit (IC).

3. A method for generating a clock pulse in a clock generator system including multiple clock generator circuits operably attached to one or more logic modules situated at various locations of an integrated circuit (IC), the method comprising: receiving a phase lock loop (PLL) clock input;enabling the PLL clock input to be aggregated by ANDing an output of a second delay path with the PLL clock input, cascading an input to a first delay path and an input to a pulse generator (PG) with an input to the second delay path from the Q output of a latch; latching on the set (S) input and the reset (R) input of the latch with the ANDing and the output of the first delay path respectively; providing a generated clock pulse on the Q output of the latch responsive to at least one of the first, the second delay paths and the phase lock loop (PLL) clock input; and responsive to the providing, reducing the margins associated with the enabling use of a PLL enable input, thereby achieving a lower interface delay penalty of a control and communication interface connected between the one or more logic modules situated at various locations of the integrated circuit (IC).

4. The method of claim 3, wherein the providing further comprises: sensing voltage at multiple regions the IC; and evaluating multiple delay paths to initiate the next cycle of the clock generator system only when the functions of all regions of the IC are correctly performed with a next clock edge of the clock pulse on the Q output.

5. The method of claim 4, further comprising: responsive to the sensing and the evaluating, compensating for voltage drops on farther away sites in the IC and to modelling of clock network effects and arbitrary logic behavior of the logic modules by at least one of the first delay path and the second delay path.

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