Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor substrate (1); a first oxide film (2) formed on the surface of the semiconductor substrate (1); a first oxide film (3) formed on the surface of the first oxide film (2); a passive element (10) formed inside the first oxide film (3); and embedded semiconductors (21)-(23) that are embedded in the surface of the first oxide film (2) immediately below the passive element (10), and that include low-concentration impurity regions (21a)-(23a), in which an interface is formed with the back surface of the first oxide film (3), and high-concentration impurity regions (21b)-(23b), which are bonded to the bottom surfaces of the low-concentration impurity regions (21a)-(23a), are exposed from the surface of the first oxide film (3), and have a contact surface to which a voltage is applied.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a method for suppressing performance degradation of passive elements at high frequencies, such as several tens of GHz, in semiconductor devices applied to analog circuits and high-frequency circuits (RF circuits). The semiconductor device disclosed in Patent Document 1 has a high-resistivity Si substrate made of n-type and p-type layers, which is divided into a CMOS region and a passive element region, an interlayer insulating film formed on the p-type layer, a wiring layer serving as an inductor or transmission line formed in the interlayer insulating film of the passive element region, and a well not formed inside the p-type layer, since the p-type layer located below the wiring layer maintains high resistance.

[0003] JP 2011-34992 A

[0004] In recent years, silicon (Si)-based semiconductor process technology, such as silicon (Si) and silicon germanium (SiGe), which have been miniaturized for logic circuits, has been increasingly applied to analog circuits in semiconductor devices. The maximum oscillation frequency of transistors using this miniaturized process has reached 500 GHz, and attention is being paid to the application of silicon-based processes to the 300 GHz band, which is expected to be utilized in the post-5G generation.

[0005] In semiconductor devices that are used in frequency bands above 100 GHz, a common approach to correcting manufacturing variations is to add a compensation circuit that adjusts the impedance of the passive elements that transmit signals. However, adding a compensation circuit to the passive elements creates a problem in that the compensation circuit affects the analog circuit.

[0006] The present disclosure has been made in consideration of the above points, and focuses on semiconductor devices that are applied to, for example, analog circuits or high-frequency circuits, which operate in a frequency band of several tens of GHz, particularly above 100 GHz, and aims to obtain a semiconductor device that is suitable for operation in a frequency band of several tens of GHz, particularly above 100 GHz.

[0007] The semiconductor device according to the present disclosure comprises a semiconductor substrate, a first oxide film formed on a surface of the semiconductor substrate, a second oxide film formed on the surface of the first oxide film, a passive element formed inside the second oxide film, and an embedded semiconductor including a low-concentration impurity region embedded in the surface of the first oxide film directly below the passive element and forming an interface with a rear surface of the second oxide film, and a high-concentration impurity region joined to a bottom surface of the low-concentration impurity region and exposed to the surface of the second oxide film, and having a contact surface to which a voltage is applied.

[0008] According to the present disclosure, a semiconductor device suitable for operation in a frequency band of several tens of GHz, particularly above 100 GHz, can be obtained.

[0009] FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment. FIG. 2 is a perspective projection view showing a main part of a semiconductor device according to a first embodiment. FIG. 3 is a schematic diagram showing a case where a voltage higher than a voltage in a passive element is applied to a high-concentration impurity region of a first buried semiconductor in the semiconductor device according to the first embodiment. FIG. 4 is a schematic diagram showing a case where a voltage lower than a voltage in a passive element is applied to a high-concentration impurity region of a first buried semiconductor in the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view showing a main part of a semiconductor device according to a second embodiment. FIG. 6 is a perspective projection view showing a main part of a semiconductor device according to the second embodiment. FIG. 7 is a cross-sectional view showing an interdigital capacitor which is a main part of a semiconductor device according to a third embodiment. FIG. 8 is an equivalent circuit diagram of an interdigital capacitor which is a main part of a semiconductor device according to the third embodiment. FIG. 9 is a diagram showing the relationship between inductive self-resonant frequency and inductance in an interdigital capacitor which is a main part of a semiconductor device according to the third embodiment.

[0010] First Embodiment. A semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 4. The semiconductor device according to the first embodiment is a semiconductor device manufactured by silicon-based semiconductor process technology applied to analog circuits or high-frequency circuits. The semiconductor device according to the first embodiment is applied to semiconductor devices in which active circuits such as amplifier circuits or oscillators that operate in frequency bands of several tens of GHz, particularly above 100 GHz, are formed. The semiconductor device according to the first embodiment is a semiconductor device that is provided with a function that can correct manufacturing variations with extremely little effect on passive elements that transmit signals, particularly in frequency bands above 100 GHz.

[0011] When designing an active circuit such as an amplifier circuit or an oscillator, the influence of manufacturing variations in passive elements such as transmission lines, resistors, capacitors, and inductors, which is not much of a problem in circuits below several tens of GHz where a signal gain of several tens of dB can be obtained, that is, the influence of variations in parasitic capacitance between the passive elements and the semiconductor substrate due to location-specific variations in the film thickness of the oxide film between the passive elements and the semiconductor substrate due to manufacturing variations within the manufacturing tolerance, becomes very large because the signal gain obtained in the frequency band above 100 GHz is small, at only several dB. The semiconductor device according to the first embodiment is a semiconductor device that can suppress degradation of high-frequency characteristics due to manufacturing variations in passive elements.

[0012] Fig. 1 is a cross-sectional view showing the characteristic features of the semiconductor device according to the first embodiment, and Fig. 2 is a perspective projection view. Although Fig. 1 and Fig. 2 show one passive element to explain the characteristic features, the semiconductor device is not limited to having one passive element but may have multiple passive elements, and may also have multiple active elements such as MOS transistors. Each of the multiple passive elements that handle high-frequency signals is also given a characteristic feature similar to that shown in Fig. 1 and Fig. 2.

[0013] 1 and 2 , the semiconductor device according to the first embodiment includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, a passive element 10, first buried semiconductor 21 to third buried semiconductor 23, and first control voltage line 31 to third control voltage line 33. A ground layer is formed on the back surface of the semiconductor substrate 1 and is set to a ground potential. The passive element 10 is a transmission line, a resistor, a capacitor, an inductor, or the like. Since the transmission line, the resistor, the capacitor, and the inductor have the same characteristic of suppressing degradation of high-frequency characteristics in the first embodiment, to avoid complexity of explanation, a transmission line will be taken as an example of the passive element 10 and will be described as the transmission line 10.

[0014] The first oxide film 2 is formed on the surface of the semiconductor substrate 1. In the first embodiment, the first oxide film 2 is a silicon oxide film (SiO ２ ) In the surface of the first oxide film 2, buried regions in which the first buried semiconductor 21 to the third buried semiconductor 23 are buried are formed by grinding away the buried regions by etching or the like, directly below the transmission line 10 and spaced apart from each other. In other regions of the surface of the first oxide film 2, MOS transistors and the like are formed, although not shown.

[0015] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surfaces of the first buried semiconductor 21 to the third buried semiconductor 23. The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and on the surfaces of each of the first buried semiconductor 21 to the third buried semiconductor 23. The second oxide film 3 has a plurality of wiring layers inside.

[0016] In the second oxide film 3, the silicon oxide film located below the transmission line 10, in contact with the lower surface of the transmission line 10, and forming the interface between the surface of the first oxide film 2 and the surfaces of each of the first to third buried semiconductors 21 to 23 will hereinafter be referred to as the lowermost oxide film in the second oxide film 3. In the first embodiment, the design value of the film thickness of the lowermost oxide film in the second oxide film 3 is, for example, 200 nm. That is, the distance between the lower surface of the transmission line 10 and the surfaces of each of the first to third buried semiconductors 21 to 23 is set to 200 nm.

[0017] The transmission line 10 is a line formed in the lowest wiring layer of multiple wiring layers arranged inside the second oxide film 3, and is a line made of a metal layer in the first embodiment. In the first embodiment, the transmission line 10 is, for example, a line having a width of 5 μm. In the first embodiment, the transmission line 10 constituting a passive element is, for example, a signal line that transmits a high-frequency signal in a frequency band exceeding 100 GHz in an analog circuit, a high-frequency circuit, or an active circuit such as an amplifier circuit or oscillator.

[0018] The first to third buried semiconductors 21 to 23 are each embedded, spaced apart from one another, in the surface of the first oxide film 2 directly below the transmission line 10. The first to third buried semiconductors 21 to 23 are each embedded in corresponding buried regions formed, spaced apart from one another, in the surface of the first oxide film 2.

[0019] The surfaces of the first to third buried semiconductors 21 to 23 are buried in the corresponding buried regions formed in the surface of the first oxide film 2, and are therefore flush with the surface of the first oxide film 2, forming a flat surface together with the surface of the first oxide film 2. The first to third buried semiconductors 21 to 23 are electrically insulated from each other by the first oxide film 2 and are electrically independent from each other. In the first embodiment, the thickness of each of the first to third buried semiconductors 21 to 23 is, for example, 80 nm.

[0020] The first buried semiconductor 21 to the third buried semiconductor 23 each include low-concentration impurity regions 21a to 23a that form an interface with the bottom surface of the second oxide film 3, and high-concentration impurity regions 21b to 23b that are in contact with the bottom surfaces of the low-concentration impurity regions 21a to 23a and have contact surfaces 21b1 to 23b1 that are exposed to the surface of the second oxide film 3 and to which a voltage is applied.

[0021] In the first embodiment, each of the first to third buried semiconductors 21 to 23 is formed as follows. First, an intrinsic semiconductor is buried in a corresponding buried region formed in the surface of the first oxide film 2. N-type impurities are implanted from the surface of the intrinsic semiconductor by ion implantation or the like to form a low-concentration n-type semiconductor. N-type impurities are ion-implanted from the surface to the bottom of the low-concentration n-type semiconductor to form a virtual electrode region, which is a high-concentration impurity region, at the bottom. Then, to form the contact surfaces 21b1 to 23b1 to which voltage is applied, a contact region, which is a high-concentration impurity region that reaches the virtual electrode region formed at the bottom by ion implantation from the surface of the low-concentration n-type semiconductor, is formed in the region set as the contact surfaces 21b1 to 23b1, for example, at one end of the virtual electrode region. The virtual electrode region and the contact region become the high-concentration impurity regions 21b to 23b, and the remaining regions become the low-concentration impurity regions 21a to 23a.

[0022] Although the low-concentration impurity regions 21a to 23a and the high-concentration impurity regions 21b to 23b in each of the first to third buried semiconductors 21 to 23 are n-type impurity regions, they may be p-type impurity regions. Alternatively, the low-concentration impurity regions 21a to 23a and the high-concentration impurity regions 21b to 23b in any of the first to third buried semiconductors 21 to 23 may be n-type impurity regions, and the low-concentration impurity regions 21a to 23a and the high-concentration impurity regions 21b to 23b in the other buried semiconductors 21 to 23 may be p-type impurity regions.

[0023] Furthermore, a combination of an N-type impurity region and a P-type impurity region may be used as long as the combination is such that, when a voltage is applied to the high-concentration impurity regions 21b to 23b, a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of each of the first to third buried semiconductors 21 to 23 by the applied voltage.

[0024] Each of the first control voltage line 31 to the third control voltage line 33 is formed in a wiring layer arranged inside the second oxide film 3, one end of which is in ohmic contact with the contact surfaces 21b1 to 23b1 of the high-concentration impurity regions 21b to 23b in the corresponding first buried semiconductor 21 to third buried semiconductor 23, and the control voltage from the corresponding first control voltage source 41 to third control voltage source 43 is applied to the other end of each line.

[0025] In the first region 101 of the transmission line 10 located immediately above the first buried semiconductor 21, a parasitic capacitance C １１ 3, when a voltage higher than that in the first region 101 of the transmission line 10 is applied to the high-concentration impurity region 21b, the voltage difference between the first region 101 and the high-concentration impurity region 21b causes electrons in the low-concentration impurity region 21a to move away from the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21, and a depletion layer is generated in the low-concentration impurity region 21a.

[0026] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high-concentration impurity region 21b. １２ Therefore, in the first region 101 of the transmission line 10, a parasitic capacitance C １１ and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high-concentration impurity region 21 b. １２ The combined parasitic capacitance C １０ [C １１ ×C １２ / (C１１ +C １２ )] are connected.

[0027] On the other hand, when a voltage lower than the voltage in the first region 101 of the transmission line 10 is applied to the high-concentration impurity region 21 b, as shown in FIG. 4, the voltage difference between the first region 101 and the high-concentration impurity region 21 b causes electrons in the low-concentration impurity region 21 a to be attracted to the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21, and a charge accumulation region is formed at the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21.

[0028] As a result, the charge storage region generates a parasitic capacitance C １２ becomes invisible, that is, the parasitic capacitance C １２ Therefore, in the first region 101 of the transmission line 10, a parasitic capacitance C １１ , and the combined parasitic capacitance C １０ The capacitance value of the parasitic capacitance C １１ The capacitance value of the combined parasitic capacitance C １０ The capacitance value of

[0029] That is, the parasitic capacitance C １２ The capacitance value of the combined parasitic capacitance C connected to the first region 101 of the transmission line 10 can be adjusted by the voltage applied to the heavily doped impurity region 21b because the extent of the depletion layer varies depending on the voltage applied to the heavily doped impurity region 21b. １０ The capacitance value of the parasitic capacitance C １１ and parasitic capacitance C １２ The combined capacitance value of the series-connected １１ ×C １２ / (C １１ +C １２ ) )] is also a parasitic capacitance C １２ The parasitic capacitance C １１ The capacitance value can be adjusted up to

[0030] In the second region 102 of the transmission line 10 located immediately above the second buried semiconductor 22, a parasitic capacitance C２１ Furthermore, when a voltage higher than the voltage in the second region 102 of the transmission line 10 is applied to the high-concentration impurity region 22 b, a depletion layer is generated in the low-concentration impurity region 22 a due to the voltage difference between the second region 102 and the high-concentration impurity region 22 b, similar to the relationship between the first region 101 of the transmission line 10 and the first buried semiconductor 21.

[0031] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 and the virtual electrode region of the high-concentration impurity region 22b. ２２ Therefore, in the second region 102 of the transmission line 10, a parasitic capacitance C ２１ and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 and the virtual electrode region of the high-concentration impurity region 22 b. ２２ The combined parasitic capacitance C ２０ [C ２１ ×C ２２ / (C ２１ +C ２２ )] are connected.

[0032] On the other hand, when a voltage lower than the voltage in the second region 102 of the transmission line 10 is applied to the high-concentration impurity region 22b, a charge accumulation region is formed at the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 due to the voltage difference between the second region 102 and the high-concentration impurity region 22b, similar to the relationship between the first region 101 of the transmission line 10 and the first buried semiconductor 21. As a result, the charge accumulation region generates a parasitic capacitance C ２２ becomes invisible, that is, the parasitic capacitance C ２２ becomes short-circuited.

[0033] Therefore, in the second region 102 of the transmission line 10, a parasitic capacitance C ２１ , and the combined parasitic capacitance C ２０ The capacitance value of the parasitic capacitance C ２１ The capacitance value of the combined parasitic capacitance C ２０ The capacitance value of

[0034] That is, the parasitic capacitance C ２２ The capacitance value of the combined parasitic capacitance C connected to the second region 102 of the transmission line 10 can be adjusted by the voltage applied to the high-concentration impurity region 22b because the extent of the depletion layer varies depending on the voltage applied to the high-concentration impurity region 22b. ２０ The capacitance value of the parasitic capacitance C ２１ and parasitic capacitance C ２２ The combined capacitance value of the series-connected ２１ ×C ２２ / (C ２１ +C ２２ ) )] is also a parasitic capacitance C ２２ The parasitic capacitance C ２１ The capacitance value can be adjusted up to

[0035] In the third region 103 of the transmission line 10 located immediately above the third buried semiconductor 23, a parasitic capacitance C ３１ Furthermore, when a voltage higher than the voltage in the third region 103 of the transmission line 10 is applied to the high-concentration impurity region 23 b, a depletion layer is generated in the low-concentration impurity region 23 a due to the voltage difference between the third region 103 and the high-concentration impurity region 23 b, similar to the relationship between the first region 101 of the transmission line 10 and the first buried semiconductor 21.

[0036] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 and the virtual electrode region of the high-concentration impurity region 23b. ３２ Therefore, in the third region 103 of the transmission line 10, a parasitic capacitance C ３１ and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 and the virtual electrode region of the high-concentration impurity region 23 b. ３２ The combined parasitic capacitance C ３０ [C ３１ ×C ３２ / (C ３１ +C ３２ )] are connected.

[0037] On the other hand, when a voltage lower than the voltage in the third region 103 of the transmission line 10 is applied to the high-concentration impurity region 23b, a charge accumulation region is formed at the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 due to the voltage difference between the third region 103 and the high-concentration impurity region 23b, similar to the relationship between the first region 101 of the transmission line 10 and the first buried semiconductor 21. As a result, the charge accumulation region generates a parasitic capacitance C ３２ becomes invisible, that is, the parasitic capacitance C ３２ becomes short-circuited.

[0038] Therefore, in the third region 103 of the transmission line 10, a parasitic capacitance C ３１ is connected to the third region 103 of the transmission line 10, and the combined parasitic capacitance C ３０ The capacitance value of the parasitic capacitance C ３１ The capacitance value of the combined parasitic capacitance C ３０ The capacitance value of

[0039] That is, the expansion of the depletion layer, that is, the width of the depletion layer, varies depending on the voltage applied to the high-concentration impurity region 23b, so that the parasitic capacitance C ３２ The capacitance value of the parasitic capacitance C ３０ The capacitance value of the parasitic capacitance C ３１ and parasitic capacitance C ３２ The combined capacitance value of the series-connected ３１ ×C ３２ / (C ３１ +C ３２ ) )] is also a parasitic capacitance C ３２ The parasitic capacitance C ３１ The capacitance value can be adjusted up to

[0040] The first buried semiconductor 21 to the third buried semiconductor 23 are electrically insulated from each other by the first oxide film 2 and are independent from each other. Therefore, the combined parasitic capacitance C １０ ~C ３０ can be adjusted separately and independently of each other.

[0041] Next, a method will be described for improving the degradation of high-frequency characteristics caused by the change in characteristic impedance of the transmission line 10, which occurs when the thickness of the bottom oxide film in the second oxide film 3 directly below the transmission line 10 differs from the set value at a specific location due to manufacturing variations, even if the difference is within the range of manufacturing tolerances.

[0042] When transmitting signals in a frequency band above 100 GHz through transmission line 10, the influence of fluctuations in the parasitic capacitance connected to transmission line 10 significantly affects the high-frequency characteristics due to changes in the characteristic impedance of transmission line 10. Therefore, the semiconductor device according to the first embodiment adjusts the change in parasitic capacitance in transmission line 10 caused by changes in the thickness of the bottom-most oxide film in second oxide film 3 directly below transmission line 10 due to manufacturing variations, thereby adjusting the characteristic impedance of transmission line 10 and improving the degradation of high-frequency characteristics caused by changes in the thickness of the bottom-most oxide film.

[0043] That is, if the thickness of the bottom oxide film in the second oxide film 3 is thinner than the set value, the parasitic capacitance C １１ ~C ３１ Since the capacitance value of is larger than the set value, the parasitic capacitance C １２ ~C ３２ The capacitance value of the combined parasitic capacitance C １０ ~C ３０ In addition, if the thickness of the bottom oxide film in the second oxide film 3 is thicker than the set value, the parasitic capacitance C １１ ~C ３１ Since the capacitance value of is smaller than the set value, the parasitic capacitance C １２ ~C ３２ The capacitance value of the combined parasitic capacitance C １０ ~C ３０ approach the set value.

[0044] Since adjustments can be made separately and independently for each of the first to third regions 101 to 103 of the transmission line 10, and the adjustments are the same, the following description will focus on the adjustment in the first region 101. Now, the thickness of the bottom oxide film in the second oxide film 3 is set to 200 nm, the thickness of the first buried semiconductor 21 is set to 80 nm, the width of the transmission line 10 is set to 5 μm, and the length of the first region 101 of the transmission line 10 is set to 120 μm.

[0045] Furthermore, silicon is used as the first buried semiconductor 21, and a silicon oxide film is used as the second oxide film 3, with the relative dielectric constant of silicon being 12 and the relative dielectric constant of the silicon oxide film being 3.8. The semiconductor substrate 1 is grounded, and since the manufacturing tolerance for film thickness control in current fine processes is ±15%, a manufacturing tolerance of ±15% is assumed.

[0046] In the semiconductor device according to the first embodiment, the thickness of the bottom oxide film in the second oxide film 3 is set to a manufacturing tolerance of ±15% for a set value of 200 nm, that is, by controlling the voltage applied to the high-concentration impurity region 21 b from 170 nm to 230 nm, the combined parasitic capacitance C １０ The design is such that the characteristic impedance of the transmission line 10 can be made to approach the set capacitance value of the transmission line 10 and the set impedance.

[0047] That is, the only difference between the case where the thickness of the bottom oxide film of the second oxide film 3 is thinner or thicker than the set value is the voltage applied to the high-concentration impurity region 21b, so an example of the case where the thickness is thinner than the set value will be described below. The set value of the thickness of the bottom oxide film of the second oxide film 3 in the first region 101 of the transmission line 10 is 200 nm, and for comparison, the parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high-concentration impurity region 21b is １２ is assumed to be 0. At this time, the parasitic capacitance C between the first region 101 of the transmission line 10 and the first buried semiconductor 21 is １１ The capacitance value of is 100 fF, and the characteristic impedance of the transmission line 10 is 50 Ω.

[0048] Here, it is assumed that the thickness of the bottom oxide film of the second oxide film 3 in the first region 101 of the transmission line 10 is reduced by −15%, which is the maximum thickness allowed by the manufacturing tolerance, to 170 nm. The parasitic capacitance C １１ The capacitance value of the transmission line 10 is 118 fF. The characteristic impedance Z of the transmission line 10 is expressed by the following equation (1) using the inductance L and the capacitance C of the transmission line 10: Z = √(L / C) (1)

[0049] Parasitic capacitance C １１ If the capacitance value of increases by 18% from 100 fF to 118 fF due to a manufacturing tolerance of -15%, the value in equation (1) will be 1.18 times. Therefore, the parasitic capacitance C １１ When the capacitance value is 118 fF, the characteristic impedance Z1 of the transmission line 10 is 1 / 1.089 of the characteristic impedance Z in the case of the set value, and the characteristic impedance Z1 is 45.9 Ω when the characteristic impedance Z in the case of the set value is 50 Ω.

[0050] That is, when the thickness of the bottom oxide film of the second oxide film 3 in the first region 101 becomes 15% thinner than the set value, the characteristic impedance Z of the transmission line 10 changes from 50 Ω to 45.9 Ω, which has a large impact on the high-frequency characteristics of a semiconductor device operating in a frequency band of several tens of GHz, especially in a frequency band exceeding 100 GHz.

[0051] In the semiconductor device according to the first embodiment, the output voltage from the first control voltage source 41 is controlled so that a voltage higher than the voltage on the transmission line 10 is applied to the high-concentration impurity region 21b from the first control voltage source 41 via the first control voltage line 31, and a depletion layer is generated in the entire low-concentration impurity region 21a, as shown in FIG. 3. As a result, a parasitic capacitance C １２ occurs, and the parasitic capacitance C １２ The capacitance value of is 796 fF.

[0052] As a result, the parasitic capacitance C １１ (capacitance value 118 fF) and parasitic capacitance C １２(capacitance value 796 fF) are connected in series. １０ In other words, when the thickness of the bottom oxide film of the second oxide film 3 in the first region 101 is reduced by 15% from the set value of 200 nm, the capacitance value of the parasitic capacitance increases by only 2% to 102 fF from the set value of 100 fF, and the characteristic impedance of the transmission line 10 also decreases by only 2% from 50 Ω to 49 Ω.

[0053] Therefore, in a semiconductor device that operates in a frequency band of several tens of GHz, particularly above 100 GHz, it is possible to improve degradation of high-frequency characteristics caused by the influence of manufacturing variations in the film thickness of the bottom oxide film in the second oxide film 3 directly below the transmission line 10.

[0054] As an example, the case where the thickness of the bottom oxide film in the second oxide film 3 is 15% thinner than the set value of 200 nm has been described. However, the spread of the depletion layer generated in the low-concentration impurity region 21 a can be adjusted by applying a voltage to the high-concentration impurity region 21 b, and as a result, the parasitic capacitance C １２ Since the capacitance value of the parasitic capacitance C can be adjusted, the parasitic capacitance C １２ The capacitance value can be finely adjusted.

[0055] In the semiconductor device according to the first embodiment, a manufacturing tolerance of ±15% is assumed, but if the manufacturing tolerance exceeds ±15%, the thickness of the first buried semiconductor 21 can be increased, and the adjustment range of the capacitance value of the combined parasitic capacitance C10 can be widened by increasing the thickness of the first buried semiconductor 21. In short, the thickness of the first buried semiconductor 21 can be set depending on the film thickness and manufacturing tolerance of the bottom oxide film in the second oxide film 3, and the voltage applied to the high-concentration impurity region 21 b from the first control voltage source 41 can also be adjusted accordingly.

[0056] Furthermore, in the second region 102 of the transmission line 10, the second buried semiconductor 22 is also electrically insulated and electrically independent by the first oxide film 2. Therefore, similarly to the first region 101 of the transmission line 10, by applying a control voltage from the second control voltage source 42 via the second control voltage line 32 to the high-concentration impurity region 22 b of the second buried semiconductor 22 in accordance with manufacturing variations in the thickness of the bottom oxide film of the second oxide film 3, the capacitance value of the combined parasitic capacitance C20 can be made to approach a set value, and deterioration of the characteristic impedance in the second region 201 of the transmission line 10 can be improved.

[0057] Furthermore, in the third region 103 of the transmission line 10, the third buried semiconductor 23 is also electrically insulated and electrically independent by the first oxide film 2. Therefore, similarly to the first region 101 of the transmission line 10, by applying a control voltage from the third control voltage source 43 via the third control voltage line 33 to the high-concentration impurity region 23 b of the third buried semiconductor 23 in accordance with manufacturing variations in the thickness of the bottommost oxide film in the second oxide film 3, the capacitance value of the combined parasitic capacitance C30 can be made to approach a set value, and deterioration of the characteristic impedance in the third region 103 of the transmission line 10 can be improved.

[0058] Therefore, even if the thickness of the bottom oxide film of the second oxide film 3 directly below the first region 101 to the third region 103 of the transmission line 10 varies to different values ​​within the range of manufacturing tolerances, by independently controlling the voltages applied to the first buried semiconductor 21 to the third buried semiconductor 23, the capacitance values ​​of the parasitic capacitances for the first region 101 to the third region 103 of the transmission line 10 can be adjusted individually, and deterioration of the characteristic impedance in the first region 101 to the third region 103 of the transmission line 10 can be improved, thereby improving deterioration of the characteristic impedance for the entire transmission line 10.

[0059] Furthermore, by arranging buried semiconductors that are electrically insulated and electrically independent by the first oxide film 2 for each of the multiple transmission lines 10, the capacitance value of the combined parasitic capacitance can be increased or decreased individually depending on the manufacturing variation of the lowest oxide film in the second oxide film 3 directly below each of the multiple transmission lines 10, making it possible to bring the combined parasitic capacitance closer to a set value, and improving the deterioration of the characteristic impedance in each of the transmission lines 10.

[0060] Furthermore, the transmission line 10 is divided into three regions, the first region 101 to the third region 103, and the buried semiconductor is placed directly underneath, but depending on the transmission line 10, it may be divided into one region or two regions and the buried semiconductor may be placed directly underneath, or it may be divided into four or more regions and the buried semiconductor may be placed directly underneath.

[0061] Although the passive element 10 has been mainly described as a transmission line, the passive element 10 may also be a resistor formed by narrowing the line width in the lowest wiring layer arranged inside the second oxide film 3, a capacitor having a pair of parallel lines arranged in the wiring layer as a pair of electrodes, or an inductor formed by bending a line in the wiring layer, which may also be formed by applying embedded semiconductors in the same manner as the transmission line.

[0062] In the above embodiment 1, the case where there is one passive element 10 is mainly described, but by adding characteristic points to each of multiple passive elements 10 in the same manner as shown in Figures 1 and 2, the parasitic capacitance in the passive element 10 can be adjusted individually for each of the multiple passive elements.

[0063] As described above, the semiconductor device according to the first embodiment includes a passive element 10 formed inside a second oxide film 3 formed on the surface of a first oxide film 2 formed on the surface of a semiconductor substrate 1, low-concentration impurity regions 21 a to 23 a that are embedded in the surface of the first oxide film 2 directly below the passive element 10 and form an interface with the back surface of the second oxide film 3, and high-concentration impurity regions 21 a to 23 a that are in contact with the bottom surfaces of the low-concentration impurity regions 21 a to 23 a and are exposed to the surface of the second oxide film 3, and have contact surfaces to which a voltage is applied. Since the device is provided with buried semiconductors 21 to 23 having pure regions 21b to 23b, the parasitic capacitance in the passive element 10 can be adjusted by controlling the voltage applied to the high-concentration impurity regions 21b to 23b in response to changes in the parasitic capacitance in the passive element 10 due to changes in the film thickness of the second oxide film 3 directly below the passive element 10 caused by manufacturing variations, and deterioration of the characteristic impedance of the passive element 10 can be improved, resulting in improvement of deterioration of high-frequency characteristics in frequency bands of several tens of GHz, particularly above 100 GHz.

[0064] The semiconductor device of embodiment 1 does not require a special circuit to improve the degradation of the characteristic impedance of the passive element 10, and can improve the degradation of the characteristic impedance of the passive element 10 with a simple configuration in which an embedded semiconductor is placed directly under the passive element 10.

[0065] Furthermore, in the semiconductor device according to the first embodiment, by arranging a plurality of electrically independent embedded semiconductors spaced apart along the passive element 10 directly below the passive element 10, the degradation of the characteristic impedance in the plurality of regions 101 to 103 of the passive element 10 can be individually improved, and the degradation of the characteristic impedance can be improved for the entire passive element 10.

[0066] Furthermore, in the semiconductor device of embodiment 1, by arranging an electrically independent embedded semiconductor directly below each of the multiple passive elements 10, spaced apart along each of the passive elements 10, the parasitic capacitance in the passive elements 10 can be adjusted individually for each of the multiple passive elements, and the deterioration of the characteristic impedance in each of the passive elements 10 can be improved individually.

[0067] Second Embodiment A semiconductor device according to a second embodiment will be described with reference to Figures 5 and 6. The semiconductor device according to the second embodiment is a semiconductor device manufactured by a silicon-based semiconductor process technology applied to analog circuits or high-frequency circuits. The semiconductor device according to the second embodiment is applied to a semiconductor device in which an active circuit such as an amplifier circuit or oscillator that operates in a frequency band of several tens of GHz, particularly above 100 GHz, is formed.

[0068] The semiconductor device according to the second embodiment is suitable for operation in a frequency band of several tens of GHz, particularly above 100 GHz, and is provided with a transmission line whose characteristics can be dynamically changed. That is, the semiconductor device according to the second embodiment is a semiconductor device that is provided with a function of performing impedance adjustment with extremely little effect on passive elements that transmit signals, particularly in a frequency band above 100 GHz.

[0069] Fig. 5 is a cross-sectional view showing the characteristic features of the semiconductor device according to the second embodiment, and Fig. 6 is a perspective projection view. Also, Figs. 5 and 6 show one transmission line to explain the characteristic features, but the semiconductor device is not limited to having one transmission line but has multiple transmission lines formed therein, and also has multiple active elements such as MOS transistors formed therein. For each of the multiple transmission lines that handle high-frequency signals, the characteristic features are given to each transmission line in the same manner as shown in Figs. 5 and 6.

[0070] 5 and 6, the semiconductor device according to the second embodiment includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, a transmission line 11, a plurality of buried semiconductors 24 to 26, and a plurality of control voltage lines 34 to 36. A ground layer is formed on the back surface of the semiconductor substrate 1, and is set to a ground potential.

[0071] The transmission line 11 has a plurality of regions 104 to 106. The regions 104 to 106 in the transmission line 11 are not physically divided regions, but are virtually set regions in which the characteristic impedance of the transmission line 11 is independently controlled. In the second embodiment, three regions 104 to 106 in the transmission line 11 are shown, but the number is not limited to three and may be four or more. Furthermore, if the transmission line 11 is branched, the branch destination may be an additional region.

[0072] The first oxide film 2 is formed on the surface of the semiconductor substrate 1. In the second embodiment, the first oxide film 2 is a silicon oxide film. Buried regions in which a plurality of buried semiconductors 24 to 26 are buried are formed on the surface of the first oxide film 2 by grinding away the buried regions by etching or the like, and spaced apart from each other, directly below the respective regions 104 to 106 of the transmission line 11. Although not shown, MOS transistors and the like are formed in other regions on the surface of the first oxide film 2.

[0073] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surfaces of the plurality of buried semiconductors 24 to 26. The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and on the surfaces of each of the plurality of buried semiconductors 24 to 26. The second oxide film 3 has a plurality of wiring layers inside.

[0074] In the second oxide film 3, the silicon oxide film that is located below the transmission line 11, contacts the lower surface of the transmission line 11, and forms the interface between the surface of the first oxide film 2 and the surfaces of each of the plurality of buried semiconductors 24 to 26 is hereinafter referred to as the lowermost oxide film in the second oxide film 3. In the second embodiment, the design value of the film thickness of the lowermost oxide film in the second oxide film 3 is, for example, 200 nm. That is, the distance between the lower surface of the transmission line 11 and the surface of each of the plurality of buried semiconductors 24 to 26 is set to 200 nm.

[0075] The transmission line 11 is a line formed in the lowest wiring layer of multiple wiring layers arranged inside the second oxide film 3, and is a line made of a metal layer in the second embodiment. In the second embodiment, the transmission line 11 is, for example, a line having a width of 5 μm. In the second embodiment, the transmission line 11 is, for example, a signal line that transmits a high-frequency signal in a frequency band exceeding 100 GHz in an analog circuit, a high-frequency circuit, or an active circuit such as an amplifier circuit or oscillator.

[0076] The plurality of buried semiconductors 24-26 correspond to the plurality of regions 104-106 of the transmission line 11, respectively, and are buried in buried regions formed in the surface of the first oxide film 2 directly below the corresponding regions of the plurality of regions 104-106 of the transmission line 11. The plurality of buried semiconductors 24-26 are arranged spaced apart from each other.

[0077] The plurality of buried semiconductors 24 to 26 each include low-concentration impurity regions 24 a to 26 a that form interfaces with the second oxide film 3, and contact surfaces 24 b that are in contact with the bottom surfaces of the low-concentration impurity regions 24 a to 26 a and are exposed to the surface of the second oxide film 3, and to which voltages are applied independently of each other. １ ~26b １ Each of the high concentration impurity regions 24b to 26b has a virtual electrode region formed at the bottom thereof and a contact surface 24b at one end of the virtual electrode region. １ ~26b １ The contact area extends from the contact area to the virtual electrode area.

[0078] The surface of each of the plurality of buried semiconductors 24 to 26 is buried in a corresponding buried region formed in the surface of the first oxide film 2, and is therefore flush with the surface of the first oxide film 2, forming a flat surface together with the surface of the first oxide film 2. The plurality of buried semiconductors 24 to 26 are electrically insulated from each other by the first oxide film 2, and are electrically independent from each other. In the second embodiment, the thickness of each of the plurality of buried semiconductors 24 to 26 is, for example, 80 nm.

[0079] Although the low-concentration impurity regions 24a to 26a and the high-concentration impurity regions 24b to 26b in each of the plurality of buried semiconductors 24 to 26 are n-type impurity regions, they may be p-type impurity regions. Also, the low-concentration impurity regions 24a to 26a and the high-concentration impurity regions 24b to 26b of any of the plurality of buried semiconductors 24 to 26 may be n-type impurity regions, and the low-concentration impurity regions 24a to 26a and the high-concentration impurity regions 24b to 26b of the other buried semiconductors 24 to 26 may be p-type impurity regions.

[0080] Furthermore, a combination of an N-type impurity region and a P-type impurity region may be used as long as the combination is such that, when a voltage is applied to the high-concentration impurity regions 24b to 26b, a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of each of the plurality of buried semiconductors 24 to 26 by the applied voltage.

[0081] Each of the plurality of control voltage lines 34 to 36 is formed in a wiring layer disposed inside the second oxide film 3, and one end of each line is connected to a contact surface 24b of the high concentration impurity regions 24b to 26b of the corresponding buried semiconductors 24 to 26. １ ~26b １ and the other end is applied with a control voltage from a corresponding control voltage source 44 to 46.

[0082] In the region 104 of the transmission line 11 directly above the buried semiconductor 24, a capacitance C ４１ Further, a control voltage from a control voltage source 44 is applied to the contact surface 24b via a control voltage line 34. １ to the high-concentration impurity region 24b, a variable capacitance C ４２ The variable capacitance C ４２ The capacitance value can be adjusted by the voltage applied to the high concentration impurity region 24b.

[0083] Therefore, in the region 104 of the transmission line 11, there is a capacitance C ４１and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 24 and the virtual electrode region of the high-concentration impurity region 24b. ４２ A variable composite capacitance C ４０ [Capacitance value: C ４１ ×C ４２ / (C ４１ +C ４２ )] are connected.

[0084] That is, when the voltage applied to the high-concentration impurity region 24b is made higher than the voltage applied to the region 104 of the transmission line 11, the variable capacitance C ４２ The capacitance value of the variable composite capacitance C ４０ The capacitance value of the variable capacitance C decreases, and the characteristic impedance in the region 104 of the transmission line 11 can be increased. On the other hand, if the voltage applied to the high-concentration impurity region 24b is made lower than the voltage in the region 104 of the transmission line 11, the variable capacitance C ４２ The capacitance value of the variable composite capacitance C ４０ The capacitance value of the transmission line 11 is increased, and the characteristic impedance in the region 104 can be reduced.

[0085] In this way, by controlling the voltage applied to the high-concentration impurity region 24b, the characteristic impedance in the region 104 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed. ４０ The capacitance value of the capacitance C ４１ and variable capacitance C ４２ A variable composite capacitance C ４０ The capacitance value [C ４１ ×C ４２ / (C ４１ +C ４２ ) is the variable capacitance C ４２ The parasitic capacitance C １１ The capacitance value can be adjusted up to

[0086] In addition, in the region 105 of the transmission line 11 immediately above the buried semiconductor 25, as in the region 104 of the transmission line 11 immediately above the buried semiconductor 24, the capacitance C ５１and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 25 and the virtual electrode region of the high-concentration impurity region 25b. ５２ A variable composite capacitance C ５０ [Capacitance value: C ５１ ×C ５２ / (C ５１ +C ５２ Therefore, by controlling the voltage applied to the high-concentration impurity region 25b, the characteristic impedance in the region 105 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed.

[0087] Furthermore, in the region 106 of the transmission line 11 immediately above the buried semiconductor 26, as in the region 104 of the transmission line 11 immediately above the buried semiconductor 24, the capacitance C ６１ and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 26 and the virtual electrode region of the high-concentration impurity region 26b. ６２ A variable composite capacitance C ６０ [Capacitance value: C ６１ ×C ６２ / (C ６１ +C ６２ Therefore, by controlling the voltage applied to the high-concentration impurity region 26b, the characteristic impedance in the region 106 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed.

[0088] Since the multiple buried semiconductors 24 to 26 are electrically insulated from each other by the first oxide film 2 and are electrically independent from each other, the voltage applied to the high-concentration impurity regions 24 b to 26 b in each of the multiple buried semiconductors 24 to 26 can also be controlled independently, and the characteristic impedance in the multiple regions 104 to 106 of the transmission line 11 can be dynamically controlled.

[0089] For example, in three adjacent regions 104 to 106 of the transmission line 11, a voltage higher than the voltage in the central region 105 of the transmission line 11 is applied to the high-concentration impurity region 25b of the buried semiconductor 25 corresponding to the central region 105 of the three regions 104 to 106, thereby increasing the characteristic impedance in the region 105 of the transmission line 11, and a voltage lower than the voltage in the corresponding regions 104, 106 of the regions 104, 106 on both sides of the transmission line 11 is applied to the high-concentration impurity regions 24b, 26b of the buried semiconductors 24, 26 corresponding to the regions 104, 106 on both sides of the transmission line 11, thereby decreasing the characteristic impedance in the regions 104, 106 of the transmission line 11.

[0090] In this way, by increasing the characteristic impedance in the central region 105 of the transmission line 11 and decreasing the characteristic impedance in the regions 104 and 106 on both sides, a mismatch in the characteristic impedance occurs between the regions 105 and 104 of the transmission line 11 and between the regions 105 and 106, causing reflections of high-frequency signals passing through the transmission line 11 and attenuating the high-frequency signals.

[0091] On the other hand, by controlling the voltage applied to the high-concentration impurity regions 24b to 26b in each of the multiple buried semiconductors 24 to 26 and making the characteristic impedances in the regions 104 to 106 of the transmission line 11 the same, high-frequency signals passing through the transmission line 11 pass through the regions 104 to 106 of the transmission line 11 without attenuation.

[0092] In addition, in the three adjacent regions 104 to 106 of the transmission line 11, a voltage lower than the voltage in the central region 105 of the transmission line 11 may be applied to the high-concentration impurity region 25 b of the buried semiconductor 25 corresponding to the central region 105 of the three regions 104 to 106, thereby lowering the characteristic impedance in the region 105 of the transmission line 11, and a voltage higher than the voltage in the corresponding regions 104, 106 of the regions 104, 106 on both sides of the transmission line 11 may be applied to the high-concentration impurity regions 24 b, 26 b of the buried semiconductors 24, 26 corresponding to the regions 104, 106 on both sides of the transmission line 11, thereby raising the characteristic impedance in the regions 104, 106 of the transmission line 11, thereby causing a mismatch in the characteristic impedance.

[0093] As described above, the semiconductor device according to the second embodiment has a plurality of buried semiconductors 24 to 26 arranged in correspondence with a plurality of regions of the transmission line 11, with respect to the transmission line 11 formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1. Each of the buried semiconductors 24 to 26 is buried in the surface of the first oxide film 2 immediately below the corresponding region of the transmission line 11, and is equipped with low-concentration impurity regions 24 a to 26 a that form an interface with the back surface of the second oxide film 3, and high-concentration impurity regions 24 b to 26 b that are in contact with the bottom surfaces of the low-concentration impurity regions 24 a to 26 a and are exposed to the surface of the second oxide film 3, and have contact surfaces to which a voltage is applied. Therefore, the characteristic impedance in the plurality of regions of the transmission line 11 can be independently and dynamically changed by controlling the voltage applied to the high-concentration impurity regions 24 b to 26 b. As a result, it is possible to arbitrarily select between generating a mismatch in characteristic impedance within the transmission line 11 to attenuate high-frequency signals passing through the transmission line 10, or matching the characteristic impedance to allow the signals to pass without attenuation.

[0094] Third Embodiment A semiconductor device according to a third embodiment will be described with reference to Figures 7 to 9. The semiconductor device according to the third embodiment is a semiconductor device manufactured by silicon-based semiconductor process technology applied to analog circuits or high-frequency circuits. The semiconductor device according to the third embodiment is applied to semiconductor devices in which active circuits such as amplifier circuits or oscillators that operate in frequency bands of several tens of GHz, particularly above 100 GHz, are formed. The semiconductor device according to the third embodiment is a semiconductor device that is given the function of being used as a variable circuit that actively changes the characteristics with extremely little effect on passive elements that transmit signals, particularly in frequency bands above 100 GHz.

[0095] The semiconductor device according to the third embodiment is a semiconductor device including a variable resonator configured with an interdigital capacitor suitable for operation at a frequency band of several tens of GHz, particularly over 100 GHz, and even at high frequencies in the terahertz range. Fig. 7 is a cross-sectional view showing the characteristics of the semiconductor device according to the third embodiment. Fig. 7 also shows a portion of a pair of electrodes of the interdigital capacitor in order to explain the characteristics. The semiconductor device also includes a plurality of active elements such as MOS transistors.

[0096] As shown in Fig. 7, the semiconductor device according to the third embodiment includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, an interdigital capacitor 50, an embedded semiconductor 27, and a control voltage line 37. A ground layer is formed on the back surface of the semiconductor substrate 1, and is set to a ground potential. The interdigital capacitor 50 is a capacitor in which a pair of comb-shaped electrodes 51, 52 are formed on the same plane. Fig. 7 shows a wiring layer that constitutes some of the electrode portions of the pair of electrodes 51, 52 of the interdigital capacitor 50 that are arranged opposite each other.

[0097] The first oxide film 2 is formed on the surface of the semiconductor substrate 1. In the first embodiment, the first oxide film 2 is a silicon oxide film. A buried region in which a buried semiconductor 27 is buried is formed on the surface of the first oxide film 2 by grinding by etching or the like, directly below two lines arranged opposite each other in a pair of electrodes 51, 52 of the interdigital capacitor 50, so as to straddle the two lines. Although not shown, a MOS transistor and the like are formed in another region on the surface of the first oxide film 2.

[0098] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surface of the buried semiconductor 27. The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and on the surface of the buried semiconductor 27. The second oxide film 3 has a plurality of wiring layers inside.

[0099] In the second oxide film 3, the silicon oxide film that is located below the pair of electrodes 51, 52 of the interdigital capacitor 50, contacts the lower surfaces of the pair of electrodes 51, 52 of the interdigital capacitor 50, and forms the interface between the surface of the first oxide film 2 and the surface of the buried semiconductor 27 is hereinafter referred to as the lowermost oxide film in the second oxide film 3. In the third embodiment, the design value of the film thickness of the lowermost oxide film in the second oxide film 3 is, for example, 200 nm. That is, the distance between the lower surfaces of the pair of electrodes 51, 52 of the interdigital capacitor 50 and the surface of the buried semiconductor 27 is set to 200 nm.

[0100] A pair of electrodes 51 and 52 of the interdigital capacitor 50 are formed in the lowest wiring layer among a plurality of wiring layers arranged inside the second oxide film 3, and are made of a metal layer in the third embodiment. A capacitance C ０ In order to avoid complication of explanation, some of the electrode portions of the pair of electrodes 51 and 52 of the interdigital capacitor 50 shown in FIG.

[0101] The buried semiconductor 27 is buried in a buried region formed on the surface of the first oxide film 2 so as to straddle the pair of electrodes 51, 52 of the interdigital capacitor 50. That is, the buried semiconductor 27 is perpendicular to the opposing surfaces of the pair of electrodes 51, 52 and is provided continuously from a region 107 directly under one electrode 51 to a region 108 directly under the other electrode 52.

[0102] The buried semiconductor 27 includes a low-concentration impurity region 27 a that forms an interface with the second oxide film 3, and a contact surface 27 b that is in contact with the bottom surface of the low-concentration impurity region 27 a and is exposed to the surface of the second oxide film 3, to which a voltage is applied independently. １ The high concentration impurity regions 27b each have a virtual electrode region formed at the bottom thereof and a contact surface 27b at one end of the virtual electrode region. １ The contact area extends from the contact area to the virtual electrode area.

[0103] The surface of the buried semiconductor 27 is buried in the buried region formed in the surface of the first oxide film 2, and is therefore flush with the surface of the first oxide film 2, forming a flat surface together with the surface of the first oxide film 2. In the second embodiment, the thickness of the buried semiconductor 27 is, for example, 80 nm.

[0104] The low concentration impurity region 27a and the high concentration impurity region 276b of the buried semiconductor 27 may be p-type impurity regions. Furthermore, a combination of an n-type impurity region and a p-type impurity region may be used as long as a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 by the applied voltage when a voltage is applied to the high concentration impurity region 27b in the buried semiconductor 27. The buried semiconductor 27 is formed in a wiring layer arranged inside the second oxide film 3, and one end of the buried semiconductor 27 is in contact with the contact surface 27b of the high concentration impurity region 27b in the buried semiconductor 27. １ The other end is in ohmic contact with the control voltage source 47 .

[0105] A first capacitance C is formed between one electrode 51 and the surface of the buried semiconductor 27. ７１ Further, a control voltage from a control voltage source 47 is applied to the contact surface 27b via a control voltage line 37. １ to the high-concentration impurity region 27 b, a first variable capacitance C ７２ This occurs.

[0106] First variable capacitance C ７２ The capacitance value of the first capacitance C between the one electrode 51 and the buried semiconductor 27 can be adjusted by the voltage applied to the high concentration impurity region 27b. ７１ and a first variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 and the virtual electrode region of the high-concentration impurity region 27b. ７２ are connected in series.

[0107] A second capacitance C is formed between the other electrode 52 and the surface of the buried semiconductor 27. ８１ Further, a control voltage from a control voltage source 47 is applied to the contact surface 27b via a control voltage line 37. １ By applying a voltage from the high-concentration impurity region 27b to the low-concentration impurity region 24a, a depletion layer is spread in the low-concentration impurity region 24a, and in the region 108 directly under the other electrode 51, a second variable capacitance C ８２ This occurs.

[0108] Second variable capacitance C ８２ The capacitance value of the second capacitance C between the other electrode 51 and the buried semiconductor 27 can be adjusted by the voltage applied to the high concentration impurity region 27b. ８１ and a second variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 and the virtual electrode region of the high-concentration impurity region 27b. ８２ are connected in series.

[0109] The interdigital capacitor 50 and the first capacitance C present on one electrode 51 ７１ and the first variable capacitance C ７２ and a second capacitance C present on the other electrode 51. ８１ and the second variable capacitance C ８２ The electronic circuit shown in Fig. 8 is an equivalent circuit diagram. The electronic circuit shown in the equivalent circuit diagram in Fig. 8 is a circuit diagram of a capacitance C formed between a pair of electrodes 51 and 52 of an interdigital capacitor 50. ０ and capacitance C ０ and a first capacitance C connected in series between one electrode 51 and the control voltage source 47. ７１ and the first variable capacitance C ７２ and a second capacitance C connected in series between the other electrode 51 and the control voltage source 47. ８１ and the second variable capacitance C ８２ The circuit is composed of the following.

[0110] In the equivalent circuit diagram of FIG. ０The inductance L connected in series with the inductance L is an inductance that exists parasitically in the pair of comb-shaped electrodes 51 and 52 of the interdigital capacitor 50. In the equivalent circuit diagram of FIG. 8, the inductance L is expressed as a capacitance C ０ are connected in series, and are shown as a single inductance L for convenience.

[0111] 8, the electronic circuit shown in FIG. 8 constitutes a variable resonator, which is an LC resonator with a series-parallel resonant circuit structure. When the control voltage from the control voltage source 47 is controlled and the voltage applied to the high-concentration impurity region 27b via the control voltage line 37 is controlled, the first variable capacitance C ７２ and the second capacitance C ８１ Since the capacitance value of the variable resonator changes, the resonant frequency of the variable resonator varies.

[0112] An example of the fluctuation of the resonant frequency of the variable resonator shown as an equivalent circuit diagram in Fig. 8 will be described with reference to Fig. 9. In Fig. 9, the horizontal axis represents frequency and the vertical axis represents inductance. The variable resonator has a capacitive resonant frequency as shown by the dashed line A in Fig. 9. The variable resonator has a capacitance C and an inductance L as shown by the dashed line B in Fig. 9. ０ and the first capacitance C ７１ and the first variable capacitance C ７２ and the second capacitance C ８１ and the second variable capacitance C ８２ has an inductive resonant frequency due to the combined capacitance connected in series.

[0113] When a voltage higher than the voltage at the pair of electrodes 51 and 52 of the interdigital capacitor 50 is applied to the heavily doped region 27 b of the buried semiconductor 27 by a control voltage from the control voltage source 47, and the spread of the depletion layer in the lightly doped region 27 a of the buried semiconductor 27 is maximized, the first variable capacitance C ７２ and the capacitance value of the second variable capacitance C ８２ The capacitance value of the first capacitance C ７１ and the first variable capacitance C ７２ and the second capacitance C ８１ and the second variable capacitance C ８２The capacitance value of the combined capacitance of the series-connected capacitors is minimum. At this time, the inductive self-resonant frequency of the variable resonator is maximum, as shown by the dashed line C in FIG.

[0114] On the other hand, when a voltage lower than the voltage at the pair of electrodes 51, 52 of the interdigital capacitor 50 is applied to the high concentration impurity region 27b of the buried semiconductor 27 by a control voltage from the control voltage source 47, a charge storage region is formed at the interface between the surface of the buried semiconductor 27 and the bottom surface of the second oxide film 3, and the first variable capacitance C ７２ and the second variable capacitance C ８２ is short-circuited, the first capacitance C ７１ and the second capacitance C ８１ The capacitance value of the combined capacitance of the series-connected capacitors is maximum. At this time, the inductive self-resonant frequency of the variable resonator is minimum, as shown by the dashed line B in FIG. 9.

[0115] Therefore, in the semiconductor device according to the third embodiment, the resonant frequency of the variable resonator shown as an equivalent circuit diagram in FIG. 8 can be changed from the minimum resonant frequency indicated by the dashed line B to the maximum resonant frequency indicated by the dashed line C, as shown in FIG. 9, by controlling the voltage applied to the high-concentration impurity region 27 b in the buried semiconductor 27.

[0116] As described above, the semiconductor device according to the third embodiment has the buried semiconductor 27 disposed corresponding to the pair of electrodes 51, 52 constituting a capacitor formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1, and the buried semiconductor 27 is buried in the surface of the first oxide film 2 directly below the pair of electrodes 51, 52, and is equipped with the low-concentration impurity region 27 a which forms an interface with the back surface of the second oxide film 3, and the high-concentration impurity region 27 b which is in contact with the bottom surface of the low-concentration impurity region 27 a and is exposed to the surface of the second oxide film 3 and has a contact surface to which a voltage is applied. Therefore, with a simple configuration in which the buried semiconductor 27 is disposed directly below the pair of electrodes 51, 52 constituting a capacitor, a small variable resonator which operates in a frequency band of several tens of GHz, particularly in a frequency band exceeding 100 GHz, and further in a high frequency band of terahertz can be realized.

[0117] Fourth Embodiment A semiconductor device according to a fourth embodiment will be described with reference to FIG. 10 . The semiconductor device according to the fourth embodiment is a semiconductor device manufactured by silicon-based semiconductor process technology applied to analog circuits or high-frequency circuits. The semiconductor device according to the fourth embodiment is a semiconductor device incorporating a variable frequency oscillator circuit that operates in a frequency band of several tens of GHz, particularly above 100 GHz. The semiconductor device according to the fourth embodiment is a semiconductor device that is provided with a function that allows it to be used as a variable frequency oscillator circuit that actively changes characteristics with extremely little effect on passive elements that transmit signals, particularly in a frequency band above 100 GHz.

[0118] The semiconductor device according to the fourth embodiment is a semiconductor device incorporating an oscillation circuit with a variable resonator, which is the LC resonator in the semiconductor device according to the third embodiment, as a load, that is, a so-called cross-coupled LC resonator loaded oscillation circuit. As shown in the circuit diagram of Fig. 10 which represents the variable resonator as a load by an equivalent circuit, the semiconductor device according to the fourth embodiment incorporates a cross-coupled LC resonator loaded oscillation circuit including first to fourth MOS transistors 61 to 64 which are cross-coupled, a current source 66, and the variable resonator 500 in the semiconductor device according to the third embodiment.

[0119] As explained in the third embodiment, the variable resonator 500 includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, an interdigital capacitor 50, an embedded semiconductor 27, and a control voltage line 37. The variable resonator 500 includes a capacitance C ０ and capacitance C ０ and a first capacitance C connected in series between one electrode 51 and the control voltage source 47. ７１ and the first variable capacitance C ７２ and a second capacitance C connected in series between the other electrode 51 and the control voltage source 47. ８１ and the second variable capacitance C ８２ It consists of

[0120] The resonant frequency of the variable resonator 500 can be changed by a control voltage from a control voltage source 47 that is applied via a control voltage line 37 to the high-concentration impurity region 27b in the buried semiconductor 27. In the variable resonator 500, one electrode 51 of the interdigital capacitor 50 is connected to a first output node 67, and the other electrode 52 of the interdigital capacitor 50 is connected to a second output node 68.

[0121] The first to fourth MOS transistors 61 to 64 are formed on the surface of the first oxide film 2. The first MOS transistor 61 is a P-type transistor connected between a power supply node 65 and a first output node 67, and has a gate electrode connected to a second output node 68. The source electrode of the first MOS transistor 61 is connected to the power supply node 65, and the drain electrode of the first MOS transistor 61 is connected to the first output node 67.

[0122] The second MOS transistor 62 is an N-type transistor connected between the first output node 67 and the current sinking end of the current source 66, and has a gate electrode connected to the second output node 68. The source electrode of the second MOS transistor 62 is connected to the current sinking end of the current source 66, and the drain electrode of the second MOS transistor 62 is connected to the first output node 67.

[0123] The third MOS transistor 63 is a P-type transistor connected between the power supply node 65 and the second output node 68, and has a gate electrode connected to the first output node 67. The source electrode of the third MOS transistor 63 is connected to the power supply node 65, and the drain electrode of the third MOS transistor 63 is connected to the second output node 68.

[0124] The fourth MOS transistor 64 is an N-type transistor connected between the second output node 68 and the current sinking end of the current source 66, and has a gate electrode connected to the first output node 67. The source electrode of the fourth MOS transistor 64 is connected to the current sinking end of the current source 66, and the drain electrode of the fourth MOS transistor 64 is connected to the second output node 68.

[0125] The current source 66 is a constant current source that draws current from the cross-coupled first to fourth MOS transistors 61 to 64 to the ground node. The cross-coupled first to fourth MOS transistors 61 to 64 are configured as a differential pair by the current source 66.

[0126] By controlling the voltage applied to the high concentration impurity region 27b in the buried semiconductor 27 that constitutes the variable resonator 500, the first variable capacitance C ７２ and the capacitance value of the second variable capacitance C ８２ Since the capacitance value of can be set to the lower side, the resonance frequency of the variable resonator 500 can be made variable, and as a result, the oscillation frequency of the cross-coupled LC resonator loaded oscillation circuit can be made variable.

[0127] As described above, the semiconductor device according to the fourth embodiment has the buried semiconductor 27 disposed corresponding to the pair of electrodes 51, 52 constituting a capacitor formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1, the buried semiconductor 27 being buried in the surface of the first oxide film 2 directly below the pair of electrodes 51, 52, and using as a load the variable resonator 500 having the following configuration: a low-concentration impurity region 27 a which forms an interface with the rear surface of the second oxide film 3; and a high-concentration impurity region 27 b which is in contact with the bottom surface of the low-concentration impurity region 27 a and is exposed to the surface of the second oxide film 3 and has a contact surface to which a voltage is applied. Therefore, with the simple configuration of disposing the buried semiconductor 27 directly below the pair of electrodes 51, 52 constituting the capacitor, the variable resonator 500 which serves as a load can be realized, and the variable resonator 500 can be miniaturized even as a frequency variable oscillator circuit which operates in a frequency band of several tens of GHz, particularly in a frequency band exceeding 100 GHz, and further in a high frequency band of terahertz.

[0128] It should be noted that the embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted.

[0129] The semiconductor device according to the present disclosure is applicable to semiconductor devices manufactured by silicon-based semiconductor process technology applied to analog circuits or high-frequency circuits, and is suitable for semiconductor devices in which active circuits such as amplifier circuits or oscillators operating in a frequency band of several tens of GHz, particularly above 100 GHz, are formed.

[0130] 1 semiconductor substrate, 2 first oxide film, 3 second oxide film, 10 passive element, 11 transmission line, 21 first buried semiconductor, 22 second buried semiconductor, 23 third buried semiconductor, 24 to 26 buried semiconductor, 27 buried semiconductor, 31 first control voltage line, 32 second control voltage line, 33 third control voltage line, 34 to 36 control voltage line, 37 control voltage line, 50 interdigital capacitor, 51, 52 electrodes, 61 to 64 first to fourth MOS transistors, 65 power supply node, 66 current source.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on the surface of the first oxide film; a passive element formed inside the second oxide film; and a buried semiconductor including: a low concentration impurity region embedded in the surface of the first oxide film directly below the passive element and forming an interface with a back surface of the second oxide film; and a high concentration impurity region bonded to a bottom surface of the low concentration impurity region and exposed to the surface of the second oxide film, the high concentration impurity region having a contact surface to which a voltage is applied.

2. The semiconductor device according to claim 1, wherein the passive elements are either a transmission line, a resistor, a capacitor, or an inductor arranged parallel to the surface of the semiconductor substrate, the low concentration impurity region is a region doped with a low concentration of N-type impurities, and the high concentration impurity region is a region doped with a high concentration of N-type impurities.

3. The semiconductor device according to claim 2, wherein the buried semiconductor comprises a plurality of buried semiconductors formed at intervals along the passive element.

4. The semiconductor device according to claim 1, wherein the passive element comprises a plurality of passive elements, and the embedded semiconductor comprises a plurality of embedded semiconductors corresponding to the plurality of passive elements, respectively.

5. A semiconductor device comprising: a semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on the surface of the first oxide film; a transmission line formed inside the second oxide film and having a plurality of regions; and a plurality of embedded semiconductors each including: a low concentration impurity region, each corresponding to a plurality of regions of the transmission line, embedded in the surface of the first oxide film directly below the corresponding region of the transmission line and forming an interface with a rear surface of the second oxide film; and a high concentration impurity region joined to a bottom surface of the low concentration impurity region, exposed to the surface of the second oxide film, and having a contact surface to which a voltage is applied independently of each other.

6. The semiconductor device according to claim 5, wherein in three adjacent regions of said plurality of buried semiconductors, one of a voltage higher or lower than the voltage in the central region of said transmission line is applied to a high concentration impurity region of said buried semiconductor corresponding to a central region of said three regions, and the other of a voltage higher or lower than the voltage in the corresponding region on either side of said transmission line is applied to high concentration impurity regions of said buried semiconductor corresponding to regions on both sides of said three regions.

7. A semiconductor device comprising: a semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on the surface of the first oxide film; a pair of electrodes forming a capacitor formed in the same conductive layer inside the second oxide film; and a buried semiconductor including: a low concentration impurity region embedded in the surface of the first oxide film directly below the pair of electrodes and forming an interface with a rear surface of the second oxide film; and a high concentration impurity region joined to a bottom surface of the low concentration impurity region and exposed to the surface of the second oxide film, the high concentration impurity region having a contact surface to which a voltage is applied.

8. The semiconductor device according to claim 7, wherein a variable resonator is formed by: a capacitance formed between a pair of electrodes of the capacitor and an inductance connected in series to the capacitance; a first capacitance connected to one of the pair of electrodes of the capacitor between the one electrode and a surface of the buried semiconductor, and a first variable capacitance connected in series to the first capacitance between the surface of the buried semiconductor and a high-concentration impurity region arranged opposite the one electrode of the buried semiconductor; a second capacitance connected to the other electrode of the pair of electrodes of the capacitor between the other electrode and the surface of the buried semiconductor, and a second variable capacitance connected in series to the second capacitance between the surface of the buried semiconductor and a high-concentration impurity region arranged opposite the other electrode of the buried semiconductor.

9. The semiconductor device according to claim 7, wherein the capacitor is an interdigital capacitor, and a variable resonator is formed by: a capacitance formed between a pair of electrodes of the capacitor, and an inductance parasitically present in the pair of electrodes connected in series to the capacitance; a first capacitance connected to one of the pair of electrodes of the capacitor between the one electrode and a surface of the buried semiconductor, and a first variable capacitance between the surface of the buried semiconductor connected in series to the first capacitance and a high-concentration impurity region arranged opposite the one electrode of the buried semiconductor; a second capacitance connected to the other electrode of the pair of electrodes of the capacitor between the other electrode and the surface of the buried semiconductor, and a second variable capacitance between the surface of the buried semiconductor connected in series to the second capacitance and a high-concentration impurity region arranged opposite the other electrode of the buried semiconductor.

10. A semiconductor device comprising a variable frequency oscillator circuit using the variable resonator in the semiconductor device according to claim 8 or 9 as a load.

11. The semiconductor device according to claim 10, comprising: a first MOS transistor connected between a power supply node and a first output node, and having a gate electrode connected to a second output node; a second MOS transistor connected between the first output node and a current sinking end of a current source, and having a gate electrode connected to the second output node; a third MOS transistor connected between the power supply node and the second output node, and having a gate electrode connected to the first output node; and a fourth MOS transistor connected between the second output node and the current sinking end of the current source, and having a gate electrode connected to the first output node, wherein a capacitor in the variable resonator has one electrode connected to the first output node and the other electrode connected to the second output node.

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