General-purpose control board

Abstract

In order to allow efficient production of a product even when a component mounted on a printed board unique to the product is changed to an alternative component, a general-purpose control board comprises a core module 10 and an extension module 20. A CPU 11 of the core module 10 has a program for realizing a cumulative specification necessary for control of a plurality of products assumed in advance. FPGAs mounted on the core module 10 and the extension module 20 have mounted thereon a plurality of function logics for controlling sensor circuits 32 and motor circuits 33, of a plurality of makers, which are mounted for each device. The CPU 11 automatically determines which maker's sensor circuit 32 and / or motor circuit 33 is mounted, and notifies an FPGA 12 and an FPGA 21 of the determination result, thereby selecting and using one of the plurality of function logics mounted on the FPGA 12 and the FPGA 21.

Description

General-purpose control board

[0001] The present disclosure relates to a general-purpose control board that can accommodate changes in components mounted on a product-specific printed circuit board.

[0002] Conventionally, there are known techniques that enable the use of substitute parts when the production of a component is discontinued without the need to select a compatible part or design and manufacture a substitute part. For example, Patent Document 1 discloses a conversion adapter equipped with a programmable element such as an FPGA (Field Programmable Gate Array) as a compatible part, which allows users to freely configure circuits. The programmable element has pre-programmed functional logic corresponding to each of multiple types of electronic components. When electronic components on an existing board become unavailable due to discontinuation of production or other reasons, a substitute part for the discontinued part can be realized by emulating the function of the discontinued part using the programmable element.

[0003] Patent Publication No. 4717554

[0004] However, the technology of Patent Document 1 is a technology that enables the construction of substitute components for electronic components such as ICs and memories mounted on printed circuit boards when the production of those components is discontinued.In addition to electronic components such as ICs and memories, products also include processors that control the entire product and programmable elements that control the ICs, etc., and there is a problem that it is not possible to respond if these processors and programmable elements become unavailable.

[0005] The present disclosure has been made in consideration of the problems with the above-mentioned conventional technology, and one of its purposes is to provide a general-purpose control board that allows products to be manufactured efficiently even when components mounted on a product-specific printed circuit board are replaced with alternative components.

[0006] The general-purpose control board of the present disclosure is a general-purpose control board that can be implemented in either a first specific board incorporated in a first device or a second specific board incorporated in a second device, and is equipped with a processor that controls the device by executing a first application that controls the user interface of the device and realizes the functions of the device, and a programmable element that implements a second application that operates the specific board based on the first application executed by the processor.

[0007] The above configuration may further include a first substrate including the processor and a first programmable element, and a second substrate including a second programmable element connected to the first programmable element.

[0008] In the above configuration, the first board and the second board may be connected using a serial I / O interface.

[0009] In the above configuration, the first board and the second board may encrypt data before communicating with each other.

[0010] In the aforementioned configuration, the first application may be changeable only from a first control device, and the second application may be changeable from both the first control device and a second control device.

[0011] In the above configuration, the device may be a valuable medium processing device that processes valuable media.

[0012] In the above configuration, the valuable medium processing device may include a plurality of sensors and / or a plurality of motors used in processing the valuable medium, and the plurality of sensors and / or the plurality of motors may be electrically connected to the programmable element.

[0013] In the above configuration, the plurality of sensors and / or the plurality of motors may be electrically connected to the processor via the programmable element.

[0014] In the above configuration, the valuable medium processing device may further include a safe, and the specific board on which the general-purpose control board is mounted may be stored inside the safe.

[0015] According to the present disclosure, it is possible to provide a general-purpose control board that allows efficient manufacturing of products even when components mounted on a product-specific printed circuit board are replaced with alternative components.

[0016] FIG. 1 is a diagram illustrating an overview of a general-purpose control board according to an embodiment. FIG. 2 is a diagram illustrating an example of a valuable medium processing device on which the base board shown in FIG. 1 is implemented. FIG. 3 is a diagram illustrating an overview of an implementation form of a general-purpose control board and a base board in a valuable medium processing device. FIG. 4 is a diagram illustrating another configuration example of a core module. FIG. 5 is a diagram illustrating an example configuration of a program implemented in the core module and an example configuration of FPGA function implementation. FIG. 6 is a diagram illustrating an example configuration of an expansion module. FIG. 7 is a diagram illustrating an implementation example of a base board that uses only the core module. FIG. 8 is a diagram illustrating an implementation example of a core module and an expansion module. FIG. 9 is a diagram illustrating another implementation example of a core module and an expansion module. FIG. 10 is a diagram illustrating an overview of an implementation example that ensures security in a valuable medium processing device.

[0017] The general-purpose control board according to the present disclosure will be described in detail below with reference to the drawings.

[0018] <Overview of General-Purpose Control Board> An overview of the general-purpose control board according to this embodiment will be described. Fig. 1 is a diagram for explaining the overview of the general-purpose control board according to this embodiment. The core module 10 shown in Fig. 1 is the general-purpose control board referred to in this embodiment. The general-purpose control board may include an expansion module 20.

[0019] The core module 10 has a CPU 11 that controls the entire device on which the general-purpose control board is mounted, and an FPGA 12 that controls a plurality of sensor circuits 32 and a plurality of motor circuits 33 .

[0020] The expansion module 20 includes an FPGA 21 for expanding functionality by increasing the number of sensor circuits 32 and motor circuits 33 mounted. The core module 10 and expansion module 20 are mounted on a base substrate 30, which is developed for each product. The core module 10 and expansion module 20 are connected via a connection cable 13 or wiring formed on the base substrate 30. The core module 10 and expansion module 20 are connected using a serial I / O interface. Examples of the serial I / O interface include RS-232C, an unbalanced transmission method, RS-422, and LVDS (Low Voltage Differential Signaling), which are differential transmission methods. Control signals from the CPU 11 and sensor data from the FPGA 21 are transmitted between the core module 10 and the expansion module 20 using the serial I / O interface. In the core module 10, the CPU 11 and FPGA 12 are connected using the external bus interface of the CPU 11. The CPU 11 and FPGA 12 are connected using a parallel I / O interface. The FPGA 12 and FPGA 21 are also connected to the external sensor circuit 32 and motor circuit 33 using a parallel I / O interface.

[0021] The base substrate 30, which is developed for each product, includes a core module 10, an extension module 20, a communication circuit 31, a plurality of sensor circuits 32, a plurality of motor circuits 33, and a plurality of connectors 34a, 34b, 34c, 34d, and 34e (hereinafter, sometimes collectively referred to as "connectors 34"). The connectors 34 are used to connect devices such as sensors and motors.

[0022] The communication circuit 31 is a circuit for communicating with a management device or the like that manages the products. The sensor circuit 32 is connected to the connector 34 via wiring formed on the base substrate 30. The sensor circuit 32 is a circuit for receiving signals from a sensor connected to the connector 34. The motor circuit 33 is connected to the connector 34 via wiring formed on the base substrate 30. The motor circuit 33 is a circuit for driving a motor connected to the connector 34.

[0023] The core module 10 and the expansion module 20 are mounted on the base substrate 30 using connectors. For example, the core module 10 and the expansion module 20 may be surface-mounted on the base substrate 30 by providing surface-mount terminals (e.g., BGA (Ball Grid Array)) on the back surfaces of the core module 10 and the expansion module 20.

[0024] The control program of the CPU 11 implemented in the core module 10 includes a program for controlling a user interface and the like that is used in common among a plurality of products, and a program for realizing cumulative specifications required for controlling a plurality of types of products that are assumed in advance. Details of the control program will be described later.

[0025] The FPGA 12 mounted on the core module 10 and the FPGA 21 mounted on the expansion module 20 are equipped with multiple functional logics for controlling sensor circuits 32 and motor circuits 33 from multiple manufacturers. The functional logics are mounted on a base board 30 developed for each device. That is, when a device is developed, a base board 30 is prepared for the device on which a CPU 11 and at least one FPGA 12, 21 are detachably mounted. The FPGAs 12, 21 are pre-installed with functional logics corresponding to multiple types of external devices, such as sensors and motors, that may be used with the device. The CPU 11 automatically determines which manufacturer's sensor circuit 32 and / or motor circuit 33 are installed. The CPU 11 notifies the FPGAs 12 and 21 of the determination result, and one of the functional logics installed on the FPGAs 12 and 21 is selected. The determination of which manufacturer's sensor circuit 32 and / or motor circuit 33 is installed may be performed by implementing functional logic for automatic determination in the FPGA 12 and FPGA 21 .

[0026] As described above, the general-purpose control board according to this embodiment includes a core module 10 and an expansion module 20. The CPU 11 of the core module 10 can execute a program for controlling a user interface shared among multiple products and a program for implementing cumulative specifications required for controlling multiple products. The FPGA 12 implemented in the core module 10 and the FPGA 21 implemented in the expansion module 20 are each equipped with multiple functional logics for controlling multiple types of sensor circuits 32 and motor circuits 33 implemented on a base substrate 30, which is developed for each device. The CPU 11 automatically determines the type of the implemented sensor circuit 32 and / or motor circuit 33 and notifies the FPGA 12 and FPGA 21 of the determination result, thereby selecting one of the multiple functional logics implemented in the FPGA 12 and FPGA 21. Therefore, by using a general-purpose control board, products can be manufactured efficiently even when components implemented on a product-specific printed circuit board are replaced with alternative components. Specifically, even if the type of sensor circuit 32 mounted on the base substrate 30 is changed, for example, due to the sensor being changed to an alternative, the core module 10 and expansion module 20 that were previously in use can be attached to the changed base substrate 30 to achieve control of the alternative sensor.

[0027] The general-purpose control board can be shared by multiple devices. Therefore, by having a large inventory of general-purpose control boards, even if it becomes difficult to obtain the CPU 11, FPGA 12, and FPGA 21 mounted on the general-purpose control board, the impact on product manufacturing can be reduced.

[0028] <Outline of Valuable Medium Processing Device> An outline of the valuable medium processing device 40 will be described as an example of a device on which the base substrate 30 is mounted. Figure 2 is a perspective view of the exterior and a schematic diagram of the configuration of the valuable medium processing device 40 on which the base substrate 30 shown in Figure 1 is mounted.

[0029] The directions (front, back, left, right, up, down) used in the following explanation correspond to the directions when the valuable medium processing device 40 installed on a horizontal surface is viewed from the front. The front side of the valuable medium processing device 40 is the side where the deposit unit 51 and the withdrawal unit 52 are formed. The rear side of the valuable medium processing device 40 is the side opposite to the side where the deposit unit 51 and the withdrawal unit 52 are formed.

[0030] The valuable medium processing device 40 includes a processing unit 41 and a safe unit 42 . The processing unit 41 is provided above the safe unit 42 .

[0031] The processing unit 41 has a processing housing 41a and a processing movable unit 41b. The processing housing 41a is formed in the shape of a rectangular parallelepiped box that extends in the front-to-rear direction and is open to the front. The processing housing 41a houses the processing movable unit 41b. The processing movable unit 41b can be pulled out to the front from the processing housing 41a. The processing movable unit 41b has a deposit unit 51, a withdrawal unit 52, a recognition unit 53, and a processing side transport unit 60.

[0032] The deposit unit 51 is an input unit into which banknotes are inserted. The deposit unit 51 is provided at the front of the processing movable unit 41b. The deposit unit 51 has an upwardly opening deposit port 51a. An operator manually inserts banknotes into the deposit unit 51 through the deposit port 51a. The deposit unit 51 can hold multiple banknotes stacked one on top of another. The deposit unit 51 is provided with a feeding mechanism that feeds out the banknotes inserted into the deposit unit 51 one by one to the processing side transport unit 60.

[0033] The dispensing unit 52 is a dispensing unit from which banknotes are dispensed. The dispensing unit 52 is provided in front of the depositing unit 51 in the front part of the movable processing unit 41b. The dispensing unit 52 can hold multiple banknotes in a stacked state. An operator can manually remove banknotes stacked in the dispensing unit 52 through the dispensing port 52a. The dispensing unit 52 may be provided with a shutter that opens and closes the dispensing port 52a.

[0034] The recognition unit 53 recognizes banknotes. The recognition unit 53 is provided in the processing-side transport unit 60, and performs a recognition process on banknotes transported by the processing-side transport unit 60. In the recognition process, the recognition unit 53 recognizes the denomination of the banknote. The recognition unit 53 may also recognize fitness, newness, authenticity, transport status, serial numbers attached to the banknotes, etc. For example, the base substrate 30 is used by the recognition unit 53.

[0035] The processing-side transport unit 60 transports banknotes within the processing unit 41. The processing-side transport unit 60 transports banknotes so that multiple banknotes are consecutively spaced apart in the transport direction. The processing-side transport unit 60 transports banknotes so that the edge of the long side of the banknote is at the front in the transport direction. The processing-side transport unit 60 may also transport banknotes so that the edge of the short side of the banknote is at the front in the transport direction.

[0036] The processing-side conveying unit 60 has a conveying path. The conveying path is composed of a conveying mechanism for conveying banknotes, such as a conveying roller and a conveying belt, a guide member for guiding the conveyed banknotes, and a branching mechanism for switching the conveying direction of the banknotes, such as a branching claw. The processing-side conveying unit 60 has a driving mechanism, such as a motor and gears. The driving mechanism drives the conveying mechanism and branching mechanism of the conveying path. The conveying path of the processing-side conveying unit 60 is connected to the depositing unit 51, the dispensing unit 52, and the safe-side conveying unit 90, which will be described later.

[0037] The safe unit 42 has a safe housing 42a and a safe movable part 42b. The safe housing 42a is formed in the shape of a rectangular parallelepiped box extending in the front-to-rear direction. An openable and closable door 130 is provided at the front end of the safe housing 42a. The door 130 can be locked. For example, the door 130 is provided with an electronic lock. The safe housing 42a houses the safe movable part 42b. The protection level of the safe housing 42a is higher than the protection level of the processing housing 41a. Specifically, the safe housing 42a is made of a metal plate having a predetermined thickness or more. The safe movable part 42b can be pulled out toward the front. When the door 130 of the safe housing 42a is opened, the operator can pull the safe movable part 42b out toward the front from the safe housing 42a.

[0038] The safe movable unit 42b has a plurality of storage devices 71 and a safe-side transport unit 90. Each of the plurality of storage devices 71 stores banknotes. Each of the plurality of storage devices 71 feeds out the stored banknotes.

[0039] The safe-side transport unit 90 transports banknotes within the safe unit 42. The safe-side transport unit 90 transports the banknotes so that multiple banknotes are continuously spaced apart in the transport direction. The safe-side transport unit 90 transports the banknotes so that the edge of the long side of the banknote is at the front in the transport direction. The safe-side transport unit 90 may also transport the banknotes so that the edge of the short side of the banknote is at the front in the transport direction.

[0040] The safe-side transport unit 90 has a transport path. The transport path is composed of, for example, a transport mechanism for transporting banknotes, such as a transport roller and a transport belt, a guide member for guiding the transported banknotes, and a branching mechanism for switching the transport direction of the banknotes, such as a branching claw. The safe-side transport unit 90 has a drive mechanism, such as a motor and gears. The drive mechanism drives the transport mechanism and branching mechanism of the transport path.

[0041] The transport path of the safe-side transport unit 90 is connected to the processing-side transport unit 60 via a through-path provided in the upper wall of the safe housing 42a. The transport path of the safe-side transport unit 90 is also connected to a plurality of storage devices 71.

[0042] The valuable medium processing device 40 having the above-described configuration can perform various banknote processing operations, including banknote deposit and withdrawal processing, but the content of each banknote processing operation and the operation of each part during each banknote processing operation are conventionally known, so explanations will be omitted.

[0043] Next, an outline of the implementation of the general-purpose control board and base board 30 in the valuable medium processing device 40 will be described. Hereinafter, parts that are the same as those in the general-purpose control board and base board 30 shown in FIG. 1 will be given the same reference numerals, and detailed explanations thereof will be omitted.

[0044] 3 is a diagram showing an outline of the implementation of the general-purpose control board and base board 30 in the valuable medium processing device 40. While FIG. 1 shows an example in which the core module 10 and the extension module 20 are provided on the base board 30, as shown in FIG. 3, the core module 10 may be provided apart from the base board 30, i.e., separately from the base board 30.

[0045] 3, valuable medium processing device 40 includes core module 10, a general-purpose control board, a base board 30 developed for each device, and a mechanical mechanism M. Core module 10 includes a CPU 11, an FPGA 12, and a connector 15 for transmitting serial I / O signals, all of which are mounted on a printed circuit board.

[0046] The CPU 11 and FPGA 12 of the core module 10 are connected via wiring formed on a printed circuit board using an external bus interface of the CPU 11. The external bus interface of the CPU 11 transmits parallel I / O signals. The FPGA 12 is connected to a connector 15 via wiring formed on the printed circuit board. The FPGA 12 is connected to the connector 15 using a serial I / O interface. The core module 10 may be provided with connectors for connecting to a sensor circuit 32 and a motor circuit 33.

[0047] The base substrate 30 has an expansion module 20, a communication circuit 31, a plurality of sensor circuits 32, a plurality of motor circuits 33, and a plurality of connectors 34a, 34b, and 35. The expansion module 20 and the connector 35 are connected using a serial I / O interface via wiring formed on the base substrate 30. The expansion module 20, the communication circuit 31, the plurality of sensor circuits 32, and the plurality of motor circuits 33 are connected using a parallel I / O interface via wiring formed on the base substrate 30. The core module 10 and the base substrate 30 are connected using a serial I / O interface via a connector 15, a connection cable 13, and the connector 35.

[0048] The plurality of sensor circuits 32 and the connector 34 are connected using a parallel I / O interface via wiring formed on the base substrate 30. In the example shown in Fig. 3, the sensor circuit 32 is connected to two connectors 34a. The plurality of motor circuits 33 and the connector 34 are connected using a parallel I / O interface via wiring formed on the base substrate 30. In the example shown in Fig. 3, the motor circuit 33 is connected to two connectors 34b.

[0049] The mechanical mechanism M includes a plurality of sensors 200 and a plurality of motors 201. The plurality of sensors 200 include line sensors, magnetic sensors, image sensors, etc. that acquire data for identifying banknotes in the recognition unit 53 of the valuable medium processing device 40. The sensors 200 and the connector 34 of the base substrate 30 are connected using a parallel I / O interface via a connection cable 36. In the example shown in FIG. 3, the sensor 200 is connected to the connector 34a.

[0050] The multiple motors 201 include a motor that drives the conveyance mechanism of the conveyance paths of the processing-side conveyance unit 60 and the safe-side conveyance unit 90 of the valuable medium processing device 40, and a motor that drives the branching mechanism. The motors 201 and the connector 34 of the base substrate 30 are connected via a connection cable 36. In the example shown in Figure 3, the motor 201 is connected to the connector 34b.

[0051] Next, another example of the configuration of the core module 10 will be described. Fig. 4 is a diagram showing another example of the configuration of the core module 10. The same components as those in the core module 10 described in Fig. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. The core module 10 shown in Fig. 4 has a CPU 11, an FPGA 12, connectors 14a and 14b (hereinafter, sometimes collectively referred to as "connectors 14"), and a connector 15.

[0052] The core module 10 shown in Fig. 4 is equipped with connectors 14a and 14b that can be directly connected to a sensor circuit 32 and a motor circuit 33 provided on the base substrate 30. This makes it possible to use the core module 10 alone by connecting the sensor circuit 32 and the motor circuit 33 to the connectors 14. The FPGA 12 and the connectors 14a and 14b are connected using a parallel I / O interface via wiring formed on the core module 10. To connect to the expansion module 20, the FPGA 12 is connected to a connector 15 via wiring formed on the core module 10 using a serial I / O interface.

[0053] Next, we will explain an example of the configuration of a program implemented in the CPU 11 of the core module 10, and an example of the configuration of functional logic of the FPGA 12 of the core module 10 and the FPGA 21 of the extension module 20. Figure 5 is a diagram showing an example of the configuration of a program implemented in the core module 10 and an example of the configuration of functional implementation of the FPGAs 12 and 21.

[0054] As shown in FIG. 5( a), the programs for operating the CPU 11 of the core module 10 include an Application program 110 and a Board Support Package (BSP) program 111. The Application program 110 is a program that differs for each product. For example, the Application program includes a program related to the user interface of the product. The Board Support Package program 111 is a program that is used in common for each product. For example, the Board Support Package program 111 includes programs related to processes such as banknote identification processing that is performed in common by multiple types of valuable medium processing devices 40 and monitoring the transport status of the processing side transport unit 60 and the safe side transport unit 90.

[0055] The FPGA 12 mounted on the core module 10 and the FPGA 21 mounted on the extension module 20 are equipped with functional logic that controls the sensor circuit 32 and motor circuit 33 mounted on the base substrate 30. The functional logic that controls the motor circuit 33 will be described below as an example.

[0056] For example, it is assumed that one of three motors 201 from companies A, B, and C will be used as the motor 201 for the mechanical mechanism M. In this case, as shown in Figure 5(b), a functional logic 100 for controlling the motor 201 from company A, a functional logic 101 for controlling the motor 201 from company B, and a functional logic 102 for controlling the motor 201 from company C are implemented in advance in the FPGA 12.

[0057] The CPU 11 of the core module 10 determines which company's motor circuit 33, A to C, is mounted on the base substrate 30. The CPU 11 sends a selection signal based on the determination result via a selection signal line 104 to a selector 103 mounted on the FPGA 12. For example, an identification mechanism for identifying which company's motor 201 the motor circuit 33 corresponds to can be mounted on the base substrate 30 so that the CPU 11 can determine which company's motor circuit 33 is mounted on the base substrate 30.

[0058] Specifically, for example, a 2-bit DIP (Dual In-line Package) switch is mounted on the base substrate 30, and when the DIP switch is set to "00," it selects a motor circuit from company A, when the DIP switch is set to "01," it selects a motor circuit from company B, and when the DIP switch is set to "10," it selects a motor circuit from company C. When the CPU 11 is powered on, it reads the setting of this DIP switch and transmits a selection signal via a selection signal line 104 to a selector 103 mounted on the FPGA 12. Note that although the case where a DIP switch is used has been described here, a circuit for sending an identification signal may be previously mounted on the motor circuit 33.

[0059] The FPGA 12 sends a signal of the functional logic selected by the selector 103 to the connector 14a. For example, when the functional logic 100 is selected by the selector 103, the FPGA 12 sends a control signal corresponding to the functional logic 100 to the connector 14a. Note that the same function is implemented in the FPGA 21 of the extension module 20.

[0060] Next, a configuration example of the expansion module 20 will be described. Fig. 6 is a diagram showing a configuration example of the expansion module 20. As shown in Fig. 6, the expansion module 20 has an FPGA 21, connectors 22a, 22b, 22c, and 22d (hereinafter, sometimes collectively referred to as "connectors 22"), and connectors 23a and 23b. The FPGA 21 and the connector 22 are connected using a parallel I / O interface via wiring formed on a printed circuit board.

[0061] The FPGA 21 and a connector 23a for connecting to the core module 10 are connected using a serial I / O interface via wiring formed on the printed circuit board. The FPGA 21 and a connector 23b for connecting to another expansion module 20 are connected using a serial I / O interface via wiring formed on the printed circuit board.

[0062] The program for operating the CPU 11 and the functional logic of the FPGA 12 and FPGA 21 can be changed from an external device, and access control related to the changes can also be executed. Specifically, for example, the program for operating the CPU 11 of the core module 10 is access-controlled so that it can be changed only from a first management device used by the manufacturer of the valuable medium processing device 40. On the other hand, the functional logic of the FPGA 12 implemented in the core module 10 and the FPGA 21 implemented in the expansion module 20 may be access-controlled so that it can be changed not only from the first management device used by the manufacturer but also from a second management device used by a company other than the manufacturer.

[0063] For example, access control may be performed based on the IP addresses and / or MAC addresses of the first management device and the second management device.

[0064] While Fig. 3 shows an example in which both the core module 10 and the expansion module 20 are used, only the core module 10 may be used. An example of an implementation of a valuable medium processing device 40 that uses only the core module 10 will be described below. Note that parts similar to those in the implementation of the valuable medium processing device 40 shown in Fig. 3 are given the same reference numerals, and detailed descriptions thereof will be omitted. Fig. 7 is a diagram showing an implementation of a base substrate 30 that uses only the core module 10.

[0065] 7 includes a base substrate 30 on which a core module 10 is mounted, a plurality of sensors 200, and a plurality of motors 201. The base substrate 30 does not include an expansion module 20, and only the core module 10 is mounted on it.

[0066] The core module 10 is mounted on a base substrate 30 using connectors 14a, 14b, and 15. The FPGA 12, the communication circuit 31, the plurality of sensor circuits 32, and the plurality of motor circuits 33 are connected using a parallel I / O interface via connectors 14a, 14b, and wiring formed on the base substrate 30.

[0067] A signal from the sensor 200 is transmitted to the CPU 11 of the core module 10 via the connection cable 36, the connector 34a, the sensor circuit 32, the connector 14a or 14b, and the FPGA 12. The CPU 11 uses the transmitted signal to execute a banknote recognition process. The CPU 11 also controls the motor 201 via the FPGA 12, the connector 14a or 14b, the motor circuit 33, the connector 34b, and the connection cable 36.

[0068] Next, an example will be described in which a general-purpose control board is installed in a valuable medium processing device 40 that controls a larger number of sensors 200 and motors 201. Note that parts that are the same as those in the example of installation in the valuable medium processing device 40 shown in Figure 7 are given the same reference numerals, and detailed explanations thereof will be omitted. Figure 8 is a diagram showing an installation form of the core module 10 and the expansion module 20.

[0069] 8 has three mechanical mechanisms M1 to M3. The first mechanical mechanism M1 has a base substrate 30a on which a core module 10 and an expansion module 20 are mounted, a plurality of sensors 200, and a plurality of motors 201. The second mechanical mechanism M2 and the third mechanical mechanism M3 each have a plurality of sensors 200 and a plurality of motors 201.

[0070] The base substrate 30a includes the core module 10, the expansion module 20, a communication circuit 31, a plurality of sensor circuits 32, a plurality of motor circuits 33, and connectors 34c, 34d, 34e, 34f, 34g, and 34h. The core module 10 and the expansion module 20 are connected using a serial I / O interface via the connector 15, the connector 23a, and wiring formed on the base substrate 30a.

[0071] The core module 10 and some of the plurality of sensor circuits 32 are connected using a parallel I / O interface via the connector 14 and wiring formed on the base substrate 30 a. The core module 10 and some of the plurality of motor circuits 33 are connected using a parallel I / O interface via the connector 14 and wiring formed on the base substrate 30 a.

[0072] The expansion module 20 and some of the multiple sensor circuits 32 are connected using a parallel I / O interface via the connector 22 and wiring formed on the base substrate 30a. The expansion module 20 and some of the multiple motor circuits 33 are connected using a parallel I / O interface via the connector 22bb and wiring formed on the base substrate 30a.

[0073] The plurality of sensor circuits 32 are connected to connectors 34c, 34e, or 34g using a parallel I / O interface according to the corresponding sensors 200. The plurality of motor circuits 33 are connected to connectors 34d, 34f, or 34h using a parallel I / O interface according to the corresponding motors 201.

[0074] The base substrate 30a and the plurality of sensors 200 are connected using a parallel I / O interface via a connector 34c and a connection cable 36. The base substrate 30a and the plurality of motors 201 are connected using a parallel I / O interface via a connector 34d and a connection cable 36.

[0075] The base substrate 30a and the plurality of sensors 200 of the second mechanical mechanism M2 are connected using a parallel I / O interface via a connector 34e and a connection cable 36. The base substrate 30a and the plurality of motors 201 of the second mechanical mechanism M2 are connected using a serial I / O interface via a connector 34f and a connection cable 36.

[0076] The base substrate 30a and the plurality of sensors 200 of the third mechanical mechanism M3 are connected using a parallel I / O interface via a connector 34g and a connection cable 36. The base substrate 30a and the plurality of motors 201 of the third mechanical mechanism M3 are connected using a parallel I / O interface via a connector 34h and a connection cable 36.

[0077] In the example shown in FIG. 8, signals from the plurality of sensors 200 of the first mechanical mechanism M1 are transmitted to the CPU 11 via the connection cable 36, the connector 34c, the sensor circuit 32, the connector 14 and the FPGA 12.

[0078] Signals from the plurality of sensors 200 of the second mechanical mechanism M2 are transmitted to the CPU 11 via the connection cable 36, connector 34e, sensor circuit 32, connector 14, and FPGA 12. Signals from the plurality of sensors 200 of the third mechanical mechanism M3 are transmitted to the CPU 11 via the connection cable 36, connector 34g, sensor circuit 32, connector 22, FPGA 21, connector 23a, connector 15, and FPGA 12. This enables the CPU 11 of the core module 10 to perform banknote recognition processing.

[0079] Control signals to the multiple motors 201 of the first mechanical mechanism M1 are transmitted from the CPU 11 to the motors 201 via the FPGA 12, connector 14, motor circuit 33, connector 34d, and connection cable 36. Control signals to the multiple motors 201 of the second mechanical mechanism M2 are transmitted from the CPU 11 to the motors 201 via the FPGA 12, connector 14, motor circuit 33, connector 34f, and connection cable 36. Control signals to the multiple motors 201 of the third mechanical mechanism M3 are transmitted from the CPU 11 to the motors 201 via the FPGA 12, connector 15, connector 23a, FPGA 21, connector 22, motor circuit 33, connector 34h, and connection cable 36. This allows the CPU 11 of the core module 10 to control each of the multiple motors 201 of the first mechanical mechanism M1, the second mechanical mechanism M2, and the third mechanical mechanism M3.

[0080] Although the above example shows the use of one base substrate 30, multiple base substrates 30 may also be used. Below, an example will be described in which two base substrates 30, 30b and four mechanical mechanisms M11 to M14 are implemented in a valuable medium processing device 40. Note that parts similar to those implemented in the valuable medium processing device 40 shown in Figures 7 and 8 are given the same reference numerals, and detailed descriptions thereof will be omitted. Figure 9 shows another implementation of the core module 10 and the expansion module 20.

[0081] The valuable medium processing device 40 shown in Figure 9 has four mechanical mechanisms M11 to M14. The first mechanical mechanism M11 has a base substrate 30c on which the core module 10 is mounted, multiple sensors 200, and multiple motors 201. The second mechanical mechanism M12 has a base substrate 30d on which the first expansion module 20a and the second expansion module 20b are mounted, multiple sensors 200, and multiple motors 201. The third mechanical mechanism M13 has multiple sensors 200 and multiple motors 201. The fourth mechanical mechanism M14 has multiple sensors 200 and multiple motors 201.

[0082] The base substrate 30c of the first mechanical mechanism M11 has a configuration in which a connector 35a is added to the base substrate 30 described in FIG. 7 in order to transmit control signals from the CPU 11 to another base substrate. The core module 10 and the connector 35a are connected using a serial I / O interface via the connector 15 and wiring formed on the base substrate 30c. The base substrates 30c and 30d are connected using a serial I / O interface via the connector 35a mounted on the base substrate 30c and the connector 35b mounted on the base substrate 30d. This enables mutual transmission of control signals transmitted from the CPU 11 and acquired data from multiple sensors 200 transmitted to the CPU 11 between the base substrates 30c and 30d.

[0083] The base substrate 30d of the second mechanical mechanism M12 has a first expansion module 20a, a second expansion module 20b, a communication circuit 31, a plurality of sensor circuits 32, a plurality of motor circuits 33, connectors 34c, 34d, 34e, 34f, 34g, 34h, and a connector 35b.

[0084] The first expansion module 20a is mounted on the base substrate 30d using a plurality of connectors 22, 23a, and 23b. The first expansion module 20a and connector 35b are connected using a serial I / O interface via the connector 23a and wiring formed on the base substrate 30d. The first expansion module 20a and the second expansion module 20c are connected using a serial I / O interface via the connector 23b, wiring formed on the base substrate 30d, and connector 23c.

[0085] The first expansion module 20a and some of the plurality of sensor circuits 32 are connected using a parallel I / O interface via the connector 22 and wiring formed on the base substrate 30d. The first expansion module 20a and some of the plurality of motor circuits 33 are connected using a parallel I / O interface via the connector 22 and wiring formed on the base substrate 30d.

[0086] The second expansion module 20b and some of the plurality of sensor circuits 32 are connected using a parallel I / O interface via the connector 22 and wiring formed on the base substrate 30d. The second expansion module 20b and some of the plurality of motor circuits 33 are connected using a parallel I / O interface via the connector 22 and wiring formed on the base substrate 30d.

[0087] The plurality of sensor circuits 32 are connected to connectors 34c, 34e, or 34g using a parallel I / O interface according to the corresponding sensors 200. The plurality of motor circuits 33 are connected to connectors 34d, 34f, or 34h using a parallel I / O interface according to the corresponding motors 201.

[0088] The base substrate 30d and the plurality of sensors 200 are connected using a parallel I / O interface via a connector 34c and a connection cable 36. The base substrate 30a and the plurality of motors 201 are connected using a parallel I / O interface via a connector 34d and a connection cable 36.

[0089] The base substrate 30d and the plurality of sensors 200 of the third mechanical mechanism M13 are connected using a parallel I / O interface via a connector 34e and a connection cable 36. The base substrate 30d and the plurality of motors 201 of the third mechanical mechanism M13 are connected using a parallel I / O interface via a connector 34f and a connection cable 36.

[0090] The base substrate 30d and the plurality of sensors 200 of the fourth mechanical mechanism M14 are connected using a parallel I / O interface via a connector 34g and a connection cable 36. The base substrate 30d and the plurality of motors 201 of the fourth mechanical mechanism M14 are connected using a parallel I / O interface via a connector 34h and a connection cable 36.

[0091] 9, a serial I / O interface is used to connect the sensors 200 to the multiple base substrates connected thereto. By transmitting and receiving signals from the serial I / O interface via the expansion module 20, it becomes possible to transmit acquired data from the multiple sensors 200 connected to each base substrate to the CPU 11 of the core module 10. This allows the CPU 11 of the core module 10 to perform banknote recognition processing.

[0092] Furthermore, a serial I / O interface is used to connect the motors 201 to the multiple base boards connected to them. By transmitting and receiving signals from the serial I / O interface via the expansion module 20, it becomes possible to transmit control signals from the CPU 11 of the core module 10 to the multiple motors 201 connected to each base board. This allows the CPU 11 of the core module 10 to control the multiple motors 201 of the first mechanical mechanism M11, the second mechanical mechanism M12, the third mechanical mechanism M13, and the fourth mechanical mechanism M14.

[0093] Although Figure 9 illustrates an example in which two base substrates are connected, three or more base substrates may be connected by implementing one or more expansion modules 20 and connectors on each base substrate and connecting them via a serial I / O interface.

[0094] To avoid security risks, encrypted communication may be performed at the bus interface between the CPU 11 and FPGA 12 of the core module 10 and at the serial I / O interface between the core module 10 and the expansion module 20.

[0095] Fig. 10 is a diagram for explaining an outline of an implementation form that ensures security in the valuable medium processing device 40. Note that Fig. 10 illustrates only a portion of the valuable medium processing device 40, omitting the illustration of the base substrate and showing only the core modules 210a, 210b and the extension modules 220a, 220b.

[0096] As shown in FIG. 10 , the core module 210 a includes a CPU 211, an FPGA 212, and a TPM (Trusted Platform Module) 216. The CPU 211 controls the entire valuable medium processing device 40 on which the base substrate is mounted. The FPGA 212 is equipped with functional logic that controls the multiple sensor circuits 32 and multiple motor circuits 33 used in the valuable medium processing device 40. The FPGA 212 is equipped with an encryption IP (Intellectual Property) core to encrypt the serial I / O interface. The type of encryption IP core is not particularly limited. For example, an IP core based on the Advanced Encryption Standard (AES) method, Secure Hash Algorithm 2 (SHA2) method, or the like may be used. The TPM 216 generates and stores a private key and the like used for encrypting communications with a second management device other than the manufacturer.

[0097] The core module 210a transmits and receives encrypted data using the TPM 216 via a system bus between the CPU 211 and FPGA 212. Between the core module 210a and the expansion module 220a, data is transmitted and received using encryption IP cores implemented in the FPGA 212 and FPGA 221. Similarly, data is transmitted and received between the core module 210b and the expansion module 220b using encryption IP cores.

[0098] Data encrypted using a private key generated based on the TPM 216 is also transmitted and received at the interface between the core module 210a implemented inside the processing unit 41 of the valuable medium processing device 40 and the core module 210b implemented inside the safe unit 42. The core module 210a may communicate with an external device, for example, a second management device other than the manufacturer of the valuable medium processing device 40, and even in such external communications, data encrypted using a private key generated based on the functions of the TPM 216 is transmitted and received.

[0099] In this way, the TPM 216 is implemented in the core module 210a, and the TPM 216 generates and stores a private key and the like used for encryption, and the private key is used to encrypt communication between the CPU 211 of the core module 210a and the CPU 211 of the core module 210b. Also, an encryption IP core is implemented in the FPGA 212 implemented in the core module 210a and the FPGA 221 implemented in the expansion module 220a, and communication between the FPGA 212 and the FPGA 221 is encrypted. This makes it possible to strengthen security by preventing eavesdropping on communication between modules and communication between modules and external devices.

[0100] In the above example, a case where the sensor circuit 32 and the motor circuit 33 mounted on the base substrate 30 are changed is described, but the present disclosure can also enable the manufacturing of the product to continue even if the FPGA used is changed to an alternative FPGA.

[0101] 1, it is assumed that one of three FPGAs from companies A, B, and C will be used as the FPGA 21 to be mounted in the expansion module 20. Each of the FPGAs 21 from companies A, B, and C is mounted with a plurality of functional logics that control sensor circuits 32 and motor circuits 33 from multiple manufacturers that are mounted on a base substrate 30 developed for each device. The plurality of functional logics mounted in the FPGA can be designed as a common program by using RTL (Register Transfer Level) design, which allows common design regardless of the FPGA manufacturer.

[0102] The CPU 11 of the core module 10 is also provided with a program that operates any of the FPGAs 21 from companies A, B, and C, and is configured to determine which company's FPGA is installed and select the corresponding program to operate. In this way, even if it becomes difficult to obtain FPGAs from company A, product manufacturing can continue by installing FPGAs from companies B or C in the expansion module 20.

[0103] Similarly, FPGAs from multiple pre-determined manufacturers can be used for the FPGA 12 mounted on the core module 10. In this way, even if it becomes difficult to obtain FPGAs from company A, product manufacturing can continue by mounting FPGAs from companies B and C on the core module 10.

[0104] The configurations illustrated in the above embodiments are merely functional schematics and do not necessarily have to be physically configured as shown. In other words, the distribution and integration of each device is not limited to the illustrated configuration, and all or part of the devices can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

Claims

1. A general-purpose control board that can be mounted on either a first unique board incorporated in a first device or a second unique board incorporated in a second device, comprising: a processor that controls the device by executing a first application that controls the user interface of the device and realizes the functions of the device; and a programmable element that implements a second application that operates the unique board based on the first application executed by the processor.

2. A general-purpose control board as described in claim 1, characterized in that it comprises: a first board including the processor and a first programmable element; and a second board including a second programmable element connected to the first programmable element.

3. The general-purpose control board according to claim 2, characterized in that the first board and the second board are connected using a serial I / O interface.

4. The general-purpose control board according to claim 3, wherein said first board and said second board communicate with each other by encrypting data.

5. The general-purpose control board according to claim 1, characterized in that the first application can be changed only from the first control device, and the second application can be changed from both the first control device and the second control device.

6. A general-purpose control board as claimed in any one of claims 1 to 4, characterized in that the device is a valuable media processing device that processes valuable media.

7. The general-purpose control board described in claim 6, characterized in that the valuable medium processing device includes a plurality of sensors and / or a plurality of motors used in processing valuable media, and the plurality of sensors and / or the plurality of motors are electrically connected to the programmable elements.

8. The general-purpose control board according to claim 6, characterized in that the plurality of sensors and / or the plurality of motors are electrically connected to the processor via the programmable elements.

9. The general-purpose control board according to claim 6, characterized in that the valuable medium processing device further comprises a safe, and the specific board on which the general-purpose control board is mounted is stored within the safe.

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