Preparation method for silicon carbide field effect transistor

Abstract

The present application discloses a preparation method for a silicon carbide field effect transistor. The method comprises: providing a first silicon carbide substrate, and epitaxially growing a silicon carbide epitaxial layer on the first silicon carbide substrate; implanting light ions into the silicon carbide epitaxial layer, wherein the light ions form an ion gathering area in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer sequentially forms a silicon carbide thin film layer, the ion gathering area, and a silicon carbide bonding layer; providing a second silicon carbide substrate, and performing conductive treatment on the surface of the second silicon carbide substrate in contact with the silicon carbide bonding layer; performing wafer bonding on the second silicon carbide substrate and the silicon carbide bonding layer; separating the silicon carbide bonding layer from the ion gathering area to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer, and the ion gathering area, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, and recycling the first substrate structure; and on the basis of the second substrate structure, preparing a field effect transistor to obtain a silicon carbide field effect transistor.

Description

A method for preparing silicon carbide field effect tube Technical Field

[0001] The present application relates to the technical field of information functional material preparation, and in particular to a method for preparing a silicon carbide field effect transistor. Background Art

[0002] Silicon carbide (SiC), a representative material for third-generation semiconductors, is typically produced using high-quality single-crystal SiC substrates produced using the PVT (Process Verification Test, Physical Vapor Transport) method. This serves as the primary raw material for devices such as SiC field-effect transistors (SiC MOSFETs). However, the production of single-crystal SiC substrates currently suffers from low SiC yields and high costs due to issues such as defect control during SiC growth and material loss caused by cutting, grinding, and polishing. This hinders large-scale SiC production and, in turn, increases the cost of producing SiC MOSFETs.

[0003] Summary of the Invention

[0004] In order to solve the above-mentioned technical problems of low silicon carbide yield and high cost, which lead to increased preparation cost of silicon carbide field effect transistors, the present application discloses a preparation method of a silicon carbide field effect transistor that can solve the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned object of the invention, the present application provides a method for preparing a silicon carbide field effect transistor, the method comprising:

[0006] providing a first silicon carbide substrate, and growing a silicon carbide epitaxial layer on the first silicon carbide substrate;

[0007] Implanting light ions into the silicon carbide epitaxial layer, wherein the light ions form an ion accumulation region in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer sequentially forms a silicon carbide thin film layer, the ion accumulation region, and a silicon carbide bonding layer;

[0008] providing a second silicon carbide substrate, and performing a conductive treatment on a surface of the second silicon carbide substrate contacting the silicon carbide bonding layer;

[0009] Wafer bonding the second silicon carbide substrate to the silicon carbide bonding layer;

[0010] peeling the silicon carbide bonding layer and the ion accumulation region to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer, and the ion accumulation region, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, and recycling the first substrate structure;

[0011] A field effect transistor is prepared based on the second substrate structure to obtain a silicon carbide field effect transistor.

[0012] In some embodiments, after peeling the silicon carbide bonding layer and the ion accumulation region to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer, and the ion accumulation region, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, the method further includes:

[0013] Performing a quality recovery process on the silicon carbide bonding layer in the second substrate structure and performing a thinning process on a side of the second silicon carbide substrate away from the silicon carbide bonding layer to obtain a target silicon carbide substrate;

[0014] The step of preparing a field effect transistor based on the second substrate structure to obtain a silicon carbide field effect transistor includes:

[0015] A field effect transistor is prepared based on the target silicon carbide substrate to obtain a silicon carbide field effect transistor.

[0016] In some embodiments, performing quality recovery processing on the silicon carbide bonding layer in the second substrate structure includes:

[0017] forming a carbon film on a surface of the second substrate structure;

[0018] Performing an annealing treatment on the second substrate structure, wherein the annealing temperature is 1700-2000° C. and the annealing time is 0.5-5 hours;

[0019] The second substrate structure after annealing is post-processed to remove the carbon film on the surface of the second substrate structure and the defective layer on the silicon carbide bonding layer, thereby restoring the quality of the silicon carbide bonding layer in the second substrate structure.

[0020] In some embodiments, the recycling of the first substrate structure includes:

[0021] performing a thermal oxidation treatment on the first substrate structure;

[0022] removing the oxide layer in the first substrate structure after thermal oxidation treatment;

[0023] The silicon carbide surface in the first substrate structure with the oxide layer removed is polished to obtain a silicon carbide substrate.

[0024] In some embodiments, the thickness of the silicon carbide epitaxial layer is 10 μm-20 μm, and the concentration of doped ions in the silicon carbide epitaxial layer is 1E12-1E15 / cm 3 , wherein the doping ions are at least one of nitrogen and phosphorus.

[0025] In some embodiments, the light ions include at least one of hydrogen ions and helium ions, and the implantation dose of the light ions is 1E17 / cm 2 -1E20 / cm 2 , the injection energy is 1MeV-3MeV.

[0026] In some embodiments, the first silicon carbide substrate is an N-type silicon carbide substrate.

[0027] In some embodiments, the second silicon carbide substrate is any one of a test-grade, mixed crystal, and polycrystalline substrate.

[0028] In some embodiments, performing conductive treatment on the contacting surfaces of the second silicon carbide substrate and the silicon carbide bonding layer includes:

[0029] Dopant ions are implanted into a first surface of the silicon carbide bonding layer opposite to the second silicon carbide substrate, and into a second surface of the second silicon carbide substrate opposite to the silicon carbide bonding layer, so as to achieve conductive treatment on the surfaces where the second silicon carbide substrate and the silicon carbide bonding layer are in contact with each other.

[0030] In some embodiments, the doping ions include at least one of nitrogen ions and phosphorus ions, and the implantation dose of the doping ions is 1E13-1E15 / cm 2 The implantation energy of the doping ions is 5keV-30keV.

[0031] The implementation of the embodiments of the present application has the following beneficial effects:

[0032] The method for preparing a silicon carbide field-effect transistor disclosed in the present application reduces the cost of preparing the silicon carbide field-effect transistor and enables rapid preparation of the silicon carbide field-effect transistor by transferring the silicon carbide bonding layer in the silicon carbide epitaxial layer on the first silicon carbide substrate to the second silicon carbide substrate and directly preparing the field-effect transistor on the second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer. In addition, by recycling the first substrate structure to reuse the silicon carbide substrate, the cost of the silicon carbide substrate can be effectively reduced, thereby further reducing the cost of preparing the silicon carbide field-effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the method for preparing the silicon carbide field-effect transistor described in the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] FIG1 is a schematic flow chart of a method for preparing a silicon carbide field effect transistor according to an embodiment of the present application;

[0035] FIG2 is a schematic diagram of epitaxially growing a silicon carbide epitaxial layer on a first silicon carbide substrate provided in an embodiment of the present application;

[0036] FIG3 is a schematic diagram of light ion implantation in a silicon carbide epitaxial layer according to an embodiment of the present application;

[0037] FIG4 is a schematic diagram of conducting a conductive treatment on the contact surfaces of the second silicon carbide substrate and the silicon carbide bonding layer according to an embodiment of the present application;

[0038] FIG5 is a schematic diagram of a second silicon carbide substrate and a silicon carbide bonding layer wafer after bonding according to an embodiment of the present application;

[0039] FIG6 is a schematic diagram of a silicon carbide bonding layer and an ion accumulation region after peeling off according to an embodiment of the present application;

[0040] FIG7 is a schematic diagram of a target silicon carbide substrate provided in an embodiment of the present application;

[0041] FIG8 is a schematic diagram of a silicon carbide field effect transistor provided in an embodiment of the present application;

[0042] FIG9 is a schematic flow chart of a method for recycling a first substrate structure provided in an embodiment of the present application;

[0043] FIG10 is a schematic diagram of recycling a first substrate structure provided in an embodiment of the present application;

[0044] FIG11 is a schematic diagram of a preparation process of a silicon carbide field effect transistor provided in an embodiment of the present application.

[0045] The reference numerals in the figure correspond to: 1-first silicon carbide substrate, 2-silicon carbide epitaxial layer, 21-silicon carbide thin film layer, 22-silicon carbide bonding layer, 3-ion accumulation region, 4-second silicon carbide substrate. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] In this application, silicon carbide (SiC), a representative material for third-generation semiconductors, combines excellent properties such as a wide bandgap (2.4eV-3.2eV), high physical strength (Mohs hardness 9.5, Knoop hardness 2480kg / mm²), high thermal conductivity (480W / mK), high corrosion resistance, high melting point, high optical second- and third-order nonlinear coefficients, a wide optical transmission window (0.37-5.6μm), and a wide defect luminescence window (visible to mid-infrared). It is an ideal material platform for high-voltage power devices. SiC materials have over 200 crystal forms, of which 3C-SiC, 4H-SiC, and 6H-SiC are the most widely used.

[0048] As shown in FIG1 , the present application provides a flow chart of a method for preparing a silicon carbide field effect transistor, which may include the following steps:

[0049] S101 , providing a first silicon carbide substrate, and growing a silicon carbide epitaxial layer on the first silicon carbide substrate.

[0050] In the embodiment of the present application, the first silicon carbide substrate may be an N-type silicon carbide substrate, which is a high-quality silicon carbide wafer substrate. As an example, the first silicon carbide substrate may be 4H-SiC prepared using a PVT method.

[0051] The present application adopts a relatively expensive N-type silicon carbide substrate, because the first silicon carbide substrate is subsequently recycled, thereby reducing the cost of using the silicon carbide substrate.

[0052] In some exemplary embodiments, a silicon carbide epitaxial layer may be grown on the surface of the first silicon carbide substrate using a homoepitaxial method, wherein the thickness of the silicon carbide epitaxial layer may be 10 μm-20 μm.

[0053] In order to adjust the resistance of silicon carbide, the present application doped the silicon carbide epitaxial layer with doping ions during epitaxial growth. In one example, the concentration of the doping ions is 1E12-1E15 / cm 3 The doping ions may be at least one of nitrogen and phosphorus. The higher the concentration of the doping ions, the lower the resistivity of the silicon carbide epitaxial layer.

[0054] In one example, specifically referring to FIG2 , it is a schematic diagram of epitaxially growing a silicon carbide epitaxial layer on a first silicon carbide substrate provided by an embodiment of the present application.

[0055] Specifically, this figure shows a process of epitaxially growing a silicon carbide epitaxial layer 2 on a first silicon carbide substrate 1 .

[0056] S103 , implanting light ions into the silicon carbide epitaxial layer, the light ions forming an ion accumulation region in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer sequentially forms a silicon carbide thin film layer, an ion accumulation region and a silicon carbide bonding layer.

[0057] In the embodiment of the present application, the light ions may include at least one of hydrogen ions and helium ions. As an example, the light ions may be H+ or He+ or H+ and He+.

[0058] In some exemplary embodiments, H+ or He+ or H+ and He+ may be implanted into the silicon carbide epitaxial layer along a direction from the outer surface of the silicon carbide epitaxial layer away from the first silicon carbide substrate toward the first silicon carbide substrate, wherein the implantation dose of light ions may be 1E17 / cm 2 -1E20 / cm 2 The implantation energy can be 1MeV-3MeV. The greater the implantation energy of the light ions, the closer the ion concentration region is to the first silicon carbide substrate. The present application adopts a higher implantation energy, which can make the thickness of the silicon carbide bonding layer thicker.

[0059] In one example, with this implantation dose and implantation energy, the thickness of the obtained silicon carbide bonding layer can reach 10-20 μm.

[0060] In this example, higher implantation energy and implantation dose are used, so that the ion accumulation region can be closer to the surface of the first silicon carbide substrate, thereby increasing the thickness of the obtained silicon carbide bonding layer.

[0061] In one example, as shown in FIG3 , it is a schematic diagram of light ion implantation in a silicon carbide epitaxial layer provided in an embodiment of the present application.

[0062] Specifically, in this figure, taking hydrogen ions as an example, hydrogen ions H+ are injected into the silicon carbide epitaxial layer 2 , and ion accumulation regions 3 are formed in the silicon carbide epitaxial layer 2 .

[0063] S105 , providing a second silicon carbide substrate, and performing conductive treatment on surfaces of the second silicon carbide substrate where the substrate contacts the silicon carbide bonding layer.

[0064] In the embodiment of the present application, the second silicon carbide substrate is any one of a test-grade, mixed crystal, and polycrystalline substrate. This type of silicon carbide substrate has a low cost and can effectively reduce the preparation cost of silicon carbide field effect transistors.

[0065] As an example, the second silicon carbide substrate can be 3C-SiC prepared by depositing a SiC film on the surface of a Si substrate using atmospheric pressure chemical vapor deposition (APCVD) and reduced pressure chemical vapor deposition (RPCVD). The second silicon carbide substrate obtained in this way is generally a polycrystalline substrate.

[0066] In some exemplary embodiments, performing conductive treatment on the contacting surfaces of the second silicon carbide substrate and the silicon carbide bonding layer may include:

[0067] Dopant ions are implanted into a first surface of the silicon carbide bonding layer opposite the second silicon carbide substrate, and into a second surface of the second silicon carbide substrate opposite the silicon carbide bonding layer, to achieve conductive treatment of the surfaces of the second silicon carbide substrate and the silicon carbide bonding layer in contact with each other. The dopant ions may include at least one of nitrogen ions and phosphorus ions.

[0068] In one example, dopant ions can be vertically implanted into the silicon carbide epitaxial layer along the outer surface of the silicon carbide epitaxial layer away from the first silicon carbide substrate toward the first silicon carbide substrate; and simultaneously, the second silicon carbide substrate can be vertically implanted along the surface of the second silicon carbide substrate close to the silicon carbide bonding layer; thereby improving the conductivity of the surface where the second silicon carbide substrate and the silicon carbide bonding layer contact each other. A high-conductivity bonding interface is obtained. As an example, the implantation dose of the dopant ions can be 1E13-1E15 / cm 2 , the implantation energy of the doping ions can be 5keV-30keV.

[0069] In one example, as shown in FIG4 , it is a schematic diagram of conducting conductive treatment on the contacting surfaces of the second silicon carbide substrate and the silicon carbide bonding layer provided by an embodiment of the present application.

[0070] Specifically, in this figure, taking nitrogen ions N+ and phosphorus ions P+ as an example, N+ and P+ are implanted into the first surface of the silicon carbide bonding layer and the second surface of the second silicon carbide substrate 4 respectively.

[0071] S107, wafer bonding the second silicon carbide substrate to the silicon carbide bonding layer;

[0072] In the embodiment of the present application, the second silicon carbide substrate and the silicon carbide bonding layer can be wafer-bonded using a bonding machine in a vacuum environment.

[0073] In one example, as shown in FIG5 , it is a schematic diagram of a second silicon carbide substrate and a silicon carbide bonding layer wafer provided in an embodiment of the present application after bonding.

[0074] Specifically, in this figure, the second silicon carbide substrate 4 and the silicon carbide bonding layer are wafer-bonded.

[0075] S109, peeling off the silicon carbide bonding layer and the ion accumulation region to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer and the ion accumulation region, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, and recycling the first substrate structure.

[0076] In the embodiment of the present application, annealing can be used to peel off the silicon carbide bonding layer and the ion accumulation region.

[0077] In one example, as shown in FIG6 , it is a schematic diagram of a silicon carbide bonding layer and an ion accumulation region after peeling off provided by an embodiment of the present application;

[0078] Specifically, in this figure, after the silicon carbide bonding layer is peeled off, a first substrate structure formed by the first silicon carbide substrate 1, the silicon carbide thin film layer 21 and the ion accumulation region 3 and a second substrate structure formed by the second silicon carbide substrate 4 and the silicon carbide bonding layer 22 are formed.

[0079] Optionally, after obtaining the second substrate structure, the method may further include performing quality recovery processing on the silicon carbide bonding layer in the second substrate structure and thinning the side of the second silicon carbide substrate away from the silicon carbide bonding layer to obtain a target silicon carbide substrate.

[0080] For performing quality recovery processing on the silicon carbide bonding layer in the second substrate structure, in some exemplary embodiments, the following method may be used:

[0081] A carbon film is formed on the surface of the second substrate structure; the second substrate structure is annealed, wherein the annealing temperature is 1700-2000°C and the annealing time is 0.5-5 hours; the second substrate structure after annealing is post-processed to remove the carbon film on the surface of the second substrate structure and the defective layer on the silicon carbide bonding layer, thereby restoring the quality of the silicon carbide bonding layer in the second substrate structure.

[0082] In one example, the thickness of the carbon film (C film) may be 100-1000 nm, and the thickness of the C film is inversely proportional to the temperature and the gas pressure.

[0083] Furthermore, the annealing process may be performed in an environment including, but not limited to, a vacuum environment and a nitrogen environment, wherein the pressure in the nitrogen environment may be 0.2-0.5 atmospheres.

[0084] Furthermore, the surface of the annealed second substrate structure is post-processed. Specifically, dry etching can be used to remove the carbon film remaining on the surface, and the gas used in this process is oxygen; further, polishing is used to remove the defective layer on the silicon carbide bonding layer, and the removal thickness can be 1.5-3μm.

[0085] In this embodiment, a higher annealing temperature is used, which can improve the degree of recovery of the quality of the silicon carbide bonding layer, and can also increase the degree of activation of the implanted nitrogen ions and phosphorus ions, thereby improving the surface conductivity.

[0086] In some exemplary embodiments, the thinning process of the second silicon carbide substrate on the side away from the silicon carbide bonding layer can be performed by wafer grinding. Specifically, the thickness of the second silicon carbide substrate can be thinned to 30-100 μm to facilitate the subsequent fabrication of silicon carbide field-effect transistors.

[0087] Specifically, as shown in FIG7 , it is a schematic diagram of a target silicon carbide substrate provided in an embodiment of the present application.

[0088] Specifically, the figure shows the silicon carbide bonding layer 22 and the second silicon carbide substrate 4, wherein the thickness of the second silicon carbide substrate 4 is 30-100 μm.

[0089] S111, preparing a field effect transistor based on the second substrate structure to obtain a silicon carbide field effect transistor.

[0090] In the embodiment of the present application, the silicon carbide bonding layer on the second substrate structure can be transferred and the field effect transistor can be directly prepared on the second silicon carbide substrate.

[0091] In some exemplary embodiments, a field effect transistor may be prepared based on the target silicon carbide substrate to obtain a silicon carbide field effect transistor.

[0092] Compared with the prior art method of transferring first and then growing epitaxy, direct transfer can avoid thermal stress during epitaxial growth and improve the preparation efficiency of silicon carbide field-effect transistors.

[0093] In some exemplary embodiments, the field effect transistor may be fabricated by methods such as ion implantation, doping activation, photolithography, and dry etching.

[0094] In one example, aluminum (Al) is implanted in the silicon carbide bonding layer to form a Pwell region (P-type hole conductive region) and a junction field effect transistor (JFET). Furthermore, higher concentrations of Al and N are implanted to form a P+ region (high-concentration hole conductive region) and an N+ region (high-concentration electron conductive region), and the doped regions are annealed and activated.

[0095] Furthermore, a gate oxide region (Gate poly) is prepared on the top layer based on the activation structure, and an intermediate insulating layer (ILD) is set around the gate oxide region. Then, a first electrode (Metal) is set on the side of the gate oxide region away from the second silicon carbide substrate, and a second electrode (Metal) is set on the side of the second silicon carbide substrate away from the gate oxide region. Then, rapid annealing is performed to prepare an ohmic contact to realize the preparation of a silicon carbide field effect transistor (SIC MOSFET).

[0096] Specifically, as shown in FIG8 , it is a schematic diagram of a silicon carbide field effect transistor provided in an embodiment of the present application.

[0097] Specifically, in this figure, the area indicated by Metal represents the electrode, the area indicated by Handle N+ represents the second silicon carbide substrate, the area indicated by N-epi layer represents the silicon carbide bonding layer, the area indicated by Pwell represents the P-type hole conduction area, the area indicated by JEFT represents the junction field effect transistor, the area indicated by P+ represents the high-concentration hole conduction area, the area indicated by N+ represents the high-concentration electron conduction area, the area indicated by Gate poly represents the gate oxide region, and the area indicated by ILD represents the intermediate insulating layer.

[0098] In this embodiment, the method for preparing a silicon carbide field effect transistor disclosed in the present application can reduce the preparation cost of the silicon carbide field effect transistor and quickly prepare the silicon carbide field effect transistor by transferring the silicon carbide bonding layer in the silicon carbide epitaxial layer on the first silicon carbide substrate to the second silicon carbide substrate, and directly preparing the field effect transistor on the second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer. In addition, by recycling the first substrate structure to reuse the silicon carbide substrate, the cost of the silicon carbide substrate can be effectively reduced, thereby further reducing the preparation cost of the silicon carbide field effect transistor.

[0099] In some exemplary embodiments, as shown in FIG9 , a schematic flow chart of a method for recycling a first substrate structure provided in an embodiment of the present application is shown. Specific steps are as follows:

[0100] S901, performing thermal oxidation treatment on the first substrate structure;

[0101] In the embodiment of the present application, the thermal oxidation treatment may be performed by wet oxidation in a pure oxygen environment at 1200-1400°C for 2-5 hours. In a preferred example, the oxidation temperature is 1300°C.

[0102] S903, removing the oxide layer in the first substrate structure after thermal oxidation treatment;

[0103] In the embodiment of the present application, a hydrogen fluoride wet etching method can be used to remove the oxide layer in the first substrate structure after the thermal oxidation treatment.

[0104] S905 , polishing the silicon carbide surface in the first substrate structure with the oxide layer removed to obtain a silicon carbide substrate.

[0105] In an embodiment of the present application, the remaining silicon carbide surface in the first substrate structure can be polished using a fine polishing method. This method allows the film removed by polishing the surface to be thinner. Specifically, the removed thickness can be less than or equal to 500 nm.

[0106] In one example, as shown in FIG10 , it is a schematic diagram of recycling a first substrate structure provided in an embodiment of the present application;

[0107] Specifically, the figure shows the silicon carbide substrate obtained after the first substrate structure is recycled.

[0108] This recycling method is different from conventional grinding and polishing. To maximize the number of uses of the substrate, it is necessary to maintain the wafer morphology of the substrate. Therefore, grinding is not used in this application. However, due to the high energy of light ion implantation, the defect layer of the epitaxial layer is deep, which is difficult to solve with simple polishing.

[0109] Because the defective layer generated after the injection of light ions is more easily oxidized, the oxidation temperature of 1300°C is higher than the oxidation temperature of silicon (Si), thereby improving efficiency. After the defective layer is completely oxidized, the intact lattice in the first silicon carbide substrate can be better preserved due to the dual protection of the single crystal and the oxide layer on the first silicon carbide substrate. Furthermore, through hydrogen fluoride wet etching and polishing treatment, the surface defective layer can be completely removed while ensuring the morphology of the wafer. The obtained silicon carbide substrate can then be reused, greatly reducing the cost of using silicon carbide and thus reducing the preparation cost of silicon carbide field-effect transistors.

[0110] In some exemplary embodiments, as shown in FIG11 , it is a schematic diagram of a preparation process of a silicon carbide field effect transistor provided in an embodiment of the present application.

[0111] Specifically, the meanings of the letters shown in this figure are the same as the meanings of the letters shown in the corresponding figures of the above embodiments.

[0112] In this figure, the preparation process of the silicon carbide field effect transistor is as follows:

[0113] Provide high-quality N-type silicon carbide substrates and grow silicon carbide epitaxial layers on N-type silicon carbide substrates;

[0114] The hydrogen ions are implanted into the silicon carbide epitaxial layer, where the hydrogen ions form an ion accumulation region in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer is sequentially formed into a silicon carbide thin film layer, an ion accumulation region, and a silicon carbide bonding layer; wherein the hydrogen ion implantation dose can be 1E17 / cm 2 -1E20 / cm 2 , the injection energy can be 1MeV-3MeV.

[0115] A polycrystalline silicon carbide substrate is provided, and nitrogen ions and phosphorus ions are implanted into a first surface of the silicon carbide bonding layer opposite to the polycrystalline silicon carbide substrate, and a second surface of the polycrystalline silicon carbide substrate opposite to the silicon carbide bonding layer; wherein the implantation dose of the nitrogen ions and the phosphorus ions may be 1E13-1E15 / cm 2 , the implantation energy of the doping ions can be 5keV-30keV.

[0116] Wafer bonding the polycrystalline silicon carbide substrate to the silicon carbide bonding layer;

[0117] peeling off the silicon carbide bonding layer and the ion accumulation region to obtain a first substrate structure formed by the N-type silicon carbide substrate, the silicon carbide thin film layer and the ion accumulation region, and a second substrate structure formed by the polycrystalline silicon carbide substrate and the silicon carbide bonding layer; and recycling the first substrate structure to obtain a silicon carbide substrate;

[0118] Performing a quality recovery process on the silicon carbide bonding layer in the second substrate structure and performing a thinning process on a side of the polycrystalline silicon carbide substrate away from the silicon carbide bonding layer to obtain a target silicon carbide substrate;

[0119] A field effect transistor is prepared based on a target silicon carbide substrate to obtain a silicon carbide field effect transistor.

[0120] The method for preparing a silicon carbide field-effect transistor of the present application can reduce the preparation cost of the silicon carbide field-effect transistor by transferring the silicon carbide bonding layer in the silicon carbide epitaxial layer to a low-cost second silicon carbide substrate, and recover the higher-quality first silicon carbide substrate for reuse. This method of reducing the cost of the silicon carbide substrate further reduces the preparation cost of the silicon carbide field-effect transistor, allowing the silicon carbide field-effect transistor to be used on a large scale.

[0121] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for preparing a silicon carbide field effect transistor, characterized in that: The method comprises: Providing a first silicon carbide substrate, and epitaxially growing a silicon carbide epitaxial layer on the first silicon carbide substrate; Injecting light ions into the silicon carbide epitaxial layer, the light ions forming an ion accumulation region in the silicon carbide epitaxial layer, so that the silicon carbide epitaxial layer sequentially forms a silicon carbide thin film layer, the ion accumulation region and a silicon carbide bonding layer; Providing a second silicon carbide substrate, and performing conductive treatment on a surface where the second silicon carbide substrate and the silicon carbide bonding layer are in contact with each other; Wafer bonding the second silicon carbide substrate to the silicon carbide bonding layer; The silicon carbide bonding layer and the ion accumulation region are peeled off to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer and the ion accumulation region, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, and the first substrate structure is recycled; A field effect transistor is prepared based on the second substrate structure to obtain a silicon carbide field effect transistor.

2. The preparation method according to claim 1, characterized in that: After the silicon carbide bonding layer and the ion accumulation region are peeled off to obtain a first substrate structure formed by the first silicon carbide substrate, the silicon carbide thin film layer and the ion accumulation region, and a second substrate structure formed by the second silicon carbide substrate and the silicon carbide bonding layer, the method further includes: Performing a quality recovery process on the silicon carbide bonding layer in the second substrate structure and performing a thinning process on a side of the second silicon carbide substrate away from the silicon carbide bonding layer to obtain a target silicon carbide substrate; The method of preparing a field effect transistor based on the second substrate structure to obtain a silicon carbide field effect transistor comprises: A field effect transistor is prepared based on the target silicon carbide substrate to obtain a silicon carbide field effect transistor.

3. The preparation method according to claim 2, characterized in that: The performing quality recovery processing on the silicon carbide bonding layer in the second substrate structure includes: forming a carbon film on a surface of the second substrate structure; Performing annealing treatment on the second substrate structure, wherein the annealing temperature is 1700-2000° C. and the annealing time is 0.5-5 hours; The second substrate structure after the annealing treatment is post-processed to remove the carbon film on the surface of the second substrate structure and the defective layer on the silicon carbide bonding layer, thereby restoring the quality of the silicon carbide bonding layer in the second substrate structure.

4. The preparation method according to claim 1, characterized in that: The recycling of the first substrate structure comprises: performing thermal oxidation treatment on the first substrate structure; removing the oxide layer in the first substrate structure after thermal oxidation treatment; The silicon carbide surface in the first substrate structure with the oxide layer removed is polished to obtain a silicon carbide substrate.

5. The preparation method according to claim 1, characterized in that: The thickness of the silicon carbide epitaxial layer is 10 μm-20 μm, and the concentration of doped ions in the silicon carbide epitaxial layer is 1E12-1E15 / cm 3 , wherein the doping ions are at least one of nitrogen and phosphorus.

6. The preparation method according to claim 1, characterized in that: The light ions include at least one of hydrogen ions and helium ions, and the implantation dose of the light ions is 1E17 / cm 2 -1E20 / cm 2 , the injection energy is 1MeV-3MeV.

7. The preparation method according to claim 1, characterized in that: The first silicon carbide substrate is an N-type silicon carbide substrate.

8. The preparation method according to claim 1, characterized in that: The second silicon carbide substrate is any one of a test-grade, mixed crystal, and polycrystalline substrate.

9. The preparation method according to claim 1, characterized in that: The step of performing conductive treatment on the surface where the second silicon carbide substrate and the silicon carbide bonding layer are in contact with each other comprises: Doping ions are implanted into a first surface of the silicon carbide bonding layer opposite to the second silicon carbide substrate, and into a second surface of the second silicon carbide substrate opposite to the silicon carbide bonding layer, so as to perform conductive treatment on surfaces where the second silicon carbide substrate and the silicon carbide bonding layer are in contact with each other.

10. The preparation method according to claim 9, characterized in that: The doping ions include at least one of nitrogen ions and phosphorus ions, and the implantation dose of the doping ions is 1E13-1E15 / cm 2 The implantation energy of the doping ions is 5keV-30keV.

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