Memory interface module and method for memory interface module

Abstract

The present application provides a memory interface module and a method for the memory interface module, an electronic device, and a non-transitory computer-readable storage medium. Multiple external memories comply with multiple different protocols. The memory interface module comprises a configuration register, a sequence generator, a signal-generating receiver, and multiple external memory interfaces. The configuration register is configured to receive a configuration instruction and configuration data from a main processor and store the configuration data. The sequence generator is configured to generate a counting sequence on the basis of the configuration data stored in the configuration register. The signal-generating receiver is configured to receive a read / write instruction of the main processor, and on the basis of the configuration data stored in the configuration register and the counting sequence, output a control signal to the external memories by means of the multiple external memory interfaces. On the basis of the embodiments, the compatibility of the memory interface module is improved.

Description

Memory interface module and method for memory interface module Technical Field

[0001] The present application relates to the field of storage, and in particular, to a memory interface module and a method for the memory interface module, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] When a chip host needs to expand its storage, it must connect to external memory through the host's memory interface module. Due to varying application scenarios, memory interface modules often need to be compatible with different types of external memory. Even the same type of external memory often has different read and write timing requirements depending on the manufacturer.

[0003] The inventors of this application discovered that existing memory interface modules typically use a state machine to split the read and write process into multiple stages when generating read and write signals, and use digital logic to control the signal flipping within each stage. This approach has certain limitations. For example, if the read and write protocol of a certain external memory requires more stages or if the signal demand in a certain stage exceeds a set threshold, the memory interface module will no longer be compatible with this external memory.

[0004] Summary of the Invention

[0005] The present application aims to propose a memory interface module and a method, an electronic device and a non-transitory computer-readable storage medium for use in the memory interface module, so as to solve the compatibility problem of the memory interface module.

[0006] According to one aspect of the present application, a memory interface module is proposed, which is used to connect a main processor and multiple external memories, and the multiple external memories comply with multiple different protocols. The memory interface module includes a configuration register, a sequencer, a signal generator receiver and multiple external memory interfaces, wherein: the configuration register is configured to receive configuration instructions and configuration data from the main processor and store the configuration data; the sequencer is configured to generate a counting sequence according to the configuration data stored in the configuration register; the signal generator receiver is configured to receive read and write instructions from the main processor, and output control signals to the external memories through the multiple external memory interfaces according to the configuration data and the counting sequence stored in the configuration register.

[0007] According to some embodiments, the configuration data includes a counting period of the sequence generator and a sequence clock frequency division coefficient of the sequence generator, and the sequence generator is configured to generate a counting sequence according to the sequence clock frequency division coefficient and the counting period.

[0008] According to some embodiments, the configuration data also includes the type of external memory of the memory interface module and the timing of the read and write signals, and the signal generator receiver is further configured to perform read and write operations on the external memory through the multiple external memory interfaces based on the type of the external memory, the timing of the read and write signals and the counting sequence generated by the sequencer.

[0009] According to some embodiments, the signal generator receiver is further configured to start, pause and / or reset the sequencer according to the configuration data stored in the configuration register.

[0010] According to some embodiments, the signal generator receiver is further configured to receive transmission error information from the external memory, and send the transmission error information to the main processor.

[0011] According to one aspect of the present application, a method for a memory interface module is proposed, wherein the memory interface module is used to connect a main processor and multiple external memories, and the multiple external memories comply with multiple different protocols. The method includes: receiving configuration instructions from the main processor and storing configuration data according to the configuration instructions; receiving read and write instructions from the main processor and generating a counting sequence according to the configuration data and the read and write instructions; receiving read and write instructions from the main processor and outputting control signals to the multiple external memories according to the counting sequence.

[0012] According to some embodiments, the configuration data includes a counting period of the sequence generator and a sequence clock division coefficient of the sequence generator, the memory interface module includes a sequence generator, and generating a counting sequence according to the configuration data includes: the sequence generator generates a counting sequence according to the sequence clock division coefficient and the counting period.

[0013] According to some embodiments, the configuration data also includes the type of external memory of the memory interface module and the timing of the read and write signals. The memory interface module also includes a signal generator receiver and multiple external memory interfaces. The receiving of read and write instructions from the main processor and outputting control signals to the multiple external memories according to the counting sequence includes: the signal generator receiver receives the read and write instructions from the main processor and outputs control signals to the multiple external memories according to the type of the external memory, the timing of the read and write signals and the counting sequence.

[0014] According to some embodiments, the method further includes: the signal generator receiver starting, pausing and / or resetting the sequencer according to a control instruction of the main processor and a feedback signal from the external memory.

[0015] According to some embodiments, the method further includes: the signal generating receiver receiving transmission error information sent from the external memory, and sending the transmission error information to the main processor.

[0016] According to one aspect of the present application, an electronic device is proposed, comprising: a processing unit; and a storage unit storing a computer program, wherein when the computer program is executed by the processing unit, the processing unit executes the method described in any of the previous embodiments.

[0017] According to one aspect of the present application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the instructions are executed by a processor, the processor executes the method as described in any of the above embodiments.

[0018] According to the embodiments of the present application, by generating a variety of configurable read and write signals, compatibility with different types of external memories is maximized, thereby improving the compatibility between the chip host and the external memory.

[0019] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. By describing the exemplary embodiments in detail with reference to the accompanying drawings, the above and other objects, features and advantages of the present application will become more apparent.

[0021] FIG1 shows a structural block diagram of a chip host according to an exemplary embodiment of the present application.

[0022] FIG2 shows a structural block diagram of a memory interface module according to an exemplary embodiment of the present application.

[0023] FIG3 shows a flow chart of a method for a memory interface module according to an example embodiment of the present application.

[0024] FIG4 shows a schematic diagram of the internal structure of a memory interface module according to an exemplary embodiment of the present application.

[0025] FIG5 shows a schematic diagram of a data writing process of a Nand Flash of a memory interface module according to an exemplary embodiment of the present application.

[0026] FIG6 shows an electronic device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical figures in the drawings represent identical or similar parts, and thus repeated description thereof will be omitted.

[0028] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices or operations may be employed. In these cases, well-known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0029] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0030] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0031] As previously mentioned, when a chip host needs to expand its storage, it must connect to external memory through the host's memory interface module. The increasing variety of external memory devices, as well as the varying timing requirements of external memory devices produced by different manufacturers, have placed higher demands on the compatibility and flexibility of the host's memory interface module. Existing memory interface modules typically use a state machine to split the read and write process into multiple stages when generating read and write signals, and use digital logic to control the signal flipping in each stage. However, if the read and write protocol of a certain external memory device requires more stages or if a signal requirement in a particular stage exceeds a set threshold, the memory interface module will no longer be compatible with this external memory device.

[0032] In order to improve the compatibility of the memory interface module, according to the embodiment of the present application, by generating a variety of configurable read and write signals, compatibility with different types of external memories is maximized, thereby improving the compatibility between the chip host and the external memory.

[0033] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0034] FIG1 shows a block diagram of a chip host according to an exemplary embodiment of the present application. The chip host shown in FIG1 includes a main processor 101, a memory interface module 103, and an external memory 105. The memory interface module 103 is used to connect the main processor 101 to multiple external memories 105, each of which complies with multiple different protocols. The memory interface module 103 performs read and write operations on the external memories 105 based on read and write instructions issued by the main processor 101.

[0035] According to some embodiments of the present application, external memory 105 includes flash memory. Flash memory (FLASH) is a form of electrically erasable programmable read-only memory (EEPROM) that can be erased or written to multiple storage locations in a single programming operation. Flash memory is a type of non-volatile memory commonly used in memory cards, USB flash drives, mobile phones, and the like.

[0036] There are several types of flash memory, including NOR FLASH, NAND FLASH, and SERIAL FLASH. NOR FLASH has longer erase and write times but allows random access to any location, making it suitable for storing infrequently updated program code, such as a computer's BIOS. Compared to NOR FLASH, NAND FLASH offers faster erase and write times, higher density, and a longer lifespan. However, it only allows sequential access to data, making it suitable for high-capacity storage devices. SERIAL FLASH is a small, low-power flash memory with the advantage of requiring fewer wires to connect to the system, saving pins, board space, and power.

[0037] Figure 2 shows a structural block diagram of a memory interface module according to an exemplary embodiment of the present application. The memory interface module shown in Figure 2 is used to connect the main processor 101 and multiple external memories 105. The multiple external memories 105 comply with multiple different protocols. The memory interface module 103 includes a configuration register 1031, a sequence generator 1033, a signal generator receiver 1035 and multiple external memory interfaces 1037.

[0038] According to an embodiment of the present application, the configuration register 1031 is configured to receive configuration instructions and configuration data from the main processor and store the configuration data; the sequence generator 1033 is configured to receive read and write instructions from the main processor 101 and generate a counting sequence based on the read and write instructions and the configuration data stored in the configuration register; the signal generator receiver 1035 is configured to receive read and write instructions from the main processor and output control signals to the external memory 105 through the multiple external memory interfaces 1037 based on the configuration data and the counting sequence stored in the configuration register.

[0039] According to some embodiments, the configuration data includes a counting period of the sequence generator 1033 and a sequence clock frequency division coefficient of the sequence generator 1033 .

[0040] In a specific embodiment, the sequence generator 1033 is configured to generate a counting sequence according to the sequence clock frequency division coefficient and the counting period.

[0041] According to some other embodiments, the configuration data further includes the type of the external memory 103 of the memory interface module 103 and the timing of the read and write signals.

[0042] In a specific embodiment, the signal generator receiver 1035 is further configured to perform read and write operations on the external memory 105 through the multiple external memory interfaces 1037 according to the type of the external memory, the timing of the read and write signals, and the counting sequence generated by the sequencer.

[0043] According to some embodiments, the timing of the read / write signal includes a count value sequence of the count sequence corresponding to a jump of a chip select signal and / or a count value sequence of the count sequence corresponding to a jump of a read / write enable signal.

[0044] According to an embodiment of the present application, the signal generator receiver 1035 is further configured to receive transmission error information from the external memory 105 and send the transmission error information to the main processor 101 .

[0045] In a specific embodiment, the signal generation receiver 1035 sends the received transmission error information to the main processor 101 through the configuration register 1031 .

[0046] In an embodiment of the present application, the signal generator receiver 1035 is also configured to start, pause and / or reset the sequencer according to the control instructions of the main processor and the feedback signal of the external memory. In other specific embodiments, the signal generator receiver 1035 sends the received transmission error information directly to the main processor 101.

[0047] According to the example shown in FIG2 , a memory interface module is proposed to be compatible with external memory modules of different types and manufacturers, so that users can generate corresponding control signals to read and write data according to the read and write timing requirements of the external memory.

[0048] FIG3 shows a flow chart of a method for a memory interface module according to an exemplary embodiment of the present application. According to an embodiment of the present application, the memory interface module is used to connect a main processor and multiple external memories.

[0049] As shown in FIG3 , in step S301 , a configuration instruction from the main processor is received, and configuration data is stored according to the configuration instruction;

[0050] In step S303, a read / write instruction is received from the main processor, and a counting sequence is generated according to the configuration data and the read / write instruction;

[0051] In step S305, a read / write instruction is received from the main processor, and control signals are output to the plurality of external memories according to the counting sequence.

[0052] According to some embodiments, the configuration data includes a count cycle of a sequencer and a sequence clock frequency division coefficient of the sequencer, and the memory interface module includes the sequencer.

[0053] In a specific example, generating the counting sequence according to the configuration data includes a sequence generator generating the counting sequence according to a sequence clock frequency division coefficient, a counting period, and a start instruction of a signal generation receiver.

[0054] According to other embodiments, the configuration data further includes the type of the external memory of the memory interface module and the timing of the read and write signals. The memory interface module further includes a signal generator and receiver and a plurality of external memory interfaces.

[0055] In a specific embodiment, receiving the read and write instructions from the main processor and outputting control signals to the multiple external memories according to the counting sequence includes a signal generator receiver receiving the read and write instructions from the main processor and outputting control signals to the multiple external memories according to the type of the external memory, the timing of the read and write signals and the counting sequence.

[0056] According to an embodiment of the present application, the timing of the read / write signal includes a count value sequence of the count sequence corresponding to a jump of the chip select signal and / or a count value sequence of the count sequence corresponding to a jump of the read / write enable signal.

[0057] According to some other embodiments, the signal generator receiver further receives transmission error information from the external memory, and sends the transmission error information to the main processor.

[0058] In a specific embodiment, the transmission error information received by the signal generating receiver is sent to the main processor via the configuration register.

[0059] In some other specific embodiments, the transmission error information received by the signal generating receiver is directly sent to the main processor.

[0060] According to an embodiment of the present application, the method shown in FIG3 further includes the signal generating receiver starting, pausing and / or resetting the sequencer according to the configuration data stored in the configuration register.

[0061] According to the embodiment shown in FIG3 , by configuring read and write signals that are not subject to phase restrictions and threshold restrictions, the memory interface module can be compatible with external memories of different types and from different manufacturers, thereby improving the compatibility of the memory interface module.

[0062] Figure 4 shows a schematic diagram of the internal structure of a memory interface module according to an exemplary embodiment of the present application. The memory interface module shown in Figure 4 includes a configuration register, a sequencer, a signal generator receiver, and an external memory interface corresponding to different external memories.

[0063] According to the memory interface module shown in FIG4 , when the main processor performs read and write operations,

[0064] First, the main processor sends configuration instructions to the configuration register according to the type and read / write mode of the external memory. The configuration data includes the serial clock frequency division coefficient, the count cycle generation count sequence, the type of external memory, and the timing of the external memory read and write signals.

[0065] Then, the main processor sends read and write commands and corresponding data to the signal generator receiver; the signal generator receiver starts, pauses and resets the sequencer according to the configuration data in the configuration register;

[0066] Then, the sequence generator generates a counting sequence according to the start, pause and reset instructions of the signal generation receiver, the sequence clock frequency division coefficient and the counting cycle.

[0067] Finally, during the write process, the signal generator receiver generates the control signal for the required output according to the sequence generated by the sequence generator. Alternatively, during the read process, the signal generator receiver sends the read data to the main processor.

[0068] According to the example shown in FIG4 , a memory interface module is proposed to be compatible with external memory modules of different types and manufacturers, so that users can generate corresponding control signals to read and write data according to the read and write timing requirements of the external memory.

[0069] Figure 5 shows a schematic diagram of the data writing process of a Nand Flash memory interface module according to an exemplary embodiment of the present application. As shown in Figure 5, the NCE signal is the Nand Flash chip select signal, and pulling it low indicates chip select; the NWE signal is the Nand Flash write enable signal, and pulling it low indicates writing.

[0070] During the write process, before the transmission begins, the main processor first sends the sequence number of each signal (for example, NWE signal and NCE signal) that needs to jump to the configuration register according to the write requirements of Nand Flash;

[0071] After the formal transmission begins, the signal NCE is pulled low, the transmitted address is valid, and the sequence generator also starts counting; when the count is 5, the threshold of NWE jump is reached, and the signal generator receiver pulls the NWE signal low; when the count is 8, the write data jump point is reached, and the signal generator receiver outputs the corresponding write data; when the count reaches 16, the threshold of NWE is reached, and the signal generator receiver pulls the NWE signal high; when the count reaches 17, the signal generator receiver invalidates the write data; when the count reaches 21; the threshold of NCE signal is reached, the write process ends, the signal generator receiver pulls the NCE signal high and resets the sequence generator to end the write.

[0072] According to the embodiment shown in FIG5 , by configuring read and write signals that are not subject to phase restrictions and threshold restrictions, the memory interface module can be compatible with external memories of different types and from different manufacturers, thereby improving the compatibility of the memory interface module.

[0073] FIG6 shows an electronic device according to an exemplary embodiment of the present application. The electronic device 200 according to this embodiment of the present application is described below with reference to FIG6. The electronic device 200 shown in FIG6 is merely an example and should not limit the functionality and scope of use of the embodiments of the present application.

[0074] As shown in FIG6 , electronic device 200 is implemented as a general-purpose computing device. Components of electronic device 200 may include, but are not limited to, at least one processing unit 210, at least one storage unit 220, a bus 230 connecting various system components (including storage unit 220 and processing unit 210), a display unit 240, and the like.

[0075] The storage unit stores program codes that can be executed by the processing unit 210, so that the processing unit 210 performs the methods described in this specification according to various exemplary embodiments of the present application. For example, the processing unit 210 can perform the method shown in FIG1 .

[0076] The storage unit 220 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 2201 and / or a cache memory unit 2202 , and may further include a read-only memory unit (ROM) 2203 .

[0077] The storage unit 220 may also include a program / utility 2204 having a set (at least one) of program modules 2205, such program modules 2205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0078] Bus 230 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0079] The electronic device 200 can also communicate with one or more external devices 300 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 200, and / or any device that enables the electronic device 200 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 250. Furthermore, the electronic device 200 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 260. The network adapter 260 can communicate with other modules of the electronic device 200 via the bus 230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device 200, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0080] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described here can be implemented by software or by combining software with necessary hardware. The technical solution according to the embodiment of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiment of the present application.

[0081] The software product can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0082] Computer-readable storage media may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0083] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0084] The computer-readable medium carries one or more programs. When the one or more programs are executed by the device, the computer-readable medium implements the aforementioned functions.

[0085] Those skilled in the art will appreciate that the modules described above can be distributed in the device according to the description of the embodiment, or can be modified accordingly to be used in one or more devices that are different from the embodiment. The modules of the above embodiment can be combined into one module or further divided into multiple submodules.

[0086] According to an embodiment of the present application, a computer program is provided, including a computer program or instructions. When the computer program or instructions are executed by a processor, the method described above can be executed.

[0087] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present application, the specific implementation methods, and the scope of application of the present application, all fall within the scope of protection of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. A memory interface module, characterized in that: The memory interface module is used to connect the main processor and multiple external memories, and the multiple external memories comply with multiple different protocols. The memory interface module includes a configuration register, a sequence generator, a signal generation receiver and multiple external memory interfaces, wherein: The configuration register is configured to receive configuration instructions and configuration data from the main processor and store the configuration data; The sequence generator is configured to receive a read / write instruction from the main processor and generate a counting sequence according to the read / write instruction and the configuration data stored in the configuration register; The signal generator receiver is configured to receive the read and write instructions of the main processor, and output a control signal to the external memory through the multiple external memory interfaces according to the configuration data stored in the configuration register and the counting sequence.

2. The memory interface module according to claim 1, wherein: The configuration data includes a counting period of the sequence generator and a sequence clock frequency division coefficient of the sequence generator, and the sequence generator is configured to generate a counting sequence according to the sequence clock frequency division coefficient and the counting period.

3. The memory interface module according to claim 2, wherein: The configuration data also includes the type of external memory of the memory interface module and the timing of the read and write signals. The signal generator receiver is also configured to perform read and write operations on the external memory through the multiple external memory interfaces according to the type of the external memory, the timing of the read and write signals and the counting sequence generated by the sequence generator.

4. The memory interface module according to claim 1, wherein: The signal generator receiver is further configured to start, pause and / or reset the sequencer according to the configuration data stored in the configuration register.

5. The memory interface module according to claim 1, wherein: The signal generation receiver is further configured to receive transmission error information from the external memory, and send the transmission error information to the main processor.

6. A method for a memory interface module, characterized in that: The memory interface module is used to connect the main processor and multiple external memories, and the multiple external memories comply with multiple different protocols. The method includes: receiving a configuration instruction from the main processor and storing configuration data according to the configuration instruction; receiving a read / write instruction from the main processor and generating a counting sequence according to the configuration data and the read / write instruction; The read and write instructions from the main processor are received, and control signals are output to the plurality of external memories according to the counting sequence.

7. The method according to claim 6, characterized in that The configuration data includes a counting period of the sequence generator and a sequence clock frequency division coefficient of the sequence generator, the memory interface module includes a sequence generator, and generating a counting sequence according to the configuration data includes: The sequence generator generates a counting sequence according to the sequence clock frequency division coefficient and the counting period.

8. The method according to claim 7, characterized in that The configuration data also includes the type of external memory of the memory interface module and the timing of read and write signals. The memory interface module also includes a signal generator receiver and multiple external memory interfaces. The receiving of read and write instructions from the main processor and outputting control signals to the multiple external memories according to the counting sequence includes: The signal generator receiver receives the read and write instructions from the main processor, and outputs control signals to the plurality of external memories according to the type of the external memories, the timing of the read and write signals, and the counting sequence.

9. The method according to claim 8, characterized in that The method further comprises: The signal generation receiver starts, pauses and / or resets the sequence generator according to the control instruction of the main processor and the feedback signal of the external memory.

10. The method according to claim 8, characterized in that The method further comprises: The signal generating receiver receives the transmission error information sent from the external memory, and sends the transmission error information to the main processor.

11. An electronic device, comprising: Processing unit; as well as A storage unit storing a computer program, which, when executed by the processing unit, enables the processing unit to execute the method according to any one of claims 6 to 10.

12. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, causes the processor to execute the method according to any one of claims 6 to 10.

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