Memory access instruction processing method and communication device

Abstract

Embodiments of the present disclosure provide a memory access instruction processing method and a communication device. The method comprises: acquiring a memory access instruction, and parsing the memory access instruction to obtain a parsing result; according to instruction type information of the memory access instruction in the parsing result, allocating for the memory access instruction an instruction processing queue adapted to the memory access instruction; determining a physical address corresponding to each memory access instruction in the instruction processing queue; determining an address access sequence of the physical address corresponding to each memory access instruction in the instruction processing queue, and executing an instruction processing policy for the memory access instruction corresponding to the access sequence conforming to a preset memory model.

Description

Memory access instruction processing method and communication device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of Chinese patent application 202310797675.2 filed on June 30, 2023, and all the disclosed contents thereof are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of communication technology, and in particular to a method for processing a memory access instruction and a communication device. Background Art

[0004] Due to the complexity of memory access and the uncertainty of storage system access latency, the processor's execution of memory access instructions can become a performance bottleneck in many application scenarios. For example, DPDK network communication, where memory accesses account for the majority of the runtime, is considered a memory-intensive application. In such applications, the processor's memory access performance significantly impacts the performance of the communication device, ultimately affecting the user experience.

[0005] Therefore, how to improve the processor's processing efficiency for memory access instructions to enhance the overall performance of communication equipment in memory-intensive applications has become a hot topic being studied by those skilled in the art.

[0006] Summary of the Invention

[0007] The main purpose of the embodiments of the present disclosure is to provide a method for processing memory access instructions and a communication device, aiming to improve the processing efficiency of the processor for memory access instructions, so as to enhance the overall performance of the communication device in memory-intensive applications.

[0008] In a first aspect, an embodiment of the present disclosure provides a method for processing a memory access instruction, characterized in that the method includes:

[0009] Obtain memory access instructions, parse the memory access instructions, and obtain parsing results;

[0010] Determine an instruction processing queue adapted to the memory access instruction according to instruction type information of the memory access instruction in the parsing result;

[0011] Determine the physical address corresponding to each memory access instruction in the instruction processing queue;

[0012] Determine the address access order of the physical addresses corresponding to each memory access instruction in the instruction processing queue, and execute the instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model.

[0013] In a second aspect, an embodiment of the present disclosure further provides a communication device, comprising: a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the aforementioned method for processing memory access instructions are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] FIG1 is a flowchart of a method for processing a memory access instruction provided by an embodiment of the present disclosure;

[0016] FIG2 is a schematic diagram of a partial architecture of a processor that executes a method for processing a memory access instruction provided by an embodiment of the present disclosure;

[0017] FIG3 is a diagram of instruction recording and submission logic in a method for processing memory access instructions provided by an embodiment of the present disclosure;

[0018] FIG4 is an instruction management logic diagram of a method for processing memory access instructions provided by an embodiment of the present disclosure;

[0019] FIG5 is a diagram of the transmission logic in the method for processing memory access instructions provided by an embodiment of the present disclosure;

[0020] FIG6 is a schematic diagram of a framework structure of a communication device provided in an embodiment of the present disclosure;

[0021] FIG7 is a schematic diagram of the framework structure of a device for processing memory access instructions provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0023] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0024] It should be understood that the terms used in this disclosure are only for the purpose of describing particular embodiments and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0025] The following embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0026] Please refer to FIG1 , which is a flowchart of the steps of a method for processing a memory access instruction provided by an embodiment of the present disclosure.

[0027] As shown in FIG1 , the method for processing a memory access instruction is applied to a communication device and executed by a processor disposed in the communication device. The method for processing a memory access instruction includes steps S101 to S104 .

[0028] Step S101: Acquire a memory access instruction, and parse the memory access instruction to obtain a parsing result.

[0029] Memory access instructions include load instructions and store instructions. Load instructions are used to obtain data from the memory, and store instructions are used to write data to the memory. The memory includes but is not limited to double data rate synchronous dynamic random access memory, also known as DDR memory.

[0030] The processor obtains data processing instructions from an instruction storage system of the communication device, filters out memory access instructions from the data processing instructions, and then parses the memory access instructions to determine whether the corresponding memory access instructions are store instructions or load instructions.

[0031] As shown in Figure 2, for example, the processor includes an analysis unit 101, a sending unit 102, an execution unit 103, and a non-blocking cache unit 105. The analysis unit 101 includes an instruction fetch front end and a decoding unit. During data processing by a communication device, the instruction fetch front end of the analysis unit 101 of the processor obtains data processing instructions from the instruction storage system of the communication device, filters out memory access instructions from the data processing instructions, and transmits the memory access instructions to the decoding unit for analysis and processing. There can be at least one decoding unit, and illustratively, there are two decoding units, and the two decoding units operate independently and in parallel, thereby efficiently implementing decoding analysis of memory access instructions. Exemplarily, the analysis unit 101 is also provided with a transmit cache unit, and the analyzed memory access instructions can be temporarily stored in the transmit cache unit.

[0032] The processor may determine, based on the parsing result of the decoding analysis by the decoding unit, whether the analyzed data processing instruction is a store instruction or a load instruction.

[0033] Step S102: allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result.

[0034] Exemplarily, the processor sets different instruction processing queues for different types of data processing instructions. After determining the instruction type information of the memory access instruction based on the analysis results, the processor adapts the corresponding instruction processing queue for the memory access instruction according to the instruction type information, thereby utilizing the instruction processing queue to achieve effective management of each memory access instruction.

[0035] As shown in FIG2 , for example, the execution unit 103 of the processor is provided with an instruction processing queue, which includes a load queue and a store queue. The load queue is used to manage the load instructions in the memory access instructions. For example, the load queue is used to record the instruction attribute information corresponding to the load instruction. The processor can obtain the execution status of the corresponding load instruction based on the instruction attribute information, thereby effectively managing the load instruction. The store queue is used to manage the load instructions in the memory access instructions. For example, the store queue is used to record the instruction attribute information corresponding to the store instruction. The processor can obtain the execution status of the corresponding store instruction based on the instruction attribute information, thereby effectively managing the store instruction.

[0036] After analyzing and obtaining instruction type information, analysis unit 101 determines whether each analyzed memory access instruction is a store instruction or a load instruction based on the type information. The corresponding memory access instruction is then transmitted to execution unit 103 via emission unit 102. Execution unit 103 then records the instruction attributes corresponding to the memory access instruction in the load queue or store queue corresponding to the memory access instruction. Different instruction processing queues record and analyze different types of memory access instructions, ensuring that instructions of different types are executed in an orderly manner.

[0037] Illustratively, during the process of transmitting instructions to the execution unit 103 , the emission unit 102 is further configured to analyze the dependency relationship between the memory access instructions to ensure that the execution unit 103 executes the memory access instructions in an orderly manner.

[0038] In some implementations, allocating an instruction processing queue adapted for the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0039] Recording the memory access instruction into the instruction processing queue adapted to the memory access instruction;

[0040] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction, and the instruction processing queue is updated.

[0041] Exemplarily, the instruction processing queue includes a load queue and a storage queue. When the current memory access instruction is determined to be a storage instruction based on the instruction type information of the parsed memory access instruction, the instruction name corresponding to the storage instruction is recorded in the storage queue. When the current memory access instruction is determined to be a load instruction based on the instruction type information of the parsed memory access instruction, the instruction name corresponding to the load instruction is recorded in the load queue.

[0042] As shown in FIG3 , for example, when the instruction type information determines that the corresponding memory access instruction is a store instruction, the store instruction is recorded in the store queue of the execution unit 103, and the head and tail pointers of the store queue are used to record the position of the store instruction in the store queue. Similarly, when the instruction type information determines that the corresponding memory access instruction is a load instruction, the load instruction is recorded in the load queue of the execution unit 103, and the head and tail pointers of the load queue are used to record the position of the load instruction in the load queue.

[0043] After the memory access instruction is added to the corresponding instruction processing queue, the instruction attribute information corresponding to the memory access instruction recorded in each instruction processing queue is obtained. The instruction attribute information recorded in different instruction processing queues is different. After the instruction attribute information corresponding to the memory access instruction recorded in the instruction processing queue is recorded in the corresponding instruction processing queue, the instruction processing queue is updated and the instruction processing queue that completes the instruction attribute information recording is used as the final instruction processing queue.

[0044] Exemplarily, the instruction attribute information includes but is not limited to the valid bit of the table entry (valid), the access address of the instruction (address), the valid byte accessed (byte_vld), the virtual address bit (virtual), whether the load instruction is executed (exec), whether the load instruction violates the memory model (order), whether the load instruction is dependent on the storage instruction address (st_mask), the feedforward data valid bit (st_fw) and the index of the feedforward storage queue (st_idx), the data used for storage (data), the information indicating the submission of the storage instruction (commit) and the successful completion information of the storage instruction (succ).

[0045] As shown in Figure 4, the loadable queue is provided with a plurality of instruction attribute storage entries, each entry representing the instruction attribute of the load instruction stored in the load queue, wherein the instruction attributes recorded in the load queue include but are not limited to the entry valid bit (valid), the access address of the instruction (address), the valid byte accessed (byte_vld), the virtual address bit (virtual), whether the load instruction is executed (exec), whether the load instruction violates the memory model (order), whether the load instruction is dependent on the store instruction address (st_mask), the feedforward data valid bit (st_fw) and the index of the feedforward store queue (st_idx).

[0046] The storage queue is provided with a plurality of instruction attribute storage entries, each entry representing the instruction attribute of the storage instruction stored in the storage queue, wherein the instruction attributes recorded in the storage queue include but are not limited to the entry valid bit (valid), the access address of the instruction (address), the valid byte accessed (byte_vld), the virtual address bit (virtual), the entry valid bit (valid), the access address of the instruction (address), the valid byte accessed (byte_vld), and the virtual address bit (virtual).

[0047] In some implementations, recording each of the memory access instructions into the instruction processing queue adapted for each of the memory access instructions includes:

[0048] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issue channels within a unit cycle;

[0049] detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0050] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0051] Exemplarily, detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0052] Determining a target instruction transmitting channel from at least two instruction transmitting channels according to the instruction transmitting priorities of the instruction transmitting channels;

[0053] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with a historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0054] When the memory access instruction in the target instruction issuance channel has no data dependency relationship with the historical memory access instruction and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel meets the instruction issuance condition.

[0055] For example, the instruction launch channel is also called the instruction launch slot. There are two instruction launch slots in the processor. Different instruction launch slots have different launch priorities. Therefore, before the storage instruction is launched, it is necessary to ensure that the memory access instruction in the launch slot with a higher launch priority is sent, and it is also necessary to detect whether there is a data dependency between the sent instruction and the historical memory access instruction. When there is a data dependency, it indicates that the current memory access instruction does not meet the instruction launch conditions, otherwise, it meets the conditions.

[0056] For example, the emission priority of emission slot 0 is higher than that of emission slot 1, that is, when there are memory access instructions to be emitted in both emission slot 0 and emission slot 1, the memory access instruction in emission slot 0 has the right to be emitted to the execution unit 103 first. When there is no instruction in emission slot 0, the memory access instruction in emission slot 1 can be emitted. Before the memory access instruction to be emitted in emission slot 0 or emission slot 1 is emitted, it is necessary to check whether the instruction in the corresponding emission slot has a data dependency relationship with the historical memory access instruction. According to the register busy table, it can be determined whether the current memory access instruction has a register dependency relationship with the previous memory access instruction. When the memory access instruction to be emitted in the corresponding emission slot has no data dependency relationship with the historical memory access instruction, the emission slot with a higher priority will first send the memory access instruction to the execution unit 103, and then the emission slot with a higher priority will send the cache instruction to the execution unit 103, so that the instruction attribute information corresponding to the cache instruction can be recorded in the corresponding instruction processing queue in the execution unit 103.

[0057] In some implementations, the method further includes: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stopping parsing the acquired memory access instructions.

[0058] For example, each instruction processing queue has a limited capacity for recording instructions. If the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, indicating that the current processor is in an overloaded state, the processor stops parsing the acquired memory access instructions.

[0059] Step S103: determining the physical address corresponding to each of the memory access instructions in the instruction processing queue.

[0060] Exemplarily, each memory access instruction corresponds to a physical address, which is used by the memory access instruction to access data. Therefore, during the execution of the memory access instruction, it is necessary to obtain the physical address corresponding to each memory access instruction in the instruction processing queue.

[0061] In some implementations, determining the physical address corresponding to each memory access instruction in the instruction processing queue includes:

[0062] Determining a virtual address of each memory access instruction according to instruction attribute information of each memory access instruction in the instruction processing queue;

[0063] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0064] Exemplarily, the instruction attribute information corresponding to each memory access instruction includes the virtual address of the memory access instruction. After the memory access instruction is successfully recorded in the instruction processing queue, the virtual address of the memory access instruction is translated into a physical address and recorded in the queue item of the instruction processing queue.

[0065] Step S104: determining an address access sequence of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and executing an instruction processing strategy for the memory access instructions corresponding to the access sequence that complies with a preset memory model.

[0066] Exemplarily, after obtaining the physical address corresponding to each memory access instruction in the instruction processing queue, the logic for performing a physical address comparison on all recorded memory access instructions in the instruction processing queue is used to check whether the address access sequence of each memory access instruction violates the address access sequence of the memory model. If the address access sequence of the memory access instruction does not violate the address access sequence of the memory model, the corresponding instruction processing strategy is executed based on the instruction type information of the memory access instruction. For example, if the memory access instruction is a load instruction, the processing strategy corresponding to the load instruction is executed; if the memory access instruction is a store instruction, the processing strategy corresponding to the store instruction is executed.

[0067] In some embodiments, executing an instruction processing strategy on the memory access instruction corresponding to the access order conforming to the preset memory model includes:

[0068] determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0069] When it is determined according to the instruction type information that the memory access instruction is a load instruction, obtaining data adapted to the load instruction from a data cache unit according to the load instruction;

[0070] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0071] Exemplarily, memory access instructions include load instructions and store instructions. Different types of memory access instructions have different functions. Therefore, corresponding operations need to be performed according to different memory access instruction types in order for the communication device to operate normally. For example, when the memory access instruction is determined to be a load instruction based on the instruction type information, data adapted to the load instruction is obtained from the data cache unit according to the load instruction, thereby reading the corresponding data from the data cache unit. When the memory access instruction is determined to be a store instruction based on the instruction type information, it is necessary to wait for an instruction submission indication. When the instruction submission indication is obtained, a data storage operation is performed according to the instruction submission indication to store the data in the corresponding memory.

[0072] In some embodiments, the processor is provided with a non-blocking cache unit 105, and the method further includes: if a cache miss occurs in the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed through the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0073] For example, when a load instruction sends a request to the data cache unit, if the corresponding data cannot be obtained, that is, a cache miss occurs in the request sent, the cache miss is managed by the non-blocking cache unit 105 to ensure that subsequent memory accesses can continue to access the data cache unit.

[0074] In some embodiments, the method further includes: obtaining the execution status of the memory access instructions in the instruction processing queue, and determining the memory access instructions that have been executed in the instruction processing queue based on the execution status; and performing instruction release operations on the memory access instructions in the instruction processing queue based on the time sequence in which the executed memory access instructions were recorded in the instruction processing queue.

[0075] For example, after the execution of the memory access instructions in the instruction processing queue is completed, the write-back submission unit 104 obtains the execution status of each memory access instruction in the instruction processing queue, determines the time order in which the memory access instructions that have been executed are recorded in the instruction processing queue according to the execution status, and then performs an instruction release operation on the memory access instruction that has been executed earliest and is recorded in the instruction processing queue to delete the corresponding memory access instruction record from the instruction processing queue, so as to reduce the instruction recording pressure of the instruction processing queue.

[0076] As shown in Figure 3, taking the instruction processing queue as the loading queue as an example, according to the execution status of the loading instructions in the loading queue, there are 3 loading instructions that have been executed in the loading queue. The first one was recorded in the loading queue 1 day ago, the second one was recorded in the loading queue 23 hours ago, and the third one was recorded in the loading queue 20 days ago. The loading instruction with the longest recording time will be released from the loading queue first.

[0077] Referring to FIG. 6 , the present disclosure further provides a communication device 20 , which includes a processor 201 and a memory 202 . The processor 201 and the memory 202 are connected via a bus 203 , such as an I2C (Inter-integrated Circuit) bus.

[0078] Specifically, the processor 201 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0079] The memory 202 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.

[0080] The processor 201 is configured to run a computer program stored in the memory 202 and implement the following steps when executing the computer program:

[0081] Obtaining a memory access instruction, parsing the memory access instruction, and obtaining a parsing result;

[0082] Allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction according to instruction type information of the memory access instruction in the parsing result;

[0083] Determining the physical address corresponding to each of the memory access instructions in the instruction processing queue;

[0084] Determine the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and execute an instruction processing strategy for the memory access instructions corresponding to the access order that complies with a preset memory model.

[0085] In some implementations, allocating an instruction processing queue adapted for the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0086] Recording the memory access instruction into the instruction processing queue adapted to the memory access instruction;

[0087] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

[0088] In some implementations, recording each of the memory access instructions into the instruction processing queue adapted for each of the memory access instructions includes:

[0089] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issue channels within a unit cycle;

[0090] detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0091] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0092] In some embodiments, detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0093] Determining a target instruction transmitting channel from at least two instruction transmitting channels according to the instruction transmitting priorities of the instruction transmitting channels;

[0094] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with a historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0095] When the memory access instruction in the target instruction issuance channel has no data dependency relationship with the historical memory access instruction and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel meets the instruction issuance condition.

[0096] In some implementations, the processor 201 is further configured to: stop parsing the acquired memory access instructions when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value.

[0097] In some implementations, determining the physical address corresponding to each memory access instruction in the instruction processing queue includes:

[0098] Determining a virtual address of each memory access instruction according to instruction attribute information of each memory access instruction in the instruction processing queue;

[0099] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0100] In some embodiments, executing an instruction processing strategy on the memory access instruction corresponding to the access order conforming to the preset memory model includes:

[0101] determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0102] When it is determined according to the instruction type information that the memory access instruction is a load instruction, obtaining data adapted to the load instruction from a data cache unit according to the load instruction;

[0103] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0104] In some implementations, the processor 201 is provided with a non-blocking cache unit, and the processor 201 is further configured to execute:

[0105] If a cache miss occurs during the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed by the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0106] In some implementations, the processor 201 is further configured to execute:

[0107] Acquiring the execution status of the memory access instruction in the instruction processing queue, and determining the memory access instruction that has been executed in the instruction processing queue according to the execution status;

[0108] An instruction release operation is performed on the memory access instructions in the instruction processing queue according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

[0109] It should be noted that, those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the processor of the communication device described above can refer to the corresponding process in the aforementioned corresponding memory access instruction processing method embodiment, and will not be repeated here.

[0110] Referring to FIG. 7 , an embodiment of the present disclosure further provides a device for processing memory access instructions, which is applied to a communication device or a processor.

[0111] As shown in Figure 7, the processing device 300 for memory access instructions includes an instruction parsing module 301, an instruction management module 302, an address conversion module 303 and an instruction processing module 304. Among them, the instruction parsing module 301 is used to obtain the memory access instruction, parse the memory access instruction, and obtain the parsing result. The instruction management module 302 is used to allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction based on the instruction type information of the memory access instruction in the parsing result. The address conversion module 303 is used to determine the physical address corresponding to each of the memory access instructions in the instruction processing queue. The instruction processing module 304 is used to determine the address access order of the physical address corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instruction corresponding to the access order that conforms to the preset memory model.

[0112] In some implementations, allocating an instruction processing queue adapted for the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0113] Recording the memory access instruction into the instruction processing queue adapted to the memory access instruction;

[0114] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

[0115] In some implementations, recording each of the memory access instructions into the instruction processing queue adapted for each of the memory access instructions includes:

[0116] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issue channels within a unit cycle;

[0117] detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0118] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0119] In some embodiments, detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0120] Determining a target instruction transmitting channel from at least two instruction transmitting channels according to the instruction transmitting priorities of the instruction transmitting channels;

[0121] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with a historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0122] When the memory access instruction in the target instruction issuance channel has no data dependency relationship with the historical memory access instruction and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel meets the instruction issuance condition.

[0123] In some implementations, the instruction parsing module 301 is further configured to stop parsing the acquired memory access instructions when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value.

[0124] In some implementations, determining the physical address corresponding to each memory access instruction in the instruction processing queue includes:

[0125] Determining a virtual address of each memory access instruction according to instruction attribute information of each memory access instruction in the instruction processing queue;

[0126] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0127] In some embodiments, executing an instruction processing strategy on the memory access instruction corresponding to the access order conforming to the preset memory model includes:

[0128] determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0129] When it is determined according to the instruction type information that the memory access instruction is a load instruction, obtaining data adapted to the load instruction from a data cache unit according to the load instruction;

[0130] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0131] In some embodiments, the processor is provided with a non-blocking cache unit, and the instruction processing module 304 is further used to perform cache miss management through the non-blocking cache unit if a cache miss occurs in the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction. The cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0132] In some implementations, the instruction management module 302 is further configured to:

[0133] Acquiring the execution status of the memory access instruction in the instruction processing queue, and determining the memory access instruction that has been executed in the instruction processing queue according to the execution status;

[0134] An instruction release operation is performed on the memory access instructions in the instruction processing queue according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

[0135] The embodiments of the present disclosure also provide a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the video data processing method of any embodiment provided in the description of the embodiments of the present disclosure.

[0136] The storage medium may be an internal storage unit of the aforementioned communication device 20, such as a hard disk or memory of the communication device 20. The storage medium may also be an external storage device of the communication device 20, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the communication device 20.

[0137] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware embodiment, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0138] It should be understood that the term "and / or" as used in this disclosure and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system that includes a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "including a..." does not exclude the presence of other identical elements in the process, method, article or system that includes the element.

[0139] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The above description is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present disclosure, and these modifications or replacements should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for processing a memory access instruction, the method comprising: Obtaining a memory access instruction, and parsing the memory access instruction to obtain a parsing result; Allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result; Determining the physical address corresponding to each of the memory access instructions in the instruction processing queue; Determine the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model.

2. The method according to claim 1, wherein: The allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes: Recording the memory access instruction to the instruction processing queue adapted to the memory access instruction; The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

3. The method according to claim 2, wherein: The step of recording each of the memory access instructions into the instruction processing queue adapted to each of the memory access instructions comprises: Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issuance channels within a unit cycle; Detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition; When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

4. The method according to claim 3, wherein: The detecting whether the memory access instruction in each of the instruction issuance channels satisfies the instruction issuance condition includes: Determining a target instruction transmission channel from at least two of the instruction transmission channels according to the instruction transmission priorities of the instruction transmission channels; Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with the historical memory access instruction, and detecting whether there is an idle execution pipeline; When there is no data dependency between the memory access instruction in the target instruction issuance channel and the historical memory access instruction, and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel satisfies the instruction issuance condition.

5. The method according to claim 2, wherein: The method further includes: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stopping parsing the acquired memory access instructions.

6. The method according to claim 1, wherein: The determining of the physical address corresponding to each of the memory access instructions in the instruction processing queue includes: Determining a virtual address of each of the memory access instructions according to instruction attribute information of each of the memory access instructions in the instruction processing queue; The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

7. The method according to claim 1, wherein: The executing instruction processing strategy for the memory access instruction corresponding to the access sequence conforming to the preset memory model includes: Determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction; When it is determined according to the instruction type information that the memory access instruction is a load instruction, acquiring data adapted to the load instruction from a data cache unit according to the load instruction; When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

8. The method according to claim 7, wherein: The processor is provided with a non-blocking cache unit, and the method further comprises: If a cache miss occurs during the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed by the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

9. The method according to claim 1, wherein: The method further comprises: Acquire the execution status of the memory access instruction in the instruction processing queue, and determine the memory access instruction that has been executed in the instruction processing queue according to the execution status; The memory access instructions in the instruction processing queue are subjected to instruction release operations according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

10. A communication device comprising: A processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the method for processing memory access instructions as described in any one of claims 1 to 9 are realized.

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