Mul_add component group, and product accumulation method and apparatus

Abstract

A mul_add component group, and a product accumulation method and apparatus, which relate to the field of chips. The mul_add component group comprises n functional circuits, m first addition circuits and a second addition circuit, wherein an output end of each functional circuit is connected to an input end of at least one first addition circuit, and input ends of the m first addition circuits are connected to output ends of a plurality of functional circuits; output ends of the m first addition circuits are connected to an input end of the second addition circuit, n being a positive integer greater than 2, and m being a positive integer greater than 1; the functional circuit is used for outputting a code to obtain a partial product after inputting a multiplicand and a multiplier; the first addition circuit is used for summing the partial products to obtain a first summation result and outputting the first summation result; and the second addition circuit is used for summing the first summation results to obtain a second summation result and outputting the second summation result. Thus, the inversion of a full adder is concentrated in some sub-circuits, thereby reducing the power consumption of a mul_add component group.

Description

Multiplier-accumulator group, multiplication-accumulation method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2023, with application number 202310789737.5 and application name “Multiplier-accumulator group, multiplication-accumulation method and device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chips, and in particular to a multiplier-accumulator group, a multiply-accumulate method, and a device. Background Art

[0003] A multiplier-accumulator group (MACG) is a circuit device used to accumulate the product results of n multiplication operations.

[0004] With the rapid development of artificial intelligence (AI) technology, neural network algorithms are also evolving rapidly. Neural networks require a large number of multiplier-accumulator groups to perform massive multiplication and accumulation operations. Therefore, the performance of these groups significantly impacts the overall performance of the neural network.

[0005] Therefore, how to improve the performance of the multiplier-accumulator group is a problem that needs to be solved at present.

[0006] Summary of the Invention

[0007] The present application provides a multiplier-accumulator group, a multiplier-accumulator method, and an apparatus for improving the performance of the multiplier-accumulator group.

[0008] In a first aspect, a multiplier-adder group is provided, comprising: n functional circuits, m first adding circuits, and second adding circuits. The output of each functional circuit is connected to the input of at least one first adding circuit, wherein at least one first adding circuit is connected to a plurality of functional circuits. The outputs of the m first adding circuits are connected to the input of the second adding circuit. n is a positive integer greater than 2, and m is a positive integer greater than 1. The functional circuit is configured to output encoded partial products after inputting a multiplicand and a multiplier. The first adding circuit is configured to sum the partial products to obtain a first summation result and output the first summation result. The second adding circuit is configured to sum the first summation result to obtain a second summation result and output the second summation result.

[0009] In the above method provided by the present application, unlike the related art, the multiplier-adder group first uses a multiplier to calculate the multiplication results of each multiplication operation separately (specifically, in each multiplier, the multiplicand and the multiplier can be first encoded to obtain partial products, and then the obtained partial products are summed to obtain the multiplication result), and then the product results of each multiplier are added to obtain the final multiplication accumulation result. In the above method provided by the present application, after the n functional circuits obtain the partial products of each multiplication operation, the output ends of the multiple functional circuits are connected to the same first adding circuit (that is, the input end of at least one first adding circuit is connected to the output ends of multiple functional circuits), and the partial products of the multiple multiplication operations are input into the same first adding circuit for addition to obtain a first summation result. The first summation results output by each first adding circuit are then added through a second adding circuit to obtain a second summation result (that is, the multiplication accumulation result). In this way, the partial products of each multiplication operation can be combined and then summed according to the characteristics of the processed data. For example, when the data input to the multiplier-adder group includes data with a rapidly changing signal level (referred to as fast-changing data) and data with a slowly changing signal level (referred to as slowly-changing data), the partial products corresponding to the fast-changing data from different functional circuits can be combined and input to a portion of the first adding circuits for summation. Alternatively, the partial products corresponding to the slowly-changing data from different functional circuits can be combined and input to another portion of the first adding circuits for summation. The summation results from each first adding circuit are then added together to obtain the final product-accumulation result. This allows the full adder flips to be concentrated in a portion of the first adding circuits, concentrating the full adder states in the first adding circuits between "no flip" (for the slowly-changing data) and "multiple bit flips" (for the fast-changing data). This reduces the frequency of "single bit flip" and thus reduces the power consumption of the multiplier-adder group.

[0010] In one implementation, the n functional circuits include p functional circuits, and an output terminal of each of the p functional circuits is connected to input terminals of a plurality of first adding circuits, where p is a positive integer.

[0011] In the above implementation, by enabling the output of a functional circuit to be connected to the inputs of multiple first adding circuits, the partial products output by a functional circuit can be split into multiple parts and output to different first adding circuits. For example, when the data input to a functional circuit includes both fast-changing and slowly-changing digits, the partial products corresponding to the fast-changing digits can be combined and input to a portion of the first adding circuits for summation; while the partial products corresponding to the slowly-changing digits can be combined and input to another portion of the first adding circuits for summation. This allows the flipping of the full adder to be concentrated in some of the first adding circuits, thereby reducing the power consumption of the multiplier-accumulator group.

[0012] In one implementation, p functional circuits are configured to output partial products obtained by encoding the multiplier and the multiplicand at different digits in the partial product to different first adding circuits.

[0013] The above implementation takes into account that, in actual applications, the positions of fast-varying and slow-varying bits in the data undergoing multiplication and accumulation operations exhibit a certain pattern. For example, the pattern may be: the high-order bits are slow-varying bits, and the low-order bits are fast-varying bits. This allows the partial products obtained by encoding the multipliers and multiplicands at different digits in the partial products to be output to different first adding circuits, thereby concentrating the flipping of the full adder in some of the first adding circuits and reducing the power of the multiplier-accumulator group.

[0014] In one implementation, the p functional circuits are configured to output a first set of partial products of the partial products to m1 first adding circuits, and to output a second set of partial products of the partial products to m2 first adding circuits. The m1 first adding circuits are different from the m2 first adding circuits, and the signal levels of the partial products of the first set of partial products change faster than those of the partial products of the second set of partial products.

[0015] In the above implementation, the first adding circuit is divided into two parts (i.e., m1 first adding circuits and m2 first adding circuits). The m1 first adding circuits are used to process partial products whose signal levels change faster, while the m2 first adding circuits are used to process partial products whose signal levels change slower. This allows the flipping of the full adder to be concentrated in the m1 first adding circuits, thereby reducing the power of the multiplier-accumulator group.

[0016] In one implementation, the p functional circuits are used to divide the partial product into q parts according to the signal level change speed, and output the partial products to different first adding circuits, where q is a positive integer greater than 1.

[0017] In the above implementation, by dividing the first adding circuit into q parts, each of the q parts is used to process partial products with different signal level change rates. This allows the flipping of the full adder to be concentrated in some of the first adding circuits, thereby reducing the power of the multiplier-accumulator group.

[0018] In one implementation, the second adding circuit includes a first subcircuit and a second subcircuit. The first subcircuit and the second subcircuit are each configured to sum data from the first adding circuit. The outputs of the m first adding circuits are connected to the inputs of the first subcircuit and the second subcircuit, respectively. The m first adding circuits are specifically configured to output a first data set from the first summation result to the first subcircuit and output a second data set from the first summation result to the second subcircuit, wherein the signal level of the data in the first data set changes faster than that of the data in the second data set.

[0019] In the above implementation, the second adding circuit is divided into two parts (i.e., a first sub-circuit and a second sub-circuit). The first sub-circuit is used to process the first data set whose signal levels change more rapidly, while the second sub-circuit is used to process the second data set whose signal levels change more rapidly. This allows the flipping of the full adder to be concentrated in the second sub-circuit, thereby reducing the power consumption of the multiplier-accumulator group.

[0020] In one implementation, the second adding circuit includes s sub-circuits, each of which is configured to sum data from the first adding circuit. The m first adding circuits are configured to divide the first summation result into s output data according to a signal level change rate, and output the s output data to each of the s sub-circuits.

[0021] In the above implementation, by dividing the second adding circuit into s sub-circuits, each of which is used to process output data with different signal level change rates, the flipping of the full adder can be concentrated in some of the sub-circuits, thereby reducing the power of the multiplier-accumulator group.

[0022] In one implementation, n functional circuits are respectively encoded in a radix-2 manner to obtain partial products, or n functional circuits are respectively encoded in a radix-4 manner to obtain partial products, or n functional circuits are respectively encoded in a radix-8 manner to obtain partial products.

[0023] In a second aspect, a multiplication-accumulation method is provided, applied to a multiplier-accumulator group. The method comprises: encoding n groups of multiplicands and multipliers to obtain n groups of partial products; dividing the n groups of partial products into m partial products, and summing the resulting m first summation results, wherein at least one partial product includes partial products from different groups; n is a positive integer greater than 2, and m is a positive integer greater than 1; and summing the m first summation results to obtain a second summation result.

[0024] In one implementation, the n groups of partial products include p groups of partial products, and each group of partial products in the p groups of partial products is divided into multiple partial products in the m groups of partial products, where p is a positive integer.

[0025] In one implementation, the partial products obtained by encoding the multipliers and multiplicands at different digits in the p groups of partial products are divided into different portions of the m partial products.

[0026] In one implementation, a first set of partial products in the p groups of partial products is divided into m1 partial products in the m groups of partial products, and a second set of partial products in the p groups of partial products is divided into m2 partial products in the m groups of partial products; wherein the m1 partial products and the m2 partial products are different, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

[0027] In one implementation, each group of partial products in the p groups of partial products is divided into q parts according to a signal level change rate, and is divided into q partial products in the m groups of partial products.

[0028] In one implementation, summing up m first summation results to obtain a second summation result includes: summing up a first data set in the m first summation results to obtain a third summation result; summing up a second data set in the m first summation results to obtain a fourth summation result; and the signal level of the data in the first data set changes faster than that of the data in the second data set.

[0029] In one implementation, summing the m first summation results to obtain a second summation result includes: dividing the m first summation results into s portions of data according to a signal level change rate, and summing the s portions of data respectively to obtain s summation results.

[0030] In one implementation, encoding n groups of multiplicands and multipliers to obtain n groups of partial products includes: encoding the n groups of multiplicands and multipliers in a radix-2 manner to obtain n groups of partial products; or encoding the n groups of multiplicands and multipliers in a radix-4 manner to obtain n groups of partial products; or encoding the n groups of multiplicands and multipliers in a radix-8 manner to obtain n groups of partial products.

[0031] In a third aspect, a chip is provided, comprising a processor and a multiplier-accumulator group as in the first aspect or any implementation of the first aspect.

[0032] In one implementation, the processor is a neural network processor NPU.

[0033] In a fourth aspect, an electronic device is provided, comprising a printed circuit board and a chip as in the third aspect or the implementation method of the third aspect; the chip is electrically connected to the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a structure of a multiplier-accumulator group provided in an embodiment of the present application;

[0035] FIG2 is a schematic diagram of a full adder provided in an embodiment of the present application;

[0036] FIG3 is a schematic diagram of the change probability of each bit of adjacent eigenvalues ​​in a feature image of a neural network provided by an embodiment of the present application;

[0037] FIG4 is a second structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0038] FIG5 is a third structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0039] FIG6 is a schematic diagram of a data compression process according to an embodiment of the present application;

[0040] FIG7 is a fourth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0041] FIG8 is a schematic diagram of a structure of an addition tree provided in an embodiment of the present application;

[0042] FIG9 is a fifth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0043] FIG10 is a second structural diagram of an addition tree provided in an embodiment of the present application;

[0044] FIG11 is a sixth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0045] FIG12 is a seventh structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0046] FIG13A is a second schematic diagram of a data compression process according to an embodiment of the present application;

[0047] FIG13B is a third schematic diagram of a data compression process according to an embodiment of the present application;

[0048] FIG14 is an eighth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0049] FIG15 is a fourth schematic diagram of a data compression process according to an embodiment of the present application;

[0050] FIG16 is a ninth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0051] FIG17 is a third structural diagram of an addition tree provided in an embodiment of the present application;

[0052] FIG18 is a tenth structural diagram of a multiplier-accumulator group provided in an embodiment of the present application;

[0053] FIG19 is a schematic flow chart of a multiplication-accumulation method provided in an embodiment of the present application;

[0054] FIG20 is a schematic diagram of a structure of a chip provided in an embodiment of the present application;

[0055] FIG21 is a second schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0056] FIG22 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0058] First, to facilitate understanding of the technical solutions provided in the embodiments of the present application, the relevant technologies involved in the embodiments of the present application are first introduced:

[0059] 1. Multiplier-add component group (MACG)

[0060] The multiplier-accumulator group refers to a circuit device used to accumulate the product results of n multiplication operations.

[0061] Currently, in order to implement multiplication-accumulation operations, related technologies (such as in the hardware design of a neural process unit (NPU)) often use multiple multipliers to form a multiplier-accumulator group so that the multiplier-accumulator group can be used to perform multiplication-accumulation operations.

[0062] Specifically, FIG1 is a schematic diagram of the structure of a multiplier-accumulator group in the related art. A multiplier-accumulator group includes multiple multipliers (e.g., multipliers M1 through Mn in the figure). Each multiplier is configured to output a multiplication result after receiving a multiplicand and a multiplier (A0-An represents the multiplicand input to each multiplier, and B0-Bn represents the multiplier input to each multiplier in the figure). The results of each multiplication are then added together by an adder (shown as "A1" in the figure) to produce the final product accumulation result.

[0063] In the process of calculating the multiplication operation, each multiplier first obtains the partial products of the multiplication operation through encoding, and then accumulates the partial products to obtain the result of the multiplication operation.

[0064] Taking multiplier Mn in Figure 1 as an example, after receiving the multiplicand An and multiplier Bn as inputs, multiplier Mn first generates partial products through a corresponding encoding circuit. Taking the radix-4 method as an example, the partial products generated by multiplier Mn in Figure 1 include PPn-0, PPn-1, ..., PPn-x. For example, PPn-0 can be understood as the partial product obtained by encoding the multiplicand with the first bit (from the lowest order), the multiplier for the second bit, and a supplementary bit (usually a 0 supplementary bit); PPn-1 can be understood as the partial product obtained by encoding the multiplicand with the first bit (from the lowest order), the second bit (from the lowest order), and the third bit (from the lowest order); and so on. PPn-1 can be understood as the partial product obtained by encoding the multiplier for the xth bit (from the lowest order), the x+1th bit (from the lowest order), and the x+3th bit (from the lowest order), with the multiplicand (where the multiplier has a total of x+3 bits). Each row of partial products includes 1 bit below it, which is used to represent +1 when taking the complement, and is represented by a black dot in Figure 1.

[0065] After encoding the partial products, the multiplier Mn can input them into the corresponding full adder for addition. This process can also be called data compression. Figure 1 uses the full adder FA as an example. After inputting three bits of equal weight (also called digits), the full adder FA outputs a sum bit S and a carry bit C. This is equivalent to using a full adder to compress the original 3-bit data into 2 bits.

[0066] As shown in Figure 1, during the first layer of compression, multiplier Mn inputs the partial products into the corresponding full adder for addition, generating the first-layer compression result. Multiplier Mn then inputs the first-layer compression result into the full adder for the next layer of compression, generating the second-layer compression result. This process continues in this manner until the compression result is obtained. Since full adders require three bits of input at a time, further data compression using full adders is unavailable after two rows of data are compressed. Therefore, these two rows of data can be used as the output result Fn of multiplier Mn.

[0067] Each multiplier then outputs the results F0-Fn and inputs them into adder A1, which further compresses the data. Specifically, the function of adder A1 can be implemented by a combination of a full adder and a half adder.

[0068] 2. Full Adder

[0069] A full adder adds three bits of input data to produce a sum S and a carry C. As shown in Figure 2(a), the full adder takes three bits x, y, and z as input and produces a sum S and a carry C.

[0070] The three bits input to the full adder can include two local bits and a carry from the lower bit. This allows a single-bit full adder to process the carry from the lower bit and output the local carry. Multiple single-bit full adders can be cascaded to create a multi-bit full adder.

[0071] Currently, in full adders using 7nm process, the power consumption statistics of full adders are shown in Table 1 below.

[0072] Table 1

[0073] When there is no signal level change between the three bits input to the full adder in the current calculation cycle and the three bits input to the full adder in the previous calculation cycle (i.e., 0 bit flips), the power consumption of the full adder is 0.0102uW. When 1 bit flips, the power consumption of the full adder is 0.3971uW, equivalent to a per-bit flip power consumption of 0.3971uW. When 2 bits flip, the power consumption of the full adder is 0.2202uW, equivalent to a per-bit flip power consumption of 0.1101uW. When 3 bits flip, the power consumption of the full adder is 0.4410uW, equivalent to a per-bit flip power consumption of 0.1470uW. It can be seen that when there is a 1-bit flip in the input data, the power consumption per-bit flip of the full adder is the highest.

[0074] The following is an introduction to the technical solutions provided in the embodiments of the present application with reference to examples:

[0075] First, with respect to the power consumption characteristics of the aforementioned full adders, the present embodiment takes into account that, during addition operations, if the flipped bits can be concentrated in a portion of the full adders, flipping can be avoided as much as possible in the other portion of the full adders. This can reduce the power consumption of the addition operation.

[0076] Take the example of adding nine single-bit values ​​using a full adder, as shown in Figure 2 (b) and (c), where PP0-PP8 represent the data input to the full adder. The data inputs PP0, PP3, and PP6 undergo signal level inversion. That is, the data input from PP0, PP3, and PP6 in the previous calculation cycle and the data input from PP0, PP3, and PP6 in the current calculation cycle undergo signal level inversion. The remaining six input data do not undergo signal level inversion. Therefore, when adding according to the method shown in Figure 2 (b), the power consumption of the three full adders in the current calculation cycle is 1.1913uW (i.e., 0.3971uW + 0.3971uW + 0.3971uW). When adding according to the method shown in Figure 2 (c), the power consumption of the three full adders in the current calculation cycle is 0.4614uW (i.e., 0.4410uW + 0.0102uW + 0.0102uW). It can be seen that when adding is performed in the manner shown in FIG2 (c), the power consumption of the full adder is significantly lower.

[0077] Furthermore, the embodiments of the present application take into account that, during a multiply-accumulate operation, the data (including the multiplicand and the multiplier) input to the multiplier-accumulator group in adjacent calculation cycles may have some digits that are identical. Consequently, when the partial products obtained by each encoding are input to the full adder for addition, the bits corresponding to some of the partial products experience signal level flips while others do not, resulting in a high frequency of 1-bit flips in the full adder.

[0078] Take the neural network calculation process as an example: In the feature map of a neural network, the eigenvalues ​​usually have the characteristics of a low change rate for high-order bits and a high change rate for low-order bits. For example, Figure 3 shows a schematic diagram of the change rate of each bit in adjacent eigenvalues ​​of a feature image. It can be seen that the change rate of the high-order bit (i.e., bit7 side) is low (approaching 0), while the change rate of the low-order bit (i.e., bit0 side) is high (exceeding 0.6). In other words, for adjacent eigenvalues, the probability of the high-order bits being the same is high, while the probability of the low-order bits being the same is low.

[0079] Furthermore, in the neural network calculation process, when the characteristic value is used as the multiplier and the preset parameter is used as the multiplicand and input into the multiplier-accumulator group shown in FIG1 for the multiplication and accumulation operation, the processing process of the multiplier Mn in FIG1 includes:

[0080] During a calculation cycle, multiplier Mn receives the multiplicand (preset parameter e) and the multiplier (eigenvalue FM-1). Multiplier Mn then encodes the preset parameter e and the eigenvalue FM-1 to obtain partial products. Following the process described above, these partial products are compressed to produce a compressed result, which is then output to adder A1. Adder A1 then further compresses the compressed results of each multiplier to obtain the final product accumulation result.

[0081] In the next calculation cycle, multiplier Mn receives the multiplicand (preset parameter e) and the multiplier (eigenvalue FM-2). Multiplier Mn then encodes the preset parameter e and the eigenvalue FM-2 to obtain partial products. At this point, it can be seen that since the multiplicands received by multiplier Mn in the two calculation cycles are the same (both are preset parameter e), and the high-order bits of the multipliers (eigenvalue FM-1 and eigenvalue FM-2) are also likely the same, only the low-order bits of the multipliers are likely different. In other words, in the partial products obtained in the two calculation cycles, the partial products obtained by encoding the high-order bits of the multiplier and multiplicand are likely to be the same. Using the addition tree T1 in Figure 1 as an example, in the addition tree T1 corresponding to the two calculation cycles, the partial products obtained by encoding the high-order bits of the multiplier and multiplicand (i.e., the partial products on the PPn-x side) are likely to be the same, while the partial products obtained by encoding the low-order bits of the multiplier and multiplicand (i.e., the partial products on the PPn-0 side) are likely to be different. In this way, when the addition tree T1 is compressed in the second calculation cycle, the signal level of the bits corresponding to some partial products is flipped, while the signal level of some bits is not flipped. This makes the frequency of 1-bit flipping in the full adder higher.

[0082] To address the above issues, embodiments of the present application provide a multiplier-adder group. The multiplier-adder group includes three or more functional circuits (hereinafter, for ease of description, referred to as n functional circuits, where n is a positive integer greater than 2), two or more first adding circuits (hereinafter, for ease of description, referred to as m first adding circuits, where m is a positive integer greater than 1), and a second adding circuit.

[0083] The output end of each functional circuit is connected to the input end of at least one first adding circuit, the input end of at least one first adding circuit is connected to the output ends of multiple functional circuits, and the output ends of the other m first adding circuits are connected to the input end of the second adding circuit.

[0084] Each functional circuit is used to output a code to obtain a partial product after inputting a multiplicand and a multiplier.

[0085] It can be seen that, since the output terminal of each functional circuit is connected to the input terminal of at least one first adding circuit, each functional circuit can output the obtained partial product to the first adding circuit.

[0086] Each first adding circuit is used to sum the partial products obtained by the functional circuits (hereinafter the summation result of each first adding circuit is referred to as a "first summation result") to obtain a first summation result, and output the first summation result.

[0087] It can be seen that, since the input terminal of the at least one first adding circuit is connected to the output terminals of the plurality of functional circuits, the at least one first adding circuit in the multiplier-accumulator group can sum the partial products from the plurality of functional circuits.

[0088] In addition, the second adding circuit is used to sum the first summing result (hereinafter the summing result of the second adding circuit is referred to as "second summing result") to obtain a second summing result.

[0089] It can be seen that since the output ends of the m first adding circuits are connected to the input ends of the second adding circuit, the second adding circuit can sum the first summation results from the m first adding circuits, and the second summation result obtained can be understood as the multiplication and accumulation result output by the multiplier-adder group, thereby completing the multiplication and accumulation operation.

[0090] In the multiplier-adder group provided in the embodiment of the present application, since the output terminals of multiple functional circuits are connected to the same first adding circuit (i.e., the input terminal of at least one first adding circuit is connected to the output terminals of multiple functional circuits), the partial products corresponding to multiple multiplication operations can be input into the same first adding circuit for addition. Compared with the method of adding partial products in units of multiplication operations in the related art, after obtaining the partial products of each multiplication operation, the partial products corresponding to different multiplication operations can be added. In this way, when the partial products include both partial products with fast signal level changes (hereinafter referred to as "fast-changing") and partial products with slow signal level changes (hereinafter referred to as "slow-changing"), on the one hand, the fast-changing partial products from different functional circuits can be put together and input into a part of the first adding circuit for summation; on the other hand, the slowly changing partial products from different functional circuits can be put together and input into another part of the first adding circuit for summation; and then the summation results of each first adding circuit are added to obtain the final product accumulation result.

[0091] This allows the full adder's flipping to be concentrated in part of the first adding circuit, which is equivalent to concentrating the full adder's states as much as possible in the "0 bit flip" and "multiple bit flip" states, reducing the frequency of the "1 bit flip" state and thus reducing power consumption.

[0092] It will be appreciated that, for ease of description, in the embodiments of the present application, the circuits included in the multiplier-adder group that implement corresponding functions are referred to as "functional circuit," "first adding circuit," and "second adding circuit," respectively. In actual applications, other names may also be used to represent the various circuits in the multiplier-adder group. For example, the "functional circuit" in the embodiments of the present application may be referred to as "encoding circuit" or "partial product generation circuit," etc. For another example, the "first adding circuit" and "second adding circuit" in the embodiments of the present application may be referred to as "primary adding circuit" and "secondary adding circuit," respectively. In the embodiments of the present application, there is no limitation on the names of the circuits that implement corresponding functions in the multiplier-adder group.

[0093] The following describes the multiplier-accumulator group provided in the embodiment of the present application with reference to examples:

[0094] FIG4 is a schematic diagram of the structure of a multiplier-adder group 10 provided in an embodiment of the present application. The multiplier-adder group 10 includes eight functional circuits (i.e., functional circuits 110 to 117), two first adding circuits (i.e., first adding circuit 120 and first adding circuit 121), and a second adding circuit 130.

[0095] The outputs of the eight functional circuits are connected to the inputs of the two first adding circuits, respectively. Furthermore, the input of first adding circuit 120 is connected to the outputs of the eight functional circuits, and the input of first adding circuit 121 is connected to the outputs of the eight functional circuits. Furthermore, the outputs of the two first adding circuits are connected to the input of second adding circuit 130.

[0096] In one implementation, when, among the partial products generated by each functional circuit, the signal level of the partial product obtained by encoding the high-bit multiplier and multiplicand changes slowly, and the signal level of the partial product obtained by encoding the low-bit multiplier and multiplicand changes quickly, the partial products generated by each functional circuit may refer to the partial products PP7-0, PP7-1, PP7-2, and PP7-1 generated by the functional circuit 117 in FIG5 : wherein, the partial products obtained by encoding the low-bit multiplier and multiplicand (i.e., PP7-0 and PP7-1 in FIG5 ) change quickly, and the partial products obtained by encoding the high-bit multiplier and multiplicand (i.e., PP7-2 and PP7-3 in FIG5 ) change slowly.

[0097] It should be noted that the functional circuits in the present embodiment primarily use the partial products obtained by encoding both the multiplicand and the multiplier in radix-4 format as an example to illustrate the operation of multiplier-accumulator group 10. Therefore, the partial products in each row of PP7-0, PP7-1, PP7-2, and PP7-1 in Figure 5 are all 10 bits, including 8 bits of data, a 1-bit sign bit extension, and a +1 when taking the 1's complement. Unless otherwise specified below, the bits included in each row of partial products can be understood in the same way as described above for the 10 bits.

[0098] In addition, in actual application, each functional circuit can also use multipliers and multiplicands with other numbers of bits. In addition, each functional circuit can also obtain partial products according to different types of encoding methods. Specifically, each functional circuit can be encoded in a base 2 manner to obtain partial products, or each functional circuit can be encoded in a base 4 manner to obtain partial products, or each functional circuit can be encoded in a base 8 manner to obtain partial products, etc. The embodiments of the present application do not limit the number of bits of the multiplier and multiplicand used by each functional circuit, and the type of encoding method used by each functional circuit.

[0099] Furthermore, in the example shown in FIG5 , each functional circuit outputs the partial product obtained by encoding the low-bit multiplier and the multiplicand to the first adding circuit 120 , and outputs the partial product obtained by encoding the high-bit multiplier and the multiplicand to the first adding circuit 121 .

[0100] The partial products received by the first adding circuit 120 are shown as an adding tree T-1 in FIG5 . Adding tree T-1 includes two rows of partial products (i.e., PP0-0 and PP0-1) obtained by encoding the low-order multipliers and multiplicands output by functional circuit 110, two rows of partial products (i.e., PP1-0 and PP1-1) obtained by encoding the low-order multipliers and multiplicands output by functional circuit 111, and so on, up to two rows of partial products (i.e., PP7-0 and PP7-1) obtained by encoding the low-order multipliers and multiplicands output by functional circuit 117.

[0101] The partial products received by the first adding circuit 121 are shown as an adding tree T-2 in FIG5 . Adding tree T-2 includes two rows of partial products (i.e., PP0-2 and PP0-3) obtained by encoding the high-order multipliers and multiplicands output by functional circuit 110, two rows of partial products (i.e., PP1-2 and PP1-3) obtained by encoding the high-order multipliers and multiplicands output by functional circuit 111, and so on, up to two rows of partial products (i.e., PP7-2 and PP7-3) obtained by encoding the high-order multipliers and multiplicands output by functional circuit 117.

[0102] The process of compressing adder tree T-2 by first adder circuit 121 is shown in FIG6 . In first adder circuit 121, the partial products of every three equally weighted bits in adder tree T-2 are first input into a full adder to obtain the first-level compression result. Taking full adder FA in FIG6 as an example, after receiving 3 bits of data, full adder FA outputs a sum S and a carry C. S and C serve as two bits in the first-level compression result, respectively. Subsequently, every three equally weighted partial products in the first-level compression result are input into the next batch of full adders to obtain the second-level compression result. This process continues in this manner, ultimately resulting in the first-level summation result.

[0103] Because the partial products input to the first adder circuit 121 are all slowly varying data, the adder tree corresponding to the first adder circuit 121 in the next calculation cycle and the adder tree T-2 corresponding to the first adder circuit 121 in the current calculation cycle contain a large amount of identical data. Consequently, when the adder tree is compressed in the next calculation cycle, the input data of some full adders in the first adder circuit 121 remains unchanged. Consequently, the signal levels of these full adders remain unchanged (i.e., a 0-bit flip), thereby maintaining low power consumption for each full adder.

[0104] On the other hand, the process of compressing adder tree T-1 by first adder circuit 120 is similar to the process of compressing adder tree T-2 by first adder circuit 121 in FIG6 , and the repeated details are not further described here. It is understood that during the process of compressing partial products by first adder circuit 120, because the partial products input to first adder circuit 120 between two adjacent calculation cycles include a large amount of varying data, the signal levels of the full adders in first adder circuit 121 are likely to vary significantly, thereby keeping these full adders in a low-power state with multiple bit flips (i.e., 2-bit flips and 3-bit flips) as much as possible.

[0105] In summary, in the above implementation, the first adding circuit 120 and the first adding circuit 121 integrate and compress the parts of the signal with fast and slow level changes, thereby reducing the power consumption of the multiplier-accumulator group.

[0106] In the examples shown in FIG5 and FIG6 , the operation process of the multiplier-accumulator group 10 is described by taking as an example the case where the signal level of the partial product obtained by encoding the high-bit multiplier and multiplicand in the partial product generated by each functional circuit changes slowly (for ease of description, the “signal level of the partial product obtained by encoding the high-bit multiplier and multiplicand changes slowly” is referred to as “high-bit slow change”) and the signal level of the partial product obtained by encoding the low-bit multiplier and multiplicand changes quickly (the “signal level of the partial product obtained by encoding the low-bit multiplier and multiplicand changes quickly” is referred to as “low-bit fast change”).

[0107] In another implementation provided below, the operation process of the multiplier-accumulator group 10 provided in the embodiment of the present application is described by taking as an example a case where, among multiple functional circuits, some functional circuits generate partial products in which the “high-order bits change slowly” and the “low-order bits change quickly”, while another functional circuit generates partial products in which the opposite is true, that is, the “low-order bits change slowly” and the “high-order bits change quickly”:

[0108] For example, as shown in FIG7 , in the multiplier-accumulator group 10 , the partial products generated by the functional circuits 110 and 113 have “low-order bits that change slowly” and “high-order bits that change quickly”, while the partial products generated by the functional circuits 114 and 117 have “high-order bits that change slowly” and “low-order bits that change quickly”.

[0109] Functional circuits 110-113 output the partial products obtained by encoding the low-bit multipliers and multiplicands to first adder circuit 120, and output the partial products obtained by encoding the high-bit multipliers and multiplicands to first adder circuit 121. Functional circuits 114-117 output the partial products obtained by encoding the low-bit multipliers and multiplicands to first adder circuit 121, and output the partial products obtained by encoding the high-bit multipliers and multiplicands to first adder circuit 120.

[0110] Furthermore, the partial products received by the first adding circuit 120 are shown as an adding tree T-1 in FIG8 . The adding tree T-1 in FIG8 includes: two rows of partial products (i.e., PP0-0 and PP0-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 110; two rows of partial products (i.e., PP1-0 and PP1-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 111; two rows of partial products (i.e., PP2-0 and PP2-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 112; and two rows of partial products (i.e., PP3-0 and PP3-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 113. In addition, the addition tree T-1 also includes: two rows of partial products (i.e., PP4-2 and PP4-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 114, two rows of partial products (i.e., PP5-2 and PP5-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 115, two rows of partial products (i.e., PP6-2 and PP6-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 116, and two rows of partial products (i.e., PP7-2 and PP7-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 117.

[0111] In addition, the partial products received by the first adding circuit 121 are shown in the adding tree T-2 in FIG8 . The adding tree T-2 in FIG8 includes: two rows of partial products (i.e., PP0-2 and PP0-3) obtained by encoding the high-bit multipliers and multiplicands output by the functional circuit 110; two rows of partial products (i.e., PP1-2 and PP1-3) obtained by encoding the high-bit multipliers and multiplicands output by the functional circuit 111; two rows of partial products (i.e., PP2-2 and PP2-3) obtained by encoding the high-bit multipliers and multiplicands output by the functional circuit 112; and two rows of partial products (i.e., PP3-2 and PP3-3) obtained by encoding the high-bit multipliers and multiplicands output by the functional circuit 113. In addition, the addition tree T-1 also includes: two rows of partial products (i.e., PP4-0 and PP4-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 114, two rows of partial products (i.e., PP5-0 and PP5-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 115, two rows of partial products (i.e., PP6-0 and PP6-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 116, and two rows of partial products (i.e., PP7-0 and PP7-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 117.

[0112] Among them, for the compression process of the addition tree T-1 and the addition tree T-2 in Figure 8 by the first addition circuit 120 and the first addition circuit 121, reference can be made to the compression process of the addition tree T-2 in Figure 6 by the first addition circuit 121 above, and the repeated content will not be repeated here.

[0113] In the multiplier-adder group shown in FIG7-FIG8, the first adding circuit 120 and the first adding circuit 121 are used to compress the integral of the signal with fast and slow level changes, thereby reducing the power consumption of the multiplier-adder group.

[0114] In another implementation, among the multiple functional circuits, some of the functional circuits generate partial products of data with fast signal level changes, while other functional circuits generate partial products of data with slow signal level changes.

[0115] For example, as shown in FIG9 , in the multiplier-accumulator group 10 , the partial products generated by the functional circuits 110 to 113 are data with slow signal level changes, and the partial products generated by the functional circuits 114 to 117 are data with fast signal level changes.

[0116] At this time, the output terminals of the functional circuits 110 - 113 may be connected only to the input terminal of the first adding circuit 120 , and the output terminals of the functional circuits 114 - 117 may be connected only to the input terminal of the first adding circuit 121 .

[0117] Functional circuits 110 to 113 output the encoded partial products to a first adding circuit 120 . Functional circuits 114 to 117 output the encoded partial products to a first adding circuit 121 .

[0118] Furthermore, the partial products received by the first adding circuit 120 are shown in the adding tree T-1 in FIG10 . The adding tree T-1 in FIG10 includes the partial products output by the functional circuit 110 (i.e., PP0-0, PP0-1, PP0-2, and PP0-3), the partial products output by the functional circuit 111 (i.e., PP1-0, PP1-1, PP1-2, and PP1-3), the partial products output by the functional circuit 112 (i.e., PP2-0, PP2-1, PP2-2, and PP2-3), and the partial products output by the functional circuit 113 (i.e., PP3-0, PP3-1, PP3-2, and PP3-3).

[0119] The partial products received by the first adder circuit 121 are shown as an adder tree T-2 in FIG10 . Adder tree T-2 in FIG10 includes the partial products output by functional circuit 114 (i.e., PP4-0, PP4-1, PP4-2, and PP4-3), the partial products output by functional circuit 115 (i.e., PP5-0, PP5-1, PP5-2, and PP5-3), the partial products output by functional circuit 116 (i.e., PP6-0, PP6-1, PP6-2, and PP6-3), and the partial products output by functional circuit 117 (i.e., PP7-0, PP7-1, PP7-2, and PP7-3).

[0120] Among them, for the compression process of the addition tree T-1 and the addition tree T-2 in Figure 10 by the first addition circuit 120 and the first addition circuit 121, reference can be made to the compression process of the addition tree T-2 in Figure 6 by the first addition circuit 121 above, and the repeated content will not be repeated here.

[0121] In the multiplier-adder group shown in FIG9-FIG10, the first adding circuit 120 and the first adding circuit 121 are used to compress the integral of the parts with fast and slow signal level changes, thereby reducing the power consumption of the multiplier-adder group.

[0122] Furthermore, it is understood that, in actual applications, not every first adding circuit in the multiplier-adder group 10 must be connected to multiple functional circuits. In some application scenarios, the multiplier-adder group 10 may also include a first adding circuit connected to only one functional circuit. For example, as shown in FIG11 , the multiplier-adder group 10 includes: functional circuits 110 to 118, first adding circuits 120 to 122, and a second adding circuit 130.

[0123] Among them, the connection relationship between the functional circuit 110-functional circuit 117 and the first adding circuit 120-first adding circuit 121, as well as the operation process of the functional circuit 110-functional circuit 117 and the first adding circuit 120-first adding circuit 121 can refer to the operation process of the functional circuit 110-functional circuit 117 and the first adding circuit 120-first adding circuit 121 in Figure 9.

[0124] In addition, the output terminal of the functional circuit 118 is connected to the input terminal of the first adding circuit 122. Here, it can be understood that the first adding circuit is used to output the product of A8 and B8 (ie, the multiplicand and the multiplier received by the functional circuit 118).

[0125] 4-10 above mainly use the example of the multiplier-adder group 10 including two first adding circuits to introduce the operation process of the multiplier-adder group 10. In other application scenarios, the multiplier-adder group 10 may include a larger number of first adding circuits.

[0126] For example, as shown in FIG. 12 , the multiplier-adder group 10 includes eight functional circuits (ie, functional circuits 110 to 117 ), four first adding circuits (ie, first adding circuits 120 to 123 ), and a second adding circuit 130 .

[0127] In one implementation, the four first adding circuits included in the multiplier-adder group 10 can be divided into two groups, one group for processing partial products with fast signal level changes, and the other group for processing partial products with slow signal level changes.

[0128] For example, in FIG12 , when the partial products output by each functional circuit all have "slowly varying high-order bits" and "fastly varying low-order bits," the partial products obtained by encoding the multipliers and multiplicands at the low-order bits in the partial products of each functional circuit can be output to first adding circuit 120 and first adding circuit 121, while the partial products obtained by encoding the multipliers and multiplicands at the high-order bits in the partial products of each functional circuit can be output to first adding circuit 122 and first adding circuit 123. In other words, first adding circuit 120 and first adding circuit 121 are used to process partial products with rapidly varying signal levels, while first adding circuit 122 and first adding circuit 123 are used to process partial products with slowly varying signal levels.

[0129] Exemplarily, the partial products received by each first adding circuit in the first adding circuit 120 to the first adding circuit 123 may be as shown in FIG. 13A and FIG. 13B .

[0130] The partial products received by the first adding circuit 120 include: partial products obtained by encoding the low-bit multipliers and multiplicands output by the functional circuits 110-113 (i.e., PP0-0, PP0-1, PP1-0, PP1-1, PP2-0, PP2-1, PP3-0, and PP3-1).

[0131] The partial products received by the first adding circuit 121 include: partial products obtained by encoding the low-bit multipliers and multiplicands output by the functional circuits 114-117 (i.e., PP4-0, PP4-1, PP5-0, PP5-1, PP6-0, PP6-1, PP7-0 and PP7-1).

[0132] The partial products received by the first adding circuit 122 include: partial products obtained by encoding the high-bit multipliers and multiplicands output by the functional circuits 110-113 (i.e., PP0-2, PP0-3, PP1-2, PP1-3, PP2-2, PP2-3, PP3-2, and PP3-3).

[0133] The partial products received by the first adding circuit 123 include: partial products obtained by encoding the high-bit multipliers and multiplicands output by the functional circuits 114-117 (i.e., PP4-2, PP4-3, PP5-2, PP5-3, PP6-2, PP6-3, PP7-2, and PP7-3).

[0134] The specific process of the first adding circuit 120-the first adding circuit 123 in Figure 13A and Figure 13B compressing the partial products to obtain the first summation results can be referred to the compression process of the addition tree T-2 in Figure 6 by the first adding circuit 121 above, and the repeated content is not repeated here.

[0135] In the multiplier-adder group 10 shown in FIG12, FIG13A and FIG13B, the first adding circuit 120 and the first adding circuit 121 are used to compress the partial integrals of the signal level changing quickly and the signal level changing slowly, thereby reducing the power consumption of the multiplier-adder group.

[0136] Furthermore, in the process of summing the first summation results from the first adding circuits by the second adding circuit 130 in the multiplier-adder group 10 shown in FIG12 , it is considered that each first summation result may also include data with rapidly varying signal levels and data with slowly varying signal levels. Therefore, multiple sub-circuits can be arranged in the second adding circuit 130 . On the one hand, data with rapidly varying signal levels from the first adding circuits can be grouped together and input to a portion of the sub-circuits for summation; on the other hand, data with slowly varying signal levels from the first adding circuits can be grouped together and input to another portion of the sub-circuits for summation.

[0137] Exemplarily, as shown in FIG. 14 , the second adding circuit 130 may include a first sub-circuit 1301 and a second sub-circuit 1302 .

[0138] The input end of the first sub-circuit 1301 is connected to the first adding circuit 120 and the first adding circuit 121 , and the input end of the second sub-circuit 1302 is connected to the first adding circuit 122 and the first adding circuit 123 .

[0139] 15 , the data received by the first sub-circuit 1301 includes the first summation result a from the first adding circuit 120 and the first summation result b from the first adding circuit 121. The data received by the first sub-circuit 1302 includes the first summation result c from the first adding circuit 122 and the first summation result d from the first adding circuit 123.

[0140] The specific process by which the first sub-circuit 1301 and the second sub-circuit 1302 compress the first summation result to obtain the third summation result and the fourth summation result can be referred to above as the process by which the first adder circuit 121 compresses the adder tree T-2 in FIG. 6 , and the repeated details are not repeated here. After the first sub-circuit 1301 and the second sub-circuit 1302 obtain the third summation result and the fourth summation result, the third summation result and the fourth summation result can be directly output as the operation result of the second adder circuit (in this case, the third summation result and the fourth summation result can be collectively used as the second summation result). Alternatively, the second adder circuit may further include a sub-circuit for summing the third summation result and the fourth summation result, so that the second adder circuit can output the sum of the third summation result and the fourth summation result as the operation result of the second adder circuit (i.e., the second summation result).

[0141] As described above with respect to FIG. 12 , since the partial products compressed by the first adding circuit 120 and the first adding circuit 121 are partial products with rapidly varying signal levels, the first summation results a and b are also data with rapidly varying signal levels. Since the partial products compressed by the first adding circuit 122 and the first adding circuit 123 are partial products with slowly varying signal levels, the first summation results c and d are also data with slowly varying signal levels.

[0142] Therefore, in the above implementation, the first sub-circuit 1301 compresses the first summation result a and the first summation result b, and the first sub-circuit 1302 compresses the first summation result c and the first summation result d, so that the data with fast signal level changes and the data with slow signal level changes can be compressed separately, thereby further reducing the power consumption of the multiplier-adder group 10.

[0143] In addition, in the example shown in FIG12 , the plurality of first adding circuits are primarily divided into two groups, one for processing partial products with rapidly varying signal levels, and the other for processing partial products with slowly varying signal levels. In other implementations, the plurality of first adding circuits may be divided into three or more groups (hereinafter referred to as dividing the plurality of first adding circuits into q groups). Furthermore, each functional circuit may divide the partial products into q parts based on the speed of signal level variation, with each partial product being output to a different first adding circuit.

[0144] For example, in Figure 16 , among the partial products output by each functional circuit, the signal level of the partial product obtained by encoding the lowest-order multiplier and multiplicand changes the fastest. Furthermore, as the number of bits of the corresponding multiplier increases, the signal level change of the partial product gradually decreases, until the signal level of the partial product obtained by encoding the highest-order multiplier and multiplicand changes the slowest. In this case, the four rows of partial products output by the functional circuits can be respectively output to different first adder circuits.

[0145] Specifically, in FIG16 , each functional circuit outputs the partial products obtained by encoding the lowest-order multiplier and multiplicand in the four rows of partial products (including: the partial product PP0-0 output by the functional circuit 110, the partial product PP1-0 output by the functional circuit 111, ..., up to the partial product PP7-0 output by the functional circuit 117) to the first adding circuit 120; each functional circuit outputs the partial products obtained by encoding the second-lowest-order multiplier and multiplicand in the four rows of partial products (including: the partial product PP0-1 output by the functional circuit 110, the partial product PP1-1 output by the functional circuit 111, ..., up to the partial product PP7-1 output by the functional circuit 117) to the first adding circuit 120. Each functional circuit outputs a partial product obtained by encoding the second-highest-order multiplier and the multiplicand in the four rows of partial products (including: the partial product PP0-2 output by the functional circuit 110, the partial product PP1-2 output by the functional circuit 111, ..., up to the partial product PP7-2 output by the functional circuit 117) to the first adding circuit 122; each functional circuit outputs a partial product obtained by encoding the highest-order multiplier and the multiplicand in the four rows of partial products (including: the partial product PP0-3 output by the functional circuit 110, the partial product PP1-3 output by the functional circuit 111, ..., up to the partial product PP7-3 output by the functional circuit 117) to the first adding circuit 123.

[0146] Furthermore, the partial products received by each of the first adding circuits 120 to 123 may be as shown in FIG. 17 .

[0147] The specific process by which first adding circuits 120-123 compress the partial products to obtain the first summation results in Figure 17 can be referred to above for the compression process performed by first adding circuit 121 on adder tree T-2 in Figure 6 , and the repeated details are omitted here. Furthermore, in Figure 17 , to simplify the diagram, the complement codes corresponding to the partial products in each row are incremented by 1, and are uniformly represented by black dots in the last row of each adder tree.

[0148] In the multiplier-adder group 10 shown in FIG16-FIG17, each functional circuit can divide the partial product into four parts according to the different signal level change speeds and output them to four first adding circuits, thereby further reducing the power consumption of the multiplier-adder group.

[0149] In addition, the example shown in FIG. 14 above mainly describes the operation of the multiplier-adder group 10 by configuring two sub-circuits within the second adding circuit, one of which processes data from the first adding circuit with rapidly varying signal levels, and the other processes data from the first adding circuit with slowly varying signal levels. In other implementations, the second adding circuit may further include three or more sub-circuits. Furthermore, each first adding circuit may divide the first summation result into s output data portions according to the rate of variation of the signal levels, with each portion of the output data being output to a different sub-circuit within the second adding circuit.

[0150] For example, as shown in FIG18 , the multiplier-adder group 10 may include eight functional circuits (i.e., functional circuits 110 to 117), six first adding circuits (i.e., first adding circuits 120 to 125), and a second adding circuit 130. The second adding circuit 130 includes a first sub-circuit 1301, a second sub-circuit 1302, and a third sub-circuit 1303.

[0151] The eight functional circuits are configured to divide the partial products into six parts according to the speed of signal level changes, and output the partial products to the six first adding circuits. The signal level of the partial products received by first adding circuit 120 changes the fastest, followed by the signal level of the partial products received by first adding circuit 121, and so on. The signal level of the partial products received by first adding circuit 125 changes the slowest.

[0152] The six first adding circuits are respectively used to sum the received partial products to obtain a first summation result, and divide the first summation result into three output data according to the signal level change speed, and output the three output data to the first sub-circuit 1301, the second sub-circuit 1302 and the third sub-circuit 1303 respectively.

[0153] Specifically, since the signal level of the partial product received by the first adding circuit 120 among the first adding circuits changes the fastest, the signal level of the partial product received by the first adding circuit 121 changes second fastest, until the signal level of the partial product received by the first adding circuit 125 changes the slowest, the signal level of the first summation result obtained by the first adding circuit 120 and the first adding circuit 121 changes the fastest, the signal level of the first summation result obtained by the first adding circuit 122 and the first adding circuit 123 changes second fastest, and the signal level of the first summation result obtained by the first adding circuit 124 and the first adding circuit 125 changes the slowest.

[0154] Therefore, the first summation result obtained by the first addition circuit 120 and the first addition circuit 121 is output to the first sub-circuit 1301; the first summation result obtained by the first addition circuit 122 and the first addition circuit 123 is output to the first sub-circuit 1302; and the first summation result obtained by the first addition circuit 124 and the first addition circuit 125 is output to the first sub-circuit 1303.

[0155] Among them, the specific operation processes of the first sub-circuit 1301, the second sub-circuit 1302 and the third sub-circuit 1303 can refer to the above description of the first sub-circuit 1301 and the second sub-circuit 1302 in Figure 15, and the repeated content is not repeated here.

[0156] Furthermore, it is understood that, in practical applications, when each functional circuit in the above example outputs partial products to the first adding circuit, if the multiplicand and multiplier input to the multiplier adder group exhibit certain regularities in their changes, these regularities can be utilized to determine the partial products to be output to different first adding circuits. For example, if the multiplicand and multiplier input to the multiplier adder group exhibit the following regularity: the multiplicand is a constant preset parameter, and only a portion of the digits of the multiplier change rapidly while another portion of the digits change slowly, the partial products with different signal level change rates can be output to different first adding circuits by encoding the partial products obtained by encoding the multiplier and multiplicand at different digits and outputting them to different first adding circuits. In this case, each functional circuit does not need to detect the signal level change rate of each partial product; instead, it is sufficient to output the partial products to different first adding circuits based on the digits of the multiplier corresponding to the partial product. For example, in the examples shown in Figures 16 and 17, each functional circuit may not need to detect the change rate of the signal level of each partial product. It only needs to output the partial product obtained by encoding the lowest-digit multiplier and multiplicand in the partial product to the first addition circuit 120, the partial product obtained by encoding the second-lowest-digit multiplier and multiplicand to the first addition circuit 121, the partial product obtained by encoding the second-highest-digit multiplier and multiplicand to the first addition circuit 122, and the partial product obtained by encoding the highest-digit multiplier and multiplicand to the first addition circuit 123. In this way, partial products with different signal level change rates can be output to different first addition circuits.

[0157] On the other hand, each functional circuit can also monitor the signal level change rate of each partial product and, based on the monitoring results, determine whether to output the partial product to a different first adding circuit. Still taking Figures 16 and 17 as an example, each functional circuit can monitor each encoded partial product. When the signal level change rate of a partial product is detected to be very fast (e.g., the signal level change rate is greater than the first speed threshold), the partial product is output to the first adding circuit 123. When the signal level change rate of a partial product is detected to be slightly faster (e.g., the signal level change rate is greater than the second speed threshold but less than the first speed threshold), the partial product is output to the first adding circuit 122. When the signal level change rate of a partial product is detected to be slightly slower (e.g., the signal level change rate is greater than the third speed threshold but less than the second speed threshold), the partial product is output to the first adding circuit 121. When the signal level change rate of a partial product is detected to be very slow (e.g., the signal level change rate is greater than the fourth speed threshold but less than the third speed threshold), the partial product is output to the first adding circuit 120. In this case, each functional circuit may include a controller for monitoring the signal level change speed of each partial product and controlling the output partial product, wherein the function of the controller may be implemented by software or hardware.

[0158] In conjunction with the examples shown in Figures 4-18 above, an embodiment of the present application provides a multiplication-accumulation method applied to a multiplier-accumulator group. As shown in Figure 19, the method may include:

[0159] S201: The multiplier-accumulator group encodes n groups of multiplicands and multipliers to obtain n groups of partial products, where n is a positive integer greater than 2.

[0160] For example, when n is 8, as shown in Figures 4, 5, 7, 9, 12, 14, 16 and 18, the eight functional circuits in the multiplier-accumulator group 10 respectively encode eight groups of multiplicands and multipliers to obtain eight groups of partial products.

[0161] For another example, when n is 9, as shown in FIG11 , the nine functional circuits in the multiplier-accumulator group 10 respectively encode nine groups of multiplicands and multipliers to obtain nine groups of partial products.

[0162] S202 , the multiplier-accumulator group divides the n groups of partial products into m partial products and sums them to obtain m first summation results.

[0163] wherein at least one of the partial products includes partial products from different groups. m is a positive integer greater than 1.

[0164] For example, when m is 2, the eight functional circuits in FIG4 , FIG5 , FIG7 and FIG9 divide the eight groups of partial products into two partial products, and output them to two first adding circuits for summation, thereby obtaining two first summation results.

[0165] For another example, when m is 3, in FIG11 , the nine functional circuits divide the nine groups of partial products into three partial products, and output them to the three first adding circuits for summation, thereby obtaining three first summation results.

[0166] For another example, when m is 4, in FIG12 , FIG14 and FIG16 , the eight functional circuits divide the eight groups of partial products into four partial products, and output them to the four first adding circuits for summation, thereby obtaining four first summation results.

[0167] For another example, when m is 6, in FIG18 , the eight functional circuits divide the eight groups of partial products into six partial products, and output them to the six first adding circuits for summation, thereby obtaining six first summation results.

[0168] S203 , the multiplier-accumulator group sums the m first summation results to obtain a second summation result.

[0169] For example, in FIG4 , FIG5 , FIG7 and FIG9 , the second adding circuit 130 adds the two first summing results from the two first adding circuits to obtain a second summing result.

[0170] For another example, in FIG11 , the second adding circuit 130 sums the three first summing results from the three first adding circuits to obtain a second summing result.

[0171] For another example, in FIG12 , FIG14 and FIG16 , the second adding circuit 130 sums the four first summing results from the four first adding circuits to obtain a second summing result.

[0172] For another example, in FIG18 , the second adding circuit 130 sums the six first summing results from the six first adding circuits to obtain a second summing result.

[0173] In one implementation, the n groups of partial products include p groups of partial products, and each group of partial products in the p groups of partial products is divided into multiple groups of partial products in the m groups of partial products, where p is a positive integer.

[0174] For example, in FIG11 , among the 8 groups of partial products generated by the functional circuits 110 - 117 in the 9 groups of partial products, each group of partial products is divided into 2 of the 3 partial products (i.e., 1 partial product received by the first adding circuit 120 and 1 partial product received by the first adding circuit 121).

[0175] In one implementation, the partial products obtained by encoding the multiplier and the multiplicand on the same digit in the p groups of partial products are divided into the same partial product among the m partial products.

[0176] For example, in FIG5 , among the eight groups of partial products generated by the functional circuits 110 - 127, the partial products obtained by encoding the multipliers and multiplicands at the lower bits are all divided into the one group of partial products received by the first adding circuit 120; and the partial products obtained by encoding the multipliers and multiplicands at the upper bits are all divided into the one group of partial products received by the first adding circuit 121.

[0177] For another example, in Figure 16, among the 8 groups of partial products generated by the functional circuits 110-127, the partial products obtained by encoding the multiplier and multiplicand at the lowest digit are divided into one partial product received by the first adding circuit 120 among the 4 partial products; the partial products obtained by encoding the multiplier and multiplicand at the second lowest digit are divided into one partial product received by the first adding circuit 121 among the 4 partial products; the partial products obtained by encoding the multiplier and multiplicand at the second highest digit are divided into one partial product received by the first adding circuit 122 among the 4 partial products; and the partial products obtained by encoding the multiplier and multiplicand at the highest digit are divided into one partial product received by the first adding circuit 123 among the 4 partial products.

[0178] In one implementation, the partial products of the p groups with faster signal level changes are divided into m1 partial products of the m partial products, and the partial products of the p groups with slower signal level changes are divided into m2 partial products of the m partial products. The m1 partial products and the m2 partial products are different.

[0179] For example, in FIG5 , the partial products with faster signal level changes among the 8 groups of partial products are divided into one partial product received by the first adding circuit 120 , and the partial products with slower signal level changes are divided into one partial product received by the first adding circuit 121 .

[0180] For another example, in Figures 7, 8, 9 and 10, the partial products in which the signal levels change slowly among the 8 groups of partial products are divided into a portion of the partial products received by the first adding circuit 120, and the partial products in which the signal levels change quickly are divided into a portion of the partial products received by the first adding circuit 121.

[0181] For another example, in Figures 12, 13A, 13B and 14, the partial products in the 8 groups of partial products whose signal levels change quickly are divided into two partial products received by the first addition circuit 120 and the first addition circuit 121, and the partial products in which the signal levels change slowly are divided into two partial products received by the first addition circuit 122 and the first addition circuit 123.

[0182] In one implementation, each group of partial products in the p groups of partial products is divided into q parts according to a signal level change rate, and is divided into q partial products in the m groups of partial products.

[0183] For example, in FIG16 , each of the eight groups of partial products is divided into four parts according to the signal level change speed, and is divided into the four partial products corresponding to the four first adding circuits respectively.

[0184] In one implementation, S203 specifically includes:

[0185] S203a1 , summing the data with the fastest signal level change speed in the m first summation results to obtain a third summation result.

[0186] S203a2: Sum the data with slow signal level changes in the m first summation results to obtain a fourth summation result.

[0187] For example, in Figure 14, the first sub-circuit 1301 sums the data with the fastest signal level change speed among the four first summation results output by the first adding circuit (i.e., the first summation result a output by the first adding circuit 120 and the first summation result b output by the first adding circuit 121) to obtain a third summation result.

[0188] The second sub-circuit 1302 sums the data with slow signal level change speed among the four first summation results output by the first adding circuit (i.e., the first summation result c output by the first adding circuit 122 and the first summation result d output by the first adding circuit 123) to obtain a fourth summation result.

[0189] In one implementation, S203 specifically includes:

[0190] S203b: Divide the m first summation results into s portions of data according to the signal level change speed, and sum the s portions of data respectively to obtain s summation results.

[0191] For example, in FIG18 , the first subcircuit 1301 , the second subcircuit 1302 , and the third subcircuit 1303 respectively sum three pieces of data to obtain three summation results.

[0192] In one implementation, S201 includes:

[0193] The n sets of multiplicands and multipliers are encoded in radix 2 to obtain n sets of partial products. Alternatively, the n sets of multiplicands and multipliers are encoded in radix 4 to obtain n sets of partial products. Alternatively, the n sets of multiplicands and multipliers are encoded in radix 8 to obtain n sets of partial products.

[0194] An embodiment of the present application further provides a chip, as shown in FIG20 , where the chip 30 includes a processor 301 and a multiplier-accumulator group 302 .

[0195] Specifically, the processor 301 may include a general-purpose central processing unit (CPU) and a memory. The processor 301 may also be a microprocessor, a field programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In a scenario where the processor 301 includes a CPU and a memory, the CPU may execute computer instructions stored in the memory.

[0196] In one implementation, the processor 301 may be an NPU.

[0197] The multiplier-accumulator group 302 is used to perform a multiplication-accumulation operation according to the operation process of the multiplier-accumulator group 10 described above in the embodiment of the present application when called by the processor 301.

[0198] In addition, the chip 30 may further include a memory 303. The memory 303 stores computer instructions, and the processor 301 may execute the computer instructions stored in the memory.

[0199] Specifically, the memory 303 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0200] In addition, the chip 30 may further include an interface 304. The interface 304 may be used to receive and send data. The interface 304 may be a communication interface or a transceiver.

[0201] In addition, the chip 30 may further include a communication line 305. For example, the communication line 305 may be a data bus for transmitting information between the above components.

[0202] FIG21 is a schematic diagram of the structure of another chip provided in an embodiment of the present application. The chip 40 includes a processor 401 .

[0203] The processor 401 includes a multiplier-adder group 4011. The multiplier-adder group 4011 is configured to, when called, perform a multiplication-accumulation operation according to the operation process of the multiplier-adder group 10 described above in the embodiment of the present application.

[0204] Specifically, the processor 401 may include a general-purpose central processing unit (CPU) and a memory, and the processor 301 may also be a microprocessor, a field programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In the scenario where the processor 401 includes a CPU and a memory, the CPU can execute computer instructions stored in the memory.

[0205] In one implementation, the processor 401 may be an NPU.

[0206] In addition, the chip 40 may further include a memory 402. The memory 402 stores computer instructions, and the processor 401 may execute the computer instructions stored in the memory.

[0207] Specifically, the memory 402 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0208] In addition, the chip 40 may further include an interface 403. The interface 403 may be used to receive and send data. The interface 403 may be a communication interface or a transceiver.

[0209] In addition, the chip 40 may further include a communication line 404. For example, the communication line 404 may be a data bus for transmitting information between the above components.

[0210] In addition, an embodiment of the present application further provides an electronic device. As shown in FIG22 , the electronic device 50 includes a printed circuit board (PCB) 501 and a chip 502 . The chip 502 is electrically connected to the PCB 501 .

[0211] The chip 502 may specifically be the aforementioned chip 30 or chip 40 .

[0212] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0213] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0214] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical business division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0215] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A multiplier-adder group, characterized in that: include: n functional circuits, m first adding circuits and m second adding circuits; The output end of each of the functional circuits is connected to the input end of at least one of the first adding circuits, wherein at least one of the first adding circuits is connected to a plurality of the functional circuits; the output ends of the m first adding circuits are connected to the input end of the second adding circuit; n is a positive integer greater than 2, and m is a positive integer greater than 1; The functional circuit is used to output the encoded partial product after inputting the multiplicand and the multiplier; The first adding circuit is used to sum the partial products to obtain a first summation result, and output the first summation result; The second adding circuit is used to sum the first summing results to obtain a second summing result, and output the second summing result.

2. The multiplier-adder group according to claim 1, characterized in that: The n functional circuits include p functional circuits, and the output end of each functional circuit in the p functional circuits is connected to the input ends of multiple first adding circuits, wherein p is a positive integer.

3. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to output partial products obtained by encoding the multipliers and multiplicands at different digits in the partial products to different first adding circuits.

4. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to output a first set of partial products in the partial products to m1 first adding circuits, and to output a second set of partial products in the partial products to m2 first adding circuits, the m1 first adding circuits are different from the m2 first adding circuits, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

5. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to divide the partial product into q parts according to the signal level change speed, and output them to different first adding circuits, where q is a positive integer greater than 1.

6. The multiplier-adder group according to any one of claims 1 to 5, characterized in that: The second adding circuit comprises a first subcircuit and a second subcircuit; the first subcircuit and the second subcircuit are respectively used to sum the data from the first adding circuit; the output ends of the m first adding circuits are respectively connected to the input end of the first subcircuit and the input end of the second subcircuit; The m first adding circuits are specifically used to output the first data set in the first summation result to the first sub-circuit, and output the second data set in the first summation result to the second sub-circuit, and the signal level of the data in the first data set changes faster than the signal level of the data in the second data set.

7. The multiplier-adder group according to any one of claims 1 to 5, characterized in that: The second adding circuit includes s sub-circuits, and the s sub-circuits are respectively used to sum the data from the first adding circuit; The m first adding circuits are specifically used to divide the first summation result into s output data according to the signal level change speed, and output the s output data to the s sub-circuits respectively.

8. The multiplier-adder group according to any one of claims 1 to 7, characterized in that: The n functional circuits are respectively encoded in a radix-2 manner to obtain partial products, or the n functional circuits are respectively encoded in a radix-4 manner to obtain partial products, or the n functional circuits are respectively encoded in a radix-8 manner to obtain partial products.

9. A multiply-accumulate method, applied to a multiplier-accumulator group, characterized in that: The method comprises: Encode n groups of multiplicands and multipliers to obtain n groups of partial products; Dividing the n groups of partial products into m partial products for summing, to obtain m first summation results, wherein at least one partial product includes partial products from different groups; n is a positive integer greater than 2, and m is a positive integer greater than 1; The m first summation results are summed to obtain a second summation result.

10. The method according to claim 9, characterized in that The n groups of partial products include p groups of partial products, each group of partial products in the p groups of partial products is divided into a plurality of partial products in the m groups of partial products, wherein p is a positive integer.

11. The method according to claim 10, characterized in that The partial products obtained by encoding the multipliers and multiplicands at different digits in the p groups of partial products are divided into different parts of the m partial products.

12. The method according to claim 10, characterized in that The first set of partial products in the p groups of partial products is divided into m1 sets of partial products in the m groups of partial products, and the second set of partial products in the p groups of partial products is divided into m2 sets of partial products in the m groups of partial products; wherein the m1 sets of partial products are different from the m2 sets of partial products, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

13. The method according to claim 10, characterized in that Each group of partial products in the p groups of partial products is divided into q parts according to a signal level change speed, and is divided into q parts of partial products in the m parts of partial products.

14. The method according to any one of claims 9 to 13, characterized in that: The step of summing the m first summation results to obtain a second summation result includes: Summing the first data sets in the m first summation results to obtain a third summation result; The second data sets in the m first summation results are summed to obtain a fourth summation result; the signal level of the data in the first data set changes faster than the signal level of the data in the second data set.

15. The method according to any one of claims 9 to 13, characterized in that: The step of summing the m first summation results to obtain a second summation result includes: The m first summation results are divided into s portions of data according to the signal level change speed, and the s portions of data are summed respectively to obtain s summation results.

16. The method according to any one of claims 9 to 15, characterized in that: The encoding of n groups of multiplicands and multipliers to obtain n groups of partial products includes: Encode n groups of multiplicands and multipliers in a radix-2 manner to obtain n groups of partial products; or, encode n groups of multiplicands and multipliers in a radix-4 manner to obtain n groups of partial products; or, encode n groups of multiplicands and multipliers in a radix-8 manner to obtain n groups of partial products.

17. A chip, characterized in that: The chip comprises a processor and a multiplier-accumulator group as claimed in any one of claims 1 to 8.

18. The chip according to claim 17, characterized in that: The processor is a neural network processor NPU.

19. An electronic device, characterized in that: It comprises a printed circuit board and the chip as claimed in claim 17 or 18; the chip is electrically connected to the printed circuit board.

Images