Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of maintaining high capacity even when a DC voltage is applied. This multilayer ceramic capacitor 1 comprises: a laminate 2 including a plurality of laminated dielectric layers and a plurality of first internal electrode layers 6a and second internal electrode layers 6b; a first external electrode 20a disposed on a first end surface E1; and a second external electrode 20b disposed on a second end surface E2. The material of the first internal electrode layers 6a and the material of the second internal electrode layers 6b are different. The first internal electrode layers 6a and the dielectric layers are Schottky-joined. The second internal electrode layers 6b and the dielectric layers are Schottky-joined or ohmic-joined. In a state in which no voltage is applied between the first external electrode 20a and the second external electrode 20b, the difference between the work function of the first internal electrode layers 6a and the work function of the dielectric layers is greater than the difference between the work function of the second internal electrode layers 6b and the work function of the dielectric layers.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] A multilayer ceramic capacitor is known that can maintain its capacitance even when a DC voltage is applied. Patent Document 1 discloses a multilayer ceramic capacitor in which the dielectric layer is made of a material such as Bi. １－ｘ Sr ｘ ) (Fe １－ｙ Ti ｙ ) O ３ It is described that a magnetic composition having an average sintered particle size of 1.0 μm or less is used, where x is 0.2≦x≦0.7 and y is 0.2≦y≦0.7.

[0003] JP 2014-189464 A

[0004] However, conventional multilayer ceramic capacitors have a problem in that the capacitance they can maintain is insufficient in some cases. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that can maintain a high capacitance even when a DC voltage is applied.

[0005] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrode layers, the laminate having first and second main surfaces opposing each other in the lamination direction, first end faces and second end faces opposing each other in a length direction that is a direction perpendicular to the lamination direction, and first side faces and second side faces opposing each other in a width direction that is a direction perpendicular to the lamination direction and the length direction, and a first external electrode arranged on the first end face and a second external electrode arranged on the second end face, wherein the material of the first internal electrode layers is different from the material of the second internal electrode layers, the first internal electrode layers and the dielectric layers are connected to each other through a Schottky junction, and the second internal electrode layers and the dielectric layers are connected to each other through a Schottky junction or an ohmic junction, and when no voltage is applied between the first external electrode layers and the second external electrode, a difference between the work function of the first internal electrode layers and the work function of the dielectric layers is larger than a difference between the work function of the second internal electrode layers and the dielectric layers.

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can maintain a high capacitance even when a DC voltage is applied.

[0007] It is a perspective view of the multilayer ceramic capacitor of the present embodiment. It is a cross-sectional view taken along line II in Fig. 1. It is a cross-sectional view taken along line II-II in Fig. 1. It is an explanatory diagram showing an enlarged view of a part of Fig. 2. It is a table showing the relationship between DC voltage and capacitance.

[0008] An embodiment of the invention will be described with reference to FIG. 1. FIG. 1 is a perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes. The external electrodes include a first external electrode 20a and a second external electrode 20b. (Laminate) The laminate 2 includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together. The shape of the laminate 2 is approximately a rectangular parallelepiped. In the laminate 2, the direction in which the dielectric layers and internal electrode layers are stacked is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the width direction W. The direction perpendicular to the stacking direction T and the width direction W is referred to as the length direction L.

[0009] In the laminate 2, of the two outer surfaces facing each other in the stacking direction T, one outer surface is designated as the first main surface M1. The remaining outer surface is designated as the second main surface M2. In the laminate 2, of the two outer surfaces facing each other in the width direction W, one outer surface is designated as the first side surface S1. The remaining outer surface is designated as the second side surface S2. In the laminate 2, of the two outer surfaces facing each other in the length direction L, one outer surface is designated as the first end surface E1. The remaining outer surface is designated as the second end surface E2. The mounting surface of the multilayer ceramic capacitor 1 is the second main surface M2. The mounting surface is the surface that faces a wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0010] Regarding the cross section of the multilayer ceramic capacitor 1, the cross section taken along line II in Fig. 1 is referred to as the LT cross section, the cross section taken along line II-II in Fig. 1 is referred to as the WT cross section, and the cross section of the laminate 2 taken along line III-III in Fig. 1 is referred to as the LW cross section.

[0011] It is preferable that the corners and ridges of the laminate 2 are rounded. The corners are the portions where three outer side surfaces of the laminate 2 intersect. The ridges are the portions where two outer side surfaces of the laminate 2 intersect. The main surface, side surfaces, and end surfaces may be partially or entirely uneven.

[0012] (Dielectric Layer) The total number of dielectric layers stacked in the laminate 2 is preferably 15 to 2000. The main material of the dielectric layers is a ceramic material. An example of the ceramic material is BaTiO ３ (barium titanate), CaTiO ３ , SrTiO ３ , CaZrO ３ The dielectric ceramic may contain, in addition to the main component, a secondary component. Examples of the secondary component include a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound.

[0013] The material forming the dielectric layer may contain a rare earth element, such as Dy or Ho.

[0014] The dielectric layer may include a layer made of a semiconductor material other than barium titanate in addition to a layer made of barium titanate. An example of a semiconductor material other than barium titanate is MoS. ２ , MoO ｘ , WSe ２ , CdTe, etc. Layers formed of semiconductor materials other than barium titanate will be described later.

[0015] The thickness of each dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0016] (Division of Laminate) The division of the laminate 2 in the stacking direction T will be described with reference to Figure 2. Figure 2 is a cross-sectional view taken along line II in Figure 1. The laminate 2 is divided into a first main surface side outer layer portion OL1, an inner layer portion IL, and a second main surface side outer layer portion OL2 in the stacking direction T. The first main surface side outer layer portion OL1, the inner layer portion IL, and the second main surface side outer layer portion OL2 are arranged in this order from the first main surface M1 to the second main surface M2 in the stacking direction T.

[0017] The first outer layer portion OL1 is a portion between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The internal layer portion IL is a portion where two internal electrode layers face each other. The second outer layer portion I is a portion between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0018] The first main surface side outer layer portion OL1 is formed by an assembly of a plurality of dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1.

[0019] The second main surface side outer layer portion OL2 is formed by an assembly of a plurality of dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0020] The inner layer portion IL is a portion sandwiched between the first outer layer portion OL1 and the second outer layer portion OL2, and is formed by stacking a plurality of internal electrode layers and a plurality of dielectric layers.

[0021] Of the dielectric layers, the dielectric layers disposed in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 are referred to as outer dielectric layers 3. Of the dielectric layers, the dielectric layers disposed in the inner layer portion IL are referred to as inner dielectric layers 4.

[0022] The following terms are used in the description of length and position: The length in the length direction L is referred to as the length direction length; The length in the width direction W is referred to as the width direction length; The length in the stacking direction T is referred to as the stacking direction length.

[0023] The position that is half the length of the length direction of the laminate 2 is referred to as the center position in the length direction. The position that is half the length of the width direction of the laminate 2 is referred to as the center position in the width direction of the laminate 2. The position that is half the length of the stacking direction of the laminate 2 is referred to as the center position in the stacking direction.

[0024] The size of the laminate 2 is not particularly limited. The length of the laminate in the longitudinal direction is preferably 0.2 mm or more and 10 mm or less. The length of the laminate 2 in the width direction is preferably 0.1 mm or more and 5 mm or less. The length of the laminate 2 in the stacking direction is preferably 0.1 mm or more and 5 mm or less.

[0025] (L Gap) The division of the laminate 2 in the longitudinal direction L will be described. The laminate 2 is divided into a first end face side outer layer portion LG1, a longitudinally facing portion LF, and a second end face side outer layer portion LG2 in the longitudinal direction L. The first end face side outer layer portion LG1, the longitudinally facing portion LF, and the second end face side outer layer portion LG2 are arranged in this order in the longitudinal direction L from the first end face E1 to the second end face E2.

[0026] The first end face side outer layer portion LG1 is a portion between the longitudinal facing portion LF and the first end face E1. The second end face side outer layer portion LG2 is a portion between the longitudinal facing portion LF and the second end face E2. The longitudinal facing portion LF is a portion where the first internal electrode layer 6 a and the second internal electrode layer 6 b face each other in the stacking direction T.

[0027] The longitudinally facing portion LF corresponds to the facing electrode portion of the internal electrode layer. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 correspond to the lead electrode portions of the internal electrode layer. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are called L gaps.

[0028] (W Gap) The division of the laminate 2 in the width direction W will be described with reference to Figure 3. Figure 3 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 is divided into a first side surface side outer layer portion WG1, a widthwise opposing portion WF, and a second side surface side outer layer portion WG2 in the width direction W. The first side surface side outer layer portion WG1, the widthwise opposing portion WF, and the second side surface side outer layer portion WG2 are arranged in this order in the width direction W from the first side surface S1 to the second side surface S2.

[0029] The widthwise facing portion WF is a portion where the internal electrode layers face each other in the stacking direction T. The first side surface side outer layer portion WG1 is a portion between the widthwise facing portion WF and the first side surface S1. The second side surface side outer layer portion WG2 is a portion between the widthwise facing portion WF and the second side surface S2. The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are called a W gap.

[0030] The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 do not have internal electrode layers in the stacking direction T. The first side surface side outer layer portion WG1 is formed by a plurality of dielectric layers located between the first side surface S1 and the outermost surface of the widthwise opposing portion WF on the first side surface S1 side.

[0031] The second side surface outer layer portion WG2 is located on the second side surface S2 side and is formed of a plurality of dielectric layers located between the second side surface S2 and the outermost surface of the widthwise facing portion WF on the second side surface S2 side.

[0032] (Internal Electrode Layers) The internal electrode layers include a plurality of first internal electrode layers 6 a and a plurality of second internal electrode layers 6 b. The first internal electrode layers 6 a are internal electrode layers exposed at the first end face E1. The second internal electrode layers 6 b are internal electrode layers exposed at the second end face E2.

[0033] The first internal electrode layer 6a is divided into a first opposing electrode portion 7a and a first lead electrode portion 8a. The first opposing electrode portion 7a is a portion facing the second internal electrode layer 6b. The first lead electrode portion 8a is a portion led out from the first opposing electrode portion 7a to the first end face E1.

[0034] The second internal electrode layer 6b is divided into a second opposing electrode portion 7b and a second lead electrode portion 8b. The second opposing electrode portion 7b is a portion facing the first internal electrode layer 6a. The second lead electrode portion 8b is a portion led out from the second opposing electrode portion 7b to the second end face E2.

[0035] The material of the internal electrode layers can be, for example, a metal such as Ni, Cu, Ag, Pd, Au, etc. Also, the material of the internal electrode layers can be, for example, an alloy containing at least one of the above-mentioned metals, such as an Ag—Pd alloy.

[0036] The internal electrode layers may be formed of Ni coated with Sn, which will be described later.

[0037] In the multilayer ceramic capacitor 1, capacitance is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b facing each other via the inner dielectric layer 4. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0038] The thickness of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably 15 or more and 2000 or less.

[0039] (External Electrodes) The external electrodes will now be described. As shown in Figures 1 and 2, the external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is connected to the first internal electrode layer 6a. The first external electrode 20a extends from the first end face E1 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2.

[0040] The second external electrode 20b is connected to the second internal electrode layer 6b and extends from the second end face E2 to a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0041] The external electrodes preferably have a base electrode layer and a plating layer. The base electrode layer may include at least one layer selected from a baked layer, a conductive resin layer, a thin film layer, etc. The conductive resin layer may be provided separately from the base electrode layer.

[0042] An example will be described in which a baked layer is provided as a base electrode layer and a conductive resin layer is provided separately from the base electrode layer. In this configuration, the first external electrode 20a includes a first base electrode layer 21a, a first conductive resin layer 22a, a first lower plating layer 23a, and a first upper plating layer 24a. The second external electrode 20b includes a second base electrode layer 21b, a second conductive resin layer 22b, a second lower plating layer 23b, and a second upper plating layer 24b.

[0043] (Base Electrode Layer) The base electrode layer includes a first base electrode layer 21a and a second base electrode layer 21b. The first base electrode layer 21a is disposed on the first end face E1, a portion of the first main surface M1, a portion of the second main surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2. The second base electrode layer 21b is disposed on the second end face E2, a portion of the first main surface M1, a portion of the second main surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2.

[0044] The base electrode layer includes a conductive metal and a glass component. The conductive metal includes at least one of Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au. The glass component includes at least one of B, Si, Ba, Mg, Al, and Li.

[0045] The base electrode layer is formed as follows: A conductive metal and a glass component are blended to obtain a conductive paste; The conductive paste is applied to the laminate; and The applied conductive paste is baked.

[0046] The conductive paste can be baked simultaneously with the firing of the internal electrode layers and the firing of the dielectric layers, or can be baked after the firing of the internal electrode layers and the firing of the dielectric layers.

[0047] When the conductive paste is baked simultaneously with the firing of the internal electrode layers and the firing of the dielectric layers, it is preferable to add a dielectric material to the conductive paste, which can improve the adhesion between the base electrode layers and the internal electrode layers.

[0048] The thickness of the base electrode layer located on the first end face E1 or the second end face E2 at the center in the stacking direction is preferably about 10 μm or more and 150 μm or less.

[0049] When the base electrode layer is a thin film layer, the thin film layer can be formed using a thin film formation method. Thin film formation methods include sputtering and vapor deposition. The thin film layer is formed as a layer in which metal particles are deposited. The thickness of the formed thin film layer is 1 μm or less.

[0050] (Conductive Resin Layer) A conductive resin layer is disposed on the base electrode layer. The conductive resin layer includes a first conductive resin layer 22a and a second conductive resin layer 22b.

[0051] The first conductive resin layer 22a is disposed on the first base electrode layer 21a. The first conductive resin layer 22a covers the first base electrode layer 21a. It is preferable that an end of the first conductive resin layer 22a contacts the laminate 2.

[0052] The second conductive resin layer 22b is disposed on the second base electrode layer 21b. The second conductive resin layer 22b covers the second base electrode layer 21b. It is preferable that an end of the second conductive resin layer 22b contacts the laminate 2.

[0053] The conductive resin layer contains a resin component and a metal component. The resin component contains a thermosetting resin. The conductive resin layer is more flexible than the base electrode layer for the following reasons: The conductive resin layer contains a resin component. The base electrode layer does not contain a resin component. The base electrode layer is a fired product containing a plating film, a metal component, a glass component, etc. For these reasons, the conductive resin layer is more flexible than the base electrode layer.

[0054] The conductive resin layer functions as a buffer layer. Cracks are less likely to occur in the multilayer ceramic capacitor 1 including the conductive resin layer. This is because when a bending stress is applied to the substrate on which the multilayer ceramic capacitor 1 is mounted, and this stress causes a physical impact on the multilayer ceramic capacitor 1, the conductive resin layer cushions the impact. Furthermore, when an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer cushions the impact.

[0055] The conductive resin layer includes a thermosetting resin. The thermosetting resin is selected from epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these resins, epoxy resin is one of the most suitable resins because epoxy resin has excellent heat resistance, moisture resistance, adhesion, etc.

[0056] The conductive resin layer contains, as a metal component, Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The metal component is preferably in the form of a filler. When the metal component is a metal powder, the surface of the metal powder may be coated with Sn, Ni, or Cu.

[0057] The metal component preferably contains Ag. Ag may be simple Ag, or may be an alloy containing Ag. Ag may also be contained as a coating material for the metal powder.

[0058] The use of Ag as a coating material for metal powder has the following advantages. Ag has the lowest resistivity of all metals, which makes it possible to reduce the electrical resistance of the conductive resin layer. Ag is also resistant to oxidation, which makes it possible to increase the resistance of the conductive resin layer.

[0059] A metal component in filler form is called a metal filler. The preferred shape of the metal filler is spherical or flat. The metal filler may be a mixture of spherical and flat metal fillers.

[0060] The average particle size of the metal filler is not particularly limited. For example, the average particle size of the metal filler can be 0.3 μm or more and 10 μm or less. The average particle size of the metal filler can be calculated using a laser diffraction particle size measurement method (based on IOS 13320). This method of calculating the average particle size can be used regardless of the shape of the filler.

[0061] The metal filler makes the conductive resin layer a conductive layer because contact between the metal filler particles forms a conductive path within the conductive resin layer.

[0062] The conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the thermosetting resin, the curing agent is selected from phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds.

[0063] The amount of metal contained in the conductive resin layer is preferably 35 vmol% or more and 75 vmol% or less with respect to the total volume of the conductive resin layer.

[0064] The amount of resin contained in the conductive resin layer is preferably 25 vmol% or more and 65 vmol% or less with respect to the total volume of the conductive resin layer.

[0065] The thickness of the conductive resin layer located on the first end face E1 or the second end face E2 at the center in the stacking direction is preferably about 10 μm or more and 200 μm or less.

[0066] When a conductive resin layer is provided on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, it is preferable that the thickness of the conductive resin layer located on the first main surface M1 or the second main surface M2, or the first side surface S1 or the second side surface S2, at the center position in the longitudinal direction is approximately 10 μm or more and 200 μm or less.

[0067] (Plating Layer) The plating layer includes a lower plating layer and an upper plating layer. The lower plating layer is a Ni plating layer. The upper plating layer is a Sn plating layer. The plating layer may be a single layer.

[0068] (Underlayer plating layer) The underlayer plating layer is disposed on the conductive resin layer. The underlayer plating layer covers at least a portion of the conductive resin layer. The underlayer plating layer includes a first underlayer plating layer 23a and a second underlayer plating layer 23b. The first underlayer plating layer 23a is disposed on the first conductive resin layer 22a. The second underlayer plating layer 23b is disposed on the second conductive resin layer 22b.

[0069] The lower plating layer is a Ni plating layer. By using a Ni plating layer as the lower plating layer, it is possible to prevent the base electrode layer and the like from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on a substrate.

[0070] (Upper-layer plating layer) The upper-layer plating layer is disposed on the lower-layer plating layer. The upper-layer plating layer covers at least a portion of the lower-layer plating layer. The upper-layer plating layer includes a first upper-layer plating layer 24a and a second upper-layer plating layer 24b. The first upper-layer plating layer 24a is disposed on the first lower-layer plating layer 23a. The second upper-layer plating layer 24b is disposed on the second lower-layer plating layer 23b.

[0071] The upper plating layer is a Sn plating layer. Solder easily wets and spreads on the Sn plating layer. By using a Sn plating layer as the upper plating layer, it is possible to easily mount the multilayer ceramic capacitor 1 on a substrate or the like.

[0072] The metal forming the lower plating layer and the metal forming the upper plating layer are not limited to Ni or Sn. Metals such as Cu, Ni, Ag, Pd, Au, and Sn, as well as alloys such as Ag—Pd alloys, can be used to form the lower plating layer or the upper plating layer.

[0073] The thickness of the lower plating layer and the upper plating layer is preferably 2 μm or more and 15 μm or less.

[0074] The external electrodes may contain Sn. The Sn content of the first external electrode 20a may be different from that of the second external electrode 20b.

[0075] It is also preferable that the shape of the first external electrode 20a is different from the shape of the second external electrode 20b. The fact that the external electrodes contain Sn and that the shapes of the external electrodes are different will be described later.

[0076] The size of the multilayer ceramic capacitor 1 is not particularly limited. The length in the longitudinal direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.2 mm or more and 10 mm or less. The length in the lamination direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 5 mm or less. The length in the width direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 10 mm or less.

[0077] (Schottky Junction) In the multilayer ceramic capacitor 1 of this embodiment, the first internal electrode layer 6a and the internal dielectric layer 4 are connected by a Schottky junction. On the other hand, the second internal electrode layer 6b and the internal dielectric layer 4 are connected by a Schottky junction or an ohmic junction.

[0078] A Schottky junction is a junction that exhibits rectification between a metal and a semiconductor. Rectification refers to the ability to pass current in only one direction. An ohmic junction is an electrical junction in which the relationship between current and voltage follows Ohm's law.

[0079] Fig. 4 is an enlarged view of the dashed-line box R1 in Fig. 3. Fig. 4 shows the first internal electrode layer 6a, the second internal electrode layer 6b, and the inner dielectric layer 4 sandwiched between the first internal electrode layer 6a and the second internal electrode layer 6b.

[0080] (State with no voltage applied) In the multilayer ceramic capacitor 1 of this embodiment, the difference between the work function of the first internal electrode layer 6a and the work function of the internal dielectric layer 4 is larger than the difference between the work function of the second internal electrode layer 6b and the work function of the internal dielectric layer 4. Therefore, in a state where no voltage is applied between the first external electrode 20a and the second external electrode 20b, the electric field generated on the first internal electrode layer 6a side is larger than the electric field generated on the second internal electrode layer 6b side.

[0081] Arrows A1 and A2 in Fig. 4 indicate electric fields. The direction of the arrows indicates the direction of the electric field. The length of the arrows indicates the strength of the electric field. In a state where no voltage is applied, an electric field indicated by arrow A1 is generated from the first internal electrode layer 6a toward the second internal electrode layer 6b. Also, an electric field indicated by arrow A2 is generated from the second internal electrode layer 6b toward the first internal electrode layer 6a. The electric field indicated by arrow A1 is referred to as the first electric field A1. Also, the electric field indicated by arrow A2 is referred to as the second electric field A2.

[0082] The first electric field A1 and the second electric field A2 have opposite directions, and the strength of the first electric field A1 is stronger than the strength of the second electric field A2.

[0083] (Residual Electric Field) As shown in Fig. 4, a residual electric field exists in the multilayer ceramic capacitor 1 even when there is no potential difference between the first internal electrode layer 6a and the second internal electrode layer 6b. The residual electric field is the electric field remaining after subtracting the weak electric field from the strong electric field. In the example shown in Fig. 4, the residual electric field is the electric field obtained by subtracting the second electric field A2 from the first electric field A1.

[0084] When the second internal electrode layer 6b and the internal dielectric layer 4 are in ohmic contact, the second electric field A2 is 0. When the second electric field A2 is 0, the residual electric field becomes the first electric field A1.

[0085] The multilayer ceramic capacitor 1 is mounted on a substrate so that the DC potential of the second internal electrode layer 6b is high and the DC potential of the first internal electrode layer 6a is low.

[0086] (Unbalanced Schottky junction) Here, the following junctions 1) and 2) are defined as unbalanced Schottky junctions: 1) A junction where there are two electric fields generated by the Schottky junction, which are directed in opposite directions and have different intensities. 2) A junction where there is an electric field generated by the Schottky junction, but there is no other electric field that cancels out the electric field.

[0087] In the example shown in Fig. 4, the strength of the electric field generated on the first internal electrode layer 6a side is different from the strength of the electric field generated on the second internal electrode layer 6b side. Therefore, the junction shown in Fig. 4 is an unbalanced Schottky junction. When an unbalanced Schottky junction occurs, a residual electric field is generated there.

[0088] (Work Function) One method for achieving an unbalanced Schottky junction is to adjust the work function values ​​of each component. The strength of the electric field generated by the Schottky junction is determined by the difference in work function between the members being joined. In the example shown in FIG. 4 , the difference between the work function of the first internal electrode layer 6a and the work function of the inner dielectric layer 4 is different from the difference between the work function of the second internal electrode layer 6b and the work function of the inner dielectric layer 4. Therefore, the strength of the electric field generated at the junction between the first internal electrode layer 6a and the inner dielectric layer 4 is different from the strength of the electric field generated at the junction between the second internal electrode layer 6b and the inner dielectric layer 4. As a result, an unbalanced Schottky junction is achieved.

[0089] There are various conceivable methods for differentiating the difference between the work function of the first internal electrode layer 6a and the work function of the inner dielectric layer 4 and the difference between the work function of the second internal electrode layer 6b and the work function of the inner dielectric layer 4. Making the material of the first internal electrode layer 6a different from the material of the second internal electrode layer 6b is one example of such a method. If the material of the first internal electrode layer 6a is different from the material of the second internal electrode layer 6b, the bonding state between the first internal electrode layer 6a and the inner dielectric layer 4 will differ from the bonding state between the second internal electrode layer 6b and the inner dielectric layer 4. As a result, the strength of the first electric field A1 can be made different from the strength of the second electric field A2.

[0090] (Sn Content of Internal Electrode Layers) There are various possible methods for differentiating the material of the first internal electrode layer 6a from the material of the second internal electrode layer 6b. One example of this method will be described. The main component of the first internal electrode layer 6a and the main component of the second internal electrode layer 6b are Ni. Then, Sn is contained in the first internal electrode layer 6a and the second internal electrode layer 6b. When Sn is contained, the Sn content of the first internal electrode layer 6a is made different from the Sn content of the second internal electrode layer 6b. By making the Sn content different, the material of the first internal electrode layer 6a can be made different from the material of the second internal electrode layer 6b.

[0091] (Sn Content of External Electrodes) Another method for achieving an unbalanced Schottky junction is to use different materials for the external electrodes. The first internal electrode layer 6a and the second internal electrode layer 6b are connected to different external electrodes. The first internal electrode layer 6a is connected to the first external electrode 20a. The second internal electrode layer 6b is connected to the second external electrode 20b. Therefore, by using different materials for the first external electrode 20a and the second external electrode 20b, the junction state of the first internal electrode layer 6a and the junction state of the second internal electrode layer 6b can be made different. This allows for an unbalanced Schottky junction to be achieved.

[0092] There are various possible methods for differentiating the material of the first external electrode 20a from the material of the second external electrode 20b. One example of such a method is to make at least one of the first external electrode 20a and the second external electrode 20b contain Sn. When making the first external electrode 20a and the second external electrode 20b contain Sn, the Sn content of the first external electrode 20a and the Sn content of the second external electrode 20b are made different. Sn may be contained in only one of the electrodes. By making the Sn content different, the material of the first external electrode 20a and the material of the second external electrode 20b can be made different.

[0093] Specifically, the Sn content may be made different between the first base electrode layer 21 a and the second base electrode layer 21 b, or between the first conductive resin layer 22 a and the second conductive resin layer 22 b.

[0094] (Dielectric Region) Another method for realizing an unbalanced Schottky junction is to use different materials for the inner dielectric layers 4. In this method, the material of the inner dielectric layer 4 in contact with the first internal electrode layer 6 a is made different from the material of the inner dielectric layer 4 in contact with the second internal electrode layer 6 b.

[0095] As shown in Figure 4, the inner dielectric layer 4 includes a plurality of dielectric regions. Each dielectric region is formed of a different material. In the example shown in Figure 4, the inner dielectric layer 4 includes a first dielectric region 4a and a second dielectric region 4b. The first dielectric region 4a contacts the first internal electrode layer 6a. The second dielectric region 4b contacts the second internal electrode layer 6b. By forming the first dielectric region 4a and the second dielectric region 4b from different materials, an unbalanced Schottky junction can be realized.

[0096] Methods for forming the dielectric regions from different materials include using different main dielectric materials, using different types of additives such as rare earth elements, and using different amounts of additives.

[0097] (Shape of External Electrodes) As described above, the multilayer ceramic capacitor 1 is mounted on a substrate so that the DC potential of the second internal electrode layers 6b is high and the DC potential of the first internal electrode layers 6a is low. When mounting the multilayer ceramic capacitor 1 on a substrate, if the first main surface M1 and the second main surface M2 can be easily distinguished, it becomes easy to mount the multilayer ceramic capacitor 1 accurately on the substrate. In other words, understanding the polarity of the external electrodes is extremely important for the multilayer ceramic capacitor 1 of this embodiment.

[0098] There are various possible methods for making it possible to easily distinguish between the first main surface M1 and the second main surface M2 of the multilayer ceramic capacitor 1. One example of such a method is to make the appearance of the first external electrode 20a different from that of the second external electrode 20b. One method for making the appearances different is to make the shapes of the external electrodes different. Examples of different shapes include having a notch in only one of the external electrodes and having a protrusion in only one of the external electrodes.

[0099] Another way to make the appearance different is to use different colors, and another way to make the appearance different is to provide an alignment mark or other marking on only one side.

[0100] The multilayer ceramic capacitor 1 of this embodiment has an unbalanced Schottky junction, which can suppress a decrease in capacitance when a DC voltage is applied. FIG. 5 is a diagram showing the relationship between DC voltage and capacitance. The horizontal axis of the graph shown in FIG. 5 represents the DC voltage applied to the multilayer ceramic capacitor 1. The vertical axis of the graph shown in FIG. 5 represents the capacitance of the multilayer ceramic capacitor 1. Graph G1 shows the c-v curve of a multilayer ceramic capacitor without an unbalanced Schottky junction. Graph G2 shows the c-v curve of the multilayer ceramic capacitor 1 of this embodiment, which has an unbalanced Schottky junction. As shown in FIG. 5, the presence of an unbalanced Schottky junction shifts the c-v curve in the positive direction on the horizontal axis. Shifting the c-v curve in the positive direction on the horizontal axis increases the value of the DC voltage at which the capacitance peaks.

[0101] As the voltage applied to the multilayer ceramic capacitor 1 of this embodiment increases, in other words, as the potential difference between the first external electrode 20a and the second external electrode 20b increases, the residual electric field is gradually canceled. The portion indicated by arrow A3 in graph G2 of FIG. 5 corresponds to the portion where the residual electric field is canceled. When the residual electric field is completely canceled, i.e., when the residual electric field disappears, the multilayer ceramic capacitor 1 enters a state where no electric field exists despite the application of a DC voltage. That is, in the multilayer ceramic capacitor 1 of this embodiment, the capacitance is greater when a DC voltage is applied than when no DC voltage is applied. Therefore, the multilayer ceramic capacitor 1 of this embodiment can suppress a decrease in capacitance when a DC voltage is applied. In other words, the multilayer ceramic capacitor 1 can maintain a high capacitance even when a DC voltage is applied.

[0102] The Schottky junction will be explained in more detail below. A Schottky junction occurs when the following conditions are met: (1) When the ceramic material of the dielectric layer is a P-type semiconductor The ceramic material (P-type semiconductor) and the internal electrode layer (metal) form a Schottky junction when the following conditions are met: <Condition> Work function φs of the ceramic material> Work function φm of the internal electrode layer (2) When the ceramic material of the dielectric layer is an N-type semiconductor The ceramic material (N-type semiconductor) and the internal electrode layer (metal) form a Schottky junction when the following conditions are met: <Condition> Work function φs of the ceramic material< Work function φm of the internal electrode layer

[0103] (Ceramic material of the dielectric layer) Oxygen vacancies occur in ceramic materials such as barium titanate. The oxygen vacancies function as donors that release electrons. Therefore, ceramic materials such as barium titanate have properties as N-type semiconductors.

[0104] Here, the amount of oxygen vacancies can be changed by adding rare earth elements such as Dy, Ho, etc. This means that the work function of the ceramic material can be adjusted to some extent by adding rare earth elements.

[0105] The generation of oxygen vacancies is suppressed by adding rare earth elements as acceptor elements to ceramic materials. In this case, the amount of rare earth elements added is greater than the minimum amount necessary to suppress the generation of oxygen vacancies. As a result, the ceramic material often functions as a P-type semiconductor.

[0106] Thus, the ceramic material can function as either a P-type semiconductor or an N-type semiconductor depending on the amount of rare earth element added.

[0107] (Barium titanate (P-type)) Barium titanate BaTiO was used as the ceramic material for the dielectric layer. ３Here, the case where barium titanate is used will be described. Here, barium titanate functions as a P-type semiconductor. The work function of barium titanate is 4.8 eV. In order to generate a Schottky junction, the work function of the internal electrode layer must be less than 4.8 eV. Ni is often used as the material for the internal electrode layer. The work function of Ni is 5.2 eV. Therefore, when the dielectric layer is formed of barium titanate and the internal electrode layer is formed of Ni, a Schottky junction does not occur between the dielectric layer and the internal electrode layer.

[0108] (Sn Coating) Here, the work function of Sn is 4.4 eV. Therefore, if the metal in contact with barium titanate is Sn, a Schottky junction will occur. Therefore, the material of the internal electrode layer is Ni coated with Sn. By using Sn as the coating agent, a Schottky junction can be generated between the dielectric layer and the internal electrode layer.

[0109] (Unbalanced Schottky Junction) When the ceramic material of the dielectric layers is barium titanate, the following configuration can be considered as a configuration for generating an unbalanced Schottky junction. The first internal electrode layer 6a is formed of Ni coated with Sn. On the other hand, the second internal electrode layer 6b is formed of Ni not coated with Sn. With this configuration, a Schottky junction is generated between the first internal electrode layer 6a and the dielectric layer. On the other hand, no Schottky junction is generated between the second internal electrode layer 6b and the dielectric layer. This makes it possible to generate an unbalanced Schottky junction.

[0110] (Barium titanate (P-type), other examples) As mentioned above, no Schottky junction occurs between the internal electrode layer made of Ni and the dielectric layer made of barium titanate, which functions as a P-type semiconductor. This is because the work function of Ni (5.2 eV) is larger than the work function of barium titanate (4.8 eV).

[0111] Therefore, a semiconductor material having a work function greater than that of Ni is placed between the internal electrode layer made of Ni and the dielectric layer made of barium titanate. This allows a Schottky junction to be generated. Examples of semiconductor materials having a work function greater than that of Ni include the following materials: MoS ２ (work function 5.38 eV), MoO ｘ (work function value 6.8 eV or less), WSe ２ (work function value of 5.27 eV or less), CdTe (work function value of 5.65 eV or less), CdS (work function value of 5.87 eV or less), etc.

[0112] (Barium titanate (N-type)) A case where the ceramic material of the dielectric layer is an N-type semiconductor will be described. As mentioned above, by adding a small amount of rare earth element, barium titanate can be made to function as an N-type semiconductor. When barium titanate functions as an N-type semiconductor, a Schottky junction can be generated between the internal electrode layer made of Ni and the dielectric layer made of barium titanate. This is because the work function φs of the ceramic material (barium titanate (4.8 eV)) is smaller than the work function φm of the internal electrode layer (work function of Ni (5.2 eV)).

[0113] (Method for confirming an unbalanced Schottky junction) A method for confirming whether an unbalanced Schottky junction has occurred will be described. When a Schottky junction has occurred, an electric field is generated even when no DC voltage is applied. In other words, a depletion layer is generated. However, it is not easy to directly confirm the electric field or depletion layer generated by the Schottky junction.

[0114] However, there are indirect methods for determining whether an unbalanced Schottky junction has occurred. Method 1 is to determine whether an unbalanced Schottky junction has occurred by checking whether capacitance increases when a DC voltage is applied. This is because an increase in capacitance when a DC voltage is applied is a phenomenon specific to the occurrence of an unbalanced Schottky junction.

[0115] Method 2 is a method of checking the work function of the material of the internal electrode layer and the work function of the dielectric material in contact with the internal electrode layer, because as mentioned above, it is possible to determine whether or not a Schottky junction has occurred based on the magnitude relationship of the work functions.

[0116] (Method for manufacturing a multilayer ceramic capacitor) A method for manufacturing the multilayer ceramic capacitor 1 will be described. (1) A conductive paste for the dielectric sheets and the internal electrode layers is prepared. The conductive paste for the dielectric sheets and the internal electrode layers contains a binder and a solvent. The binder may be an organic binder. The solvent may be an organic solvent.

[0117] (2) A conductive paste for the internal electrode layers is printed on the dielectric sheet in a predetermined pattern. The internal electrode layer pattern is formed by printing the conductive paste. The printing is performed by screen printing, gravure printing, or the like.

[0118] When the internal electrode layers are formed of Ni coated with Sn, when printing the conductive paste, for example, a paste containing Ni may be printed and then a paste containing Sn may be printed thereon.

[0119] When a dielectric layer made of a material other than barium titanate is disposed between an internal electrode layer and a dielectric layer made of, for example, barium titanate, a material containing a material other than barium titanate may be printed on the dielectric sheet before printing a conductive paste on the dielectric sheet made of barium titanate.

[0120] (3) A predetermined number of dielectric sheets for the outer layer portion are stacked. No internal electrode layer pattern is printed on the dielectric sheets for the outer layer portion. A dielectric sheet with an internal electrode layer pattern printed thereon is stacked on top of the stacked dielectric sheets. A predetermined number of other dielectric sheets for the outer layer portion are stacked on top of that. A laminated sheet is produced by stacking these sheets.

[0121] (4) The laminated sheets are pressed in the stacking direction to produce a laminated block. The pressing method can be isostatic pressing.

[0122] (5) The laminated block is cut to a predetermined size. This cutting process cuts out laminated chips. When cutting, the corners and ridges of the laminated chips may be rounded. The rounding process may be performed by barrel polishing.

[0123] (6) The laminated chip is fired. This firing produces a laminate. The firing temperature is preferably 900° C. or higher and 1200° C. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0124] External electrodes are provided on the laminate. (7) A conductive paste that will become the base electrodes is applied to both end surfaces of the laminate. The conductive paste contains a glass component and a metal component. The application method can be, for example, a dipping method. After application, a baking process is performed. This baking process forms the base electrode layer. The preferred temperature for the baking process is 700°C or higher and 900°C or lower.

[0125] (8) A conductive resin layer is formed on the base electrode layer. First, a conductive resin paste containing a resin component and a metal component is prepared. The conductive resin paste is applied to the base electrode layer. The application method can be a dipping method. After application, a heat treatment is performed. The heat treatment temperature is 200°C or higher and 550°C or lower. The resin is thermally cured by this heat treatment. The conductive electrode layer is formed by this thermal curing. The atmosphere during the heat treatment is preferably a nitrogen gas atmosphere. The preferred oxygen concentration during the heat treatment is 100 ppm or lower. When the oxygen concentration is 100 ppm or lower, the resin is less likely to scatter. Furthermore, when the oxygen concentration is 100 ppm or lower, the metal component is less likely to oxidize.

[0126] (9) After forming the conductive resin layer, a Ni plating layer is formed on the surface of the conductive resin layer. This Ni plating layer becomes the underlayer plating layer. The method for forming the Ni plating layer may be an electrolytic plating method. A preferred plating method is barrel plating.

[0127] (10) A Sn plating layer is formed on the Ni plating layer. The Sn plating layer becomes the upper plating layer. The method for forming the Sn plating layer may be an electrolytic plating method. A preferred plating method is barrel plating.

[0128] When the external electrodes contain Sn, for example, Sn may be contained in the conductive paste that serves as the base electrode. When the Sn content of the first external electrode 20a and the Sn content of the second external electrode 20b are to be different from each other, conductive pastes with different Sn contents may be prepared and applied to the desired positions.

[0129] Alternatively, when Sn is contained in the external electrodes, Sn may be contained in the conductive resin paste that becomes the conductive resin layer, for example. Furthermore, when the Sn content of the first external electrode 20a and the Sn content of the second external electrode 20b are to be different, conductive resin pastes with different Sn contents may be prepared and applied to the desired positions.

[0130] Furthermore, when the first external electrode 20a and the second external electrode 20b are to have different shapes, they can be processed into appropriate layers in the process of forming the external electrodes. Alternatively, after the external electrodes are formed, the first external electrode 20a and the second external electrode 20b may have different shapes by forming a notch in a part of the external electrode or by pressing a mold onto the external electrode.

[0131] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible.

[0132] <1> A multilayer ceramic capacitor including a laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrode layers, the laminate having first and second main surfaces opposing each other in a lamination direction, first end faces and second end faces opposing each other in a length direction that is a direction perpendicular to the lamination direction, and first and second side faces opposing each other in a width direction that is a direction perpendicular to the lamination direction and the length direction, a first external electrode disposed on the first end face, and a second external electrode disposed on the second end face, wherein the material of the first internal electrode layer is different from the material of the second internal electrode layer, the first internal electrode layer and the dielectric layer are Schottky junction, and the second internal electrode layer and the dielectric layer are Schottky junction or ohmic junction, and in a state where no voltage is applied between the first external electrode and the second external electrode, a difference between a work function of the first internal electrode layer and a work function of the dielectric layer is larger than a difference between a work function of the second internal electrode layer and the dielectric layer, Multilayer ceramic capacitor.

[0133] <2> The multilayer ceramic capacitor according to <1>, wherein the first internal electrode layer includes Ni and Sn covering the Ni.

[0134] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the first external electrodes contain Sn.

[0135] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the dielectric layers are composed of a plurality of different dielectric regions, and the dielectric region in contact with the first internal electrode layer is different from the dielectric region in contact with the second internal electrode layer.

[0136] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first external electrodes and the second external electrodes have different appearances.

[0137] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 Outer dielectric layer 4 Inner dielectric layer 6a First internal electrode layer 6b Second internal electrode layer 20a First external electrode 20b Second external electrode E1 First end face E2 Second end face M1 First main surface M2 Second main surface S1 First side surface S2 Second side surface

Claims

1. A laminate including a plurality of laminated dielectric layers and a plurality of first and second internal electrode layers, the laminate having a first main surface and a second main surface opposed to each other in a lamination direction, a first end surface and a second end surface opposed to each other in a length direction which is a direction perpendicular to the lamination direction, and a first side surface and a second side surface opposed to each other in a width direction which is a direction perpendicular to the lamination direction and the length direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the material of the first internal electrode layer and the material of the second internal electrode layer are different, the first internal electrode layer and the dielectric layer are connected to each other in a Schottky junction, and the second internal electrode layer and the dielectric layer are connected to each other in a Schottky junction or an ohmic junction, and in a state in which no voltage is applied between the first external electrode and the second external electrode, a difference between a work function of the first internal electrode layer and a work function of the dielectric layer is greater than a difference between a work function of the second internal electrode layer and a work function of the dielectric layer, Multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the first internal electrode layer includes Ni and Sn covering the Ni.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the first external electrode contains Sn.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the dielectric layer is composed of a plurality of different dielectric regions, and the dielectric region in contact with the first internal electrode layer is different from the dielectric region in contact with the second internal electrode layer.

5. The multilayer ceramic capacitor according to claim 1, wherein the first external electrode and the second external electrode have different appearances.

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