Solid-state imaging device

Abstract

[Problem] To provide a solid-state imaging device that can suitably form a transistor on an SOI structure. [Solution] A solid-state imaging device according to the present disclosure comprises: a semiconductor substrate; an insulating film that is disposed on the semiconductor substrate; a semiconductor layer that is disposed on the insulating film; and a plurality of transistors that include at least one first transistor having a source / drain region in the semiconductor substrate and at least one second transistor having a source / drain region in the semiconductor layer. The plurality of transistors include: a low-voltage transistor that includes a gate insulating film having a first film thickness; a first high-voltage transistor that has a first threshold voltage and that includes a gate insulating film having a second film thickness, which is greater than the first film thickness; and a second high-voltage transistor that has a second threshold voltage, which is lower than the first threshold voltage, and that includes a gate insulating film having the second film thickness. The second high-voltage transistor is included in the second transistor.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] In solid-state imaging devices such as CIS (CMOS Image Sensors), the comparator circuits and load circuits in AD (Analog to Digital) converters are generally configured with HV (High Voltage) transistors rather than LV (Low Voltage) transistors, which are classified into SVT transistors with a high threshold voltage and ULVT transistors with a low threshold voltage.

[0003] ULVT transistors are capable of outputting large currents. Therefore, comparison circuits and load circuits in AD converters are generally constructed with ULVT transistors to reduce noise. However, ULVT transistors have a problem of high power consumption due to their large leakage current.

[0004] JP 2006-165808 A JP 2011-211213 A

[0005] In order to reduce the power consumption of a solid-state imaging device, it is conceivable to form all of the transistors of the solid-state imaging device on a full depletion semiconductor-on-insulator (FD-SOI) substrate rather than on a bulk semiconductor substrate. The FD-SOI substrate has an SOI structure in which an insulating film and a semiconductor layer are provided in this order on a semiconductor substrate.

[0006] By adopting an FD-SOI substrate, it is possible to reduce the leakage current of these transistors and reduce the power consumption of the solid-state imaging device. However, it is necessary to redesign the models of these transistors from models for bulk semiconductor substrates to models for FD-SOI substrates, which requires a lot of time and cost.

[0007] Therefore, the present disclosure provides a solid-state imaging device that allows transistors to be suitably formed on an SOI structure.

[0008] A solid-state imaging device according to a first aspect of the present disclosure includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, a semiconductor layer provided on the insulating film, and a plurality of transistors including one or more first transistors each including a source / drain region in the semiconductor substrate and one or more second transistors each including a source / drain region in the semiconductor layer. The plurality of transistors includes a low-voltage transistor including a gate insulating film having a first thickness, a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage, and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage. This allows transistors to be suitably formed on an SOI structure. For example, by arranging the second high-voltage transistor on an SOI structure, it is possible to reduce leakage current in the second high-voltage transistor, which is prone to leakage current problems. Furthermore, by limiting the transistors arranged on the SOI structure to a portion of transistors (second transistors), such as the second high-voltage transistor, it is possible to reduce the effort and cost required to redesign a model.

[0009] In this first aspect, the low-voltage transistor may be included in the second transistor, which makes it possible to reduce leakage current of the low-voltage transistor, for example.

[0010] In this first aspect, the low-voltage transistor may be included in the first transistor, which makes it possible to reduce the time and cost required to recreate a model of the low-voltage transistor, for example.

[0011] In this first aspect, the low-voltage transistor may be provided in a digital circuit, which makes it possible to more suitably form transistors in the digital circuit using low-voltage transistors, for example.

[0012] In this first aspect, the first high-voltage transistor may be included in the first transistor, which makes it possible to reduce the time and cost required to recreate a model of the first high-voltage transistor, for example.

[0013] In this first aspect, the first high-voltage transistor may be provided in an analog circuit, which makes it possible to suitably form a transistor in the analog circuit by using the first high-voltage transistor, for example.

[0014] In this first aspect, the first high-voltage transistor may be provided in the analog circuit other than the comparator circuit and the load circuit, thereby making it possible to form transistors in the analog circuit other than the comparator circuit and the load circuit using the first high-voltage transistor, and to form transistors in the comparator circuit or the load circuit using the second high-voltage transistor.

[0015] In this first aspect, the second high-voltage transistor may be provided in a comparator circuit or a load circuit, which makes it possible to suitably form a transistor in the comparator circuit or the load circuit by using the second high-voltage transistor.

[0016] In this first aspect, the second high-voltage transistor in the comparator circuit may be provided in a differential circuit, which makes it possible to suitably form the differential circuit in the comparator circuit, for example.

[0017] In this first aspect, the second high-voltage transistor in the comparator circuit may have a first conductivity type, and the second high-voltage transistor in the load circuit may have a second conductivity type different from the first conductivity type, thereby making it possible, for example, to make the second high-voltage transistor in the comparator circuit an N-type MOSFET and the second high-voltage transistor in the load circuit a P-type MOSFET.

[0018] In this first aspect, the semiconductor layer may be formed of the same semiconductor material as the semiconductor substrate, which allows, for example, the source / drain regions of the first transistor and the source / drain regions of the second transistor to be formed in different semiconductor regions made of the same semiconductor material.

[0019] In this first aspect, the semiconductor material may be silicon, which allows, for example, the source / drain regions of the first transistor and the source / drain regions of the second transistor to be formed in different semiconductor regions both made of silicon.

[0020] In this first aspect, the insulating film may be an oxide film, which makes it possible to realize an SOI structure including, for example, a silicon substrate, a silicon oxide film, and a silicon layer.

[0021] A solid-state imaging device according to a second aspect of the present disclosure includes a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a semiconductor layer disposed on the insulating film, and a plurality of transistors, including one or more first transistors each including a source / drain region in the semiconductor substrate and one or more second transistors each including a source / drain region in the semiconductor layer, the second transistors including a transistor disposed in a comparison circuit or a load circuit. This allows transistors to be suitably formed on an SOI structure. For example, by arranging transistors in the comparison circuit or the load circuit on an SOI structure, it is possible to reduce leakage current in the comparison circuit or the load circuit, which often include transistors prone to leakage current problems. Furthermore, by limiting the transistors disposed on the SOI structure to only a portion of transistors (second transistors), such as those in the comparison circuit or the load circuit, it is possible to reduce the effort and cost required to reconstruct the model.

[0022] In the second aspect, the transistor in the comparator circuit may be provided in a differential circuit, which makes it possible to suitably form the differential circuit in the comparator circuit, for example.

[0023] In this second aspect, the transistor in the comparator circuit may have a first conductivity type, and the transistor in the load circuit may have a second conductivity type different from the first conductivity type, which makes it possible to use, for example, an N-type MOSFET as the transistor in the comparator circuit and a P-type MOSFET as the transistor in the load circuit.

[0024] In this second aspect, the first transistor may include a transistor provided in an analog circuit other than the comparator circuit and the load circuit, thereby making it possible to more suitably form, for example, a transistor in an analog circuit other than the comparator circuit and the load circuit using the first transistor.

[0025] In this second aspect, the first transistor or the second transistor may include a transistor provided in a digital circuit, which makes it possible to suitably form, for example, a transistor in the digital circuit using the first transistor or the second transistor.

[0026] In this second aspect, the plurality of transistors may include a low-voltage transistor including a gate insulating film having a first thickness, a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage, and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage, the second high-voltage transistor being included in the second transistor and being provided in the comparator circuit or the load circuit. This makes it possible to suitably form transistors in the comparator circuit or the load circuit using the second high-voltage transistor, for example.

[0027] In this second aspect, the first high-voltage transistor may be included in the first transistor and provided in an analog circuit other than the comparator circuit and the load circuit, and the low-voltage transistor may be included in the first transistor or the second transistor and provided in a digital circuit, thereby making it possible to suitably form transistors in analog circuits and digital circuits, for example.

[0028] FIG. 10 is a block diagram showing the configuration of a solid-state imaging device of the first embodiment. FIG. 11 is a cross-sectional view showing the structure of a solid-state imaging device of the first embodiment. FIG. 12 is a cross-sectional view (1 / 2) showing an example of a transistor of the first embodiment. FIG. 13 is a cross-sectional view (2 / 2) showing an example of a transistor of the first embodiment. FIG. 14 is a cross-sectional view showing the structure of a solid-state imaging device of the first embodiment. FIG. 15 is a cross-sectional view showing the structure of a solid-state imaging device of the second embodiment. FIG. 16 is a block diagram showing an example of the configuration of an electronic device. FIG. 17 is a block diagram showing an example of the configuration of a mobile object control system. FIG. 18 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 8. FIG. 19 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. FIG. 19 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0030] 1 is a block diagram showing the configuration of a solid-state imaging device according to Embodiment 1. The solid-state imaging device of this embodiment is, for example, an image sensor such as a CIS.

[0031] The solid-state imaging device of this embodiment includes a pixel array region 11, a plurality of load circuits 12, a plurality of comparison circuits 13, a plurality of counter circuits 14, a plurality of horizontal scanning circuits 15, a plurality of vertical scanning circuits 16, a DA (Digital to Analog) converter 17, a charge pump 18, a scanning control unit 21, a PS (Parallel to Serial) converter 22, a delay line 23, a transmission unit 24, a plurality of sense amplifiers 25, and a PLL (Phase Locked Loop) 26.

[0032] The pixel array region 11 includes a plurality of pixels 1 arranged in a two-dimensional array, a plurality of vertical signal lines 2 extending in the vertical direction (column direction), and a plurality of horizontal signal lines 3 extending in the horizontal direction (row direction). Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. The pixel transistor may be, for example, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, a switch transistor, or the like. These pixel transistors may be shared by several pixels 1.

[0033] The load circuit 12, the comparison circuit 13, the counter circuit 14, and the horizontal scanning circuit 15 are electrically connected to the pixels 1 via vertical signal lines 2. The vertical scanning circuit 16 is electrically connected to the pixels 1 via horizontal signal lines 3. The load circuit 12 and the pixels 1 form a source follower circuit. The comparison circuit 13, together with the load circuit 12 and the counter circuit 14, forms an AD converter, which converts the pixel signals read from the pixels 1 from analog signals to digital signals. The comparison circuit 13 compares the pixel signals with a reference signal, and the counter circuit 14 counts the time until the comparison result of the comparison circuit 13 is inverted. The horizontal scanning circuit 15 horizontally scans multiple vertical signal lines 2 (readout columns) to read out the pixel signals. Meanwhile, the vertical scanning circuit 16 vertically scans the pixels 1 row by row via multiple horizontal signal lines 3.

[0034] The DA converter 17 converts the pixel signal from a digital signal to an analog signal, inversely to the AD converter. The charge pump 18 supplies a predetermined voltage to the vertical scanning circuit 16. The vertical scanning circuit 16 uses the voltage supplied from the charge pump 18 to generate a signal for driving the pixel 11.

[0035] The scanning control unit 21 generates various signals for controlling the operations of the horizontal scanning circuit 15 and the vertical scanning circuit 16 based on a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, etc. The signals generated by the scanning control unit 21 are, for example, clock signals and control signals.

[0036] The PS converter 22 converts the image data obtained from the pixel signals from parallel signals to serial signals. This image data is transferred from the PS converter 22 to a transmitter 24 via a delay line 23 and output from the transmitter 24 to the outside of the solid-state imaging device.

[0037] The sense amplifier 25 transfers image data from the pixel array region 11 to the PS converter 22 via the scan control unit 21. The PLL 26 generates a reference clock signal and supplies it to the scan control unit 21.

[0038] 2 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment, and shows a vertical cross section of the solid-state imaging device shown in FIG.

[0039] 2, the solid-state imaging device of this embodiment includes a semiconductor substrate 31, a buried insulating film 32, a semiconductor layer 33, multiple contact layers 35, an isolation insulating film 36, an interlayer insulating film 37, multiple contact plugs 38, and multiple transistors T1 to T3. The buried insulating film 32 is an example of an insulating film of the present disclosure. The transistor T3 is an example of a first transistor of the present disclosure. The transistors T1 and T2 are examples of second transistors of the present disclosure.

[0040] 2 shows X-axis, Y-axis, and Z-axis, which are perpendicular to each other. The X-axis and Y-axis correspond to the horizontal direction, and the Z-axis corresponds to the vertical direction. The +Z-axis corresponds to the upward direction, and the -Z-axis corresponds to the downward direction. Note that the -Z-axis may or may not strictly coincide with the direction of gravity.

[0041] The semiconductor substrate 31 is, for example, a Si (silicon) substrate. The semiconductor substrate 31 of this embodiment is a bulk semiconductor substrate (bulk Si substrate). In FIG. 2, the top surface of the semiconductor substrate 31 is perpendicular to the Z direction. The semiconductor substrate 31 includes a bulk region 31a, an N-well region 31b, a P-well region 31c, a backplate region 31d, and a backplate region 31e.

[0042] The N-well region 31b is an N-type region formed on the bulk region 31a. The P-well region 31c is a P-type region formed on the bulk region 31a. The backplate region 31d is formed on the N-well region 31b. The backplate region 31e is formed on the P-well region 31c. The backplate regions 31d and 31e may be N-type or P-type regions. In this embodiment, one of the backplate regions 31d and 31e is an N-type region, and the other of the backplate regions 31d and 31e is a P-type region. One of the N-conductivity type and the P-conductivity type is an example of a first conductivity type in the present disclosure. The other of the N-conductivity type and the P-conductivity type is an example of a second conductivity type in the present disclosure.

[0043] The buried insulating film 32 is formed on the semiconductor substrate 31. In this embodiment, the buried insulating film 32 is not formed on the entire upper surface of the semiconductor substrate 31, but is formed only on a part of the upper surface of the semiconductor substrate 31. The buried insulating film 32 is made of, for example, SiO ２ In this case, the buried insulating film 32 is also called a BOX (Buried Oxide) film.

[0044] The semiconductor layer 33 is formed on the buried insulating film 32. The buried insulating film 32 and the semiconductor layer 33 are formed in this order on the semiconductor substrate 31, and together with the semiconductor substrate 31, form an SOI structure. The semiconductor layer 33 is formed on the upper surface of the semiconductor substrate 31 via the buried insulating film 32. Like the buried insulating film 32, the semiconductor layer 33 of this embodiment is not formed on the entire upper surface of the semiconductor substrate 31, but is formed only on a portion of the upper surface of the semiconductor substrate 31. The semiconductor layer 33 is, for example, a Si layer such as a polysilicon layer. In this embodiment, the semiconductor substrate 31 and the semiconductor layer 33 are formed of the same semiconductor material (here, silicon). The semiconductor layer 33 is also called an SOI layer.

[0045] Each of the transistors T1 to T3 includes a gate insulating film 41, a gate electrode 42, a sidewall insulating film 43, and a source / drain region 44. The gate insulating film 41 is formed on the semiconductor substrate 31 or the semiconductor layer 33. The gate electrode 42 is formed on the gate insulating film 41. The sidewall insulating film 43 is formed on the side surface of the gate electrode 42. The source / drain regions 44 are formed in the semiconductor substrate 31 or the semiconductor layer 33 so as to sandwich the gate electrode 42.

[0046] 2, transistors T1 and T2 are formed on a semiconductor layer 33, and transistor T3 is formed on a semiconductor substrate 31. Therefore, the source / drain region 44 of transistor T1 and the source / drain region 44 of transistor T2 are formed in the semiconductor layer 33. On the other hand, the source / drain region 44 of transistor T3 is formed in the semiconductor substrate 31. In FIG. 2, transistors T1 and T2 are formed on an SOI structure, whereas transistor T3 is formed on a bulk semiconductor substrate rather than on an SOI structure.

[0047] In this embodiment, the transistors T1 to T3 are MOSFETs. These transistors T1 to T3 may be NMOS or PMOS. In the SOI structure of this embodiment, one of the transistors T1 and T2 is an NMOS, and the other of the transistors T1 and T2 is a PMOS.

[0048] The contact layer 35 is formed on the N-well region 31b and the P-well region 31c. The contact layer 35 is, for example, a semiconductor layer or a metal layer.

[0049] The element isolation insulating film 36 is formed in the semiconductor substrate 31, the buried insulating film 32, and the semiconductor layer 33 to isolate the transistors T1 to T3 from one another. In FIG. 2, the element isolation insulating film 36 is formed between the N-well region 31b and the P-well region 31c, between the semiconductor layer 33 and the contact layer 35, etc. The element isolation insulating film 36 is made of, for example, SiO ２ The element isolation insulating film 36 is also called an STI (Shallow Trench Isolation) film.

[0050] The interlayer insulating film 37 is formed on the semiconductor substrate 31, the buried insulating film 32, the semiconductor layer 33, the contact layer 35, and the element isolation insulating film 36 so as to cover the transistors T1 to T3. The interlayer insulating film 37 is made of, for example, SiO ２ It is a membrane.

[0051] The contact plugs 38 are formed in the interlayer insulating film 37 on the contact layer 35, on the gate electrodes 42 of the transistors T1 to T3, and on the source / drain regions 44 of the transistors T1 to T3. The N-well 31b and the P-well 31c are electrically connected to the contact plugs 38 via the contact layer 35. The contact plugs 38 are, for example, a semiconductor layer or a metal layer.

[0052] Next, various examples of the transistors of this embodiment will be described with reference to Figures 3 and 4. The above-mentioned transistors T1 to T3 are included in these examples.

[0053] 3 and 4 are cross-sectional views showing examples of the transistor according to the first embodiment.

[0054] 3A to 4B, the transistor T includes the above-described gate insulating film 41, gate electrode 42, sidewall insulating film 43, and source / drain regions 44. The source / drain regions 44 are included in the semiconductor substrate 31 or the semiconductor layer 33.

[0055] The transistor T shown in FIG. 3A is an LV transistor and includes a gate insulating film 41 having a thickness Z1. The transistor T shown in FIG. 3B is an HV transistor and includes a gate insulating film 41 having a thickness Z2. The thickness Z2 is set to be thicker than the thickness Z1 (Z2>Z1). The solid-state imaging device of this embodiment includes both an LV transistor and an HV transistor. The LV transistor is an example of a low-voltage transistor of the present disclosure. The thickness Z1 is an example of a first thickness of the present disclosure. The thickness Z2 is an example of a second thickness of the present disclosure.

[0056] 4A and 4B show two types of HV transistors having different threshold voltages Vth. The transistor T shown in FIG. 4A is an HV transistor having a threshold voltage V1 and is called an SVT transistor. The transistor T shown in FIG. 4B is an HV transistor having a threshold voltage V2 and is called an ULVT transistor. The threshold voltage V2 is set lower than the threshold voltage V1 (V2<V1). The solid-state imaging device of this embodiment includes both an SVT transistor and an ULVT transistor. The SVT transistor is an example of a first high-voltage transistor of the present disclosure. The ULVT transistor is an example of a second high-voltage transistor of the present disclosure. The threshold voltage V1 is an example of a first threshold voltage of the present disclosure. The threshold voltage V2 is an example of a second threshold voltage of the present disclosure.

[0057] 5 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. The structure of the solid-state imaging device shown in FIG. 5 corresponds to an example of the structure of the solid-state imaging device shown in FIG.

[0058] 5 shows a transistor T4 in addition to the above-described transistors T1 to T3. Like the transistors T1 to T3, the transistor T4 includes the above-described gate insulating film 41, gate electrode 42, sidewall insulating film 43, and source / drain regions 44. Note that FIG. 5 omits illustration of some of the components shown in FIG. 2 (such as the N-well region 31b, the P-well region 31c, the backplate regions 31d and 31e, and the contact layer 35).

[0059] 5, transistors T1, T2, and T4 are formed on a semiconductor layer 33, and transistor T3 is formed on a semiconductor substrate 31. Thus, source / drain regions 44 of transistors T1, T2, and T4 are formed in the semiconductor layer 33, and source / drain regions 44 of transistor T3 are formed in the semiconductor substrate 31. In FIG. 5, transistors T1, T2, and T4 are formed on an SOI structure, whereas transistor T3 is formed on a bulk semiconductor substrate rather than on an SOI structure. Transistor T3 in this embodiment is an example of a first transistor of the present disclosure, and transistors T1, T2, and T4 in this embodiment are examples of a second transistor of the present disclosure.

[0060] 5, transistor T1 is an ULVT transistor and a differential MOS transistor. The differential MOS transistor is a MOSFET that forms a differential circuit within comparison circuit 13. Because transistor T1 is an ULVT transistor, it includes a gate insulating film 41 having a film thickness Z2 and has a threshold voltage V2. Here, transistor T1 is an NMOS transistor. For example, each comparison circuit 13 in this embodiment includes multiple comparators, and transistor T1 forms a differential pair within one of the comparators.

[0061] 5, transistor T2 is also an ULVT transistor and a load MOS. The load MOS is a MOSFET that constitutes load circuit 12. Because transistor T2 is an ULVT transistor, it includes a gate insulating film 41 having a thickness Z2 and has a threshold voltage V2. Transistor T2 is a PMOS in this example. For example, each load circuit 14 in this embodiment includes multiple active loads, and transistor T2 constitutes one of the active loads.

[0062] 5, transistor T3 is an SVT transistor and forms part of an analog circuit within the solid-state imaging device of this embodiment. However, transistor T3 forms part of an analog circuit other than comparison circuit 13 and load circuit 12. Examples of this analog circuit include DA converter 17 and charge pump 18. Because transistor T3 is an SVT transistor, it includes a gate insulating film 41 having a thickness Z2 and has a threshold voltage V1. Note that transistor T3 may be an NMOS or PMOS transistor.

[0063] 5, the transistor T4 is an LV transistor and constitutes a digital circuit in the solid-state imaging device of this embodiment. Because the transistor T4 is an LV transistor, it includes a gate insulating film 41 having a thickness Z1. The transistor T4 may be an NMOS or a PMOS.

[0064] Next, the solid-state imaging device of this embodiment will be described in further detail with reference to FIG.

[0065] In this embodiment, it is desirable that all transistors in each comparison circuit 13 and all transistors in each load circuit 12 are ULVT transistors. This is because it is desirable to reduce noise by configuring the comparison circuit 13 and the load circuit 12 with ULVT transistors that output a large current. In this case, it is desirable to arrange the comparison circuit 13 and the load circuit 12 on an SOI structure. This is because power consumption increases if the comparison circuit 13 and the load circuit 12 are configured with ULVT transistors that have a large leakage current.

[0066] Therefore, in this embodiment, all transistors in each comparison circuit 13 and all transistors in each load circuit 12 are arranged as ULVT transistors on an SOI structure, like transistors T1 and T2 shown in FIG. 5 . This makes it possible to reduce the power consumption of the comparison circuit 13 and the load circuit 12 while reducing noise in the comparison circuit 13 and the load circuit 12. Because the SOI structure is a fully depleted device, arranging the ULVT transistors on the SOI structure makes it possible to effectively reduce the leakage current of the ULVT transistors. Furthermore, because the operation of transistors on the SOI structure can be controlled by a back bias, it is possible to expand the dynamic range while reducing the leakage current.

[0067] In this embodiment, it is desirable to use SVT transistors for the transistors in the analog circuits other than the comparator circuit 13 and the load circuit 12. This is because the analog circuits other than the comparator circuit 13 and the load circuit 12 do not require as much noise reduction as the comparator circuit 13 and the load circuit 12. In this case, the analog circuits other than the comparator circuit 13 and the load circuit 12 may be arranged on a bulk semiconductor substrate. This is because the problems of leakage current and power consumption are not that significant.

[0068] Therefore, in this embodiment, the transistors in the analog circuits other than the comparator circuit 13 and the load circuit 12 are arranged on a bulk semiconductor substrate as SVT transistors, such as transistor T3 shown in FIG. 5. This makes it possible to reduce the effort and cost required to remodel these transistors from a bulk semiconductor substrate model to an SOI structure model. In this case, it becomes possible to utilize existing intellectual property (IP) for these transistors, thereby shortening the development period for solid-state imaging devices.

[0069] In this embodiment, it is desirable that the transistors in the digital circuit be LV transistors. This is because digital circuits generally do not require high voltages like analog circuits. In this case, it is desirable that the transistors in the digital circuit be arranged on an SOI structure. This is because LV transistors consume large amounts of power due to the thin film thickness Z1 of the gate insulating film 41.

[0070] Therefore, in this embodiment, the transistors in the digital circuit are arranged on an SOI structure as LV transistors, such as the transistor T4 shown in Fig. 5. This makes it possible to reduce the power consumption of the digital circuit.

[0071] As described above, in this embodiment, the ULVT transistors in the comparison circuit 13 and the load circuit 12, and the LV transistors in the digital circuit are formed on an SOI structure, while the SVT transistors in the other analog circuits are formed on a bulk semiconductor substrate. Therefore, this embodiment makes it possible to suitably form these transistors on an SOI structure and a bulk semiconductor substrate. For example, by placing the ULVT transistors on an SOI structure, it becomes possible to reduce the leakage current of the ULVT transistors, which are prone to leakage current problems. Furthermore, by limiting the transistors placed on the SOI structure to a portion of the transistors, it becomes possible to reduce the effort and cost required to recreate the model.

[0072] Note that comparison circuit 13 or load circuit 12 may include not only ULVT transistors but also SVT transistors or LV transistors. In this case, the SVT transistors may be disposed on a bulk semiconductor substrate. Also, analog circuits other than comparison circuit 13 and load circuit 12 may include not only SVT transistors but also ULVT transistors or LV transistors. In this case, the ULVT transistors or LV transistors may be disposed on an SOI structure. Also, digital circuits may include not only LV transistors but also ULVT transistors or SVT transistors. In this case, the SVT transistors may be disposed on a bulk semiconductor substrate.

[0073] Second Embodiment FIG. 6 is a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment.

[0074] The solid-state imaging device of this embodiment ( FIG. 6 ) has a structure similar to that of the solid-state imaging device of the first embodiment ( FIG. 5 ). However, the transistor T4 of this embodiment is formed on the semiconductor substrate 31, not on the semiconductor layer 33. Therefore, the source / drain regions 44 of the transistor T4 of this embodiment are formed in the semiconductor substrate 31. The transistors T3 and T4 of this embodiment are examples of the first transistor of the present disclosure, and the transistors T1 and T2 of this embodiment are examples of the second transistor of the present disclosure.

[0075] In the first embodiment, the transistors in the digital circuit are arranged as LV transistors on an SOI structure, such as transistor T4 shown in FIG. 5. This makes it possible to reduce the power consumption of the digital circuit. On the other hand, in the present embodiment, the transistors in the digital circuit are arranged as LV transistors on a bulk semiconductor substrate, such as transistor T4 shown in FIG. 6. This makes it possible to reduce the effort and cost required to remodel the transistors in the digital circuit from a model for a bulk semiconductor substrate to a model for an SOI structure.

[0076] The transistors in the digital circuit may be arranged on an SOI structure as in the first embodiment, or on a bulk semiconductor substrate as in the present embodiment. If it is desired to reduce the power consumption of the digital circuit, it is desirable to adopt the digital circuit of the first embodiment. On the other hand, if it is desired not to remodel the transistors in the digital circuit, it is desirable to adopt the digital circuit of this embodiment.

[0077] As described above, in this embodiment, the ULVT transistors in the comparison circuit 13 and the load circuit 12 are formed on an SOI structure, while the SVT transistors in the other analog circuits and the LV transistors in the digital circuits are formed on a bulk semiconductor substrate. Therefore, this embodiment makes it possible to suitably form these transistors on an SOI structure and a bulk semiconductor substrate. For example, by placing the ULVT transistors on an SOI structure, it becomes possible to reduce the leakage current of the ULVT transistors, which are prone to leakage current problems. Furthermore, by limiting the transistors placed on the SOI structure to a portion of the transistors, it becomes possible to reduce the effort and cost required to recreate the model.

[0078] The digital circuit of this embodiment may include not only LV transistors but also ULVT transistors or SVT transistors, in which case the ULVT transistors may be arranged on an SOI structure.

[0079] 7 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0080] The camera 100 includes an optical unit 101 including a lens group and the like, an imaging device 102 which is the solid-state imaging device of the first or second embodiment, a DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, a frame memory 104, a display unit 105, a recording unit 106, an operation unit 107, and a power supply unit 108. The DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, the operation unit 107, and the power supply unit 108 are connected to one another via a bus line 109.

[0081] The optical unit 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light formed on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0082] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one frame of a moving image or still image captured by the imaging device 102.

[0083] The display unit 105 includes a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 on a recording medium such as a hard disk or semiconductor memory.

[0084] The operation unit 107, under the operation of the user, issues operation commands for various functions of the camera 100. The power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources.

[0085] By using the solid-state imaging device of the first or second embodiment as the imaging device 102, it is possible to expect to obtain a good image.

[0086] The solid-state imaging device can be applied to various other products, for example, the solid-state imaging device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0087] 8 is a block diagram showing an example of the configuration of a mobile object control system. The mobile object control system shown in FIG. 8 is a vehicle control system 200.

[0088] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 8, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 8 further shows components of the integrated control unit 250, such as a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0089] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates braking force for the vehicle, etc.

[0090] Body system control unit 220 controls the operation of various devices equipped in the vehicle body in accordance with various programs. For example, body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, backup lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 220. Body system control unit 220 receives input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0091] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture images outside the vehicle and receives the captured images from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0092] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 231 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 231 may be visible light or invisible light such as infrared light. The imaging unit 231 includes the solid-state imaging device of the first or second embodiment.

[0093] The in-vehicle information detection unit 240 detects information about the inside of a vehicle equipped with the vehicle control system 200. A driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240, for example. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver or determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. This camera may include the solid-state imaging device of the first or second embodiment, and may be, for example, the camera 100 shown in FIG. 7 .

[0094] The microcomputer 251 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside information detection unit 230 or the inside information detection unit 240, and output control commands to the drivetrain control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), such as vehicle collision avoidance, impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, collision warning, and lane departure warning.

[0095] In addition, the microcomputer 251 can perform cooperative control for purposes such as autonomous driving, in which the vehicle travels autonomously without the driver's operation, by controlling the driving force generating device, steering mechanism, or braking device based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0096] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information about the outside of the vehicle acquired by the outside information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0097] The audio / video output unit 252 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 8, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0098] FIG. 9 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0099] 9 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0100] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the top of the windshield inside the vehicle mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0101] FIG. 9 shows an example of the imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of imaging unit 304 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 301 to 304, an overhead image of vehicle 300 viewed from above can be obtained. Hereinafter, imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311 to 314."

[0102] At least one of the image capturing units 301 to 304 may have a function of acquiring distance information. For example, at least one of the image capturing units 301 to 304 may be a stereo camera including multiple image capturing devices, or may be an image capturing device having pixels for detecting a phase difference.

[0103] For example, the microcomputer 251 (FIG. 8) calculates the distance to each three-dimensional object within the imaging ranges 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 300 and that is traveling in approximately the same direction as the vehicle 300 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 251 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle and perform automatic braking control (including adaptive cruise control), automatic acceleration control (including adaptive cruise control), and the like. In this way, according to this example, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without driver operation.

[0104] For example, based on the distance information obtained from the imaging units 301 to 304, the microcomputer 251 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. The microcomputer 251 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drivetrain control unit 210.

[0105] At least one of the image capturing units 301-304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 301-304. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 301-304 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the images captured by the image capturing units 301-304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like representing the pedestrian in a desired position.

[0106] FIG. 10 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0107] 10 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0108] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the example shown in the figure, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0109] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target inside the body cavity of the patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0110] An optical system and an image sensor are provided inside the camera head 502, and light reflected from an object to be observed (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 601 as RAW data.

[0111] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502 and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0112] Under the control of the CCU 601 , the display device 602 displays an image based on the image signal that has been subjected to image processing by the CCU 601 .

[0113] The light source device 603 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0114] The input device 604 is an input interface for the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0115] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 sends gas into the body cavity of the patient 532 via the insufflation tube 511 to ensure a clear field of view for the endoscope 500 and a working space for the surgeon. The recorder 607 is a device capable of recording various types of information related to the surgery. The printer 608 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0116] The light source device 603, which supplies illumination light to the endoscope 500 when photographing the surgical site, can be configured from a white light source formed, for example, by an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 603 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 502 in synchronization with the irradiation timing. This method allows color images to be obtained without providing a color filter to the image sensor.

[0117] Furthermore, the light source device 603 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0118] The light source device 603 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0119] FIG. 11 is a block diagram showing an example of the functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0120] The camera head 502 has a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera head control unit 705. The CCU 601 has a communication unit 711, an image processing unit 712, and a control unit 713. The camera head 502 and the CCU 601 are connected to each other via a transmission cable 700 so as to be able to communicate with each other.

[0121] The lens unit 701 is an optical system provided at the connection portion with the lens barrel 501. Observation light taken in from the tip of the lens barrel 501 is guided to the camera head 502 and enters the lens unit 701. The lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0122] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 702 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these image signals. Alternatively, the imaging unit 702 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 531 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 702 is composed of a multi-chip type, multiple lens units 701 may be provided corresponding to each imaging element. The imaging unit 702 may be, for example, a solid-state imaging device according to the first or second embodiment.

[0123] Furthermore, the imaging unit 702 does not necessarily have to be provided in the camera head 502. For example, the imaging unit 702 may be provided inside the lens barrel 501, immediately after the objective lens.

[0124] The driving unit 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control unit 705. This allows the magnification and focus of the image captured by the imaging unit 702 to be adjusted appropriately.

[0125] The communication unit 704 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0126] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601 and supplies the control signal to the camera head control unit 705. The control signal includes information relating to the image capturing conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing an image, and / or information specifying the magnification and focus of the captured image.

[0127] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0128] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0129] The communication unit 711 is configured by a communication device for transmitting and receiving various types of information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0130] Furthermore, the communication unit 711 transmits to the camera head 502 a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0131] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data, sent from the camera head 502 .

[0132] The control unit 713 performs various controls related to the imaging of the surgical site, etc. by the endoscope 500 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0133] Furthermore, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal subjected to image processing by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated during use of the energy treatment tool 512, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 602, the control unit 713 may use the recognition results to superimpose various surgical support information on the image of the surgical site. Superimposing the surgical support information and presenting it to the surgeon 531 reduces the burden on the surgeon 531 and enables the surgeon 531 to proceed with the surgery reliably.

[0134] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable of these.

[0135] In the illustrated example, communication is performed by wire using the transmission cable 700, but communication between the camera head 502 and the CCU 601 may also be performed wirelessly.

[0136] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, multiple embodiments may be implemented in combination.

[0137] The present disclosure may also be configured as follows.

[0138] (1) A solid-state imaging device comprising: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a semiconductor layer provided on the insulating film; and a plurality of transistors including one or more first transistors each including a source / drain region in the semiconductor substrate and one or more second transistors each including a source / drain region in the semiconductor layer, wherein the plurality of transistors include: a low-voltage transistor including a gate insulating film having a first thickness; a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage; and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage, wherein the second high-voltage transistor is included in the second transistor.

[0139] (2) The solid-state imaging device according to (1), wherein the low-voltage transistor is included in the second transistor.

[0140] (3) The solid-state imaging device according to (1), wherein the low-voltage transistor is included in the first transistor.

[0141] (4) The solid-state imaging device according to (1), wherein the low-voltage transistor is provided in a digital circuit.

[0142] (5) The solid-state imaging device according to (1), wherein the first high-voltage transistor is included in the first transistor.

[0143] (6) The solid-state imaging device according to (1), wherein the first high-voltage transistor is provided in an analog circuit.

[0144] (7) The solid-state imaging device according to (6), wherein the first high-voltage transistor is provided in the analog circuit other than the comparator circuit and the load circuit.

[0145] (8) The solid-state imaging device according to (1), wherein the second high-voltage transistor is provided in a comparison circuit or a load circuit.

[0146] (9) The solid-state imaging device according to (8), wherein the second high-voltage transistor in the comparator circuit is provided in a differential circuit.

[0147] (10) The solid-state imaging device according to (8), wherein the second high-voltage transistor in the comparison circuit has a first conductivity type, and the second high-voltage transistor in the load circuit has a second conductivity type different from the first conductivity type.

[0148] (11) The solid-state imaging device according to (1), wherein the semiconductor layer is formed of the same semiconductor material as the semiconductor substrate.

[0149] (12) The solid-state imaging device according to (11), wherein the semiconductor material is silicon.

[0150] (13) The solid-state imaging device according to (1), wherein the insulating film is an oxide film.

[0151] (14) A solid-state imaging device comprising: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a semiconductor layer provided on the insulating film; and a plurality of transistors including one or more first transistors including source / drain regions in the semiconductor substrate and one or more second transistors including source / drain regions in the semiconductor layer, wherein the second transistors include a transistor provided in a comparison circuit or a load circuit.

[0152] (15) The solid-state imaging device according to (14), wherein the transistor in the comparator circuit is provided in a differential circuit.

[0153] (16) The solid-state imaging device according to (14), wherein the transistor in the comparator circuit has a first conductivity type, and the transistor in the load circuit has a second conductivity type different from the first conductivity type.

[0154] (17) The solid-state imaging device according to (14), wherein the first transistor includes a transistor provided in an analog circuit other than the comparator circuit and the load circuit.

[0155] (18) The solid-state imaging device according to (14), wherein the first transistor or the second transistor includes a transistor provided in a digital circuit.

[0156] (19) The solid-state imaging device described in (14), wherein the plurality of transistors include: a low-voltage transistor including a gate insulating film having a first thickness; a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage; and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage, wherein the second high-voltage transistor is included in the second transistor and is provided in the comparison circuit or the load circuit.

[0157] (20) The solid-state imaging device according to (19), wherein the first high-voltage transistor is included in the first transistor and is provided in an analog circuit other than the comparison circuit and the load circuit, and the low-voltage transistor is included in the first transistor or the second transistor and is provided in a digital circuit.

[0158] 1: pixel, 2: vertical signal line, 3: horizontal signal line, 11: pixel array region, 12: load circuit, 13: comparison circuit, 14: counter circuit, 15: horizontal scanning circuit, 16: vertical scanning circuit, 17: DA converter, 18: charge pump, 21: scanning control section, 22: PS converter, 23: delay line, 24: transmission section, 25: sense amplifier, 26: PLL, 31: semiconductor substrate, 31a: bulk region, 31b: N-well region, 31c: P-well region, 31d: backplate region, 31e: backplate region, 32: buried insulating film, 33: semiconductor layer, 35: contact layer, 36: element isolation insulating film, 37: interlayer insulating film, 38: contact plug, 41: gate insulating film, 42: gate electrode, 43: sidewall insulating film, 44: source / drain region

Claims

1. A solid-state imaging device comprising: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a semiconductor layer provided on the insulating film; and a plurality of transistors including one or more first transistors including source / drain regions in the semiconductor substrate and one or more second transistors including source / drain regions in the semiconductor layer, wherein the plurality of transistors include: a low-voltage transistor including a gate insulating film having a first thickness; a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage; and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage, wherein the second high-voltage transistor is included in the second transistor.

2. The solid-state imaging device according to claim 1, wherein the low-voltage transistor is included in the second transistor.

3. The solid-state imaging device according to claim 1, wherein the low-voltage transistor is included in the first transistor.

4. The solid-state imaging device according to claim 1, wherein the low-voltage transistor is provided within a digital circuit.

5. The solid-state imaging device according to claim 1, wherein the first high-voltage transistor is included in the first transistor.

6. The solid-state imaging device according to claim 1, wherein the first high-voltage transistor is provided in an analog circuit.

7. The solid-state imaging device according to claim 6, wherein the first high-voltage transistor is provided in the analog circuit other than the comparator circuit and the load circuit.

8. The solid-state imaging device according to claim 1, wherein the second high-voltage transistor is provided in a comparator circuit or a load circuit.

9. The solid-state imaging device according to claim 8, wherein the second high-voltage transistor in the comparator circuit is provided in a differential circuit.

10. The solid-state imaging device according to claim 8, wherein the second high-voltage transistor in the comparator circuit has a first conductivity type, and the second high-voltage transistor in the load circuit has a second conductivity type different from the first conductivity type.

11. The solid-state imaging device according to claim 1, wherein the semiconductor layer is formed of the same semiconductor material as the semiconductor substrate.

12. The solid-state imaging device according to claim 11, wherein the semiconductor material is silicon.

13. The solid-state imaging device according to claim 1, wherein the insulating film is an oxide film.

14. A solid-state imaging device comprising: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a semiconductor layer provided on the insulating film; and a plurality of transistors including one or more first transistors having source / drain regions in the semiconductor substrate and one or more second transistors having source / drain regions in the semiconductor layer, wherein the second transistors include a transistor provided in a comparison circuit or a load circuit.

15. The solid-state imaging device according to claim 14, wherein the transistor in the comparator circuit is provided in a differential circuit.

16. The solid-state imaging device according to claim 14, wherein the transistors in the comparator circuit have a first conductivity type, and the transistors in the load circuit have a second conductivity type different from the first conductivity type.

17. The solid-state imaging device according to claim 14, wherein the first transistor includes a transistor provided in an analog circuit other than the comparator circuit and the load circuit.

18. The solid-state imaging device according to claim 14, wherein the first transistor or the second transistor includes a transistor provided in a digital circuit.

19. The solid-state imaging device of claim 14, wherein the plurality of transistors include: a low-voltage transistor including a gate insulating film having a first thickness; a first high-voltage transistor including a gate insulating film having a second thickness thicker than the first thickness and having a first threshold voltage; and a second high-voltage transistor including a gate insulating film having the second thickness and having a second threshold voltage lower than the first threshold voltage, the second high-voltage transistor being included in the second transistor and being provided within the comparator circuit or the load circuit.

20. The solid-state imaging device of claim 19, wherein the first high-voltage transistor is included in the first transistor and is provided in an analog circuit other than the comparison circuit and the load circuit, and the low-voltage transistor is included in the first transistor or the second transistor and is provided in a digital circuit.

Images