High-electron-mobility transistor, RF switch circuit, power amplifier circuit, and wireless communication terminal

Abstract

A high-electron-mobility transistor according to an embodiment of the present technology comprises a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode. The gate insulating film has a first insulating film in contact with the semiconductor layer, and a second insulating film in contact with the first insulating film and the gate electrode. The first insulating film and the second insulating film satisfy the following relational expressions (A), (B), and (C).　Relational expression (A): EOT (T1) / EOT (T2) ≥ 1.43. Relational expression (B): EOT (T2) ≤ 0.75 nm. Relational expression (C): ε1 ≥ ε2. T1: thickness (nm) of first insulating film. T2: thickness (nm) of second insulating film. EOT (T1): equivalent oxide film thickness of first insulating film. EOT (T2): equivalent oxide film thickness of second insulating film. ε1: relative dielectric constant of first insulating film. ε2: relative dielectric constant of second insulating film. EOT: equivalent oxide film thickness (film thickness equivalent to that of silicon oxide film in terms of capacitance).

Description

High electron mobility transistor, RF switch circuit, power amplifier circuit and wireless communication terminal

[0001] The present technology relates to a high electron mobility transistor, an RF switch circuit, a power amplifier circuit, and a wireless communication terminal.

[0002] High electron mobility transistors made of nitride semiconductors have a wide band gap as well as extremely large breakdown voltage and saturated electron velocity, and are therefore attracting attention for increasing the power and speed of electronic devices (see, for example, Patent Document 1).

[0003] JP 2009-302435 A

[0004] However, further improvements in operating characteristics are required for high electron mobility transistors made of nitride semiconductors. Therefore, it is desirable to provide a high electron mobility transistor capable of achieving further improvements in operating characteristics, as well as an RF switch circuit, a power amplifier circuit, and a wireless communication terminal that include such a high electron mobility transistor.

[0005] A high electron mobility transistor according to an embodiment of the present technology includes a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film in contact with the semiconductor layer and a second insulating film in contact with the first insulating film and the gate electrode. The first insulating film and the second insulating film satisfy the following relational expressions (A), (B), and (C): EOT(T1) / EOT(T2)≧1.43 (A); EOT(T2)≦0.75 nm (B); ε1≧ε2 (C), where T1: thickness of the first insulating film (nm); T2: thickness of the second insulating film (nm); EOT(T1): equivalent oxide thickness of the first insulating film; EOT(T2): equivalent oxide thickness of the second insulating film; ε1: relative dielectric constant of the first insulating film; ε2: relative dielectric constant of the second insulating film; EOT: equivalent oxide thickness (thickness equivalent to a silicon oxide film in terms of capacitance).

[0006] An RF switch circuit according to an embodiment of the present technology includes the above-described high electron mobility transistor.

[0007] A power amplifier circuit according to an embodiment of the present technology includes the above-described high electron mobility transistor.

[0008] A wireless communication terminal according to an embodiment of the present technology includes the above-described high electron mobility transistor.

[0009] FIG. 1 is a diagram illustrating an example of a cross-sectional configuration of a high electron mobility transistor according to an embodiment of the present technology. FIG. 2 is a diagram illustrating an example of a planar configuration of the high electron mobility transistor of FIG. 1. FIG. 3 is a diagram illustrating an example of an energy band of a high electron mobility transistor of a comparative example. FIG. 4 is a diagram illustrating an example of an energy band of the high electron mobility transistor of FIG. 1 of an example. FIG. 5 is a diagram illustrating an example of a threshold voltage variation when stress is applied to high electron mobility transistors of an example and a comparative example. FIG. 6 is a diagram illustrating conditions for the gate insulating film of FIG. 1. FIG. 7A is a diagram illustrating a manufacturing process of the high electron mobility transistor of FIG. 1. FIG. 7B is a diagram illustrating a manufacturing process subsequent to FIG. 7A. FIG. 7C is a diagram illustrating a manufacturing process subsequent to FIG. 7B. FIG. 7D is a diagram illustrating a manufacturing process subsequent to FIG. 7C. FIG. 8 is a diagram illustrating a modified cross-sectional configuration of the high electron mobility transistor of FIG. 1. FIG. 9 is a diagram illustrating a modified cross-sectional configuration of the high electron mobility transistor of FIG. 1. FIG. 10 is a diagram illustrating an example circuit configuration of an RF switch circuit. Fig. 11 is a diagram illustrating an example of the circuit configuration of a wireless communication device, and Fig. 12 is a diagram illustrating an example of the circuit configuration of a power amplifier module.

[0010] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.

[0011] <1. Background> Fifth generation mobile communications (5G) uses radio waves in the high frequency band, which results in significant propagation loss and requires radio waves to be transmitted at high power. This requires devices that are high-output, highly efficient, and heat-resistant, especially for mobile terminals.

[0012] GaN-based materials, a type of III-V semiconductor, are characterized by high voltage resistance, high heat resistance, and high saturated drift velocity. In high-electron mobility transistors (HEMTs) using GaN-based materials, a two-dimensional electron gas (2DEG) is formed at the heterojunction. This 2DEG has high mobility and a high sheet electron density. Due to these characteristics, GaN-based HEMTs are capable of low resistance, high speed, and high voltage operation, making them promising high-frequency devices for 5G terminals.

[0013] Focusing on the gate structure, GaN-based HEMTs can be broadly divided into Schottky types, in which the gate metal and semiconductor layer form a Schottky junction, and MIS structure types, in which the gate metal and semiconductor layer are joined via an insulating film. Of these, MIS HEMTs have an insulating film between the semiconductor and gate metal, which suppresses gate leakage during off-state operation and reduces power consumption. For this reason, MIS HEMTs are suitable for use in mobile terminals.

[0014] On the other hand, in devices for mobile terminals, due to circuit size constraints, specifically the lack of space to implement a feedback circuit that compensates for threshold voltage fluctuations, it is extremely important to prevent threshold voltage fluctuations during device operation. In MIS-type HEMTs, the presence of a gate insulating film creates an interface state at the interface between the gate insulating film and the semiconductor layer. During device operation, charges are injected from the gate metal into the interface state, and the charges are trapped, resulting in threshold voltage fluctuations. Furthermore, increasing the thickness of the gate insulating film to suppress charge injection into the interface between the gate insulating film and the semiconductor layer reduces the gain of the transistor. Thus, in MIS-type HEMTs, there is a trade-off between suppressing threshold voltage fluctuations and improving gain.

[0015] In order to solve this problem and achieve suppression of threshold voltage fluctuation and improvement of gain, the above-mentioned Patent Document 1 discloses that fluctuation is suppressed by configuring an insulating film to have two or more layers.

[0016] In the invention described in Patent Document 1, by configuring the insulating film to have two or more layers, charge injection from the gate metal to the interface between the gate insulating film and the semiconductor layer is suppressed, and it is expected that the threshold voltage fluctuation will be suppressed. However, the following problems still remain.

[0017] In the invention described in Patent Document 1, the gate insulating film is composed of a first insulating film in contact with the semiconductor and a second insulating film stacked on the first insulating film. When considering threshold voltage fluctuations, it is necessary to consider not only the interface between the gate insulating film and the semiconductor layer, but also the influence on the threshold voltage of traps to interface states generated at the interface between the first insulating film and the second insulating film. In other words, it is necessary to consider the influence of charges injected into the interface between the first insulating film and the second insulating film, which causes threshold voltage fluctuations.

[0018] The invention described in Patent Document 1 specifies that the thickness of the second insulating film must be 2 nm or more. However, such a thickness makes it impossible to obtain a sufficient effect of suppressing threshold voltage fluctuation due to the influence of charges injected into the interface between the first insulating film and the second insulating film. Furthermore, the invention described in Patent Document 1 does not sufficiently thin the gate insulating film, resulting in a decrease in transistor gain. The present inventors have conducted extensive research into a configuration that can achieve both suppression of threshold voltage fluctuation and improvement in gain, and have come up with the following configuration. This configuration is described in detail below.

[0019] 2. Embodiments [Configuration] A high electron mobility transistor (HEMT) according to an embodiment of the present technology will be described. FIG. 1 illustrates an example cross-sectional configuration of a HEMT 1 according to the present embodiment. FIG. 2 illustrates an example planar configuration of the HEMT 1 of FIG. 1. The HEMT 1 has a so-called heterojunction structure in which a barrier layer 23 is stacked on a channel layer 22. In the HEMT 1, electrons accumulate at a high concentration near the heterojunction interface in the channel layer 22, forming a so-called two-dimensional electron gas region 22A (2DEG). This two-dimensional electron gas region 22A exhibits high electron mobility. In particular, the barrier layer 23 stacked on the channel layer 22 induces an extremely high electron concentration on the surface of the channel layer 22.

[0020] 1, the HEMT 1 includes a semiconductor layer 20 on a substrate 10. The semiconductor layer 20 includes, for example, a buffer layer 21, a channel layer 22, and a barrier layer 23, in this order from the substrate 10 side. The buffer layer 21 can be omitted as necessary.

[0021] The substrate 10 is, for example, a semi-insulating single-crystal GaN substrate. In this embodiment, a buffer layer 21 is provided between the substrate 10 and the channel layer 22. Therefore, the substrate 10 may be, for example, a SiC substrate, a sapphire substrate, or a Si substrate, or may be a SCAM substrate, a gallium oxide (Ga ２ O ３ ) substrate, an AlN substrate or a diamond substrate.

[0022] The buffer layer 21 is, for example, a compound semiconductor layer formed by epitaxial growth on the substrate 10. When the lattice constants of the substrate 10 and the channel layer 22 are different from each other, adjusting the lattice constant with the buffer layer 21 can improve the crystal quality of the channel layer 22 and suppress warpage of the wafer after the channel layer 22 is formed. When the substrate 10 is a Si substrate and the channel layer 22 is made of GaN, the buffer layer 21 is composed of, for example, AlN, AlGaN, or GaN. Note that the buffer layer 21 does not necessarily have to be a single layer and may be composed of, for example, a stack of at least two materials selected from AlN, AlGaN, and GaN. When the buffer layer 21 is composed of a ternary material (e.g., AlGaN), the buffer layer 21 may have a composition in which the composition of the ternary material gradually changes in the thickness direction. The buffer layer 21 does not necessarily have to be a compound semiconductor layer formed by epitaxial growth. For example, at least the portion of the buffer layer 21 that contacts the substrate 10 may be an incomplete epitaxial crystal growth layer due to uncertainties in the manufacturing process.

[0023] The channel layer 22 is, for example, a compound semiconductor layer formed by epitaxial growth on the substrate 10 or the buffer layer 21. The channel layer 22 is provided at least in a portion facing the gate electrode 33 (described later). The channel layer 22 is composed of a nitride semiconductor (e.g., GaN). When the HEMT 1 is in operation, a two-dimensional electron gas region 22A is generated near the heterojunction interface in the channel layer 22, thereby forming a channel region near the heterojunction interface in the channel layer 22. The channel region constitutes part of the current path between the source and drain electrodes 31 and 32 and is a region where carriers accumulate due to the difference in polarization charge between the barrier layer 23 and the channel layer 22. The channel layer 22 may be composed of a nitride semiconductor (e.g., u-GaN) without doping. In this case, impurity diffusion of carriers in the channel layer 22 is suppressed, achieving high carrier mobility.

[0024] The barrier layer 23 is, for example, a compound semiconductor layer formed by epitaxial growth on the channel layer 22. The barrier layer 23 has a role of accumulating carriers in the channel layer 22 due to polarization between the barrier layer 23 and the channel layer 22. The barrier layer 23 is made of a material that can accumulate carriers at the interface between the barrier layer 23 and the channel layer 22 due to the difference in polarization charge between the barrier layer 23 and the channel layer 22. Examples of such materials include Al ｘ In １－ｘ N (0≦x<1), or Al １－ｘ－ｙ In ｘ Ga ｙ N (0≦x<1, 0≦y<1, x+y=1). The barrier layer 23 is, for example, u-Al with no impurities added. １－ｘ－ｙ In ｘ Ga ｙ N (0≦x<1, 0≦y<1, x+y=1) In this case, impurity diffusion of carriers in the channel layer 22 is suppressed, and carrier movement with high mobility is achieved.

[0025] 1, the HEMT 1 further includes an insulating layer 24 and a gate insulating film 25 on the semiconductor layer 20. The insulating layer 24 is provided so as to cover the barrier layer 23. The insulating layer 24 is made of a material that is insulating from the barrier layer 23 and the gate electrode 33 (described later), protects the surface of the barrier layer 23 from impurities such as ions, and forms a good interface between the insulating layer 24 and the barrier layer 23 to prevent deterioration of the device characteristics. The insulating layer 24 is made of a material such as Al ２ O ３ , HfO ２ , or SiO ２ The insulating layer 24 is made of, for example, Al ２ O ３ , HfO ２ and SiO ２The insulating layer 24 may have a structure in which at least two of the above materials are stacked. For example, as shown in FIG. 1 , the insulating layer 24 has openings 26 and 27 for providing source and drain electrodes 31 and 32, and an opening 28 for providing a gate electrode 33. The surface of the barrier layer 23 is exposed at the bottom of the openings 26, 27, and 28. A cap layer may be provided between the insulating layer 24 and the barrier layer 23. The cap layer is a layer stacked on the barrier layer 23, and is, for example, a layer formed by stacking GaN or SiN on the barrier layer 23, or a layer formed by stacking GaN and SiN on the barrier layer 23.

[0026] The gate insulating film 25 is provided so as to cover the inner surface of the opening 28 and the upper surface of the insulating layer 24. The gate insulating film 25 is provided in the opening 28 between the barrier layer 23 and the gate electrode 33. The gate insulating film 25 is in contact with the surface of the barrier layer 23 exposed at the bottom of the opening 28. For example, as shown in the enlarged view in FIG. 1 , the gate insulating film 25 has a first insulating film 25 a in contact with the surface of the barrier layer 23 and a second insulating film 25 b in contact with the first insulating film 25 a and the gate electrode 33.

[0027] The first insulating film 25a and the second insulating film 25b satisfy the following relational expressions (1), (2), and (3): EOT(T1) / EOT(T2)≧1.43 (1) EOT(T2)≦0.75 nm (2) ε1≧ε2 (3) T1: thickness (nm) of the first insulating film 25a T2: thickness (nm) of the second insulating film 25b EOT(T1): equivalent oxide thickness of the first insulating film 25a EOT(T2): equivalent oxide thickness of the second insulating film 25b ε1: relative dielectric constant of the first insulating film 25a ε2: relative dielectric constant of the second insulating film 25b EOT: equivalent oxide thickness (film thickness equivalent in terms of capacitance to a silicon oxide film)

[0028] The first insulating film 25a is made of an insulating material containing a metal element of Group 4 or Group 5. The second insulating film 25b is made of an insulating material containing a metal element or a semiconductor element of Group 13 or Group 14. Both the first insulating film 25a and the second insulating film 25b have a single-layer structure. The first insulating film 25a is made of, for example, HfO ２, HfAlO, TiO ２ , NbO, Nb ２ O ５ , or ZrO ２ The second insulating film 25b has a thickness of, for example, 1 nm or less, and is made of, for example, Al ２ O ３ , GeO ２ , SiO ２ Alternatively, the first insulating film 25a may be made of SiN or the like. For example, the first insulating film 25a may be made of HfO ２ The second insulating film 25b is made of Al ２ O ３ The combination of materials for the first insulating film 25a and the second insulating film 25b is not limited to the above. The first insulating film 25a and the second insulating film 25b may be, for example, a combination of materials as follows. The materials for the first insulating film 25a and the second insulating film 25b are not limited to the above materials. First insulating film 25a Second insulating film 25b HfO ２ SiN HfO ２ SiO ２ TiO ２ Al ２ O ３

[0029] At least one of the first insulating film 25 a and the second insulating film 25 b may be a graded layer whose composition gradually changes in the thickness direction. Furthermore, in the first insulating film 25 a and the second insulating film 25 b, interdiffusion of elements may occur at or near the interface between the first insulating film 25 a and the second insulating film 25 b. Even when the first insulating film 25 a and the second insulating film 25 b have such a configuration, the first insulating film 25 a and the second insulating film 25 b each have no internal interface, and therefore can be said to have a substantially single-layer structure.

[0030] The first insulating film 25a and the second insulating film 25b may satisfy the following relational expression (4): If the first insulating film 25a and the second insulating film 25b satisfy the following relational expression (5), the first insulating film 25a is an 8-nm-thick HfO２ The second insulating film 25b is made of Al ２ O ３ In this case, the total thickness of the gate insulating film 25 is 10 nm, and the high frequency characteristics of the HEMT 1 are not as good as when the total thickness of the gate insulating film 25 is less than 10 nm, and the HEMT 1 is not very suitable for use as a power amplifier, for example. EOT(T1)+EOT(T2)<2.3 nm (4) EOT(T1)+EOT(T2)=2.3 nm (5)

[0031] The HEMT 1 further includes a source / drain electrode 31 in the opening 26 and a source / drain electrode 32 in the opening 27, as shown in FIG. 1 . The HEMT 1 further includes a gate electrode 33 in the opening 28, as shown in FIG. 1 . The source / drain electrodes 31 and 32 are in ohmic contact with the barrier layer 23 (semiconductor layer 20) through the openings 26 and 27. The gate electrode 33 is in contact with the gate insulating film 25 within the opening 28. The source / drain electrodes 31 and 32 are made of, for example, a stack of Ti / Al / Ni / Au. The gate electrode 33 is made of, for example, a stack of Ni / Au.

[0032] The HEMT 1 is formed in an active region 10a of a semiconductor layer 20, for example, as shown in Fig. 2. The active region 10a of the semiconductor layer 20 is surrounded by an element isolation region 10b that is made highly resistive by implanting ions such as boron, for example, as shown in Fig. 2. Therefore, the active region 10a is island-shaped in the semiconductor layer 20.

[0033] [Manufacturing Method] Next, a manufacturing method of the HEMT 1 according to this embodiment will be described. Figures 7A to 7D are diagrams for explaining the manufacturing process of the HEMT 1 according to this embodiment.

[0034] First, a semiconductor layer 20 is formed on the substrate 10. For example, the semiconductor layer 20 is formed on the substrate 10 by epitaxial growth. Next, an element isolation region 10b (not shown) and source / drain regions (not shown) are formed in the semiconductor layer 20. For example, selective regrowth or ion implantation can be used to form the source / drain regions. Thereafter, an insulating layer 24 is formed so as to cover the surface of the semiconductor layer 20 (FIG. 7A). For example, an ALD (Atomic Layer Deposition) method or a CVD (Chemical Vapor Deposition) method is used to form an insulating layer 24 so as to cover the surface of the semiconductor layer 20. ２ O ３ or SiO ２ In this way, the insulating layer 24 is formed on the semiconductor layer 20.

[0035] Next, the insulating layer 24 is pattern-etched to form openings 26, 27 (not shown) and opening 28 that expose the surface of the barrier layer 23 ( FIG. 7B ). Here, dry etching is preferably used to prevent the openings 26, 27, and 28 from widening. To reduce damage to the barrier layer 23, dry etching and wet etching may be combined. For example, dry etching may be used until a small portion of the insulating layer 24 remains at the bottom of the openings 26, 27, and 28, and then wet etching may be used until the surface of the barrier layer 23 is exposed at the bottom of the openings 26, 27, and 28. Furthermore, the openings 26, 27, and 28 do not necessarily need to be formed simultaneously. For example, the process of forming openings 26 and 27 and the process of forming opening 28 may be performed in separate processes.

[0036] Next, a first insulating film 25a is formed so as to cover the inner surfaces of the openings 26, 27 (not shown) and the opening 28 and the surface of the barrier layer 23 (FIG. 7C). For example, a HfO ２ A first insulating film 25a is formed by depositing a film of Al 25b to a thickness of about 6 nm. Next, a second insulating film 25b is formed so as to cover the surface of the first insulating film 25a (FIG. 7D). For example, Al 25b is deposited by ALD. ２ O ３A second insulating film 25b is formed by depositing a film of Ti, Al, Ni, and Au to a thickness of about 1 nm. Thereafter, the source / drain electrodes 31, 32 and the gate electrode 33 are formed. For example, by using a vapor deposition method, Ti, Al, Ni, and Au are deposited in this order to form the source / drain electrodes 31, 32 and the gate electrode 33. In this manner, the HEMT 1 is manufactured.

[0037] [Effects] Next, the effects of the HEMT 1 according to this embodiment will be described in comparison with a comparative example.

[0038] 3 shows an example of the energy band of a HEMT of the comparative example. In the comparative example, threshold voltage fluctuation due to stress during operation is mainly caused by charge injection from the gate electrode 33 into level A present at the interface between the single-layer gate insulating film 125 and the barrier layer 23. If the thickness of the gate insulating film 125 is T, the relative dielectric constant of the gate insulating film 125 is εr, and the charge captured at level A is ΔQ, the resulting threshold voltage fluctuation is ΔVth ∝ (T / εr) × ΔQ.

[0039] From this relational expression, three methods can be listed as possible methods for suppressing the threshold voltage fluctuation: (1) Reducing the film thickness T of the gate insulating film 125; (2) Increasing the relative dielectric constant εr of the gate insulating film 125; (3) Suppressing the injection of charges into level A.

[0040] In method (1), if the gate insulating film 125 is thin, gate leakage increases and the breakdown voltage of the transistor deteriorates, making it difficult to adopt method (1). Method (2) requires changing the material of the gate insulating film 125. However, changing the material of the gate insulating film 125 is difficult, making it difficult to adopt method (2). For these reasons, the inventors of the present application aimed to suppress threshold voltage fluctuations by method (3).

[0041] FIG. 4 shows an example of the energy band of the HEMT of the embodiment. In the embodiment, the gate insulating film 125 is composed of a stack of a first insulating film 25a and a second insulating film 25b. This creates a level B at the interface between the first insulating film 25a and the second insulating film 25b, and a portion of the charge injected from the gate electrode 33 during stress is captured by the level B. As a result, the charge captured at the level B is not injected into the level A, and charge injection into the level A can be suppressed, thereby minimizing threshold voltage fluctuations. Furthermore, by making the second insulating film 25b thinner than the first insulating film 25a, the distance from the gate electrode 33 to the level B can be shortened. As a result, the influence of the charge captured at the level B on threshold voltage fluctuations can be minimized. Furthermore, by making the second insulating film 25b thinner than the first insulating film 25a, the occurrence of gain reduction caused by a decrease in gate capacitance can be minimized. If the gate insulating film 125 is made of a single layer of HfO2, a material with a high dielectric constant is used for the gate insulating film 125, as in method (2). However, the amount of charge injected into level A is larger than when the gate insulating film 125 has a stacked structure, and therefore the amount of threshold voltage fluctuation cannot be sufficiently suppressed. This also shows that using a stacked structure for the gate insulating film 125 is important in minimizing the impact of threshold voltage fluctuation.

[0042] Next, the effect of improving threshold voltage variation according to the embodiment was verified by experiment. FIG. 5 shows an example of threshold voltage variation when stress is applied to the HEMTs of the embodiment and the comparative example. FIG. 6 shows the conditions of the gate insulating film 25 based on the results of FIG. 5. In the verification of FIG. 5, a bias that causes a current of 50 mA / mm to flow was applied as stress to the HEMT. In addition, in FIG. 5, in order to eliminate the influence of threshold voltage differences depending on the film configuration, the vertical axis uses values ​​obtained by subtracting the threshold voltage after stress from the threshold voltage at each time. The horizontal axis uses normalized stress time.

[0043] 5, a material having a relative dielectric constant of 20 was used as the first insulating film 25a, a material having a relative dielectric constant of 10 was used as the second insulating film 25b, EOT(T1) / EOT(T2) was set to 0.75, and the EOT(T2) of the second insulating film 25b was set to 1.56. In Examples 1 and 2 of FIG. 5, a material having a relative dielectric constant of 20 (HfO ２ ) is used as the second insulating film 25b, and a material having a relative dielectric constant of 10 (Al ２ O ３ 5, EOT(T1) / EOT(T2)=3, and the EOT(T2) of the second insulating film 25b was set to 0.39. In Example 2 of FIG. 5, EOT(T1) / EOT(T2)=5, and the EOT(T2) of the second insulating film 25b was set to 0.234.

[0044] In the comparative example of Fig. 5, a threshold voltage fluctuation of approximately 0.6 V occurs during stress, whereas in Examples 1 and 2 of Fig. 5, a fluctuation of less than 0.1 V occurs, which is approximately 1 / 6 of the threshold voltage fluctuation in the comparative example. Since a power amplifier for a mobile terminal is required to have a threshold voltage fluctuation of less than 0.1 V, for example, the fluctuation amounts in Examples 1 and 2 of Fig. 5 can meet this requirement.

[0045] The reason for using a high-dielectric-constant material for the first insulating film 25a is that the first insulating film 25a is thicker than the second insulating film 25b. In Examples 1 and 2 of FIG. 5, T1 > T2 holds. If a low-dielectric-constant material is used for the first insulating film 25a, the majority of the gate insulating film 25 will be made of a low-dielectric-constant material, which will result in a decrease in gain. Therefore, the first insulating film 25a needs to have a higher dielectric constant than the second insulating film 25b.

[0046] Furthermore, from the experimental results of Examples 1 and 2 shown in FIG. 5, it was found that the first insulating film 25a was made of HfO ２ The second insulating film 25b is made of Al ２ O ３ It can be seen that by setting the above, the threshold voltage fluctuation during stress can be reduced to 0.1 V or less. In this case, the first insulating film 25a and the second insulating film 25b satisfy the following relational expression (6): EOT(T1) / EOT(T2)≧3 (6)

[0047] On the other hand, according to the above-mentioned Patent Document 1, HfO ２ and Al ２ O ３ It can be seen that there is a certain range in the relative dielectric constant of . If we redefine relational expression (6) taking into account a certain margin in this range of relative dielectric constant, we obtain relational expression (1).

[0048] The second insulating film 25b is also made of Al. ２ O ３ When the EOT is calculated assuming that the typical relative dielectric constant of Al is 10 and the film thickness of the second insulating film 25b is 1 nm, the second insulating film 25b satisfies the following relational expression (7). ２ O ３ and the range of the relative dielectric constant of the second insulating film 25b. ２ O ３ Considering the use of a material with a lower dielectric constant than EOT(T2) 0.39 nm, the above-mentioned relational expression (2) is obtained.

[0049] Furthermore, examples are provided for possible combinations of the first insulating film 25a and the second insulating film 25b, and when EOT(T1) / EOT(T2) and EOT(T2) are calculated for each example, the values ​​plotted in Fig. 6 are obtained. From Fig. 6, it can be seen that in five examples, the first insulating film 25a and the second insulating film 25b satisfy the following relational expression (8): EOT(T1) / EOT(T2)≧2 (8)

[0050] In this manner, in this embodiment, by forming the first insulating film 25a and the second insulating film 25b so as to satisfy the above-mentioned conditions, it is possible to realize a HEMT 1 with excellent operating characteristics.

[0051] 3. Modifications Next, a description will be given of modifications of the HEMT 1 according to the above embodiment. In the following, common components will be given common reference numerals, and descriptions of the common components will be omitted as appropriate.

[0052] [Modification A] In the above embodiment, the second insulating film 25b may have a multi-layer structure in which adjacent films have different dielectric constants. In this modification, the second insulating film 25b has a structure in which insulating films 25b1, 25b2, 25b3, and 25b4 are stacked in this order from the first insulating film 25a side, as shown in FIG. 8. In this case, the total thickness of the insulating films 25b1, 25b2, 25b3, and 25b4 is T2. The insulating layers 25b1 and 25b3 may be made of, for example, Al. ２ O ３ The insulating layers 25b2 and 25b4 are made of, for example, SiO ２ The number of films included in the second insulating film 25b is not limited to four, but may be two, three, or five or more.

[0053] In this modification, the second insulating film 25b has a multi-layer structure. This allows most of the charges injected from the gate electrode 33 to be captured at the interface closest to the gate electrode 33 among the multiple interfaces included in the second insulating film 25b. As a result, the influence of the charges captured at level B on the threshold voltage fluctuation can be minimized. In addition, the occurrence of a decrease in gain caused by a decrease in gate capacitance can be minimized.

[0054] [Modification B] In the above embodiment and its modifications, for example, as shown in FIG. 9, a back barrier layer 29 may be provided between the buffer layer 21 and the channel layer 22. The back barrier layer 29 is a compound semiconductor layer formed by epitaxial growth on the buffer layer 21. The back barrier layer 29 is made of a compound semiconductor material that raises the energy band on the back barrier layer 29 side in the channel layer 22. The back barrier layer 29 is made of, for example, Al ｘ Ga ｙ In ｘ N (x+y+z=1, x≧0, y≧0, z≧0). The back barrier layer 29 is made of, for example, u-Al, which is not doped with impurities. ｘ Ga ｙ In ｘIt may be made of N. By providing the back barrier layer 29 between the buffer layer 21 and the channel layer 22 in this way, it is possible to realize a HEMT 1 with excellent operating characteristics.

[0055] [Variation C] In the above-described embodiment and its variations, the present technology is applied to a HEMT. However, in the above-described embodiment and its variations, the present technology can also be applied to a FET. That is, in the above-described embodiment and its variations, a FET may be used instead of the HEMT 1.

[0056] [Variation D] In the above embodiment and variations thereof, the second insulating film 25b may have a thickness of, for example, 1 nm or more and less than 2 nm, which can improve the dielectric strength of the device while suppressing fluctuations in threshold voltage.

[0057] 4. Application Examples Next, application examples of the HEMT 1 according to the above-described embodiment and its modified examples will be described. In the following, common components will be assigned common reference numerals, and descriptions of the common components will be omitted as appropriate.

[0058] 10 shows an example of an RF switch circuit 2. The RF switch circuit 2 is used in a mobile communication system such as a mobile phone, and includes, for example, a first terminal IN, a second terminal IO, a third terminal OUT, a first switching element SW1, and a second switching element SW2.

[0059] The first terminal IN is used to input a transmission signal. The second terminal IO is connected to an antenna. The third terminal OUT is used to output a reception signal received by the antenna. The first switching element SW1 is connected between the first terminal IN and the second terminal IO. The second switching element SW2 is connected between the second terminal IO and the third terminal OUT. Either or both of the first switching element SW1 and the second switching element SW2 are configured by the HEMT 1 according to the above-described embodiment and its modified examples.

[0060] A third switching element SW3 is connected between the first terminal IN and a power supply (ground in this example). A fourth switching element SW4 is connected between the third terminal OUT and a power supply (ground in this example). Either or both of the third switching element SW3 and the fourth switching element SW4 are configured by the HEMT 1 according to the above-described embodiment and its modifications.

[0061] In the RF switch circuit 2, during transmission, i.e., when a transmission signal is output from the transmission system of the wireless communication device to the antenna, the first switching element SW1 and the fourth switching element SW4 are in a conductive state, and the second switching element SW2 and the third switching element SW3 are in a non-conductive state. At this time, the transmission signal is input from the first terminal IN and output to the second terminal IO via the first switching element SW1.

[0062] During reception, i.e., when a signal received by an antenna is input to the reception system of the wireless communication device, the first switching element SW1 and the fourth switching element SW4 are in a non-conductive state, and the second switching element SW2 and the third switching element SW3 are in a conductive state. At this time, the reception signal received by the antenna is input from the second terminal IO and output to the third terminal OUT via the second switching element SW2.

[0063] In this manner, the HEMT 1 according to the above-described embodiment and its modification is used in this application example, which makes it possible to improve power saving.

[0064] [Application Example β] Fig. 11 shows an example of a wireless communication terminal 3. The wireless communication terminal 3 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection. The wireless communication terminal 3 includes, for example, an antenna ANT, an RF switch circuit 2, a high-power amplifier HPA, a high-frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F (for example, a wireless LAN (W-LAN; Wireless Local Area Network), Bluetooth (registered trademark), etc.). The RF switch circuit 2 has, for example, the configuration shown in Fig. 10. The high-frequency integrated circuit RFIC and the baseband unit BB are connected by the interface unit I / F.

[0065] In the wireless communication terminal 3, during transmission, i.e., when a transmission signal is output from the transmission system of the wireless communication terminal 3 to the antenna ANT, the transmission signal output from the baseband unit BB is output to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the RF switch circuit 2.

[0066] During reception, that is, when a signal received by the antenna ANT is input to the reception system of the wireless communication terminal 3, the received signal is input to the baseband unit BB via the RF switch circuit 2 and the high-frequency integrated circuit RFIC. The signal processed by the baseband unit BB is output from output units such as the audio output unit MIC, the data output unit DT, and the interface unit I / F.

[0067] In this manner, the HEMT 1 according to the above-described embodiment and its modification is used in this application example, which makes it possible to improve power saving.

[0068] [Application Example γ] Fig. 12 shows an example of a power amplifier module 4. The power amplifier module 4 has power amplifiers configured with the HEMTs 1 according to the above-described embodiment and its modifications connected in multiple stages on the same board. Fig. 12 shows the circuit configuration of the power amplifier module 4 that complies with the W-CDMA specification requirements.

[0069] 12, the power amplifier module 4 includes an input matching circuit 51, a front-stage power amplifier 52, an intermediate matching circuit 53, a rear-stage power amplifier 54, and an output matching circuit 55. The gain of the front-stage power amplifier 52 is set to 15.0 dB, and the gain of the rear-stage power amplifier 54 is set to 14.0 dB.

[0070] The front-stage power amplifier 52 and the rear-stage power amplifier 54 are configured to include the HEMT 1 according to the above-described embodiment and its modified example as an amplifying element.

[0071] In this manner, the HEMT 1 according to the above-described embodiment and its modification is used in this application example, which makes it possible to improve power saving.

[0072] Although the present technology has been described above by way of embodiments, modifications, and application examples, the present technology is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present technology are not limited to the effects described in this specification. The present technology may have effects other than those described in this specification.

[0073] For example, in the above-described embodiments, the semiconductor layer 20 is mainly made of a GaN-based semiconductor, but it may be mainly made of a III-V group or II-VI group semiconductor, for example, it may be mainly made of a GaAs-based semiconductor.

[0074] Furthermore, for example, the present technology can be configured as follows: (1) A high electron mobility transistor comprising: a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode, wherein the gate insulating film has a first insulating film in contact with the semiconductor layer and a second insulating film in contact with the first insulating film and the gate electrode, and the first insulating film and the second insulating film satisfy the following relational expressions (A), (B), and (C): EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) (2) The high electron mobility transistor according to (1), wherein the first insulating film and the second insulating film both have a single-layer structure. (3) The high electron mobility transistor according to (1), wherein the first insulating film has a single-layer structure, and the second insulating film has a multilayer structure in which adjacent films have different dielectric constants. (4) The high electron mobility transistor according to any one of (1) to (3), wherein the first insulating film and the second insulating film satisfy the following relational expression (D): EOT(T1) + EOT(T2) < 2.3 nm (D). (5) The high electron mobility transistor according to any one of (1) to (4), wherein the second insulating film has a thickness of 1 nm or less. (6) The high electron mobility transistor according to any one of (1) to (4), wherein the second insulating film has a thickness of 1 nm or more and less than 2 nm. (7) The high electron mobility transistor according to any one of (1) to (6), wherein the first insulating film contains a metal element of Group 4 or Group 5, and the second insulating film contains a metal element or semiconductor element of Group 13 or Group 14. (8) The high electron mobility transistor according to any one of (1) to (7), wherein the semiconductor layer has a channel layer made of a nitride semiconductor at least in a portion facing the gate electrode.(9) The semiconductor layer includes Al between the gate insulating film and the channel layer. ｘ In １－ｘ N (0≦x<1), or Al １－ｘ－ｙ In ｘ Ga ｙ (10) The high electron mobility transistor according to (8), further comprising a barrier layer made of AlN (0≦x<1, 0≦y<1, x+y=1), in a portion of the semiconductor layer facing the barrier layer with the channel layer interposed therebetween. ｘ Ga ｙ In ｘN(x+y+z=1, x≧0, y≧0, z≧0). (11) The high electron mobility transistor according to any one of (1) to (10), wherein the first insulating film and the second insulating film satisfy the following relational expression (E): EOT(T1) / EOT(T2)≧2 (E). (12) The high electron mobility transistor according to any one of (1) to (10), wherein the first insulating film and the second insulating film satisfy the following relational expression (F). EOT(T1) / EOT(T2)≧3 (F) (13) An RF switch circuit comprising: a high electron mobility transistor, the high electron mobility transistor having a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having a first insulating film in contact with the semiconductor layer, and a second insulating film in contact with the first insulating film and the gate electrode, the first insulating film and the second insulating film satisfying the following relational expressions (A), (B), and (C). EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) (14) A high electron mobility transistor is provided, the high electron mobility transistor having: a semiconductor layer; a gate electrode; and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having: a first insulating film in contact with the semiconductor layer; and a second insulating film in contact with the first insulating film and the gate electrode, The power amplifier circuit, wherein the first insulating film and the second insulating film satisfy the following relational expressions (A), (B), and (C):EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) (15) A high electron mobility transistor is provided, the high electron mobility transistor having: a semiconductor layer; a gate electrode; and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having: a first insulating film in contact with the semiconductor layer; and a second insulating film in contact with the first insulating film and the gate electrode, A wireless communication terminal, wherein the first insulating film and the second insulating film satisfy the following relational expressions (A), (B), and (C): EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness equivalent in terms of capacitance to a silicon oxide film).

[0075] This application claims priority based on Japanese Patent Application No. 2023-106351, filed on June 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0076] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A high electron mobility transistor comprising: a semiconductor layer; a gate electrode; and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having: a first insulating film in contact with the semiconductor layer; and a second insulating film in contact with the first insulating film and the gate electrode, the first insulating film and the second insulating film satisfying the following relational expressions (A), (B), and (C): EOT(T1) / EOT(T2)≧1.43...(A) EOT(T2)≦0.75 nm...(B) ε1≧ε2...(C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) 2. The high electron mobility transistor according to claim 1, wherein the first insulating film and the second insulating film each have a single-layer structure.

3. The high electron mobility transistor according to claim 1, wherein the first insulating film has a single-layer structure, and the second insulating film has a multi-layer structure in which adjacent films have different relative dielectric constants.

4. The high electron mobility transistor according to claim 1, wherein the first insulating film and the second insulating film satisfy the following relational expression (D): EOT(T1)+EOT(T2)<2.3 nm (D).

5. The high electron mobility transistor according to claim 1, wherein the second insulating film has a thickness of 1 nm or less.

6. The high electron mobility transistor according to claim 1, wherein the second insulating film has a thickness of 1 nm or more and less than 2 nm.

7. The high electron mobility transistor according to claim 1, wherein the first insulating film contains a metal element of Group 4 or Group 5, and the second insulating film contains a metal element or semiconductor element of Group 13 or Group 14.

8. The high electron mobility transistor according to claim 1, wherein the semiconductor layer has a channel layer made of a nitride semiconductor at least in a portion facing the gate electrode.

9. The semiconductor layer has an Al layer between the gate insulating film and the channel layer. ｘ In １－ｘ N (0≦x<1), or Al １－ｘ－ｙ In ｘ G ｙ 9. The high electron mobility transistor according to claim 8, further comprising a barrier layer composed of N, where 0≦x<1, 0≦y<1, x+y=1.

10. The semiconductor layer is provided with Al at a portion facing the barrier layer with the channel layer therebetween. ｘ G ｙ In ｘ 10. The high electron mobility transistor according to claim 9, further comprising a back barrier layer composed of N(x+y+z=1, x≧0, y≧0, z≧0).

11. The high electron mobility transistor according to claim 1, wherein the first insulating film and the second insulating film satisfy the following relational expression (E): EOT(T1) / EOT(T2)≧2 (E) 12. The high electron mobility transistor according to claim 1, wherein the first insulating film and the second insulating film satisfy the following relational expression (F): EOT(T1) / EOT(T2)≧3 (F).

13. An RF switch circuit comprising a high electron mobility transistor, the high electron mobility transistor having a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having a first insulating film in contact with the semiconductor layer, and a second insulating film in contact with the first insulating film and the gate electrode, the first insulating film and the second insulating film satisfying the following relational expressions (A), (B), and (C). EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) 14. A power amplifier circuit comprising a high electron mobility transistor, the high electron mobility transistor having a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having a first insulating film in contact with the semiconductor layer, and a second insulating film in contact with the first insulating film and the gate electrode, the first insulating film and the second insulating film satisfying the following relational expressions (A), (B), and (C). EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film) 15. A wireless communication terminal comprising a high electron mobility transistor, the high electron mobility transistor having a semiconductor layer, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode, the gate insulating film having a first insulating film in contact with the semiconductor layer, and a second insulating film in contact with the first insulating film and the gate electrode, the first insulating film and the second insulating film satisfying the following relational expressions (A), (B), and (C). EOT(T1) / EOT(T2)≧1.43 (A) EOT(T2)≦0.75 nm (B) ε1≧ε2 (C) T1: thickness (nm) of the first insulating film T2: thickness (nm) of the second insulating film EOT(T1): equivalent oxide thickness of the first insulating film EOT(T2): equivalent oxide thickness of the second insulating film ε1: relative dielectric constant of the first insulating film ε2: relative dielectric constant of the second insulating film EOT: equivalent oxide thickness (film thickness capacitively equivalent to a silicon oxide film)

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