Capacitor

Abstract

In this capacitor, a dielectric layer has a rectangular shape including a first edge extending from a first side to a second side. A first electrode and a second electrode face each other across the dielectric layer in the thickness direction and each have a rectangular shape with four edges parallel to the four edges of the dielectric layer. First wiring extends from the first electrode to an end portion on the first side of the first edge. Second wiring extends from the second electrode to an end portion on the second side of the first edge. A first edge portion on the second side of the first wiring is inclined with respect to the first edge in a first direction located on the second side toward the first electrode. A second edge portion on the first side of the second wiring is inclined with respect to the first edge in a second direction located on the first side toward the second electrode.

Description

capacitor

[0001] The present disclosure relates to capacitors.

[0002] A multilayer ceramic capacitor having multiple dielectric layers and multiple electrodes that are alternately stacked is known (see, for example, Patent Document 1 listed below). In FIGS. 26 to 30 of Patent Document 1, two rectangular electrodes face each other, sandwiching a rectangular dielectric layer. Wiring extends from one electrode toward a pair of diagonal corners of the dielectric layer. Wiring extends from the other electrode toward the other pair of diagonal corners of the dielectric layer. External terminals for connection to the outside are provided at each diagonal corner, covering the side surfaces of the dielectric layer. In the above configuration, each wire is rectangular in shape, with corners overlapping the electrodes. That is, the edges of the wire extend in a direction perpendicular to the sides of the electrodes and the sides of the dielectric layer.

[0003] JP 2016-149479 A

[0004] A capacitor according to one aspect of the present disclosure includes a dielectric layer, a first electrode, a second electrode, a first wiring, and a second wiring. The dielectric layer has a rectangular shape including a first side extending from a first side to a second side. The first electrode and the second electrode face each other, sandwiching the dielectric layer in the thickness direction. Each electrode has a rectangular shape with four sides parallel to the four sides of the dielectric layer. The first wiring extends from the first electrode to an end of the first side of the first side. The second wiring extends from the second electrode to an end of the first side of the first side. A first edge on the second side of the first wiring is inclined with respect to the first side in a first direction that is closer to the first electrode than the second side. A second edge on the first side of the second wiring is inclined with respect to the first side in a second direction that is closer to the second electrode than the first side.

[0005] Fig. 2 is a perspective view showing a capacitor according to an embodiment. Fig. 3 is a schematic exploded perspective view of the capacitor of Fig. 1. Fig. 4 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 5 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 6 is a planar perspective view illustrating the effect of the capacitor of Fig. 1. Fig. 7 is a table showing the characteristics of capacitors according to examples and comparative examples.

[0006] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic. Therefore, for example, the dimensional ratios in the drawings do not necessarily correspond to the actual ones. Furthermore, the dimensional ratios may not match between drawings. Certain shapes and / or dimensions may be exaggerated, and details may be omitted. However, the above does not deny that the actual shapes and / or dimensions may be as shown in the drawings, or that features of shapes and / or dimensions may be extracted from the drawings.

[0007] In the following description, when referring to a "rectangle" (or rectangular shape), a "square" (or square shape), and a "rectangle" (or rectangular shape), the corners may be chamfered by a curved surface or the like, as long as the concept of the shape is valid. For example, one side may be chamfered by a length of 1 / 10 or 1 / 20 or less of the length of the side. It goes without saying that, when viewed microscopically, the corners may be rounded due to manufacturing precision (errors). The same applies to other polygons, etc.

[0008] (Overview of the embodiment) Fig. 1 is a perspective view showing a capacitor 1 according to an embodiment. For convenience, Fig. 1 and other figures described below are illustrated with a Cartesian coordinate system D1D2D3. The capacitor 1 may be used with either side designated as upper or lower. However, in the description of the embodiment, for convenience, the +D3 side may be designated as upper, and terms such as upper surface and lower surface may be used.

[0009] The capacitor 1 is, for example, a multilayer ceramic capacitor. The capacitor 1 has a roughly rectangular parallelepiped body 3 and four external terminals 5 located at the four corners of the body 3 in a plan view (as viewed in the direction D3). The external terminals 5 contribute to electrical connection between the capacitor 1 and other electronic components (for example, a circuit board (not shown)).

[0010] Fig. 2 is an exploded perspective view of the capacitor 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 2 is a schematic view for understanding the shapes and relative positions of the electrodes. Therefore, Fig. 2 shows fewer layers, which will be described later, than Fig. 3.

[0011] The main body 3 has a first electrode 9A and a second electrode 9B (sometimes referred to as "electrodes 9" without distinction between them) that face each other with a dielectric layer 7 in between. From another perspective, the main body 3 has a plurality of dielectric layers 7 and a plurality of electrodes 9 that are alternately stacked one by one. The first electrode 9A is connected to a pair of external terminals 5 via a pair of first wirings 11A. The second electrode 9B is connected to another pair of external terminals 5 via a pair of second wirings 11B. Note that, hereinafter, the first wirings 11A and the second wirings 11B will sometimes be referred to as "wirings 11" without distinction between them.

[0012] The planar shape of the dielectric layer 7 is generally rectangular (square in the illustrated example). The planar shape of the electrode 9 is generally rectangular (square in the illustrated example) having four sides parallel to the four sides of the dielectric layer 7. A pair of wirings 11 extend from a pair of opposing corners of the electrode 9 and reach a pair of corners of the dielectric layer 7 located outside the corners. When viewed from above, the pair of first wirings 11A and the pair of second wirings 11B are located at a pair of different corners of the dielectric layer 7.

[0013] Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. From another perspective, it is a plan view of the upper surface of the first electrode 9A. In this figure, the second wiring 11B is also indicated by a dotted line.

[0014] Focus on the first side 7a, which is one of the four sides of the dielectric layer 7 (here, the side on the -D1 side is taken as an example). In this case, the first wiring 11A on the -D1 side can be considered to extend to the end of the first side 7a on the +D2 side. Similarly, the second wiring 11B on the -D1 side can be considered to extend to the end of the first side 7a on the -D2 side. Note that, hereinafter, the first wiring 11A and the second wiring 11B may refer to those on the -D1 side unless otherwise specified.

[0015] Here, the first edge 11Aa, which is the edge on the -D2 side of the first wiring 11A, is inclined relative to the first side 7a so that it is positioned closer to the -D2 side as it approaches the first electrode 9A. The second edge 11Ba, which is the edge on the +D2 side of the second wiring 11B, is inclined relative to the first side 7a so that it is positioned closer to the +D2 side as it approaches the second electrode 9B. By inclining the first edge 11Aa and the second edge 11Ba in this way, it is possible to reduce the equivalent series inductance, for example (details will be described later).

[0016] The above is an overview of the embodiment. Below, the embodiment will be roughly described in the following order: 1. Overall structure of capacitor (FIGS. 1 to 4) 2. Functional section 2.1. Functional section in general 2.2. Dielectric layer 2.3. Electrode 2.4. Wiring 3. Cover 3.1. Cover in general 3.2. Insulating layer 3.3. Dummy electrode 4. External terminal 5. Capacitor manufacturing method 6. Effects of inclined wiring 6.1. Principle 6.2. Example 7. Summary of the embodiment

[0017] (1. Overall Configuration of Capacitor) As can be understood from the description of the outline of the embodiment, the capacitor 1 may be configured in various ways as long as it has a first wiring 11A extending from the first electrode 9A to one end of the first side 7a on the upper surface of the dielectric layer 7, and a second wiring 11B extending to the other end of the first side 7a on the lower surface of the dielectric layer 7. In other words, the overall configuration of the capacitor 1 is not limited to that illustrated in Figures 1 to 4. However, in describing the embodiment, for convenience, the description may be based on the illustrated example without any particular mention.

[0018] The capacitor 1 is configured as, for example, a surface-mounted chip component. Specifically, the capacitor 1 is placed with the -D3 side or +D3 side facing a circuit board (not shown). The four pads on the circuit board are joined to the four external terminals 5 with a conductive bonding material (e.g., solder) (not shown), thereby mounting the capacitor on the circuit board.

[0019] The configuration (internal structure and external shape) of the capacitor 1 is, for example, roughly (excluding asymmetry due to differences in the orientations of the first wiring 11A and the second wiring 11B, for example) plane-symmetric with respect to a plane of symmetry (not shown) that is parallel to the D1D2 plane and passes through the center of the capacitor 1 in the thickness direction. Also, the configuration of the capacitor 1 is, for example, 180° rotationally symmetric when viewed in the D3 direction. Of course, the capacitor 1 does not have to have such symmetry.

[0020] As described above, the shape of the main body 3 shown in Fig. 1 is generally a thin rectangular parallelepiped. This rectangular parallelepiped may be square (as shown in the example) or rectangular (excluding squares; the same applies below) in plan view. For convenience, in the description of the embodiments, a square shape may be assumed unless otherwise specified.

[0021] The specific dimensions of the main body 3 (or the capacitor 1) are arbitrary. For example, when the capacitor 1 is relatively small, the lengths of the main body 3 (or the capacitor 1) in the D1 direction and the D2 direction are each 400 μm to 800 μm, and the thickness in the D3 direction is 50 μm to 100 μm.

[0022] As shown in Fig. 3, the portion of the main body 3 where the dielectric layers 7 and the electrodes 9 (and wiring 11) are alternately stacked is referred to as the functional portion 13. The functional portion 13 may be a part of the main body 3 (as in the illustrated example), or it may be the entire main body 3. In the example of Fig. 3, the main body 3 has two covers 15 that overlap the upper and lower surfaces of the functional portion 13, respectively. The covers 15 contribute to, for example, improving the strength of the main body 3.

[0023] Note that, unless otherwise specified or unless a contradiction occurs, multiple components of the same type (e.g., 5, 7, 9, 11, 15, 17, 19, or 21) may be provided with the same (or corresponding) shape, size, material, and position, etc., as compared to each other. For example, multiple dielectric layers 7 may be configured with the same shape, size, and material, and may overlap each other without excess or deficiency in planar perspective. Therefore, unless otherwise specified or unless a contradiction occurs, a description of one component may be considered to be common to multiple components of the same type. Furthermore, individual mention of multiple components of the same type overlapping without excess or deficiency in planar perspective may be omitted.

[0024] A layered (film-like) component (e.g., 5, 7, 9, 11, 17, or 21) may be entirely made of one material, but may also be made of layers made of different materials.

[0025] Here is an example of an embodiment different from the illustrated example. Instead of having four external terminals 5, the capacitor 1 may have two external terminals 5 at both ends of its longitudinal direction in a plan view. In this configuration, for example, assuming that the D2 direction is the longitudinal direction, one first wiring 11A may extend from approximately the entire +D2 side of the first electrode 9A toward the +D2 side, and one second wiring 11B may extend from approximately the entire −D2 side of the second electrode 9B toward the −D2 side. Furthermore, for example, as in FIG. 4 , the edge of the wiring 11 may be inclined with respect to the −D1 side and / or the +D1 side. Furthermore, the capacitor 1 may have an exterior resin covering the entire illustrated structure and lead wires connected to the external terminals 5 (for example, a total of four or two) and extending from the exterior resin.

[0026] (2. Functional Part) (2.1. Functional Part in General) In the functional part 13, the configuration in which the first edge portion 11Aa and the second edge portion 11Ba are inclined, as described in the overview of the embodiment, is established, for example, on all four sides of the dielectric layer 7. Also, it is established on all of the dielectric layers 7. However, the above configuration may be established on only one of the four sides. Also, it may be established on only some of the dielectric layers 7.

[0027] The functional section 13 has a shape that is, for example, roughly a thin rectangular parallelepiped. Its planar shape is the same as that of the main body section 3. However, unlike the illustrated example, the planar shape of the functional section 13 may differ from that of the main body section 3 by, for example, covering the side surface of the functional section 13 that is perpendicular to the first edge 7a with another insulating layer. The specific thickness of the functional section 13 is arbitrary. For example, the thickness of the functional section 13 may be 0.2 to 0.8 times the thickness of the main body section 3 (both thicknesses are based on the surface of the insulating portion).

[0028] The functional section 13 has multiple dielectric layers 7. However, theoretically, the functional section 13 may have only one dielectric layer 7. The first electrodes 9A and the second electrodes 9B are alternately stacked one by one, sandwiching the dielectric layer 7 therebetween. Unlike the example shown in the figure, the first electrodes 9A and the second electrodes 9B may be alternately stacked two by two. That is, the layers may be stacked in the thickness direction in the following order: first electrode 9A, dielectric layer 7, first electrode 9A, dielectric layer 7, second electrode 9B, dielectric layer 7, second electrode 9B, dielectric layer 7, first electrode 9A, dielectric layer 7, first electrode 9A...

[0029] (2.2. Dielectric Layer) The dielectric layer 7 is basically a layer having a constant thickness (at least between the electrodes 9). The thickness of the dielectric layer 7 may be set appropriately depending on the characteristics required of the capacitor 1. Examples of a relatively thin thickness include a thickness between the electrodes 9 of 3 μm or less or 1 μm or less. The shape and dimensions of the dielectric layer 7 in a planar view are the same as the shape and dimensions of the functional section 13 in a planar view. The material of the dielectric layer is, for example, ceramics, and the specific type is also optional. The number of laminated dielectric layers 7 (electrodes 9) is optional. For example, there are 10 to 30 layers.

[0030] (2.3. Electrodes) The electrodes 9 are layer-like and have a certain thickness. The thickness of the electrodes 9 is arbitrary, and may be thinner than, approximately the same as, or thicker than the thickness of the region of the dielectric layer 7 between the electrodes 9. The material of the electrodes 9 is, for example, a metal. The specific type of metal is arbitrary, and may be, for example, a base metal (e.g., Ni or Cu).

[0031] As described above, the planar shape of the electrode 9 is, for example, a rectangle having four sides parallel to the four sides of the dielectric layer 7. The relationship between the two planar shapes may be square-square (as in the illustrated example), square-rectangle, or rectangle-square. The outer edge of the electrode 9 is spaced inward from the outer edge of the dielectric layer 7 along its entire periphery (along all four sides). However, they may partially overlap. The geometric center of the electrode 9 roughly coincides with the geometric center of the dielectric layer 7, for example. However, they may be offset from each other.

[0032] The dimensions of the electrode 9 in a planar view are arbitrary as long as there is a distance between the first side 7a of the dielectric layer 7 and one side of the electrode 9 parallel to the first side 7a (as long as the length of the electrode 9 in the D1 direction is shorter than the length of the dielectric layer 7 in the D1 direction). For example, when comparing the lengths of the parallel sides of the electrode 9 and the dielectric layer 7, the former may be 0.6 to 0.9 or 0.8 to 0.9 relative to the latter. Furthermore, for example, the distance between the parallel sides of the electrode 9 and the dielectric layer 7 may be 0.05 to 0.20 or 0.05 to 0.10 of the length of the dielectric layer 7 in the opposing direction. The above-mentioned example lengths and example distances may apply to, for example, all four sides.

[0033] (2.4. Wiring) The wiring 11 is in the form of a layer having a certain thickness. The wiring 11 is, for example, formed integrally with the electrode 9. That is, the material and thickness of the wiring 11 are the same as the material and thickness of the electrode 9. The wiring 11 extends from the electrode 9 to the edge of the dielectric layer 7 and is exposed on the side surface of the main body 3. The external terminal 5 is joined to this exposed portion. This electrically connects the external terminal 5 and the electrode 9.

[0034] More specifically, the wiring 11 extends from a corner of the electrode 9 to a corner of the dielectric layer 7 located outside the electrode 9. In other words, the two lateral edges of the wiring 11 extend from two intersecting sides of the electrode 9 and reach two sides of the dielectric layer 7 that are parallel to the two intersecting sides. The center line (not shown) of the wiring 11 extends from the vertex of the corner of the electrode 9 (which is integral with the wiring 11 but can be identified from the two intersecting sides of the electrode 9) to the vertex of the corner of the dielectric layer 7. From another perspective, the wiring 11 has a shape that is symmetrical with respect to a line (not shown) that extends from the vertex of the corner of the electrode 9 to the vertex of the corner of the dielectric layer 7. Therefore, a description of one of the two edges of the wiring 11 may be applied to the other edge, unless a contradiction arises.

[0035] Unlike the illustrated example, the center line of the wiring 11 may be offset from the line from the vertex of the electrode 9 to the vertex of the dielectric layer 7. Furthermore, the offset between the center line of the wiring 11 and the line between the vertices may be so large that one edge of the wiring 11 overlaps or exceeds the line between the vertices. Furthermore, the center line of the wiring 11 and the line between the vertices may be inclined relative to each other.

[0036] The wiring 11 extends linearly with a constant width, for example. In other words, the edges on both sides of the wiring 11 are linear and parallel to each other over the entire length.

[0037] Unlike the illustrated example, the width of the wiring 11 may vary depending on the position in the longitudinal direction of the wiring 11 over part or all of the length of the wiring 11. Furthermore, the center line, one edge, and / or both edges of the wiring 11 may be curved (bent and / or bent) over part or all of the length of the wiring 11.

[0038] In the illustrated example, the inclination of the wiring 11 described in the overview of the embodiment is established on all four sides of the dielectric layer 7. From another perspective, in each wiring 11, both of the two lateral edges are inclined with respect to the side of the dielectric layer 7 (and electrode 9) to which it is connected. However, the inclination of the wiring 11 may be established on only one of the two edges.

[0039] Only a portion of the first edge 11Aa or the second edge 11Ba may be inclined with respect to the first side 7a. In this case, the length by which the first edge 11Aa (or the second edge 11Ba) is inclined with respect to the first side 7a may be, for example, 0.5 or more or 0.8 or more of the length of the first edge 11Aa.

[0040] The dimensions of the wiring 11 are arbitrary. For an example of the length of the wiring 11, see the example (described above) of the distance between the side of the dielectric layer 7 and the side of the electrode 9. The width of the wiring 11 may be set, for example, so that the length L1 ( FIG. 4 ) of the wiring 11 in contact with one side of the dielectric layer 7 is 0.3 to 0.4 times the length of one side of the electrode 9 and / or 0.2 to 0.4 times the length of one side of the dielectric layer 7.

[0041] The inclination angle θ ( FIG. 4 ) of the first edge 11Aa (or the second edge 11Ba) relative to the first side 7a is also arbitrary. For example, the inclination angle θ may be 18° or more and 80° or less, or 30° or more and 60° or less. When the first edge 11Aa is not linear, the inclination angle θ may be, for example, 0.6 or more, 0.8 or more, or may be true over the entire length of the first edge 11Aa. The effect of the inclination angle θ on the characteristics of the capacitor 1 will be described later in the description of an example ( FIG. 6 ).

[0042] (3. Cover) (3.1. Covers in general) The cover 15 shown in FIG. 3 is provided on both the upper and lower surfaces of the functional part 13, for example. Unlike the example shown, the cover 15 may be provided on only one of the upper and lower surfaces of the functional part 13. The cover 15 is, for example, a layer having a shape and dimensions that overlap the functional part 13 exactly in planar perspective. The thickness of the cover 15 is roughly constant. The proportion of the thickness of the cover 15 to the thickness of the main body part 3 is the reverse of the proportion of the thickness of the functional part 13 to the thickness of the main body part 3 (as described above), so examples of specific proportions will be omitted.

[0043] Each cover 15 has, for example, at least one (plurality in the illustrated example) insulating layer 17 and at least one (plurality in the illustrated example) dummy layer 21 (the reference numerals cover FIG. 3 ) overlapping the insulating layer 17. Each dummy layer 21 has, for example, four dummy electrodes 19 as shown in FIG. 2 . The dummy electrodes 19 contribute to, for example, reinforcing the cover 15 and / or improving the connection strength between the main body 3 and the external terminals 5. Unlike the illustrated example, the cover 15 may have only one or more insulating layers 17 (it may not have the dummy layer 21).

[0044] The insulating layers 17 and the dummy layers 21 are alternately stacked one on top of the other. In other words, the dummy layers 21 are provided at the boundaries of all the insulating layers 17. Unlike the illustrated example, the dummy layers 21 may be provided only at some of the boundaries. For example, the dummy layers 21 may not be provided at one or more boundaries relatively close to the functional section 13, and the dummy layers 21 may be provided only at one or more boundaries relatively far from the functional section 13. In such a case, however, two or more insulating layers 17 that are in close contact with each other without a dummy layer 21 interposed therebetween may be regarded as a single insulating layer 17.

[0045] (3.2. Insulating Layer) The insulating layer 17 is a layer having a substantially constant thickness, excluding variations in thickness resulting from the presence or absence of overlap with the conductor layers (9, 11, and 19). The planar shape of the insulating layer 17 is, for example, the same as the planar shape of the dielectric layer 7. The material of the insulating layer 17 is arbitrary. For example, the material of the insulating layer 17 may be the same as or different from the material of the dielectric layer 7. Furthermore, the material of the insulating layer 17 may be, for example, ceramics or a material other than ceramics.

[0046] The thickness of the insulating layer 17 is arbitrary. For example, the thickness of the insulating layer 17 may be thicker (in the illustrated example), equal to, or thinner than the thickness of the dielectric layer 7 (both of which are thicknesses between conductor layers or thicknesses of regions not overlapping with conductor layers; the same applies hereinafter in this paragraph). For example, the thickness of the insulating layer 17 may be two or more times, five or more times, or ten or more times the thickness of the dielectric layer 7, and may be 5 μm or more and 20 μm or less.

[0047] 3, the top layer of the functional section 13 is a conductor layer including electrodes 9 and wiring 11. The top electrode 9 is covered by the bottom insulating layer 17 of the upper cover 15. However, as long as the top electrode 9 and the dummy electrode 19 of the upper cover 15 are insulated from each other, the configuration at the boundary may be different from that shown in the example.

[0048] For example, the top layer of the functional section 13 may be the dielectric layer 7. The top dielectric layer 7 may overlap the bottom insulating layer 17 of the upper cover 15, or the top dielectric layer 7 may overlap the bottom dummy electrode 19. Furthermore, all of the dielectric layers 7 and all of the insulating layers 17 do not need to be distinguishable from each other in terms of their materials, thicknesses, etc.

[0049] In either embodiment, however, the material between the electrodes 9 functions as a dielectric for increasing capacitance. Also, the material between the uppermost of the plurality of electrodes 9 and the lowermost of the plurality of dummy electrodes 19 of the upper cover 15 functions as an insulating layer for insulating them. From this perspective, the insulating layer between the uppermost of the plurality of electrodes 9 and the lowermost of the plurality of dummy electrodes 19 may be considered as the insulating layer 17 of the cover 15, regardless of whether it has the same configuration as the dielectric layer 7 between the electrodes 9 or the insulating layer 17 between the dummy layers 21, or whether it is a combination of the previous two layers.

[0050] Although the upper cover 15 is taken as an example, the same applies to the lower cover 15. However, the terms "top layer" and "bottom layer" are interchangeable.

[0051] (3.3. Dummy Electrode) The dummy electrode 19 (in other words, the dummy layer 21) is, for example, a layer having a certain thickness. The material of the dummy electrode 19 is, for example, a metal. The specific type of metal is arbitrary, and is, for example, a base metal (e.g., Ni and Cu). The material of the dummy electrode 19 may be the same as or different from the material of the electrode 9 (and the wiring 11).

[0052] In a plan view, the position, shape, and size of the dummy electrodes 19 are arbitrary. In the example of FIG. 2 , the dummy electrodes 19 are located at the four corners of the dielectric layer 7 in a planar perspective view. From another perspective, the positions of the dummy electrodes 19 correspond to the positions of the external terminals 5. Furthermore, the planar shape of the dummy electrodes 19 is rectangular (more specifically, square). The lengths of the four sides of the dummy electrodes 19 are the same as the length L1 of the wiring 11 on the first side 7a described above. In other words, the lengths of the wiring 11 and the dummy electrodes 19 are the same on each side of the dielectric layer 7. Furthermore, the size of the dummy electrodes 19 in a plan view is approximately the same as the size of the external terminals 5 in a plan view.

[0053] The dummy electrode 19 may overlap the electrode 9 in a planar perspective view (in the illustrated example, it overlaps a corner of the electrode 9), or may not overlap. In the latter case, the dummy electrode 19 may be formed, for example, in an L-shape along a corner (two intersecting sides) of the dielectric layer 7. When the dummy electrode 19 overlaps the electrode 9, for example, a large area of ​​the dummy electrode 19 is ensured, thereby improving the effect of improving strength provided by the dummy electrode 19. When the dummy electrode 19 does not overlap the electrode 9, for example, the electrical influence of the dummy electrode 19 on the electrode 9 is reduced.

[0054] The dummy electrodes 19 are exposed, for example, on the side surfaces of the main body 3. These exposed portions are joined to the external terminals 5. As a result, the dummy electrodes 19 contribute to improving the connection strength between the main body 3 and the external terminals 5. Unlike the example shown in the figure, the dummy electrodes 19 do not have to be connected to the external terminals 5. For example, the dummy electrodes 19 may be provided so as not to be exposed from the side surfaces of the main body 3, and may contribute to improving the strength of the main body 3 without contributing to improving the connection strength with the external terminals 5.

[0055] The thickness of the dummy electrode 19 is arbitrary. For example, the thickness of the dummy electrode 19 may be thicker than, equal to, or thinner than the thickness of the electrode 9 (as in the illustrated example). For example, the thickness of the dummy electrode 19 may be two or more times, five or more times, or ten or more times the thickness of the electrode 9. Furthermore, the thickness of the dummy electrode 19 may be thinner than, equal to, or thicker than the thickness of the insulating layer 17 (as in the illustrated example).

[0056] 3, a dummy layer 21 is provided on the top layer of the upper cover 15. The four dummy electrodes 19 are covered by the external terminals 5. Unlike the illustrated example, the dummy layer 21 does not necessarily have to be provided on the top layer of the upper cover 15.

[0057] As described above, the layered (film-like) component may be composed of two or more layers. The external terminal 5 may also be composed of two or more layers. In this case, the lower layer of the external terminal 5 and the uppermost dummy electrode 19 may or may not be distinguishable from the viewpoint of thickness and / or material. Therefore, the presence or absence of the dummy electrode 19 may be determined by the presence or absence of the dummy electrode 19 covered by the insulating layer 17 from the side opposite to the functional portion 13 (dielectric layer 7).

[0058] In the illustrated example, the four dummy electrodes 19 overlap the electrodes 9 in a planar perspective view, and the four dummy electrodes 19 are connected to external terminals 5 at different potentials. Therefore, the dummy layer 21 and the conductive layer including the electrodes 9 need to be separated by the dielectric layer 7 and / or the insulating layer 17. However, this does not apply in cases where some or all of the four dummy electrodes 19 do not overlap the electrodes 9 in a planar perspective view, or where some or all of the four dummy electrodes 19 are not connected to the external terminals 5.

[0059] (4. External Terminals) The external terminals 5 shown in FIG. 1 are, for example, generally layered and cover the four surfaces (top, bottom, and two side surfaces) of the main body 3 at the four corners of the main body 3 in a plan view. This allows the external terminals 5 to be connected to the wiring 11 on the two side surfaces of the main body 3, and also allows the capacitor 1 to be surface-mounted on either the top or bottom surface. Note that, ignoring the reduction in practicality, the external terminals 5 may cover only two surfaces (a combination of the top or bottom surface and one side surface). Unlike the illustrated example, in an embodiment in which two external terminals 5 are provided on both ends of the main body 3, the external terminals 5 may cover all five surfaces at both ends. In an embodiment in which a lead wire is connected to the external terminals 5, the external terminals 5 may only cover at least one side surface.

[0060] The shape, dimensions, and material of the portions on each surface of the external terminal 5 are arbitrary. As described above, the planar shape and dimensions of the portion of the external terminal 5 located on the upper or lower surface of the main body 3 are generally the same as those of the dummy electrode 19 (e.g., square). Therefore, the description of the planar shape and dimensions of the dummy electrode 19 may be applied to the above-mentioned portion of the external terminal 5. Furthermore, the planar shape and dimensions of the portion of the external terminal 5 located on the side surface of the main body 3 are rectangular with the same lateral length as the portion located on the upper or lower surface. The thickness of the external terminal 5 (film) may be, for example, thicker than the thickness of the electrode 9 and the dummy electrode 19. The material of the external terminal 5 may be, for example, an Ag or Cu layer plated with Ni and Sn.

[0061] 4, attention will be focused on the external terminal 5 (hereinafter referred to as the "first external terminal 5A") located on the +D2 side of the first side 7a. As will be understood from the above description, the end of the first edge portion 11Aa on the first side 7a side and the end of the first external terminal 5A on the -D2 side are located at approximately the same position in the D2 direction. The above-mentioned ends being located at approximately the same position may be defined as, for example, when the positional deviation of the above-mentioned ends is small as follows.

[0062] The distance parallel to the first side 7a between the end of the first edge 11Aa on the first electrode 9A side and the end of the first edge 11Aa on the first side 7a side is defined as d1. In this case, the distance between the end of the first edge 11Aa on the first side 7a side and the end of the first external terminal 5A on the −D2 side along the first side 7a may be less than ½, less than ⅕, or less than 1 / 10 of the distance d1 (approximately 0 in the illustrated example).

[0063] As can be understood from the above description, the specific value of the distance d1 is arbitrary. For example, the distance d1 may be 0.2 or less, 0.1 or less, or 0.08 or less relative to the length of the first side 7a. And / or, in an aspect in which the capacitor 1 is relatively small, the distance d1 may be 100 μm or less or 50 μm or less.

[0064] And / or, instead of or in addition to the range of comparison with the distance d1, the distance between the ends may be within a predetermined absolute range, for example, in a relatively small capacitor 1, the distance between the ends may be less than 20 μm, less than 10 μm, or less than 5 μm.

[0065] The above-mentioned range of distance between the ends may be allowed only on the +D2 side with respect to the -D2 side end of the first external terminal 5A (i.e., it may be required that the first edge portion 11Aa be connected to the first external terminal 5A), or it may be allowed on both the +D2 side and the -D2 side.

[0066] As can be seen from FIG. 4 , the side surface of the film constituting the first external terminal 5A is not necessarily perpendicular to the first edge 7a. That is, the position of the end of the first external terminal 5A in the direction D2 may differ between the inner surface (i.e., the surface connected to the wiring 11) and the outer surface of the first external terminal 5A. If such a difference in position becomes an issue when determining whether the distance between the first edge 11Aa and the first external terminal 5A falls within the above-mentioned range, the position of the end of the inner surface may be used as the reference. Of course, if there is no impact on the determination, there is no need to distinguish between the inner surface and the outer surface of the external terminal 5A.

[0067] Although the first edge portion 11Aa and the first external terminal 5A are used as an example, the same applies to the second edge portion 11Ba and the external terminal 5 connected to the second edge portion 11Ba (sometimes referred to as the "second external terminal 5B").

[0068] (5. Manufacturing Method of Capacitor) The manufacturing method of the capacitor 1 may be various methods, for example, it may be the same as a known method. An example is shown below.

[0069] First, ceramic green sheets that will become the dielectric layers 7 and the insulating layers 17 are prepared. Next, a conductive paste that will become the conductor layers including the electrodes 9 or the dummy layers 21 is applied to the ceramic green sheets. Next, the ceramic green sheets are stacked to prepare a laminate that will become the main body 3.

[0070] The above-described steps up to the fabrication of the laminate are carried out, for example, on a mother substrate of the size from which a large number of main body portions 3 are obtained. The arrangement of the main body portions 3 on the mother substrate is arbitrary. For example, the main body portions 3 are arranged vertically and horizontally parallel to the D1 direction and the D2 direction. In this case, the portions of the wiring 11 located on the sides of the dielectric layer 7 of adjacent main body portions 3 may be connected to each other.

[0071] After the laminate is produced, the mother substrate including the laminate is divided (e.g., cut) into pieces having a size roughly corresponding to the size of the main body 3. Next, the laminate having the size of the main body 3 is fired. Before and / or after firing the laminate, polishing (e.g., barrel polishing) of the side surfaces of the main body 3 may be performed. Thereafter, a metal film is formed on the main body 3, and the external terminals 5 are formed.

[0072] (6. Effects of Wiring Inclination) (6.1. Principle) FIG. 5 is a schematic diagram for explaining the principle of the effects of inclining the first edge portion 11Aa and the second edge portion 11Ba. In FIG. 5, the upper and lower diagrams correspond to FIG. 4 with the external terminals 5 omitted. The upper diagram shows a capacitor 101 according to a comparative example. The lower diagram shows a capacitor 1 according to the embodiment.

[0073] In the capacitor 101, the wiring 111 (first wiring 111A and second wiring 111B) has a square shape with corners overlapping the electrode 9. That is, the edges of the wiring 111 (first edge 111Aa and second edge 111Ba) are perpendicular to the first side 7a. In the capacitor 101, a current path from the first wiring 111A to the second wiring 111B runs along the first edge 111Aa and the second edge 111Ba, as indicated by arrow a1. The shape of this path resembles three sides of a rectangle, since the first edge 111Aa and the second edge 111Ba are perpendicular to the first side 7a.

[0074] On the other hand, in capacitor 1, the first edge 11Aa and the second edge 11Ba are inclined. As a result, the current path corresponding to the current path indicated by arrow a1 in capacitor 101 has a shape resembling two legs and an upper base of a trapezoid, as indicated by arrow a3. Here, for example, assume that the length L1 at which wiring 11 or 111 contacts first side 7a is the same. In this case, the path indicated by arrow a3 is shorter than the path indicated by arrow a1. As a result, the equivalent series inductance of capacitor 1 is reduced compared to capacitor 101.

[0075] Furthermore, for example, variations in the equivalent series inductance and / or the equivalent series resistance can be reduced depending on the manufacturing method of the capacitor 1. Specifically, this is as follows.

[0076] In the capacitor 101, as shown in region R1, the edges of the electrode 9 and the wiring 111 are perpendicular to each other. That is, the conductor layer including the electrode 9 and the wiring 111 has a 90° concave corner. In such a region, the corners are likely to be rounded, resulting in errors from the intended shape. This in turn leads to errors in the length of the current path along these edges. As a result, the equivalent series inductance and / or equivalent series resistance are likely to vary.

[0077] On the other hand, in capacitor 1, as shown in region R3, the edge of electrode 9 and the edge of wiring 11 form a concave corner at an angle greater than 90°. Therefore, compared to region R1, errors such as rounded corners are less likely to occur. As a result, the equivalent series inductance and / or equivalent series resistance are less likely to vary.

[0078] As described above, the main body portion 3 may be produced by dividing the mother substrate into individual pieces, and on the mother substrate, adjacent main body portions 3 may be connected to each other at the portions of the wiring 11 that are located on the sides of the dielectric layer 7. In this case, as shown in regions R5 and R7, the edges of adjacent wirings 111 or adjacent wirings 11 are connected to each other. The angle of the concave corners is smaller in region R7 than in region R5, making it more likely that errors in the rounding of the corners will occur.

[0079] However, the portion where such an error occurs is removed as a waste margin during singulation and / or removed during polishing, thereby reducing the effect of region R7 on the variations in equivalent series inductance and / or equivalent series resistance.

[0080] 6.2. Examples Fig. 6 is a table showing the characteristics of capacitors according to examples and comparative examples. This diagram shows, for example, that the above-mentioned effects are achieved.

[0081] In this figure, "No." is an identification number assigned to the sample. "θ (°)" is the inclination angle of the edge of the wiring 11 (or 111) with respect to the side of the dielectric layer 7 (see FIG. 4). "ESL (pH)" is the value of the equivalent series inductance. "CV_ESL (%)" is the coefficient of variation (standard deviation of ESL / average value of ESL) indicating the variation in equivalent series inductance (ELS). "CV_ESR (%)" is the coefficient of variation (standard deviation of ESR / average value of ESR) indicating the variation in equivalent series resistance (ESR).

[0082] As shown in "No.", six types of prototypes were produced with inclination angles θ ranging from 18° to 90°. θ = 90° is a comparative example, and the others are examples. For each type, multiple prototypes were produced, and the ESL and ESR were measured. The ESL value shown in Figure 6 is the average value of multiple prototypes.

[0083] The dimensions of the examples and comparative examples are as follows: Length of one side of the dielectric layer 7: 590 μm Distance between one side of the parallel electrodes 9 and one side of the dielectric layer 7: 40 μm Length L1 ( FIG. 4 ): 175 μm Thickness of the dielectric layer 7: 1 μm Number of laminated dielectric layers 7: 20

[0084] 6, the more the edge of the wiring 11 is inclined, the smaller the ESL becomes, and it has been confirmed that this provides the effects described with reference to arrows a1 and a3 in FIG.

[0085] Furthermore, the CV of ESL is smallest when θ is 45° and increases as θ becomes smaller or larger than 45°. The same is true for the CV of ESR. This is thought to be because, as θ decreases from 90° to 45°, the shape errors of the corners of regions R1 and R3 in Figure 5 decrease, while as θ decreases from 45° to 18°, the shape errors of the corners of regions R5 and R7 in Figure 5 increase.

[0086] The CV of ESL is kept at 4% or less when θ is in the range of 30° or more and 60° or less (from another perspective, within a range of 60°-30°=30°). In contrast, when θ is 12° or 20° away from the above range (θ=12° or 80°), the CV of ESL is more than doubled to 10%. For this reason, the range of θ may be selected to be 30° or more and 60° or less. Furthermore, a narrower range of 40° or more and 50° or less may be selected.

[0087] The same can be said about the CV of ESR. That is, when θ is in the range of 30° or more and 60° or less, the CV of ESR is 3% or less. In contrast, when θ is 12° or 20° away from the above range (θ = 12° or 80°), the CV of ESR is more than double, at 11% or 8%. For this reason, the range of the inclination angle may be selected to be 30° or more and 60° or less. Furthermore, a narrower range of 40° or more and 50° or less may be selected.

[0088] However, even in the examples where θ is outside the range of 30° to 60° (θ = 18° or 80°), the ESL CV and ESR CV are smaller than those of the comparative example (θ = 90°). Furthermore, from the perspective of reducing the ESL value, it is sufficient for θ to be somewhat smaller than 90°, and the smaller the better. Therefore, the range of θ is not limited to the above range.

[0089] (7. Summary of the Embodiment) As described above, the capacitor 1 includes a dielectric layer 7, a first electrode 9A, a second electrode 9B, a first wiring 11A, and a second wiring 11B. The dielectric layer 7 has a rectangular shape including a first side 7a extending from a first side (+D2 side) to a second side (-D2 side). The first electrode 9A and the second electrode 9B face each other across the dielectric layer 7 in the thickness direction, and each has a rectangular shape with four sides parallel to the four sides of the dielectric layer 7. The first wiring 11A extends from the first electrode 9A to the end of the first side 7a on the +D2 side. The second wiring 11B extends from the second electrode 9B to the end of the first side 7a on the -D2 side. A first edge 11Aa on the -D2 side of the first wiring 11A is inclined with respect to the first side 7a in a first direction that is closer to the first electrode 9A and is positioned closer to the -D2 side. A second edge 11Ba on the +D2 side of the second wiring 11B is inclined with respect to the first side 7a in a second direction that is positioned closer to the +D2 side as it approaches the second electrode 9B.

[0090] Therefore, as described above, for example, ESL can be reduced. Also, by making the angle of the concave corner formed by the electrode 9 and the wiring 11 (see region R3 in FIG. 5 ) greater than 90°, the likelihood of errors occurring in the shape of the corner being rounded can be reduced. As a result, for example, variations in ESL and ESR can be reduced.

[0091] The first edge 11Aa may be inclined in the first direction from the first electrode 9A to the first side 7a. Similarly, the second edge 11Ba may be inclined in the second direction from the second electrode 9B to the first side 7a.

[0092] In this case, for example, assuming that the positions of both ends of the first edge portion 11Aa are constant, the distance between the both ends can be shorter than in a configuration in which a portion of the first edge portion 11Aa is not inclined toward the first side 7a (this configuration may also be included in the technology related to the present disclosure). As a result, the effect of reducing ESL is improved. The same applies to the second edge portion 11Ba. Note that, from the perspective of reducing the CV of ESL and the CV of ESR, the portion of the first edge portion 11Aa that extends to the first side 7a does not need to be inclined toward the first side 7a.

[0093] The first edge 11Aa may be linear from the first electrode 9A to the first side 7a, and the second edge 11Ba may be linear from the second electrode 9B to the first side 7a.

[0094] In this case, for example, assuming that the positions of both ends of the first edge portion 11Aa are constant, the both ends can be connected over the shortest distance compared to an embodiment in which the first edge portion 11Aa is curved (this embodiment may also be included in the technology related to the present disclosure). As a result, the effect of reducing ESL is improved. The same applies to the second edge portion 11Ba. Note that, from the perspective of reducing the CV of ESL and the CV of ESR, the first edge portion 11Aa may be curved so that the θ of the portion connected to the electrode 9 is relatively small and the θ of the portion reaching the first side 7a is relatively large.

[0095] The capacitor 1 may further include a first external terminal 5A and a second external terminal 5B. The first external terminal 5A may be connected to the first wiring 11A at an end on the first side (+D2) of the first edge 7a, covering the side surface of the dielectric layer 7. The second external terminal 5B may be connected to the second wiring 11B at an end on the second side (-D2) of the first edge 7a, covering the side surface of the dielectric layer 7. The distance parallel to the first edge 7a between the end of the first edge 11Aa on the first electrode 9A side and the end of the first edge 11Aa on the first side 7a side is defined as a first distance (distance d1). In this case, the distance between the end of the first edge 11Aa on the first side 7a side and the end of the first external terminal 5A on the -D2 side of the portion along the first side 7a may be less than half the first distance. Similarly, the distance parallel to the first side 7a between the end of the second edge 11Ba on the second electrode 9B side and the end of the second edge 11Ba on the first side 7a side is defined as a second distance (distance d1). In this case, the distance between the end of the second edge 11Ba on the first side 7a side and the end of the second external terminal 5B on the +D2 side of the portion along the first side 7a may be less than half the second distance.

[0096] In this case, the contact area between the first wiring 11A and the first external terminal 5A is larger than in a configuration in which the end of the first edge 11Aa on the first side 7a side is separated from the end of the first external terminal 5A on the −D2 side by a distance d1 or more on the +D2 side by a distance d1 or more (referred to as an “another configuration” in this paragraph; this other configuration may also be included in the technology according to the present disclosure). This increases the bonding strength. Furthermore, assuming that the connection position of the first edge 11Aa to the electrode 9 is constant, the first edge 11Aa is shorter than in the other configuration. As a result, the effect of reducing ESL is improved. Furthermore, because the first wiring 11A does not protrude from the first external terminal 5A toward the −D2 side, or the protrusion amount is small, the likelihood of an unintended short circuit occurring due to a conductive bonding material bonded to the external terminal 5A is reduced.

[0097] The angle (tilt angle θ) that the first edge 11Aa makes with respect to the first side 7a from the first electrode 9A to the first side 7a may be 30° or more and 60° or less. Similarly, the angle (tilt angle θ) that the second edge 11Ba makes with respect to the first side 7a from the second electrode 9B to the first side 7a may be 30° or more and 60° or less.

[0098] In this case, as described with reference to FIG. 6, the CV of the ESL and the CV of the ESR can be reduced.

[0099] An edge (reference numeral omitted) of the first wiring 11A opposite the first edge 11Aa may be parallel to the first edge 11Aa. An edge (reference numeral omitted) of the second wiring 11B opposite the second edge 11Ba may be parallel to the second edge 11Ba. That is, the first wiring 11A and the second wiring 11B may extend with a constant width.

[0100] In this case, for example, the current paths along the two edges on both sides of the wiring 11 can be made uniform and linear, thereby reducing the likelihood of fluctuations in characteristics due to unintended current disturbances, for example.

[0101] The capacitor 1 may further include four dummy electrodes 19 located at the four corners of the dielectric layer 7 in a planar perspective view, and an insulating layer 17 overlapping the four dummy electrodes 19 from the side opposite the dielectric layer 7. In other words, the dummy electrodes 19 may be provided inside the cover 15.

[0102] In this case, for example, the cover 15 can be reinforced with dummy electrodes 19. The four corners of the main body 3 are areas that are prone to external force. Examples of external force include a force caused by the capacitor 1 coming into contact with another component before the capacitor 1 is mounted, and a force that the capacitor 1 receives from another component (e.g., a circuit board) via a bonding material after the capacitor 1 is mounted. By reinforcing the areas prone to force with the dummy electrodes 19, the main body 3 is efficiently reinforced. From another perspective, the overlap between the dummy electrodes 19 and the electrodes 9 is reduced in planar perspective view, thereby reducing the electrical influence of the dummy electrodes 19 on the electrodes 9.

[0103] The capacitor 1 may further have four external terminals 5 that overlap the side surfaces of the dielectric layer 7 at the four corners of the dielectric layer 7 and are joined to the four dummy electrodes 19 .

[0104] In this case, for example, the dummy electrodes 19 contribute not only to improving the strength of the four corners of the main body 3 but also to improving the bonding strength between the main body 3 and the external terminals 5. This in turn reduces the likelihood that the external terminals 5 and the wiring 11 will become separated, improving electrical reliability.

[0105] The insulating layer 17 may be thicker than the dielectric layer 7. And / or the dummy electrode 19 may be thicker than the first electrode 9A and the second electrode 9B. And / or the capacitor 1 may have a plurality of dummy layers 21 and a plurality of insulating layers 17, with the dummy layers 21 including four dummy electrodes 19 and the insulating layers 17 being alternately stacked.

[0106] In either case, the dummy electrodes 19 have the effect of improving strength and the like.

[0107] The technology according to the present disclosure is not limited to the above-described embodiments and may be implemented in various forms.

[0108] The capacitor may be part of a multi-functional electronic component. For example, in Fig. 4, the position and size of the electrode 9 may remain the same as in the illustrated example, but the dielectric layer 7 may be longer on the +D1 side than in the illustrated example, the two wirings 11 on the +D1 side may be omitted, and another electronic element (e.g., an inductor) may be provided to be connected to the external terminal 5 on the +D1 side. Alternatively, for example, the other electronic element may be provided at a position separate from the functional unit 13 in the D3 direction.

[0109] From the present disclosure, a concept may be extracted that does not require the edges of the wiring 11 to be inclined toward the sides of the dielectric layer 7. For example, a concept may be extracted that requires dummy electrodes 19 to be provided at the four corners, that the insulating layer 17 to be thicker than the dielectric layer 7, and / or that the dummy electrodes 19 to be thicker than the electrodes 9. In these cases, for example, the effect of shortening the current path indicated by arrow a3 ( FIG. 5 ) may not be achieved. Therefore, electrodes 9 at different potentials do not need to face each other. For example, two electrodes connected to external terminals at different potentials may be provided in different regions of the same layer, and an electrode facing both of the two electrodes and not connected to an external terminal may be provided. That is, two (or three or more) parallel plate capacitors connected in series may be included in the chip.

[0110] 1...capacitor, 7...dielectric layer, 7a...first side, 9A...first electrode, 9B...second electrode, 11A...first wiring, 11B...second wiring, 11Aa...first edge, 11Ba...second edge.

Claims

1. A capacitor comprising: a rectangular dielectric layer including a first side extending from a first side to a second side; rectangular first and second electrodes opposing each other across the dielectric layer in the thickness direction, each having four sides parallel to the four sides of the dielectric layer; a first wiring extending from the first electrode to an end of the first side of the first side; and a second wiring extending from the second electrode to an end of the first side of the first side, wherein a first edge of the first wiring on the second side is inclined with respect to the first side in a first orientation located on the second side as it approaches the first electrode, and a second edge of the first side of the second wiring is inclined with respect to the first side in a second orientation located on the first side as it approaches the second electrode.

2. The capacitor according to claim 1, wherein the first edge is inclined in the first direction from the first electrode to the first side, and the second edge is inclined in the second direction from the second electrode to the first side.

3. The capacitor according to claim 2, wherein the first edge is linear from the first electrode to the first side, and the second edge is linear from the second electrode to the first side.

4. The capacitor according to any one of claims 1 to 3, further comprising: a first external terminal covering the side surface of the dielectric layer at an end on the first side of the first side and connected to the first wiring; and a second external terminal covering the side surface of the dielectric layer at an end on the second side of the first side and connected to the second wiring, wherein when a distance parallel to the first side between an end of the first edge portion on the first electrode side and an end of the first edge portion on the first side is defined as a first distance, a distance between an end of the first edge portion on the first side and an end of the first external terminal on the second side of the portion along the first side is less than 1 / 2 of the first distance, and when a distance parallel to the first side between an end of the second edge portion on the second electrode side and an end of the second edge portion on the first side is defined as a second distance, a distance between an end of the second edge portion on the first side and an end of the first side of the portion along the first side of the second external terminal is less than 1 / 2 of the second distance.

5. A capacitor as claimed in any one of claims 1 to 4, wherein an angle which the first edge portion forms with the first side is greater than or equal to 30° and less than or equal to 60° from the first electrode to the first side, and an angle which the second edge portion forms with the first side is greater than or equal to 30° and less than or equal to 60° from the second electrode to the first side.

6. A capacitor as described in claim 3 or claim 4 or 5 which directly or indirectly cites claim 3, wherein an edge of the first wiring opposite to the first edge is parallel to the first edge, and an edge of the second wiring opposite to the second edge is parallel to the second edge.

7. The capacitor according to any one of claims 1 to 6, further comprising: four dummy electrodes located at the four corners of the dielectric layer in a plan view; and an insulating layer overlapping the four dummy electrodes from the side opposite the dielectric layer.

8. The capacitor according to claim 7, further comprising four external terminals overlapping side surfaces of said dielectric layer at four corners of said dielectric layer and joined to said four dummy electrodes.

9. The capacitor according to claim 7 or 8, wherein the insulating layer is thicker than the dielectric layer.

10. The capacitor according to any one of claims 7 to 9, wherein the dummy electrode is thicker than the first electrode and the second electrode.

11. The capacitor according to any one of claims 7 to 10, comprising a plurality of dummy layers and a plurality of insulating layers, the dummy layers including the four dummy electrodes and the insulating layers being alternately stacked.

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