Quantum computer simulator having low latency and high scalability

Abstract

A quantum computer simulator having low latency and high scalability is provided. The quantum computer simulator according to an embodiment of the present invention comprises: a memory controller for reading state vectors included in a state group from an external memory; a re-ordering module for sorting the read state vectors in a designated order in the state group; an internal memory in which the state vectors sorted by the re-ordering module are stored; and PEs for performing a gate computation of a quantum circuit by using the state vectors stored in the internal memory, wherein the state group is a group in which pairs of state vectors are arranged in order, and a pair of state vectors are two input state vectors of a gate required for a computation of an output state vector of the gate in a PE. Therefore, even in a quantum circuit using a large number of qubits, burst read / write can be efficiently performed in an external memory such that latency in the external memory can be remarkably reduced, and thus quantum computation speed can very rapidly be improved.

Description

A quantum computer simulator with low latency and high scalability

[0001] This patent application is related to the development project for hardware / software convergence memory solution technology for convergence memory and high-speed computation engine control among the PIM AI semiconductor core technology development project of the Ministry of Trade, Industry and Energy in 2023, and the development project for quantum computing SoC architecture and S / W platform solution technology of the basic research project of the Korea Electronics Technology Institute in 2022.

[0002] The present invention relates to a simulator of a quantum circuit model, and more particularly, to a hardware structure capable of quickly performing simulation of a quantum circuit model on a classical computer.

[0003] Quantum computers are capable of solving existing NP-complete problems in polynomial time using various new algorithms, such as Shor's algorithm and Groover's algorithm. This technology can potentially break the RSA cryptosystem, which currently utilizes the properties of prime numbers. However, conducting research on actual quantum computers is limited by resources, so simulations on classical computers are essential for studying algorithms using quantum circuits.

[0004] To perform these simulations quickly, various methods for accelerating operations in FPGAs are being studied. However, due to the nature of quantum operations that do not perform sequential read / write, even if the hardware structure is well designed, the operation speed decreases due to latency in external memory.

[0005] Additionally, a hardware structure with scalability is essential for porting to hardware in various environments.

[0006] The present invention has been devised to solve the above problems, and the purpose of the present invention is to provide a quantum computer simulator that can efficiently perform burst read / write from an external memory even in a quantum circuit using a large number of qubits, and can easily increase or decrease the number of PEs (Processing Elements) without changing the control logic according to a given application / environment.

[0007] According to one embodiment of the present invention for achieving the above object, a quantum computer simulator includes: a memory controller for reading state vectors included in a state group from an external memory; a re-ordering module for sorting the read state vectors in an order specified in the state group; an internal memory for storing the state vectors sorted by the re-ordering module; and PEs (Processing Elements) for performing gate operations of a quantum circuit using the state vectors stored in the internal memory; wherein the state group is a group in which pair state vectors are listed in order, and the pair state vectors are input state vectors of two gates required for calculating the output state vector of the gate in the PE. The memory controller can perform burst reading of the state vectors from the external memory.

[0008] The state vectors stored in the internal memory are updated with the operation results by PEs, the reordering module sorts the updated state vectors in the internal memory into their original order, and the memory controller can burst write the sorted state vectors to the external memory.

[0009] The internal memory includes a plurality of memories, and the memory controller stores all state vectors in a first memory among the plurality of memories when the number of state vectors in a state group is less than or equal to the number of state vectors that can be stored in one memory, and the PEs can perform gate operations by using two consecutive state vectors in the first memory as a pair of state vectors.

[0010] When the number of state vectors in a state group exceeds the number of state vectors that can be stored in one memory, the memory controller can perform a burst read of some of the state vectors included in the state group from an external memory and store them in a first memory, and perform a burst read of the remaining state vectors included in the state group from an external memory and store them in a second memory.

[0011] Some of the state vectors may be the first state vectors among the pair state vectors, and the rest of the state vectors may be the second state vectors among the pair state vectors.

[0012] PEs can perform gate operations using a first state vector constituting a pair state vector stored in a first memory and a second state vector constituting a pair state vector stored in a second memory.

[0013] When a gate of a quantum circuit is applied to the Nth qubit, one group of states becomes 2 N A pair of state vectors can be included. The number of PEs and the number of internal memories are extensible.

[0014] A quantum computer simulation method according to another embodiment of the present invention includes a step in which a memory controller reads state vectors included in a state group from an external memory; a step in which a re-ordering module sorts the read state vectors in a specified order in the state group; a step in which an internal memory stores state vectors sorted by the re-ordering module; and a step in which PEs perform gate operations of a quantum circuit using the state vectors stored in the internal memory; wherein the state group is a group in which pair state vectors are listed in order, and the pair state vectors are input state vectors of two gates required for the operation of an output state vector of a gate in the PE.

[0015] According to another embodiment of the present invention, a quantum computer simulator comprises: a memory controller that reads state vectors included in a state group from an external memory; a re-ordering module that sorts the read state vectors in an order specified in the state group; an internal memory in which the state vectors sorted by the re-ordering module are stored and the state vectors are updated with the results of gate operations of a quantum circuit performed using the stored state vectors; wherein the re-ordering module sorts the updated state vectors in the internal memory into their original order, and the memory controller writes the sorted state vectors to an external memory; the state group is a group in which pair state vectors are listed in order, and the pair state vectors are input state vectors of two gates required for the operation of an output state vector of the gate.

[0016] A quantum computer simulation method according to another embodiment of the present invention includes: a step in which a memory controller reads state vectors included in a state group from an external memory; a step in which a re-ordering module arranges the read state vectors in a specified order in the state group; a step in which the state vectors arranged by the re-ordering module are stored in an internal memory; a step in which the state vectors in the internal memory are updated with gate operation results of a quantum circuit performed using the state vectors stored in the internal memory; a step in which the re-ordering module arranges the updated state vectors in the internal memory in their original order; and a step in which the memory controller writes the arranged state vectors to an external memory; wherein the state group is a group in which pair state vectors are listed in order, and the pair state vectors are input state vectors of two gates required for operation of an output state vector of the gate.

[0017] As described above, according to embodiments of the present invention, even in a quantum circuit using a large number of qubits, efficient burst read / write from an external memory is possible, thereby drastically reducing latency in the external memory, thereby greatly improving the quantum computation speed.

[0018] Additionally, according to embodiments of the present invention, the number of PEs can be easily increased or decreased without changing the control logic, thereby enabling quantum computer simulation without restrictions according to a given application / environment.

[0019] Figure 1 is a diagram illustrating a single qubit gate.

[0020] Figures 2 and 3 are diagrams illustrating pair state vectors.

[0021] FIG. 4 is a diagram illustrating the configuration of a quantum computing simulator according to one embodiment of the present invention;

[0022] FIG. 5 is a flowchart provided to explain a quantum computing operation method according to another embodiment of the present invention.

[0023] Hereinafter, the present invention will be described in more detail with reference to the drawings.

[0024] In an embodiment of the present invention, a method is proposed for quickly performing simulation of a quantum circuit model by designing a quantum circuit simulator running on a classical computer with a hardware structure capable of burst R / W for external memory and easily expanding the PE (Processing Element) without changing the control logic.

[0025] This technology improves the difficulty of efficient read / write when performing gate operations in quantum circuits because the state vectors required for the operations are stored at addresses far away in external memory, and improves the difficulty of securing scalability of hardware IP due to complex memory control.

[0026] Here, a classical computer is a computer commonly used today that performs bit (0 or 1)-based operations, and is a concept corresponding to a quantum computer that performs qubit-based operations.

[0027] In a quantum circuit consisting of N qubits, the state vector is 2 N ×1 can be expressed as a matrix, and each entry of the matrix represents the probability that the corresponding state will be measured. Figure 1 illustrates a qubit gate (U gate) configured in a quantum circuit with two qubits (q0, q1). When the state vector |A> is input to the qubit gate of the illustrated quantum circuit, the process of calculating and outputting the state vector |B> is as follows.

[0028]

[0029] The underlined vectors represent states that have changed from the input state. The final output state vector is as follows.

[0030]

[0031] According to this, it can be seen that in gate operations, the computation of the output state vector does not require all input state vectors. Specifically,

[0032] 1) Only the input state vectors a|00> and c|10> are required for the operation of the output state vector |00>,

[0033] 2) Only the input state vectors b|01> and d|11> are required for the operation of the output state vector |01>.

[0034] 3) The operation of the output state vector |10> requires only the input state vectors a|00> and c|10>,

[0035] 4) Only the input state vectors b|01> and d|11> are required to compute the output state vector |11>.

[0036] In an embodiment of the present invention, two input state vectors required for calculating an output state vector are defined as a pair state vector.

[0037] Assuming a quantum circuit with three qubits, if a gate is applied to the first qubit (q0), the state vectors that change the value of q0 become pair state vectors, and the four pair state vectors can be represented as in the table in Fig. 2. In addition, if a gate is applied to the second qubit (q1), the state vectors that change the value of q1 become pair state vectors, and the four pair state vectors can be represented as in the table in Fig. 3.

[0038] For a quantum circuit with N qubits, the pair state vectors can be generalized as follows.

[0039] 0) If the gate is applied to the first qubit (q0)

[0040] - Pair state vector

[0041] (|000>, |001>), (|010>, |011>), (|100>, |101>), ...

[0042] - The pair state vector can be simply expressed as an index as follows.

[0043] (0, 1), (2, 3), (4, 5), ...

[0044] - To enable burst read / write, pair state vectors are grouped into the smallest units and divided into state groups as follows. One state group [] contains 1(=2 0 ) contains pair state vectors.

[0045] [(0, 1)],

[0046] [(2, 3)],

[0047] [(4, 5)],

[0048] ...

[0049]

[0050] 1) When the gate is applied to the second qubit (q1)

[0051] - Pair state vector

[0052] (|000>, |010>), (|001>, |011>), (|100>, |110>), (|101>, |111>), ...

[0053] - The pair state vector can be simply expressed as an index as follows.

[0054] (0, 2), (1, 3), (4, 6), (5, 7), ...

[0055] - To enable burst read / write, pair state vectors are grouped into the smallest units and divided into state groups as follows. One state group [] contains 2 (=2 1 ) contains pair state vectors.

[0056] [(0, 2), (1, 3)],

[0057] [(4, 6), (5, 7)],

[0058] ...

[0059]

[0060] 2) When the gate is applied to the third qubit (q2)

[0061] - The pair state vector can be simply expressed as an index as follows.

[0062] (0, 4), (1, 5), (2, 6), (3, 7), ...

[0063] - To enable burst read / write, pair state vectors are grouped into the smallest units and divided into state groups as follows. One state group [] contains 4 (=2 2 ) contains pair state vectors.

[0064] [(0, 4), (1, 5), (2, 6), (3, 7)],

[0065] ...

[0066]

[0067] N) If the gate is applied to the Nth qubit (qN)

[0068] - The pair state vector can be simply expressed as an index as follows.

[0069] (0, 2 N ), (1, 2 N + 1), ..., (2 N - 1, 2 N + 2 N -1), (2 2N , 2 2N + 2 N ), (2 2N + 1, 2 2N + 2 N + 1), ..., (2 2N + 2 N - 1, 2 2N + 2 N + 2 N -1), ...

[0070] - To enable burst read / write, pair state vectors are grouped into the smallest units and divided into state groups as follows. One state group [] contains 2 N Contains a pair of state vectors.

[0071] [(0, 2 N ), (1, 2 N + 1), ..., (2 N - 1, 2 N + 2 N -1)],

[0072] [(2 2N , 2 2N + 2 N ), (2 2N + 1, 2 2N + 2 N + 1), ..., (2 2N + 2 N - 1, 2 2N + 2 N + 2 N -1)],

[0073] ...

[0074]

[0075] A method for performing quantum computing simulations by utilizing the concepts of pair state vectors and state groups presented above is described in detail below with reference to FIGS. 4 and 5.

[0076] FIG. 4 is a diagram illustrating the configuration of a quantum computing simulator according to an embodiment of the present invention. As illustrated, the quantum computing simulator (100) according to an embodiment of the present invention is configured to include a DMA controller (110), an SRAM set (120, 121), a re-ordering module (130), and a processing element (PE) 140.

[0077] The DMA controller (110) is configured to Burst Read / Write state vectors from external memory (10), and the SRAM sets (120, 121) are spaces where state vectors are temporarily stored.

[0078] The re-ordering module (130) is configured to align the order of state vectors, and the order alignment is performed when state vectors are moved from an external memory (10) to an SRAM set (120, 121) and when state vectors are moved from an SRAM set (120, 121) to an external memory (10).

[0079] PEs (140) perform gate operations using state vectors stored in the SRAM set (120, 121), specifically, pair state vectors.

[0080] The gate operation process by the proposed quantum computing simulator (100) will be described in detail below with reference to FIG. 5. FIG. 5 is a flowchart provided to explain a quantum computing operation method according to another embodiment of the present invention.

[0081] For gate operations, the re-ordering module (130) first checks the position of the qubit to which the gate of the quantum circuit is applied (S205), checks the state groups (S210), and checks the number of state vectors in the state groups (S215).

[0082] A state group is a set of paired state vectors that are the smallest unit capable of burst read / write. Since a paired state vector consists of two state vectors, the number of state vectors in a state group is twice the number of paired state vectors contained in the state group.

[0083] Specifically, when the gate of the quantum circuit to be operated is applied to the Nth qubit, the state group is 2 N Since it contains two pair state vectors, the state group has 2 N+1 The state vectors of the dog are included.

[0084] If the number of state vectors in a state group is less than or equal to the number of state vectors that can be stored in one SRAM (S220-Y), the re-ordering module (130) controls the DMA controller (110) to perform a burst read of the state vectors included in the state group from an external memory (10), and stores the burst read state vectors in the order specified in the state group in SRAM #0 (120) (S225).

[0085] The following PEs (140) perform gate operations using the state vectors stored in SRAM #0 (120) by step S225 (S230). In step S230, the gate operations are performed as follows.

[0086] 0) PE #0 performs gate operation using the first state vector and the second state vector, which are the first pair state vectors stored in SRAM #0 (120).

[0087] 1) PE #1 performs gate operations using the third state vector and the fourth state vector, which are the second pair state vectors stored in SRAM #0 (120).

[0088] 2) PE #2 performs gate operations using the fifth state vector and the sixth state vector, which are the third pair state vectors stored in SRAM #0 (120).

[0089] ....

[0090] The status vectors of SRAM #0 (120) are updated by the operation results in step S230 (S235), and the re-ordering module (130) controls the DMA controller (110) to Burst Write the updated status vectors of SRAM #0 (120) to the external memory (10) in the original order (S240).

[0091] Meanwhile, if the number of state vectors in a state group exceeds the number of state vectors that can be stored in one SRAM (S220-N), the re-ordering module (130) controls the DMA controller (110) to perform a burst read on some of the state vectors included in the state group and stores the burst read state vectors in SRAM #0 (120) in the order within the state group (S245), and then controls the DMA controller (110) to perform a burst read on the remaining state vectors in the current state group and stores the burst read states in SRAM #1 (121) in the order within the state group (S250).

[0092] Some of the state vectors that are burst read and stored in SRAM #0 (120) at step S245 are the first state vectors among the pair state vectors, and the rest of the state vectors that are burst read and stored in SRAM #1 (121) at step S250 are the second state vectors among the pair state vectors.

[0093] For example, if the state group is [(0, 2 N ), (1, 2 N + 1), ..., (2 N - 1, 2 N + 2 N -1)], some state vectors (the first state vectors among the pair state vectors) are 0, 1, ..., 2 N - 1, and the remaining state vectors (the second state vectors among the pair state vectors) are 2 N , 2 N + 1, ..., 2 N + 2 N It's -1.

[0094] The following PEs (140) perform gate operations using the state vectors stored in SRAM #0 (120) by step S245 and the state vectors stored in SRAM #1 (121) by step S250 (S255). In step S255, the gate operations are performed as follows.

[0095] 0) PE #0 performs a gate operation using the first state vector stored in SRAM #0 (120), which is the first pair state vector, and the first state vector stored in SRAM #1 (121).

[0096] 1) PE #1 performs gate operations using the second state vector stored in SRAM #0 (120), which is the second pair state vector, and the second state vector stored in SRAM #1 (121).

[0097] 2) PE #2 performs gate operations using the third state vector stored in SRAM #0 (120), which is the third pair state vector, and the third state vector stored in SRAM #1 (121).

[0098] ....

[0099] The state vectors of SRAM #0 (120) and SRAM #1 (121) are updated by the operation results in step S255 (S260), and the re-ordering module (130) controls the DMA controller (110) to Burst Write the updated state vectors of SRAM #0 (120) and the updated state vectors of SRAM #1 (121) to the external memory (10) in the original order (S265).

[0100] Steps S210 to S265 are repeated until all state groups are completed (S270). The gate operation procedure illustrated in FIG. 5 is then repeated until all gates constituting the quantum circuit are completed.

[0101] So far, we have described in detail a preferred embodiment of a quantum computer simulator with low latency by burst read / write.

[0102] In the quantum computer simulator presented in the above example, the number of PEs (140) can be expanded as needed. However, since there is a limit to the number of pins that can output to one clock of SRAMs (210, 211), the number of SRAMs must also increase as the number of PEs (140) increases, and no changes to the SRAM control logic are required.

[0103] In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and various modifications can be made by a person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present invention.

Claims

1. A memory controller that reads the state vectors included in the state group from external memory; A reordering module that sorts the read state vectors into a specified order in the state group; Internal memory where the state vectors sorted by the reordering module are stored; It includes PEs (Processing Elements) that perform gate operations of a quantum circuit using state vectors stored in internal memory; The status group is, A group in which pair state vectors are listed in order, The pair state vector is, A quantum computer simulator characterized by two gate input state vectors required for the computation of the output state vector of the gate in PE.

2. In claim 1, The memory controller is A quantum computer simulator characterized by burst reading of state vectors from external memory.

3. In claim 2, The state vectors stored in internal memory are Updated with the results of operations by PEs, The re-ordering module is Sort the updated state vectors in the internal memory in their original order, The memory controller is A quantum computer simulator characterized by burst writing of sorted state vectors to external memory.

4. In claim 1, Internal memory is, Contains multiple memories, The memory controller is If the number of state vectors in a state group is less than or equal to the number of state vectors that can be stored in one memory, store all state vectors in the first memory among the multiple memories, PEs, A quantum computer simulator characterized in that it performs gate operations by using two consecutive state vectors in the first memory as pair state vectors.

5. In claim 4, The memory controller is, A quantum computer simulator characterized in that, when the number of state vectors in a state group exceeds the number of state vectors that can be stored in one memory, some of the state vectors included in the state group are burst-read from an external memory and stored in a first memory, and the remaining state vectors included in the state group are burst-read from an external memory and stored in a second memory.

6. In claim 5, Some of the state vectors are, The first state vectors among the pair state vectors, The rest of the state vectors are, A quantum computer simulator characterized by the second state vectors among the pair state vectors.

7. In claim 6, PEs, A quantum computer simulator characterized in that a gate operation is performed using a first state vector constituting a pair state vector stored in a first memory and a second state vector constituting a pair state vector stored in a second memory.

8. In claim 1, When the gate of a quantum circuit is applied to the Nth qubit, 2 in one state group N A quantum computer simulator characterized by including a pair of state vectors.

9. In claim 1, The number of PEs and the number of internal memories are A quantum computer simulator featuring scalability.

10. A step in which the memory controller reads the state vectors included in the state group from external memory; A step in which the reordering module sorts the read state vectors in a specified order in the state group; A step in which the internal memory stores state vectors sorted by the re-ordering module; A step in which PEs (Processing Elements) perform gate operations of a quantum circuit using state vectors stored in internal memory; The status group is, A group in which pair state vectors are listed in order, The pair state vector is, A quantum computer simulation method characterized in that the input state vectors of two gates required for the calculation of the output state vector of the gate in PE.

11. A memory controller that reads the state vectors included in the state group from external memory; A reordering module that sorts the read state vectors into a specified order in the state group; An internal memory in which state vectors sorted by a re-ordering module are stored and the state vectors are updated with the results of gate operations of a quantum circuit performed using the stored state vectors; The re-ordering module is Sort the updated state vectors in the internal memory in their original order, The memory controller is, Write the sorted state vectors to external memory, The status group is, A group in which pair state vectors are listed in order, The pair state vector is, A quantum computer simulator characterized by two gate input state vectors required for the computation of the gate output state vector.

12. A step in which the memory controller reads the state vectors included in the state group from external memory; A step in which the reordering module sorts the read state vectors in a specified order in the state group; A step in which state vectors sorted by a reordering module are stored in internal memory; A step in which the state vectors of the internal memory are updated based on the results of gate operations of a quantum circuit performed using the state vectors stored in the internal memory; The re-ordering module sorts the updated state vectors in the internal memory into their original order; A memory controller includes a step of writing the sorted state vectors to an external memory; The status group is, A group in which pair state vectors are listed in order, The pair state vector is, A quantum computer simulation method characterized by having two input state vectors of gates required for the calculation of the output state vector of the gate.

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