EAS circuit and tag

Abstract

An EAS circuit is shown and described herein. The EAS circuit comprises a substrate with first and second electric conductive layers disposed on opposite sides of the substrate, one of the electric conductive layers comprising an inductive coil and a capacitor. The EAS circuit is configured to increase the magnetic flux through the center of the inductor coil and / or allow for providing an inductor coil with a larger coil area. The capacitor is located adjacent to the outer perimeter of the inductor coil. The capacitor may be foldable onto the first electric conductive layer or the second electric conductive layer to an area within the outer perimeter of the inductor coil.

Description

EAS CIRCUIT AND TAGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 524,042 entitled “EAS CIRCUIT AND TAG'’ filed on June 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.FIELD OF INVENTION

[0002] The present invention relates to an electronic article surveillance (EAS) circuit for an EAS tag or label. In particular, the present invention relates to an EAS circuit configured to reduce or eliminate obstruction to the path of the magnetic field flux.BACKGROUND

[0003] Resonance security tags are employed in electronic article surveillance (EAS) systems to detect unauthorized removal of articles from a location such as from a retail environment, warehouse area, etc. EAS circuits generally include a conductive material layer pattern, typically a coil pattem(forming an inductor) and a capacitor forming a resonance circuit having a suitable resonance frequency. The resonating frequency is ty pically tuned to a frequency band width center frequency of 8.2 MHz. Often, the capacitor is centrally located within the interior of the coil pattern (or within a perimeter of the tag or label), thereby hindering the available area for placing the coil pattern and obstructing the path of the magnetic field flux.SUMMARY

[0004] The following presents a summary of this disclosure to provide a basic understanding of some aspects. This summary is intended to neither identify key or critical elements nor define any limitations of embodiments or claims. Furthermore, this summary may provide a simplified ovendew of some aspects that may be described in greater detail in other portions of this disclosure.

[0005] The following description and the drawings disclose various illustrative aspects. Some improvements and novel aspects may be expressly identified, while others may be apparent from the description and drawings.

[0006] Provided is an EAS circuit having a coil inductor and a capacitor, where the circuit is configured to increase the magnetic flux through the center of the coil inductor.

[0007] In accordance with an embodiment, there is provided an electronic article surveillance (EAS) circuit comprising a substrate having a first side and a second side opposite the first side; a first layer disposed on the first side of the substrate, the first layer comprising a first coil inductor having an outermost coil section defining an outer perimeter of the coil inductor, and a first innermost coil section defining a first opening , and a first capacitor plate disposed adjacent to the coil inductor and extending outwardly beyond the outer perimeter of the coil inductor in a first state; and a second layer disposed on the second side of the substrate, the second layer comprising a second capacitor plate at least partially overlying the first capacitor plate, wherein the second layer is connected to the coil inductor via a first connector.

[0008] In an embodiment, the first and second capacitor plates are configured to be folded over and onto the second layer in a second state such that each of said first and second capacitor plates is at least partially disposed between the outer perimeter of the coil inductor and the opening.

[0009] In an embodiment, the second layer comprises a second coil inductor, and the second capacitor plate extends outwardly beyond the outer perimeter of the second coil inductor of the second layer in the first state.

[0010] In an embodiment, the second coil inductor comprises a second innermost coil section defining a second opening.

[0011] In an embodiment, a second connector extends from the second innermost coil section and toward the second opening, wherein the second connector is configured to connect to the first connector through the substrate.

[0012] In an embodiment, first and second capacitor plates are configured to be folded over and onto the first layer in a second state such that each of said first and second capacitor plates is at least partially disposed between the outer perimeter of the first coil inductor and the first opening.

[0013] In an embodiment, outer edges of the first and second capacitor plates are disposed inward relative to the outer perimeter of the first coil inductor.

[0014] In an embodiment, each the first lay erand the second layer defines a fold line disposed adjacent to the outer perimeter of the first coil inductor, said fold lines being disposed in a common plane.

[0015] In an embodiment, the first connector is disposed adjacent to the first innermost coil section.

[0016] In an embodiment, the EAS circuit further comprises a second connector extending inwardly toward a second opening.

[0017] In an embodiment, the second layer comprises a second coil inductor defining the second opening.

[0018] In an embodiment, the first connector and the second connector are configured to connect through the substrate.

[0019] In an embodiment, the substrate is a planar dielectric substrate.

[0020] In an embodiment, the first capacitor plate, the coil inductor, and the first connector are disposed on a first planar surface of the substrate.

[0021] In an embodiment, the second capacitor plate and the second connector are disposed on a second planar surface of the substrate opposite the first planar surface.

[0022] In an embodiment, a second connector is disposed adj acent to the innermost coil section, wherein the second connector is configured to at least partially overly the first connector to connect the first and second layers.

[0023] In an embodiment, the first layer is a first electrically conductive layer, and the second layer is a second electrically conductive layer.

[0024] In an embodiment, the first and second capacitor plates are configured to fold via a fold line.

[0025] In an embodiment, the fold line comprises a living hinge, a perforated section, or an area of reduced cross-sectional thickness.

[0026] In an embodiment, the first and second capacitor plates are configured to fold via a notch.

[0027] In an embodiment, the first capacitor plate is etched onto a first surface of the substrate, and the second capacitor plate is etched onto a second surface of the substrate opposite the first surface.

[0028] In an embodiment, the first connector comprises a conductive trace pad.

[0029] In an embodiment, the EAS circuit has a resonant frequency between about12 and 15 MHz.

[0030] In an embodiment, the EAS circuit has a resonant frequency in a range between about 7.7 to 9.5 MHz.

[0031] In accordance with another embodiment, an EAS label comprises a substrate with a first planar surface and a second planar surface opposite the first planar surface; and a first layer disposed on the first planar surface, and a second layer disposed on the second planar surface, wherein the first layer comprises a first capacitor plate and a first coil inductor, wherein the first coil inductor defines an opening extending between the first planarsurface and the second planar surface of the substrate, wherein the first capacitor plate is disposed adjacent to the first coil inductor and extends outwardly beyond an outermost perimeter of the EAS label.

[0032] In accordance with an embodiment, the first capacitor plate is configured to fold over and onto the second layer via a first fold line.

[0033] In accordance with an embodiment, the first fold line defines the outermost perimeter of the EAS label.

[0034] In accordance with an embodiment, the first fold line comprises a hinge or pivot.

[0035] In accordance with an embodiment, the first capacitor plate is configured to fold over and onto the second layer from an outer position toward an inner position.

[0036] In accordance with an embodiment, the inner position is located between about 160 and 190 degrees from the outer position.

[0037] In accordance with an embodiment, the second layer comprises a second capacitor plate at least partially overlying the first capacitor plate in a direction orthogonal to the first and second planar surfaces of the substrate.

[0038] In accordance with an embodiment, the second capacitor plate is configured to fold over and onto the first layer.

[0039] In accordance with an embodiment, the first and second capacitor plates are connected via a first connector and a second connector.

[0040] In accordance with an embodiment, the first connector is disposed in the first layer and adjacent to the opening, and the second connector extends from the second capacitor plate in a direction toward the opening such that the second connector at least partially overlies the first connector.

[0041] In accordance with an embodiment, the first and second capacitor plates are configured to fold via a notch

[0042] In an accordance with an embodiment, the notch extends into the outer perimeter of the first coil inductor or the second coil inductor.

[0043] In accordance with an embodiment, the first capacitor plate is etched onto the first planar surface of the substrate, and the second capacitor plate is etched onto the second planar surface of the substrate.

[0044] In accordance with an embodiment, the first layer is a first electrically conductive layer, and wherein the second layer is a second electrically conductive layer.

[0045] In accordance with an embodiment, the second layer comprises a second coil inductor and a connector, wherein the second coil inductor defines an opening, and wherein the connector extends from the second coil inductor toward the opening.

[0046] In accordance with an embodiment, the second layer comprises a second capacitor plate, wherein the second capacitor plate and the second coil inductor define a second fold line therebetw een.

[0047] In accordance with an embodiment, the first capacitor plate and the first coil inductor define a first fold line therebetween.

[0048] In accordance with an embodiment, the first and second capacitor plates are configured to fold onto the second layer via the first and second fold lines.

[0049] In accordance with an embodiment, the first and second capacitor plates are configured to fold onto the first layer via the first and second fold lines.BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings illustrate various systems, apparatuses, devices and related methods, in which like reference characters refer to like parts throughout, and in which:

[0051] FIG. 1 is a perspective view of an EAS circuit in accordance with an embodiment of the present technology;

[0052] FIG. 2 is a cross-section of the EAS circuit of FIG. 1;

[0053] FIG. 3 is a top view- of an EAS circuit in a first unfolded state;

[0054] FIG. 4 is a top view of the EAS circuit of FIG. 2 with a folded section; and

[0055] FIG. 5 is a perspective view of an EAS circuit .DETAILED DESCRIPTION

[0056] Reference will now be made to exemplary embodiments, examples of which are illustrated in the accompanying drawings. It is to be understood that other embodiments may be utilized and structural and functional changes may be made. Moreover, features of the various embodiments may be combined or altered. As such, the following description is presented by way of illustration only and should not limit in any way the various alternatives and modifications that may be made to the illustrated embodiments. In this disclosure, numerous specific details provide a thorough understanding of the subject disclosure. It should be understood that aspects of this disclosure may be practiced with other embodiments not necessarily including all aspects described herein, etc.

[0057] As used herein, the words “example” and “exemplary” means an instance, or illustration. The words “example” or “exemplary” do not indicate a key or preferred aspect or embodiment. The word “or” is intended to be inclusive rather than exclusive, unless context suggests otherwise. As an example, the phrase “A employs B or C.” includes any inclusive permutation (e.g., A employs B; A employs C; or A employs both B and C). As another matter, the articles “a” and “an” are generally intended to mean “one or more” unless context suggest otherwise.

[0058] Herein, the terms “substantially,” “about,” and variations thereof are intended to note that the described features are equal or approximately equal to a value as desired, for example, a value that is exact, within 10% of exact, or within 5% of exact, etc.

[0059] Provided is an EAS circuit for an EAS label. The EAS circuit comprises a coil inductor and a capacitor, where the circuit is configured to increase the magnetic flux through the center of the coil inductor and maximize the available area for placement of the coil inductor, maximizing the inductance performance thereof. The coil inductor and the capacitor are configured such that an interior region of the coil inductor is substantially unobstructed. In particular, the capacitor is disposed in a region adjacent the periphery of the coil inductor. The capacitor can be folded toward the center of the coil inductor such that an interior, center region of the coil inductor remains substantially open. By keeping the interior region of the coil inductor substantially open, the magnetic flux can penetrate through the coil inductor relatively unobstructed. This allows for higher rates of detection, and maintaining the resonance frequency. Additionally, a circuit in accordance with the present technology having the capacitor adjacent the outer perimeter of the coil inductor and foldable toward an interior area thereof allows for maximizing the area the coil inductor can occupy, and achieving maximum inductance for a given label size. It also allows for a design to maximize the interior region or window defined within the coil inductor.

[0060] FIGs. 1 and 2 show an EAS circuit 100 comprising a substrate layer 110 having an upper surface 112 and a lower surface 114, a first electrically conductive layer 120 disposed on the lower surface 114, and a second electrically conductive layer 130 disposed on the upper surface 112.

[0061] The first electrically conductive layer 120 comprises a coil inductor 122. The coil inductor 122 is defined by a multi-turn coil antenna defining a plurality of coil sections 122a- 122g. The coil inductor 122 has an outer periphery defined by the outermost coil section 122a and an interior region or opening 126 interior to coil section 122g. The first conductive layer 120 includes a first capacitor plate 129 extending from and adjacent the outermost coil section 122a. That is, the capacitor plate 129 forming the capacitor is disposedexterior to the outer perimeter of the coil inductor 122, i.e., in an un-folded or first state. In embodiments, the perimeter of the coil inductor 122 substantially corresponds to the perimeter of the EAS label (i.e., the distance covered by the side(s) thereof). In such embodiments, the first capacitor plate 129 may be disposed outside the perimeter of the E AS label, maximizing the available area on the EAS label for placing the coil inductor 122, thereby increasing the inductance performance thereof.

[0062] The first conductive layer 120 includes a connector 128 disposed in the interior region 126 of the coil inductor 122. The connector 128 is disposed away from the center of the interior region (or opening / window) 126. The connector 128 will connect the first electrically conductive layer 120 with the second electrically conductive layer 130. In embodiments, the connector 128 may comprise a conductive material.

[0063] The second conductive layer 130 includes a capacitor plate 132, which is disposed on the substrate 110 such that it overlies a portion of the capacitor plate 129 of the first conductive layer 120. The capacitor plate 132 of the second conductive layer 130 is disposed proximate to the outer periphery or perimeter of the of the coil inductor 122 such that some or all portions of the capacitor plate 132 are disposed outside the outer periphery of the coil inductor 122 (or EAS label), i.e., in the first / un-folded state (e g., such that there is no overlap with any coil). The capacitor plate 132 can be disposed such that it overlaps one or more of the coil sections defining the coil inductor 122.

[0064] The second conductive layer 130 includes a connector 134 extending from the capacitor plate 132. Connector 134 extends inwardly (toward the opening 126) to at least partially overly the connector 128 of the first conductive layer 120. respectively, to connect the first conductive layer 120 and the second conductive layer 130. The connector 134 may be connected to the connector 128 of the first conductive layer 120 by any suitable means including, for example, welding. In embodiments, the connector 128 may comprise a conductive material.

[0065] The capacitor plates 129 and 132 of the first and second conductive layers 120 and 103 (collectively forming part of the capacitor) and the substrate layer 110 may beconfigured to fold about a fold line L (FIG. 2), i.e., to a folded or second state. The capacitor plates 129 and 132 can be folded onto the first conductive layer 120 or onto the second conductive layer 130 (via the fold line L) in a direction towards the center of the coil inductor 122, thereby disposing the capacitor plates 129 and 132 in between an outer periphery’ of the coil inductor 122 (or EAS label) and the opening 126. In embodiments, the fold line L may embody a living hinge, a line or area of reduced thickness, a perforated line, and the like. In embodiments, each of the capacitor plates 129 and 132 and the substratelayer 110 may comprise or define a fold line, wherein the fold line is disposed in a common plane (e.g., a vertical plane). In embodiments, the substrate layer 120 may comprise a dieletric foil material or another suitable example of a malleable, dielectric material to allow the capacitor plates 129 and 132 (disposed on the substrate layer 120) to fold via the fold line L. Thus the present technology provides a resonant circuit structure that has a substantially open center region or window 126 such that the magnetic flux is free to pass through the coil inductor 122 with little or no obstruction. Additionally, the EAS circuit of the present technology, which places the capacitor (comprising the capacitor plates 129 and 132) at least partially or entirely outside the periphery or perimeter of the coil inductor 122 (and foldable toward the interior thereof) allows for maximizing the space (available placement area) the coil inductor 122 can occupy within a given EAS label footprint. Prior circuit designs, which arrange the capacitor plate 132 within an area of the EAS label footprint (e.g., in a comer area thereof) or in an area / region interior to the innermost coil of the inductor coil 122, undesirably block magnetic flux (from passing through the area / region interior) or reduce the available space for placing the coil inductor 122.

[0066] The capacitor plate 129 and the capacitor plate 132 can be folded in either direction, i.e., it can be folded onto the second conductive layer 130 side, or it can be folded onto the first conductive layer 120 side, increasing the arrangement possibilities based on the particular EAS label application as desired. FIG. 3 illustrates a top view of an example EAS circuit in the unfolded / first state (FIG. 3), wherein the capacitor plates 129 and 132 extend outwardly and away from the interior region or window 126 of the EAS circuit in the unfolded / first state. FIG. 4 illustrates a top view of the EAS circuit in the second / folded stated, where the capacitor plates 129 and 132 have been folded onto the second conductive layer 130 toward the surface 112 of the substrate layer, thereby disposing the capacitor plates 129 and 132 in between an outer periphery' 123 of the coil inductor 122 and the window or opening 126 /

[0067] The capacitor plates 129 and 132 adjacent the periphery of the outermost coil section 122a can be shaped or configured as may be desired for a particular purpose or intended application. It can be rectangular or otherwise angled or shaped such as, for example, triangular, trapezoid, curved, hemispherical, etc. The region 129' accommodating the capacitor plates 129 and 132 can optionally include other features that may facilitate folding the plates 129 and 132 onto the first or second conductive layers 120 and 130, for example, a living hinge, a fold line (comprising reduced thickness), a perforated line, and the like. FIGs. 3 and 4 show an EAS circuit 100’ that is generally similar to the circuit 100 except that the coil inductor 122’ includes coil sections 122a-122i. In the embodiment shownin FIGs. 3 and 4, the capacitor plate region 129’ includes notches 140a and 140b on each side of the capacitor plates, which may facilitate folding the capacitor plates onto the first or second conductive layers 120 and 130.

[0068] It will also be appreciated that the capacitor plate 129 and capacitor plate 132 can be configured to fold to provide an edge 141 (FIG. 4) that is flush or substantially flush with the edge 123 of the outer most coil section 122a on which the respective capacitor plate is disposed. In FIGs. 3 and 4, the capacitor plates 129 and 132 are configured such that when folded, the capacitor plate edges are recessed (in a direction toward the opening 126') relative to the edge 124 of coil inductor 122. It is also contemplated that the capacitor plate edges may be disposed at least partially outside the periphery of the edge 124 of the coil inductor 122.

[0069] The EAS circuit may be provided with one or more capacitor designs. At least one of the capacitor arrangements is configured to be folded. Regardless of the number of capacitor arrangements, the interior region of the coil antenna, and particularly the center most region, is substantially open and free of any obstructions.

[0070] By way of example only, the coil inductor 122, the capacitor plate 129, and the connector 128 may be etched on a surface of the substrate 110 whereby a multi-turn conductive trace, thereby forming the coil, terminates in a conductive trace pad which forms one plate of the connector 128.

[0071] The EAS circuit can be provided with a configuration to allow for deactivation of the capacitor. The configuration for deactivation can be designed to cause the capacitor to short out. The deactivation mechanism can be provided by a dimple (not shown). The dimple provides a shorter distance between the tip of the dimple and the opposing plate, than between the remaining surfaces of the tw o plates. When a high level of electromagnetic energy is applied to the tag, a voltage in excess of the breakdown voltage can be created between the tip of the dimple and the opposing plate. This causes the dielectric material to break down, thereby substantially short circuiting the tw o plates to each other. When the capacitor shorts out in the weakened area, its capacitance goes substantially to zero and the resonant frequency of the tag is moved out of the range of frequencies being swept by the detection equipment. The dimple can be configured such that the circuit and tag are permanently deactivated or such that they can be deactivated and optionally reactivated.

[0072] The substrate 110 may be constructed of any suitable solid material or composite structure of materials. Generally, the substrate is a dielectric layer and is constructed of a material such that the substrate is insulative and can be used as a dielectric.In some cases, the planar dielectric substrate 110 is formed of an insulated dielectric material, for example, a polymeric material such as polyethylene or polypropylene. However, it will be recognized by those skilled in the art that other dielectric materials may alternatively be employed in forming the planar dielectric substrate 110. Furthermore, the substrate may take on different shapes than those shown in FIGs. 1-4, for example, a substantially round substrate, a triangular substrate, or any other shape as desired based on the EAS label application.

[0073] On the opposite side of the planar dielectric substrate 110, another conductive trace pad may be etched to form the second capacitor plate, while an electrical connection is made through the planar dielectric substrate 110 from this second plate to the other end of the coil on the first side of the planar dielectric substrate 110. The non- conductive planar dielectric substrate 110 then acts as the dielectric between the two conductive trace pads to form the capacitor.

[0074] The EAS circuit can be formed by providing a first conductive layer defining an EAS coil antenna on a first surface of a substrate. The substrate is configured with a flap section adjacent an edge of the substrate to accommodate a corresponding capacitor plate of the EAS coil antenna extending from a periphery of an outermost coil section. A second conductive layer defining the capacitor plate and connecting member is then disposed on the second surface of the substrate. It will be appreciated that the order of forming the first and second conductive layers is not limited and can be done in any order or simultaneously.

[0075] The circuit can be provided to have a resonant frequency as desired for a particular purpose or intended application. In embodiments, the resonant frequency can be from about 5 to about 15 MHz. In embodiments, the resonant frequency is from about 7.7 to about 9.5 MHz. In one embodiment, the circuit can be tuned to a frequency in a range between about 12 and 15 MHz, for example, about 13.56 MHz for HF RFID applications.

[0076] Turning now to FIG. 5, another example of an EAS circuit 1000 is shown. The EAS circuit 1000 may include features similar to the features of the EAS circuit 100 discussed above. In the embodiment shown, the first conductive layer 1120 may include a first coil inductor 1122, and the second conductive layer 1130 may include a second coil inductor 1131. The second coil inductor 1131 may include a plurality of coil sections 1122a- 1122g (e.g., similar to 122a-122g in FIG. 1) defining a window or opening 1127. The first and second coil inductors 1122 and 1 131 may be disposed on opposing sides of a substrate 1110 sandwiched therebetween.

[0077] First and second capacitor plates 1129 and 1132 may be disposed adjacent outer peripheries of the first and second coil inductors 1122, 1131, respectively, and beconfigured to fold over in the same manner as disclosed above with respect to EAS circuit 110. A first connector 1128 may extend inwardly from the first coil inductor 1122. and a second connector 1134 may extend inwardly from the second coil inductor 1131 (e.g., from an innermost coil section 1122g toward the opening 1127) such that the second connector 1 134 at least partially overlaps the first connector 1128.

[0078] Notches 1140a and 1140b extend into outer peripheries of the coil inductors 1122 and 1131, respectively. The notches 1140a and 1140b may facilitate folding the first and second capacitor plates 1129 and 1132 from the first state (i.e., un-folded state) to the second state (i.e., the folded state). In embodiments, the first conductive layer 1120 may define a first fold line LI between the first coil inductor 1122 and the first capacitor plate 1129, and the second conductive layer 1130 may define a second fold line L2 between the second coil inductor 1122 and the second capacitor plate 1129. The fold lines LI and L2 may take on any suitable form, for example, a living hinge, a perforated section, or an area of reduced cross-sectional thickness. It is contemplated that the substrate 11 10 may also define a fold line coinciding with fold lines LI and L2, for example, in embodiments wherein an outer edge of the substrate 1110 extends past an edge of the first and second coil inductors 1122 and 1131. In embodiments, a single fold line may comprise the respective fold lines such that the fold lines are disposed in a common plane (e.g.. a vertical plane orthogonal to a planar surface of the substrate 11 10). In embodiments, the single fold line or fold lines may define an outer periphery' of an EAS label.

[0079] What has been described above includes examples of the present specification. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present specification, but one of ordinary' skill in the art may recognize that many further combinations and permutations of the present specification are possible. Accordingly, the present specification is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term ‘‘includes’’ is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

[0080] The foregoing description identifies various, non-limiting embodiments of an EAS circuit. Modifications may occur to those skilled in the art and to those who may make and use the invention. The disclosed embodiments are merely for illustrative purposes and not intended to limit the scope of the invention or the subject matter set forth in the claims.

Claims

CLAIMSWhat is claimed is:

1. An electronic article surveillance (EAS) circuit comprising: a substrate having a first side and a second side opposite the first side; a first layer disposed on the first side of the substrate, the first layer comprising: a first coil inductor having an outermost coil section defining an outer perimeter of the coil inductor, and a first innermost coil section defining a first opening, and a first capacitor plate disposed adjacent to the first coil inductor and extending outwardly beyond the outer perimeter of the first coil inductor in a first state; and a second layer disposed on the second side of the substrate, the second layer comprising a second capacitor plate at least partially overlying the first capacitor plate, wherein the second layer is connected to the first coil inductor via a first connector.

2. The EAS circuit of claim 1, wherein the first and second capacitor plates are configured to be folded over and onto the second layer in a second state such that each of said first and second capacitor plates is at least partially disposed between the outer perimeter of the first coil inductor and the opening.

3. The EAS circuit of claim 1, wherein the second layer comprises a second coil inductor, and the second capacitor plate extends outwardly beyond the outer perimeter of the second coil inductor of the second layer in the first state.

4. The EAS circuit of claim 3, wherein the second coil inductor comprises a second innermost coil section defining a second opening.

5. The EAS circuit of any of claims 3 and 4. wherein a second connector extends from the second innermost coil section and toward the second opening, wherein the second connector is configured to connect to the first connector through the substrate.

6. The EAS circuit of claim 1, wherein the first and second capacitor plates are configured to be folded over and onto the first layer in a second state such that each of said first and second capacitor plates is at least partially disposed between the outer perimeter of the first coil inductor and the first opening.

7. The EAS circuit of any of claims 1-6, wherein outer edges of the first and second capacitor plates are disposed inward relative to the outer perimeter of the first coil inductor.

8. The EAS circuit of any of claims 1-7, wherein each the first layer and the second layer defines a fold line disposed adjacent to the outer perimeter of the first coil inductor, said fold lines being disposed in a common plane.

9. The EAS circuit of any of claims 1-8, wherein the first connector is disposed adj acent to the first innermost coil section.

10. The EAS circuit of any of claims 6-9, wherein the EAS circuit further comprises a second connector extending inwardly toward a second opening.

11. The EAS circuit of claim 10, wherein the first connector and the second connector are configured to connect through the substrate.

12. The EAS circuit of claim 1 1, wherein the substrate is a planar dielectric substrate.

13. The EAS circuit of claim 12, wherein the first capacitor plate, the coil inductor, and the first connector are disposed on a first planar surface of the substrate.

14. The EAS circuit of claim 13, wherein the second capacitor plate and the second connector are disposed on a second planar surface of the substrate opposite the first planar surface.

15. The EAS circuit of any of claims 1 -5, wherein a second connector is disposed adjacent to the first innermost coil section, wherein the second connector is configured to at least partially overly the first connector to connect the first and second layers.

16. The EAS circuit of any of claims 1-15, wherein the first layer is a first electrically conductive layer, and wherein the second layer is a second electrically conductive layer.

17. The EAS circuit of any of claims 1-16, wherein the first and second capacitor plates are configured to fold via a fold line.

18. The EAS circuit of claim 17. wherein the fold line comprises a living hinge, a perforated section, or an area of reduced cross-sectional thickness.

19. The EAS circuit of any of claims 1-18, wherein the first and second capacitor plates are configured to fold via a notch.

20. The EAS circuit of any of claims 1-19, wherein the first capacitor plate is etched onto a first surface of the substrate, and the second capacitor plate is etched onto a second surface of the substrate opposite the first surface.

21. The E AS circuit of any of claims 1-20, wherein the first connector comprises a conductive trace pad.

22. The EAS circuit of any of claims 1-21, wherein the EAS circuit has a resonant frequency between about 12 and 15 MHz.

23. The EAS circuit of any of claims 1-22, wherein the EAS circuit has a resonant frequency in a range between about 7.7 to 9.5 MHz.

24. An EAS label comprises: a substrate with a first planar surface and a second planar surface opposite the first planar surface; and a first layer disposed on the first planar surface, and a second layer disposed on the second planar surface, wherein the first layer comprises a first capacitor plate and a first coil inductor, wherein the first coil inductor defines an opening extending between the first planar surface and the second planar surface of the substrate, wherein the first capacitorplate is disposed adjacent to the first coil inductor and extends outwardly beyond an outermost perimeter of the EAS label.

25. The EAS label of claim 24, wherein the first capacitor plate is configured to fold over and onto the second layer via a first fold line.

26. The EAS label of claim 24 or claim 25, wherein the first fold line defines the outermost perimeter of the EAS label.

27. The EAS label of claim 26, wherein the first fold line comprises a hinge or pivot.

28. The EAS label of any of claims 24-27. wherein first capacitor plate is configured to fold over and onto the second layer from an outer position toward an inner position.

29. The EAS label of claim 28, wherein the inner position is located between about 160 and 190 degrees from the outer position.

30. The EAS label of any of claims 24-29, wherein the second layer comprises a second capacitor plate at least partially overlying the first capacitor plate in a direction orthogonal to the first and second planar surfaces of the substrate.

31. The EAS label of claim 30, wherein the second capacitor plate is configured to fold over and onto the first layer.

32. The EAS label of any of claims 24-31, wherein the first and second capacitor plates are connected via a first connector and a second connector.

33. The EAS label of claim 32, wherein the first connector is disposed in the first layer and adjacent to the opening, and wherein the second connector extends from the second capacitor plate in a direction toward the opening such that the second connector at least partially overlies the first connector.

34. The EAS label of any of claims 24-33, wherein the first and second capacitor plates are configured to fold via a notch.

35. The EAS label of claim 34, said notch extending into the outer perimeter of the first coil inductor or a second coil inductor.

36. The EAS label of any of claims 24-35, wherein the first capacitor plate is etched onto the first planar surface of the substrate, and the second capacitor plate is etched onto the second planar surface of the substrate.

37. The EAS label of any of claims 24-36, wherein the first layer is a first electrically conductive layer, and wherein the second layer is a second electrically conductive layer.

38. The EAS label of claim 24, wherein the second layer comprises a second coil inductor and a connector, wherein the second coil inductor defines an opening, and wherein the connector extends from the second coil inductor toward the opening.

39. The EAS label of claim 40, wherein the second layer comprises a second capacitor plate, wherein the second capacitor plate and the second coil inductor define a second fold line therebetween.

40. The EAS label of any of claim 38 or 39, wherein the first capacitor plate and the first coil inductor define a first fold line therebetween41. The EAS label of claim 40, wherein the first and second capacitor plates are configured to fold onto the second layer via the first and second fold lines.

42. The EAS label of claim 40, wherein the first and second capacitor plates are configured to fold onto the first layer via the first and second fold lines.

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