Semiconductor integrated circuit device

Abstract

A power tap array (CRT) including a power tap (TAP) is provided adjacent to a plurality of cell rows (CR). A cell (C1) comprises: transistors overlapping in a plan view; VDD power supply wiring (21) formed in a BM0 layer; and VSS power supply wiring (11) formed in an M0 layer. The power tap (TAP) comprises: VSS power supply wiring (22) formed in the BM0 layer; VSS power supply wiring (12) formed in the M0 layer; and a connection structure for connecting between the VSS power supply wiring (12, 22). The size of the cell (C1) in an X-direction is larger than the arrangement pitch of VSS power supply wiring (24) formed in a BM1 layer.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a layout structure of a semiconductor integrated circuit device.

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method is a method for designing an LSI chip by preparing basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions as standard cells (sometimes simply referred to as cells), arranging multiple standard cells on the semiconductor substrate, and connecting these standard cells with wiring.

[0003] To increase the integration density of semiconductor integrated circuit devices, there is a technology called CFET (Complementary Field Effect Transistor) in which transistors are stacked vertically relative to a substrate. In this specification, the direction perpendicular to the substrate is referred to as the depth direction. Also proposed is a semiconductor integrated circuit device in which a wiring layer is provided on the backside of the transistor, and power wiring and signal wiring are provided on this backside wiring layer.

[0004] Patent Document 1 discloses a semiconductor integrated circuit device using CFET technology, in which a wiring layer is provided on the backside of a transistor, and in which a power tap cell is provided to connect a power supply wiring (VSS) provided on the backside wiring layer with a power supply wiring provided on the topside wiring layer.

[0005] US Patent Application Publication No. 2023 / 0069137 (FIG. 4B)

[0006] However, in the configuration of Patent Document 1, a transistor cannot be placed in the power tap cell because a via is provided to connect the top wiring layer and the back wiring layer, i.e., the transistor can only be placed between the power tap cells.

[0007] On the other hand, as the voltage of semiconductor integrated circuit devices continues to decrease, it has become necessary to arrange power supply wiring densely to avoid problems such as performance degradation and malfunction due to power supply voltage drops. Therefore, in the configuration of Patent Document 1, it is necessary to reduce the spacing between power tap cells. This reduces the maximum width of cells that can be arranged between power tap cells, reducing the degree of freedom in arranging cells with large circuit scales, such as flip-flops. This makes it difficult to design semiconductor integrated circuit devices, resulting in problems such as performance degradation.

[0008] The present disclosure provides a layout structure for a semiconductor integrated circuit device equipped with a power tap that allows a high degree of freedom in arranging cells with large circuit scales.

[0009] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes: a plurality of cell rows each including a plurality of standard cells lined up in a first direction, the cell rows being arranged adjacent to each other in a second direction perpendicular to the first direction; and a power tap row including a plurality of power taps lined up in the first direction and adjacent to the plurality of cell rows in the second direction, the plurality of cell rows including a first standard cell, the first standard cell including a first transistor of a first conductivity type, a second transistor of a second conductivity type formed above the first transistor in a depth direction and overlapping the first transistor in a plan view, a first power supply wiring formed in a first wiring layer on a back surface side of the first and second transistors, extending in the first direction, and supplying a first power supply voltage to the first transistor, and a second power supply wiring formed in a second wiring layer on an upper surface side of the first and second transistors. the power tap comprises: a third power supply wiring formed in the first wiring layer, extending in the first direction, and supplying the second power supply voltage; a fourth power supply wiring formed in the second wiring layer, extending in the first direction, overlapping with the third power supply wiring in a plan view, and supplying the second power supply voltage; and a connection structure connecting the third power supply wiring and the fourth power supply wiring; the semiconductor integrated circuit device comprises a plurality of fifth power supply wirings formed in a third wiring layer below the first wiring layer, extending in the second direction, and supplying the second power supply voltage, the plurality of fifth power supply wirings being arranged at a first pitch in the first direction, and a size of the first standard cell in the first direction being larger than the first pitch.

[0010] According to this aspect, a semiconductor integrated circuit device includes a power tap row including a plurality of power taps, adjacent to a plurality of cell rows including standard cells aligned in a first direction. Each first standard cell in the cell row includes first and second transistors that overlap in a plan view, a first power supply wiring formed in a first wiring layer on the back side and supplying a first power supply voltage, and a second power supply wiring formed in a second wiring layer on the top side and supplying a second power supply voltage. The power tap includes a third power supply wiring formed in the first wiring layer and supplying a second power supply voltage, a fourth power supply wiring formed in the second wiring layer and supplying the second power supply voltage, and a connection structure connecting the third and fourth power supply wirings. Since the power tap row is provided separately from the plurality of cell rows, there is no need to arrange power tap cells in the plurality of cell rows. The semiconductor integrated circuit device also includes a plurality of fifth power supply wirings formed in a third wiring layer below the first wiring layer and supplying the second power supply voltage. The size of the first standard cell in the first direction is greater than a first pitch at which the plurality of fifth power supply wirings are arranged. That is, since the degree of freedom in arranging cells with large circuit scales in a plurality of cell rows increases, the design of the semiconductor integrated circuit device becomes easier and the performance can be improved.

[0011] According to the present disclosure, a layout structure that allows a high degree of freedom in arranging cells with large circuit scales can be realized for a semiconductor integrated circuit device that includes a power tap.

[0012] 1A and 1B are plan views showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to an embodiment, where (a) is a diagram showing the M0 layer and the M1 layer, and (b) is a diagram showing the BM0 layer and the BM1 layer; FIG. 1C is a plan view showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to an embodiment, where (a) is a diagram showing the M0 layer and the M1 layer, and (b) is a diagram showing the BM0 layer and the BM1 layer; BM3 to BM5 layers are shown; FIG. BM4 is a plan view showing an example of the layout of an inverter cell, where (a) is the bottom and (b) is the top; FIG. BM5 is a plan view showing another example of the configuration of a semiconductor integrated circuit device according to an embodiment; FIG. BM6 is a plan view showing an example of the layout structure of an inverter cell, where (a) is the bottom and (b) are the top; FIG. BM7 is a plan view showing an example of the layout structure of an inverter cell, where (a) is the bottom and (b) are the top; FIG. BM8 is a plan view showing an example of the layout structure of a two-input NAND circuit cell, where (a) is the bottom and (b) are the top; FIG. BM9 is a plan view showing an example of the layout structure of a two-input NOR circuit cell, where (a) is the bottom and (b) is the top;

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells), and at least some of the plurality of standard cells include nanosheet field effect transistors (FETs). In the present disclosure, the transistors included in the standard cells are not limited to nanosheet FETs.

[0014] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0015] 1 to 3B are plan views showing examples of layouts of circuit blocks included in a semiconductor integrated circuit device according to an embodiment. The block layouts in FIGS. 1 to 3B are configured by arranging standard cells. In FIGS. 1 to 3B, only the cell frames and power supply wiring of the standard cells are shown, and the internal structure of the standard cells and wiring between the standard cells are not shown.

[0016] In this embodiment, the power supply wiring is formed in the M0 layer, M1 layer, M2 layer, M3 layer, M4 layer, and M5 layer, which are wiring layers provided on the top surface of the semiconductor chip on which the transistors are formed. The layers are more distant from the transistors in the order of M0 layer, M1 layer, M2 layer, M3 layer, M4 layer, and M5 layer. The power supply wiring is also formed in the BM0 (Backside Metal 0) layer, BM1 layer, BM2 layer, BM3 layer, BM4 layer, and BM5 layer, which are wiring layers provided on the back surface of the semiconductor chip on which the transistors are formed. The layers are more distant from the transistors in the order of BM0 layer, BM1 layer, BM2 layer, BM3 layer, BM4 layer, and BM5 layer.

[0017] Figure 1(a) shows the M0 and M1 layers, and Figure 1(b) shows the BM0 and BM1 layers. Figure 2A shows the M1, M2, and M3 layers, and Figure 2B shows the M3, M4, and M5 layers. Figure 3A shows the BM1, BM2, and BM3 layers, and Figure 3B shows the BM3, BM4, and BM5 layers.

[0018] 1(a), 2A, and 2B show the configuration as viewed from the top, with the M1, M2, M3, M4, and M5 layers stacked in this order from the M0 layer upward, while FIG. 1(b), 3A, and 3B show the configuration as viewed from the back, with the BM1, BM2, BM3, BM4, and BM5 layers stacked in this order from the BM0 layer upward.

[0019] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0020] In the layout of FIG. 1A, a plurality of cells C arranged in the X direction constitute a cell row CR. A plurality of cell rows CR (nine rows in FIG. 1A) are arranged in the Y direction. The plurality of cells includes cells having logic functions such as inverters, NAND gates, and NOR gates. The specific layout of the cells will be described later.

[0021] In addition, power tap rows CRT extending in the X direction are arranged between the cell rows CR. In FIG. 1(a), power tap rows CRT are arranged between the third and fourth cell rows CR from the top of the figure, and between the third and fourth cell rows CR from the bottom of the figure. Power tap cells TAP are formed in the power tap row CRT. The power tap cells TAP connect the VSS wiring on the top surface side of the semiconductor chip with the VSS wiring on the back surface side. The height (size in the Y direction) of the power tap row CRT is smaller than the height of the cell row CR. A detailed layout of the power tap cells will be described later. As will be described later, it is also possible to provide power taps in the power tap row CRT without using cells.

[0022] As shown in FIG. 1A, on the top surface of the semiconductor chip, power supply wiring 11 and 12 extending in the X direction are formed in the M0 layer. The power supply wiring 11 and 12 supply VSS. The power supply wiring 11 overlaps with the cell row CR in a plan view, and the power supply wiring 12 overlaps with the power tap row CRT in a plan view. Furthermore, a power supply wiring 13 extending in the Y direction is formed in the M1 layer. The power supply wiring 13 supplies VSS. The power supply wiring 11 and 12 in the M0 layer and the power supply wiring 13 in the M1 layer are connected via a via 31 formed at a position where they intersect in a plan view. This forms a mesh-shaped VSS power supply wiring.

[0023] 1B, on the back side of the semiconductor chip, power supply wiring 21 and 22 extending in the X direction are formed in the BM0 layer. The power supply wiring 21 supplies VDD, and the power supply wiring 22 supplies VSS. The power supply wiring 21 overlaps with the cell row CR in a plan view, and the power supply wiring 22 overlaps with the power tap row CRT in a plan view.

[0024] Furthermore, power supply wiring 23 and 24 extending in the Y direction are formed on the BM1 layer. The power supply wiring 23 supplies VDD, and the power supply wiring 24 supplies VSS. The power supply wiring 21 on the BM0 layer and the power supply wiring 23 on the BM1 layer are connected via a via 41 formed at a position where they intersect in a planar view. This forms a mesh-like VDD power supply wiring. The power supply wiring 22 on the BM0 layer and the power supply wiring 24 on the BM1 layer are connected via a via 42 formed at a position where they intersect in a planar view. This forms a mesh-like VSS power supply wiring.

[0025] Each cell C of the cell row CR receives a supply of VDD from a power supply wiring 21 formed in the BM0 layer, and a supply of VSS from a power supply wiring 11 formed in the M0 layer. The design data for each cell includes a VDD power supply wiring in the BM0 layer and a VSS power supply wiring in the M0 layer, and by arranging each cell in the X direction, the power supply wiring 21 formed in the BM0 layer and the power supply wiring 11 formed in the M0 layer are formed continuously in the X direction.

[0026] The power supply wiring 13 of the M1 layer and the power supply wiring 23, 24 of the BM1 layer are laid out during block layout design. In the configurations of Figures 1(a) and 1(b), the power supply wiring 13 of the M1 layer and the power supply wiring 24 that supplies VSS to the BM1 layer have the same arrangement pitch in the X direction and are arranged at the same position in the X direction. In other words, the power supply wiring 13 of the M1 layer and the power supply wiring 24 that supplies VSS to the BM1 layer overlap in a planar view.

[0027] In the BM1 layer, the power supply wiring 23 that supplies VDD and the power supply wiring 24 that supplies VSS are alternately arranged in the X direction.

[0028] 1A, a cell C1 having a large width (size in the X direction) is arranged in the cell row CR. The width of the cell C1 is larger than the wiring spacing of the power supply wiring 13 in the M1 layer. In other words, the cell C1 overlaps with two or more (three in the figure) power supply wirings 13 in the M1 layer in a plan view.

[0029] 2A and 2B show examples of the configuration of power supply wiring in layers above the M1 layer. As shown in Fig. 2A, in the M2 layer, a short power supply wiring 14 is arranged in the same position in the Y direction as the power supply wirings 11 and 12 in the M0 layer. The power supply wiring 14 is formed around the same position in the X direction as the power supply wiring 13 in the M1 layer. The width of the power supply wiring 14 may or may not be the same as the width of the power supply wirings 11 and 12 in the M0 layer.

[0030] In the M3 layer, power supply wiring 15 extending in the Y direction is arranged. The power supply wiring 15 is arranged at the same position in the X direction as the power supply wiring 13 in the M1 layer. The width of the power supply wiring 15 may or may not be the same as the width of the power supply wiring 13 in the M1 layer.

[0031] A via 32 is formed between the power supply wiring 14 of the M2 layer and the power supply wiring 13 of the M1 layer. Furthermore, a via 33 is formed between the power supply wiring 15 of the M3 layer and the power supply wiring 14 of the M2 layer. The vias 32 and 33 overlap, in plan view, with the via 31 formed between the power supply wirings 11 and 12 of the M0 layer and the power supply wiring 13 of the M1 layer. This reduces the resistance of the power supply wiring, thereby making it possible to suppress a drop in the power supply voltage.

[0032] 2B, power supply wiring 16 extending in the X direction is arranged in the M4 layer. The wiring pitch of the power supply wiring 16 is larger than that of the power supply wirings 11 and 12 in the M0 layer. The power supply wiring 16 overlaps with a portion of the power supply wiring 11 in the M0 layer in a plan view. The power supply wiring 16 is also wider than the power supply wiring 11 in the M0 layer.

[0033] In the M5 layer, power supply wiring 17 extending in the Y direction is arranged. The wiring pitch of the power supply wiring 17 is larger than that of the power supply wiring 13 in the M1 layer. The power supply wiring 17 overlaps with a portion of the power supply wiring 13 in the M1 layer in a plan view. The power supply wiring 17 is also wider than the power supply wiring 13 in the M1 layer.

[0034] A via 34 is formed between the power supply wiring 15 of the M3 layer and the power supply wiring 16 of the M4 layer. Furthermore, a via 35 is formed between the power supply wiring 16 of the M4 layer and the power supply wiring 17 of the M5 layer. The via 34 overlaps, in plan view, with the via 33 formed between the power supply wiring 14 of the M2 layer and the power supply wiring 15 of the M3 layer. Furthermore, the via 35 overlaps with a portion of the via 34 in plan view. This reduces the resistance of the power supply wiring, thereby making it possible to suppress a drop in the power supply voltage.

[0035] It should be noted that there may be more wiring layers on the top surface of the semiconductor chip. Specifically, for example, multiple wiring layers with the same structure as the M2 and M3 layers may be repeated. Alternatively, multiple wiring layers with the same structure as the M4 and M5 layers may be repeated. Alternatively, power supply wiring with a larger wiring width and wiring pitch may be formed in a layer above the M5 layer.

[0036] 3A and 3B show examples of the configuration of power supply wiring in layers below the BM1 layer. As shown in FIG. 3A, power supply wiring 25 and 26 extending in the X direction are arranged in the BM2 layer. The power supply wiring 25 supplies VDD, and the power supply wiring 26 supplies VSS. The power supply wiring 25 overlaps with the power supply wiring 21 in the BM0 layer in a planar view, and the power supply wiring 26 overlaps with the power supply wiring 22 in the BM0 layer in a planar view. The widths of the power supply wirings 25 and 26 are the same as the widths of the power supply wirings 21 and 22 in the BM0 layer. However, they do not have to be the same.

[0037] In the BM3 layer, power supply wiring 27 and 28 extending in the Y direction are arranged. The power supply wiring 27 supplies VDD, and the power supply wiring 28 supplies VSS. The power supply wiring 27 is arranged at the same position in the X direction as the power supply wiring 23 in the BM1 layer. The width of the power supply wiring 27 is the same as the width of the power supply wiring 23 in the BM1 layer, although this does not have to be the same. The power supply wiring 28 is arranged at the same position in the X direction as the power supply wiring 24 in the BM1 layer. The width of the power supply wiring 28 is the same as the width of the power supply wiring 24 in the BM1 layer, although this does not have to be the same.

[0038] With respect to VDD, the power supply wiring 23 in the BM1 layer and the power supply wiring 25 in the BM2 layer are connected via a via 43 formed at a position where they intersect in a planar view. The power supply wiring 25 in the BM2 layer and the power supply wiring 27 in the BM3 layer are connected via a via 44 formed at a position where they intersect in a planar view. The vias 43 and 44 overlap with the via 41 formed between the power supply wiring 21 in the BM0 layer and the power supply wiring 23 in the BM1 layer in a planar view. This reduces the resistance of the power supply wiring, thereby suppressing a drop in the power supply voltage.

[0039] With respect to VSS, the power supply wiring 24 in the BM1 layer and the power supply wiring 26 in the BM2 layer are connected via a via 45 formed at a position where they intersect in a planar view. The power supply wiring 26 in the BM2 layer and the power supply wiring 28 in the BM3 layer are connected via a via 46 formed at a position where they intersect in a planar view. The vias 45 and 46 overlap with the via 42 formed between the power supply wiring 22 in the BM0 layer and the power supply wiring 24 in the BM1 layer in a planar view. This reduces the resistance of the power supply wiring, thereby making it possible to suppress a drop in the power supply voltage.

[0040] 3B, power supply wiring 29 and 2A extending in the X direction are arranged on the BM4 layer. The power supply wiring 29 supplies VDD, and the power supply wiring 2A supplies VSS.

[0041] The power supply wiring 29 has a larger wiring pitch than the power supply wiring 25 in the BM2 layer. The power supply wiring 29 overlaps with a portion of the power supply wiring 25 in the BM2 layer in plan view, and has a larger width than the power supply wiring 25 in the BM2 layer.

[0042] The power supply wiring 2A overlaps with the power supply wiring 26 in the BM2 layer in a plan view, and has a width greater than that of the power supply wiring 26 in the BM2 layer.

[0043] In the BM5 layer, power supply wirings 2B and 2C are arranged extending in the Y direction. The power supply wiring 2B supplies VDD, and the power supply wiring 2C supplies VSS.

[0044] The power supply wiring 2B has a larger wiring pitch than the power supply wiring 27 in the BM3 layer. The power supply wiring 2B overlaps with a portion of the power supply wiring 27 in the BM3 layer in a plan view, and has a larger width than the power supply wiring 27 in the BM3 layer.

[0045] The power supply wiring 2C has a larger wiring pitch than the power supply wiring 28 in the BM3 layer. The power supply wiring 2C overlaps with a portion of the power supply wiring 28 in the BM3 layer in a plan view, and has a larger width than the power supply wiring 28 in the BM3 layer.

[0046] With respect to VDD, the power supply wiring 27 in the BM3 layer and the power supply wiring 29 in the BM4 layer are connected via a via 47 formed at a position where they intersect in a planar view. The power supply wiring 29 in the BM4 layer and the power supply wiring 2B in the BM5 layer are connected via a via 48 formed at a position where they intersect in a planar view. The via 47 overlaps with the via 41 formed between the power supply wiring 21 in the BM0 layer and the power supply wiring 23 in the BM1 layer in a planar view. The via 48 overlaps with the via 47 in a planar view. This reduces the resistance of the power supply wiring, thereby suppressing a drop in the power supply voltage.

[0047] With respect to VSS, the power supply wiring 28 in the BM3 layer and the power supply wiring 2A in the BM4 layer are connected via a via 49 formed at a position where they intersect in a planar view. The power supply wiring 2A in the BM4 layer and the power supply wiring 2C in the BM5 layer are connected via a via 4A formed at a position where they intersect in a planar view. The via 49 overlaps with the via 42 formed between the power supply wiring 22 in the BM0 layer and the power supply wiring 24 in the BM1 layer in a planar view. The via 4A overlaps with the via 49 in a planar view. This reduces the resistance of the power supply wiring, thereby suppressing a drop in the power supply voltage.

[0048] It should be noted that there may be more wiring layers on the back side of the semiconductor chip. Specifically, for example, multiple wiring layers having the same structure as the BM2 layer and the BM3 layer may be repeated. Alternatively, multiple wiring layers having the same structure as the BM4 layer and the BM5 layer may be repeated. Alternatively, power supply wiring with a larger wiring width and wiring pitch may be formed in a layer further below the BM5 layer.

[0049] (Other Configuration Examples) All or part of the power supply wiring formed on the back surface side of the transistor may be configured using a semiconductor chip other than the semiconductor chip on which the transistor is configured.

[0050] Fig. 4 shows another example of the configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 3 shown in Fig. 4 is configured by stacking a first semiconductor chip 1 (chip A) and a second semiconductor chip 2 (chip B). Chip A has standard cells having transistors and the like arranged therein. Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0051] The power supply wiring for the above-mentioned BM0 layer to BM5 layer may be formed on chip B. Also, some of the BM0 layer to BM5 layer, for example, the power supply wiring for the BM1 layer to BM5 layer, may be formed on chip B. In this case, the power supply wiring for the BM0 layer is formed on the back side of chip A.

[0052] (Cell Layout) As examples of the cells C that make up the cell string CR, examples of layout structures will be described for an inverter cell, a two-input NAND cell, and a two-input NOR cell.

[0053] <Inverter Cell> Figures 5 and 6 show examples of the layout structure of an inverter cell, with Figures 5(a) and (b) being plan views, Figure 6(a) being a cross-sectional view in the horizontal direction in a plan view, and Figure 6(b) being a cross-sectional view in the vertical direction in a plan view. Specifically, Figure 5(a) shows the lower part, which is a portion including a lower layer transistor (here, a P-type nanosheet FET) formed on the side closer to the substrate, and Figure 5(b) shows the upper part, which is a portion including an upper layer transistor (here, an N-type nanosheet FET) formed on the side farther from the substrate. Figure 6(a) is a cross-section taken along line X1-X1' in Figures 5(a) and (b), and Figure 6(b) is a cross-section taken along line Y1-Y1' in Figures 5(a) and (b).

[0054] As shown in Fig. 5A, a power supply wiring 101 extending in the X direction is arranged in the BM0 layer within the cell. The power supply wiring 101 supplies VDD. The power supply wiring 101 is shared with other cells in the cell row including the inverter cell, and becomes the power supply wiring 21 extending in the X direction shown in Fig. 1B.

[0055] As shown in Fig. 5B, a power supply wiring 102 extending in the X direction is arranged in the cell on the M0 layer. The power supply wiring 102 supplies VSS. The power supply wiring 102 is shared with other cells in the cell row including the inverter cell, and serves as the power supply wiring 11 extending in the X direction shown in Fig. 1A.

[0056] An active region 111 that constitutes the channel, source, and drain of a P-type nanosheet FET is formed above the power supply wiring 101. The active region 111 includes a nanosheet 112 that becomes the channel of the P-type nanosheet FET. A portion 113 of the active region 111 that becomes the source of the P-type nanosheet FET is connected to the power supply wiring 101 through a via.

[0057] An active region 121 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the active region 111 and below the power wiring 102. The active region 121 includes a nanosheet 122 that becomes the channel of the N-type nanosheet FET. A portion 123 of the active region 121 that becomes the source of the N-type nanosheet FET is connected to the power wiring 102 through a via and a local wiring.

[0058] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0059] The gate wiring 131 extends in the Y direction at approximately the center of the cell in the X direction, and also extends in the Z direction from the bottom to the top of the cell. The gate wiring 131 surrounds the outer peripheries of the nanosheets 112 and 122 in the Y and Z directions via a gate insulating film (not shown). The gate wiring 131 serves as the gates of the P-type nanosheet FET and the N-type nanosheet FET. Dummy gate wirings 132 and 133 are also formed on the cell frame on both sides in the X direction.

[0060] A local wiring 141 extending in the Y direction is formed at the bottom. The local wiring 141 is connected to a portion 114 that will become the drain of the P-type nanosheet FET in the active region 111. A local wiring 142 extending in the Y direction is formed at the top. The local wiring 142 is connected to a portion 124 that will become the drain of the N-type nanosheet FET in the active region 121. The local wiring 141 and the local wiring 142 are connected via a via.

[0061] Signal wiring 151 and 152 extending in the X direction are formed on the M0 layer. The signal wiring 151 corresponds to the input A of the inverter circuit. The signal wiring 152 corresponds to the output Y of the inverter circuit. The signal wiring 151 is connected to the gate wiring 131 via a via. The signal wiring 152 is connected to the local wiring 142 via a via.

[0062] <Two-Input NAND Cell> FIG. 7 is a plan view showing an example of the layout structure of a two-input NAND cell, where (a) shows the lower part and (b) shows the upper part.

[0063] As shown in Fig. 7A, a power supply wiring 103 extending in the X direction is arranged in the BM0 layer within the cell. The power supply wiring 103 supplies VDD. The power supply wiring 103 is shared with other cells in the cell string including the two-input NAND cell, and serves as the power supply wiring 21 extending in the X direction shown in Fig. 1B.

[0064] As shown in Fig. 7B, a power supply line 104 extending in the X direction is arranged in the cell on the M0 layer. The power supply line 104 supplies VSS. The power supply line 104 is shared with other cells in the cell string including the two-input NAND cell, and serves as the power supply line 11 extending in the X direction shown in Fig. 1A.

[0065] Other layout structures can be easily inferred from the above description of the inverter cell, and therefore detailed description thereof will be omitted here.

[0066] <Two-Input NOR Cell> FIG. 8 is a plan view showing an example of the layout structure of a two-input NOR cell, where (a) shows the lower part and (b) shows the upper part.

[0067] As shown in Fig. 8A, a power supply wiring 105 extending in the X direction is arranged in the BM0 layer within the cell. The power supply wiring 105 supplies VDD. The power supply wiring 105 is shared with other cells in the cell string including the two-input NOR cell, and serves as the power supply wiring 21 extending in the X direction shown in Fig. 1B.

[0068] As shown in Fig. 8B, a power supply wiring 106 extending in the X direction is arranged in the cell on the M0 layer. The power supply wiring 106 supplies VSS. The power supply wiring 106 is shared with other cells in the cell row including the two-input NOR cell, and serves as the power supply wiring 11 extending in the X direction shown in Fig. 1A.

[0069] Other layout structures can be easily inferred from the above description of the inverter cell, and therefore detailed description thereof will be omitted here.

[0070] Note that the layout structures of cells other than the inverter cell, the two-input NAND cell, and the two-input NOR cell can be easily inferred from the above explanation, and therefore detailed explanations will be omitted here. For example, the wide cell C1 shown in Figure 1(a) also has, like the inverter cell, a P-type nanosheet FET as a lower layer transistor, an N-type nanosheet FET as an upper layer transistor, a power supply wiring formed in the BMO layer to supply VDD, and a power supply wiring formed in the M0 layer to supply VSS.

[0071] <Power Tap Cell> Figure 9 shows an example of the layout structure of power tap cells TAP arranged in a power tap row CRT, with (a) and (b) being plan views and (c) being a cross-sectional view. Figure 9(a) shows the lower part and Figure 9(b) shows the upper part. Figure 9(c) is a cross-section taken along line X1-X1' in Figures 9(a) and 9(b).

[0072] As shown in Fig. 9A, a power supply wiring 201 extending in the X direction is arranged in the BM0 layer within a cell. The power supply wiring 201 supplies VSS. As the power tap cells are lined up in the X direction, the power supply wiring 201 is supplied to other power tap cells, forming the power supply wiring 22 extending in the X direction as shown in Fig. 1B.

[0073] As shown in Fig. 9B, a power supply wiring 202 extending in the X direction is arranged in the cell on the M0 layer. The power supply wiring 202 supplies VSS. The power supply wiring 202 is supplied to other power tap cells as the power tap cells are lined up in the X direction, forming the power supply wiring 12 extending in the X direction shown in Fig. 1A.

[0074] The power supply wiring 201 in the B-M0 layer and the power supply wiring 202 in the M0 layer are connected via a via 211, which is an example of a connection structure. Note that the connection structure connecting the power supply wiring 201 and the power supply wiring 202 is not limited to a single via 211. For example, the connection structure connecting the power supply wiring 201 and the power supply wiring 202 may be configured using wiring and vias in multiple layers that are configured to overlap in a planar view.

[0075] The height (size in the Y direction) of the power tap cell shown in Fig. 9 is smaller than that of the inverter cell etc. described above, but is not limited to this.

[0076] By preparing power tap cells such as those shown in Figure 9 in advance and arranging them in the X direction, the above-mentioned power tap row CRT can be constructed, and the VSS wiring on the top side can be connected to the VSS wiring on the back side.

[0077] 10 is a cross-sectional view showing the configuration in the vicinity of the power tap cell. In addition to the cross-sectional structure of FIG. 9C, the structure of FIG. 10 shows a power wiring 203 in the BM1 layer and a power wiring 204 in the M1 layer. The power wiring 203 in the BM1 layer is connected to the power wiring 201 in the BM0 layer via a via 212. The power wiring 204 in the M1 layer is connected to the power wiring 202 in the M0 layer via a via 213.

[0078] The vias 212 and 213 are arranged at positions that overlap with the via 211 of the power tap cell in the X direction. This allows a linear path to be formed from the power wiring in the M1 layer to the power wiring in the BM1 layer, thereby reducing the resistance of the power wiring and suppressing a drop in the power supply voltage.

[0079] In this embodiment, the power tap array CRT is configured by arranging the power tap cells TAP in a row. Alternatively, the power tap array CRT may be configured by arranging necessary power wiring, for example, the power wiring 12 shown in FIG. 1(a) and the power wiring 22 shown in FIG. 1(b), and arranging connection structures such as vias that connect these power wirings. In other words, the power taps included in the power tap array CRT are not limited to those configured by cells.

[0080] According to this embodiment, in a semiconductor integrated circuit device, a power tap row CRT including multiple power taps is provided adjacent to multiple cell rows CR including standard cells C arranged in the X direction. The standard cells C include a P-type nanosheet FET and an N-type nanosheet FET that overlap in a planar view, a power supply wiring 22 formed in the BM0 layer to supply VDD, and a power supply wiring 11 formed in the M0 layer to supply VSS. The power tap includes a power supply wiring 22 formed in the BM0 layer to supply VSS, a power supply wiring 12 formed in the M0 layer to supply VSS, and a via 211 connecting the power supply wirings 12 and 22. Because the power tap row CRT is provided separately from the multiple cell rows CR, there is no need to place power tap cells in the multiple cell rows CR. The semiconductor integrated circuit device also includes multiple power supply wirings 24 formed in the BM1 layer to supply VSS. The width of cell C1, i.e., its size in the X direction, is greater than the pitch at which the power supply wirings 24 are arranged. In other words, in multiple cell rows CR, the degree of freedom in arranging cells with large circuit scales such as cell C1 is increased, making it easier to design semiconductor integrated circuit devices, thereby improving the performance of the semiconductor integrated circuit devices.

[0081] Furthermore, the height of the power tap row CRT, that is, the size in the Y direction, is smaller than the height of the cell row CR, thereby making it possible to suppress an increase in the area of ​​the semiconductor integrated circuit device.

[0082] In the above-described embodiment, a power supply wiring that supplies VDD to the BM0 layer and a power supply wiring that supplies VSS to the M0 layer are formed, but the power supplies VDD and VSS may be reversed. That is, a power supply wiring that supplies VSS to the BM0 layer and a power supply wiring that supplies VDD to the M0 layer may be formed. In this case, in the configuration of the above-described embodiment, VDD and VSS are all swapped, and the conductivity type of the nanosheet FET provided in the cell is set to N-type on the lower layer side and P-type on the upper layer side.

[0083] In the above-described embodiment, the nanosheet is illustrated as three sheet structures stacked on top of each other in a planar view, and the cross-sectional shape of the sheet structure is rectangular, but the number of sheet structures and cross-sectional shape of the nanosheet are not limited to this.

[0084] In addition, in the above-described embodiments, the transistor is a nanosheet FET, but this is not limiting. For example, a finFET or other types of transistors may be used.

[0085] The present disclosure can increase the degree of freedom in arranging cells with large circuit scales in a semiconductor integrated circuit device equipped with a power tap, which is useful for reducing costs and improving performance of the semiconductor integrated circuit device, for example.

[0086] REFERENCE SIGNS LIST 1 First semiconductor chip 2 Second semiconductor chip 3 Semiconductor integrated circuit device 11 Power supply wiring (second power supply wiring) 12 Power supply wiring (fourth power supply wiring) 21 Power supply wiring (first power supply wiring) 22 Power supply wiring (third power supply wiring) 24 Power supply wiring (fifth power supply wiring) 101, 103, 105 Power supply wiring (first power supply wiring) 102, 104, 106 Power supply wiring (second power supply wiring) 201 Power supply wiring (third power supply wiring) 202 Power supply wiring (fourth power supply wiring) 211 Via (connection structure) C, C1 Standard cell CR Cell row CRT Power tap row TAP Power tap cell M0 to M5 Wiring layer on the upper surface side of the transistor BM0 to BM5 Wiring layer on the back surface side of the transistor

Claims

1. A semiconductor integrated circuit device comprising: a plurality of cell rows, each of which includes a plurality of standard cells aligned in a first direction, the cell rows being adjacent to each other in a second direction perpendicular to the first direction; and a power tap row, the power tap row including a plurality of power taps aligned in the first direction and adjacent to the plurality of cell rows in the second direction, the plurality of cell rows comprising a first standard cell, the first standard cell comprising: a first transistor of a first conductivity type; and a second transistor of a second conductivity type, the second transistor being formed above the first transistor in a depth direction and overlapping the first transistor in a planar view; a first power supply wiring formed in a first wiring layer on the back side of the first and second transistors, extending in the first direction, and supplying a first power supply voltage to the first transistor; and a second power supply wiring formed in a second wiring layer on the top side of the first and second transistors, extending in the first direction, and supplying a second power supply voltage to the second transistor, the power tap comprising: a third power supply wiring formed in the first wiring layer, extending in the first direction, and supplying the second power supply voltage. a fourth power supply wiring formed in the second wiring layer, extending in the first direction, overlapping with the third power supply wiring in a planar view, and supplying the second power supply voltage; and a connection structure connecting the third power supply wiring and the fourth power supply wiring; the semiconductor integrated circuit device further comprises a plurality of fifth power supply wirings formed in a third wiring layer below the first wiring layer, extending in the second direction, and supplying the second power supply voltage, the plurality of fifth power supply wirings being arranged at a first pitch in the first direction, and a size of the first standard cell in the first direction is larger than the first pitch.

2. A semiconductor integrated circuit device according to claim 1, wherein the connection structure of the power tap is configured by a via that overlaps the third and fourth power wirings in a plan view, that contacts the third power wiring, and that contacts the fourth power wiring.

3. A semiconductor integrated circuit device according to claim 1, wherein the size of said power tap in said second direction is smaller than the size of said cell row in said second direction.

4. A semiconductor integrated circuit device according to claim 1, comprising: a first semiconductor chip in which the first and second transistors are formed; and a second semiconductor chip attached to the back side of the first semiconductor chip, and the third wiring layer in which the plurality of fifth power supply wirings are formed is provided on the second semiconductor chip.

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