Heteroepitaxial wafer and method for manufacturing same

The heteroepitaxial wafer with a silicon germanium layer thickness and germanium concentration relationship of Film thickness (nm) <1.4×10⁷ × [Ge (%)]⁻⁴⁵ effectively prevents metal impurity capture during device heat treatment, addressing the issue of lattice mismatch and dislocation formation, and ensuring reliable device performance for logic devices.

WO2025009407A1PCT designated stage expired Publication Date: 2025-01-09SHIN ETSU HANDOTAI CO LTD
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Patent Information

Application Number
PCT/JP2024/022396
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-07-05
Filing Date
2024-06-20
Publication Date
2025-01-09

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Abstract

The present invention provides a heteroepitaxial wafer which is obtained by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and epitaxially growing a silicon layer on the silicon germanium layer, and which is characterized in that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer satisfies [film thickness (nm)] < 1.4 × 107 × [Ge (%)]-4.5. As a result, provided is a heteroepitaxial wafer free of trapped metallic impurities.
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Citation Information

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