Semiconductor device and preparation method therefor, and semiconductor wafer

Abstract

The present application provides a semiconductor device and a preparation method therefor, and a semiconductor wafer. The semiconductor device has a first region and a second region, and comprises a first structure layer, a second structure layer, a first electrode structure, and a second electrode structure. The material of the first structure layer comprises single crystal diamond. In the first structure layer, a portion located in the first region is electrically isolated from a portion located in the second region, and the portion of the first structure layer located in the second region is subjected to hydrogen termination treatment. The second structure layer is arranged on the first structure layer, is located in the first region, and forms a heterojunction structure with the first structure layer. The material of the second structure layer comprises a single crystal AlN film or a doped single crystal AlN film. The first electrode structure comprises a first source electrode, a first gate electrode, and a first drain electrode. The first electrode structure is arranged in the first region, and is at least partially located on the side of the second structure layer away from the first structure layer. The second electrode structure comprises a second source electrode, a second gate electrode, and a second drain electrode, and is arranged on the portion of the first structure layer located in the second region. The second electrode structure and the first electrode structure are located on the same side of the first structure layer.

Description

Semiconductor device and preparation method thereof, semiconductor wafer Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a method for preparing the same, and a semiconductor wafer. Background Art

[0002] An increasing number of power electronics, sensor signal conditioning, and radio frequency communication devices are required to operate at high temperatures. These devices require integrated circuits, such as mixed-signal circuits with analog circuits, analog-to-digital converters, embedded microcontrollers, and on-chip memory. Related technologies often use complementary metal oxide semiconductor (CMOS) technology based on silicon semiconductors to form CMOS circuits that integrate PMOS and NMOS transistors to implement different logic functions. However, this type of structure is not reliable for stable and continuous operation at high temperatures (e.g., above 125°C).

[0003] Summary of the Invention

[0004] According to a first aspect of an embodiment of the present application, a semiconductor device is provided, comprising a first region and a second region, including:

[0005] a first structural layer, wherein the material of the first structural layer includes single crystal diamond, and a portion of the first structural layer located in the first region is electrically isolated from a portion located in the second region; wherein the portion of the first structural layer located in the second region is hydrogen terminated;

[0006] a second structural layer, provided on the first structural layer and located in the first region, the second structural layer and a portion of the first structural layer located in the first region forming a heterojunction structure; wherein the material of the second structural layer is a single crystal AlN thin film or a doped single crystal AlN thin film;

[0007] a first electrode structure comprising a first source electrode, a first gate electrode, and a first drain electrode, wherein the first electrode structure is disposed in the first region and at least partially located on a side of the second structure layer facing away from the first structure layer;

[0008] The second electrode structure includes a second source, a second gate and a second drain. The second electrode structure is disposed on the first structural layer and located in the second region, and is located on the same side of the first structural layer as the first electrode structure.

[0009] In some embodiments, the first drain is connected to the second source, and the first gate is connected to the second gate.

[0010] In some embodiments, the first structural layer serves as a substrate; or

[0011] The semiconductor device includes a substrate located on a surface of the first structure layer facing away from the second structure layer.

[0012] In some embodiments, if the first structure layer serves as a substrate, the thickness of the first structure layer is 100 μm-500 μm; if the semiconductor device includes another layer in contact with the first structure layer as a substrate, the thickness of the first structure layer is 0.2 μm-10 μm; and / or,

[0013] The thickness of the second structural layer is 2nm-30nm.

[0014] In some embodiments, the first structure layer serves as a channel layer in the first region, the second structure layer serves as a barrier layer in the first region, and the semiconductor device includes:

[0015] The cap layer provided in the first region is provided on a surface of the second structural layer facing away from the first structural layer.

[0016] In some embodiments, the semiconductor device is not provided with a cap layer, wherein the first source electrode and the first drain electrode are both provided on a surface of the second structure layer away from the first structure layer; or

[0017] Part of the first source electrode is located on the surface of the second structure layer away from the first structure layer, and another part thereof penetrates the second structure layer and contacts the surface of the first structure layer; part of the first drain electrode is located on the surface of the second structure layer away from the first structure layer, and another part thereof penetrates the second structure layer and contacts the surface of the first structure layer; or

[0018] The semiconductor device is provided with a cap layer, wherein the first source electrode and the first drain electrode are both provided on a surface of the cap layer away from the first structural layer; or

[0019] Part of the first source electrode is located on the surface of the cap layer away from the first structural layer, and another part thereof penetrates the cap layer and a portion of the depth of the second structural layer; part of the first drain electrode is located on the surface of the cap layer away from the first structural layer, and another part thereof penetrates the cap layer and a portion of the depth of the second structural layer; or

[0020] Part of the first source electrode is located on the surface of the cap layer away from the first structural layer, and another part passes through the cap layer and the second structural layer and contacts the surface of the first structural layer; part of the first drain electrode is located on the surface of the cap layer away from the first structural layer, and another part passes through the cap layer and the second structural layer.

[0021] In some embodiments, the semiconductor device is not provided with a cap layer, wherein the first gate is provided on a surface of the second structure layer away from the first structure layer; or

[0022] A portion of the first gate is located on a surface of the second structure layer facing away from the first structure layer, and another portion thereof penetrates a partial depth of the second structure layer;

[0023] The semiconductor device is provided with a cap layer, which penetrates the cap layer and contacts the surface of the second structural layer; or

[0024] A portion of the first gate is disposed on a surface of the cap layer away from the first structural layer, and another portion thereof penetrates a portion of the cap layer and the second structural layer.

[0025] In some embodiments, if the first gate penetrates a portion of the depth of the second structure layer, a distance between a bottom end of the first gate and a bottom surface of the second structure layer is 2 nm-15 nm.

[0026] In some embodiments, a portion of the first structural layer not covered by the second structural layer is provided with an isolation zone, and the isolation zone is used to electrically isolate the first region from the second region.

[0027] In some embodiments, the isolation zone extends from the surface of the first structural layer in contact with the second structural layer into the first structural layer, the depth of the isolation zone is 2nm-20nm, and the width of the isolation zone is 0.1μm-5μm; and / or

[0028] The isolation zone is formed by etching, oxygen plasma treatment or ion implantation.

[0029] In some embodiments, a two-dimensional electron gas is formed at the interface between the first structure layer and the second structure layer in the first region, and the first region forms an N-type transistor based on the two-dimensional electron gas; a two-dimensional hole gas is formed at the surface of the first structure layer in the second region, and the second region forms a P-type transistor based on the two-dimensional hole gas;

[0030] The semiconductor device is a CMOS device or an integrated circuit that integrates an N-type transistor formed based on the two-dimensional electron gas in the first region and a P-type transistor formed based on the two-dimensional hole gas in the second region.

[0031] According to a second aspect of an embodiment of the present application, a semiconductor wafer is provided, comprising a plurality of chips arranged in an array, each chip integrating a plurality of semiconductor devices as described above.

[0032] According to a third aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising:

[0033] forming a first structural layer; wherein the material of the first structural layer includes single crystal diamond;

[0034] forming a second structural layer, the second structural layer being located on the first structural layer and in the first region, and forming a heterojunction structure with a portion of the first structural layer located in the first region; wherein the material of the second structural layer is a single crystal AlN thin film or a doped single crystal AlN thin film;

[0035] performing hydrogen termination treatment on a portion of the first structural layer located in the second region;

[0036] electrically isolating a portion of the first structural layer located in the first area from a portion located in the second area;

[0037] A first electrode structure and a second electrode structure are generated; wherein the first electrode structure includes a first source, a first gate and a first drain, and is arranged in the first region and at least partially located on a side of the second structure layer away from the first structure layer; the second electrode structure includes a second source, a second gate and a second drain, and the second electrode structure is arranged on the first structure layer and located in the second region, and is located on the same side of the first structure layer as the first electrode structure.

[0038] In some embodiments, after generating the first electrode structure and the second electrode structure, the method includes:

[0039] The first drain is connected to the second source, and the first gate is connected to the second gate.

[0040] In some embodiments, before forming the first structural layer, the method includes: providing a substrate;

[0041] The forming of the first structural layer comprises:

[0042] The first structure layer is formed on the substrate.

[0043] In some embodiments, after providing the substrate, the method includes:

[0044] polishing and cleaning the surface of the substrate;

[0045] The forming the first structural layer on the substrate comprises:

[0046] The first structural layer is formed on the surface of the substrate after polishing and cleaning.

[0047] In some embodiments, after forming the second structural layer, the method includes:

[0048] A cap layer is formed on a surface of the second structural layer facing away from the first structural layer.

[0049] In some embodiments, electrically isolating the portion of the first structural layer located in the first area from the portion located in the second area includes:

[0050] An isolation zone is provided on a portion of the first structural layer not covered by the second structural layer, and the isolation zone is used to electrically isolate the first region from the second region.

[0051] In some embodiments, the isolation zone extends inward from the surface of the first structural layer in contact with the second structural layer, the depth of the isolation zone is 2nm-20nm, and the width of the isolation zone is 0.1μm-5μm; and / or

[0052] The isolation zone is formed by etching, oxygen plasma treatment or ion implantation.

[0053] In some embodiments, forming the second structural layer 2 includes:

[0054] forming a second structural material layer on the first structural layer 1;

[0055] The portion of the second structural material layer located in the second region is removed to form the second structural layer.

[0056] Based on the above technical solution, in the semiconductor device, the first structural layer is made of single crystal diamond, and the second structural layer located in the first region is made of single crystal AlN thin film or doped single crystal AlN thin film, so that a two-dimensional electron gas is formed at the interface between the first structural layer and the second structural layer. The portion of the first structural layer located in the second region is hydrogen-terminated, so that a two-dimensional hole gas is formed on the surface of a portion of the first structural layer. Diamond material has excellent high-temperature resistance and thermal conductivity, high bandgap and breakdown voltage, and high electron and hole mobility. Compared with silicon-based complementary metal oxide semiconductor (CMOS) technology, the semiconductor device can form an integrated circuit that integrates N-type transistors ("NMOS") based on two-dimensional electron gas and P-type transistors ("PMOS") based on two-dimensional hole gas. The integrated circuit fabricated in this manner can have the same functions and applications as silicon-based CMOS integrated circuits, realize the same various logic functions as silicon-based CMOS circuits, and can operate more continuously and stably at high temperatures, even at temperatures as high as 350°C or above, and can achieve higher output power, operating frequency, and breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] FIG1 is a cross-sectional view of a semiconductor device provided in one embodiment of the present application;

[0058] FIG2 is a cross-sectional view of another semiconductor device provided by an embodiment of the present application;

[0059] FIG3 is a cross-sectional view of another semiconductor device provided by an embodiment of the present application;

[0060] FIG4 is a cross-sectional view of another semiconductor device provided by an embodiment of the present application;

[0061] FIG5 is a schematic diagram of an energy band of a heterojunction structure provided by one embodiment of the present application;

[0062] FIG6 is a schematic structural diagram of a semiconductor wafer provided in one embodiment of the present application;

[0063] FIG7 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0064] 8 to 17 are diagrams of a manufacturing process of a semiconductor device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0065] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different drawings represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application. The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0066] The present application provides a semiconductor device, a method for manufacturing the same, and a semiconductor wafer. The semiconductor device comprises a first region and a second region, and includes a first structural layer 1, a second structural layer 2, a first electrode structure, and a second electrode structure. The material of the first structural layer 1 comprises single crystal diamond, and the two portions of the first structural layer 1 located in the first region and the second region are electrically isolated; the portion of the first structural layer 1 located in the second region undergoes hydrogen termination. The second structural layer 2 is disposed above the first structural layer 1 and located in the first region, forming a heterojunction structure with the portion of the first structural layer 1 located in the first region; the material of the second structural layer 2 comprises a single crystal AlN film or a doped single crystal AlN film. The first electrode structure comprises a first source, a first gate, and a first drain. The first electrode structure is disposed in the first region and is at least partially located on the side of the second structural layer 2 facing away from the first structural layer 1. The second electrode structure comprises a second source, a second gate, and a second drain. The second electrode structure is disposed above the first structural layer 1 and located in the second region, and is located on the same side of the first structural layer 1 as the first electrode structure. In the semiconductor device, the first structure layer 1 is made of a single-crystal diamond material, and the second structure layer 2 located in the first region is made of a single-crystal AlN thin film or a doped single-crystal AlN thin film, so that a two-dimensional electron gas (2EG) is formed at the interface between the first structure layer 1 and the second structure layer 2. The portion of the first structure layer 1 located in the second region undergoes a hydrogen termination treatment, so that a two-dimensional hole gas (2DG) is formed on the surface of a portion of the first structure layer 1. Furthermore, diamond material exhibits excellent properties such as high-temperature resistance and thermal conductivity, a high bandgap and breakdown voltage, and high electron and hole mobility. This enables the semiconductor device and its integrated circuit, which incorporates N-type transistors based on the 2DG and P-type transistors based on the 2DG, to operate more consistently and stably at high temperatures, even up to 350°C or higher, compared to silicon-based complementary metal oxide semiconductor (CMOS) technology. Furthermore, the device can achieve higher output power, operating frequency, and breakdown voltage.

[0067] The semiconductor device, its manufacturing method, and semiconductor wafer are described in detail below with reference to FIG. 1 to FIG. 17 .

[0068] First, please describe the semiconductor device with reference to FIG. 1 to FIG. 5 .

[0069] Figure 1 is a cross-sectional view of a semiconductor device 100 according to one embodiment of the present application. Figure 5 is a schematic diagram of an energy band structure of a heterojunction structure according to one embodiment of the present application. Referring to Figure 1 and, where necessary, Figure 5 , semiconductor device 100 comprises a first region S1 and a second region S2. The semiconductor device includes a first structural layer 1, a second structural layer 2, a first electrode structure, and a second electrode structure.

[0070] The material of the first structural layer 1 includes single crystal diamond, and the portion of the first structural layer 1 located in the first region S1 is electrically isolated from the portion located in the second region S2. The second structural layer 2 is disposed above the first structural layer 1 and located in the first region S1. The first structural layer 2 forms a heterojunction structure with the first structural layer 1 located in the first region S1. The material of the second structural layer 2 includes a single crystal AlN thin film or a doped single crystal AlN thin film. The first electrode structure includes a first source 71, a first gate 72, and a first drain 73. The first electrode structure is disposed in the first region S1 and is at least partially located on the side of the second structural layer 2 facing away from the first structural layer 1.

[0071] Diamond has unique physical, chemical and electrical properties. For example, diamond has extremely low chemical reactivity, which makes it suitable for use in highly corrosive environments. Diamond's room temperature thermal conductivity is 10W / cm*K-20W / cm*K, the highest among known materials, and can reach several times that of materials such as copper and silicon. Diamond is an electrical insulator at room temperature, with a resistivity of up to 10 16 Furthermore, diamond is a wide-bandgap semiconductor material with a bandgap width of approximately 5.5 eV, and has both high electron mobility (4500 cm2 / Vs) and high hole mobility (3800 cm2 / V·s).

[0072] Diamond can be grown using high-pressure, high-temperature (HPHT) methods. For example, the diamonds formed using this method often have cubic structures, octahedral structures, or combinations of these. Diamond can also be grown using chemical vapor deposition (CVD) methods, such as plasma-enhanced chemical vapor deposition (PECVD) and microwave plasma chemical vapor deposition (MPCVD).

[0073] Aluminum nitride (AlN) is a new III-V semiconductor material with the largest bandgap and direct bandgap among III-V compound semiconductors. The bandgap of AlN is approximately 6.2 eV. It also exhibits excellent piezoelectric properties, high thermal conductivity, high resistivity, a strong breakdown field, and a low dielectric constant.

[0074] In this application, a material comprising single-crystal diamond can be used as the first structural layer 1. This first structural layer 1 can also serve as a substrate layer, i.e., it has the additional function of a substrate layer. As mentioned above, diamond has excellent physical, chemical, and mechanical properties and can be used directly as a substrate layer. In the semiconductor device 100 shown in Figure 1, the first structural layer 1 also serves as the substrate layer. In the first region S1, AlN is grown on the surface of the first structural layer 1 as the second structural layer 2.

[0075] In this embodiment, in the first region S1, the first structural layer 1 serves as a channel layer, and the second structural layer 2 serves as a barrier layer. Due to the excellent properties of diamond, the first structural layer 1 formed of diamond material serves as the channel layer. Diamond material has a large bandgap, resulting in a high breakdown voltage. Diamond material also has high thermal conductivity, allowing it to withstand high output power. Furthermore, diamond material has high electron and hole mobility, enabling high operating frequencies.

[0076] Based on the excellent performance of the above-mentioned diamond and AlN materials, in the first region S1, the first structural layer 1 formed by the single-crystal diamond material serves as the channel layer, and the second structural layer 2 formed by the single-crystal AlN thin film material serves as the barrier layer. The heterojunction structure formed by these two layers has a larger bandgap width, higher electron mobility, higher electron concentration, higher breakdown voltage, and higher thermal conductivity, compared with the heterojunction structure formed by structural layers of other different materials (such as the heterojunction structure formed by AlxGa(1-x)N (where x ranges from 0 to 1) as the channel layer and AlN as the barrier layer, etc.).

[0077] It is understood that in this embodiment, in the first region S1, the diamond first structural layer 1 can serve as both the substrate layer and the channel layer, thereby simplifying the overall structural film layer of the semiconductor device. In this embodiment, the thickness of the first structural layer 1 is 100 μm-500 μm. The thickness of the second structural layer 2 is 2 nm-30 nm. This is merely an example, and the specific thicknesses of the first structural layer 1 and the second structural layer 2 can be set according to specific circumstances.

[0078] As shown in Figure 5, Ec is the energy level at the bottom of the conduction band, Ev is the energy level at the top of the valence band, △Ec is the band step difference at the bottom of the conduction band formed by the different band gap widths of AlN material and diamond material, and E Fis the Fermi level in equilibrium. As shown in Figure 5, the band gap width of the second structural layer 2 (i.e., AlN) is greater than the band gap width of the first structural layer 1 (i.e., diamond), and there is a band step difference between the conduction band bottom of the second structural layer 2 and the first structural layer 1. The band step difference causes the conduction band bottom energy band to bend, so that in the first region S1, a two-dimensional potential well is formed at the interface between the first structural layer 1 and the second structural layer 2. The two-dimensional potential well confines electrons therein, so that electrons form a two-dimensional electron gas (2DEG) in the two-dimensional potential well, as shown in the shaded area in Figure 5. That is, in the embodiment of the present application, even if the second structural layer 2 is not ion-doped, the heterojunction structure located in the first region S1 can obtain a higher surface density of the two-dimensional electron gas, which can well solve the problem that the application of AlN and diamond materials in semiconductor devices is limited due to the difficulty of doping.

[0079] As shown in FIG. 1 , in this embodiment, the first source electrode 71 , the first drain electrode 73 and the first gate electrode 72 are all disposed on a surface of the second structure layer 2 facing away from the first structure layer 1 .

[0080] The manufacturing method of the first source electrode 71 and the first drain electrode 73 may include process steps such as coating, alignment / exposure, development, metal deposition, metal stripping (or etching), desizing, cleaning, and annealing. The source and drain electrodes are generally formed by a combination of several metals through high-temperature annealing to form an alloy to reduce resistance. These metals include Ti, Al, Ni, Pt, Au, or others, and can be a single metal or a combination of multiple metals (e.g., 2-6 types). They are usually deposited layer by layer on the aluminum nitride epitaxial layer (i.e., the second structural layer 2) through metal evaporation or sputtering. For example, the source and drain electrodes can be composed of four metal layers, namely Ti, Al, Ti, and Au. The thickness ranges of these four metal layers are, for example, 2nm-25nm, 30nm-300nm, 20nm-100nm, and 50nm-500nm. For example, Ti 25nm, Al 50nm, Ti 100nm, and Au 250nm can be selected respectively, with a total thickness of 450nm. The metal layers can also be of other combinations and thicknesses. The annealing process is performed in an RTA (rapid thermal annealing) furnace at a temperature generally between 700-900°C, usually around 800°C, in an argon or nitrogen environment for 30 to 90 seconds to form an ohmic contact to reduce resistance.

[0081] The first gate 72 is typically deposited layer by layer onto the second structural layer 2 by metal evaporation or sputtering. The fabrication method for the first gate 72 includes process steps such as resist coating, alignment / exposure, development, metal deposition, metal stripping (etching), resist removal, and cleaning, which are not described in detail here. In the structure shown in FIG14 , the first gate 72 is a Schottky layer, with the metal electrode directly formed on the surface of the second structural layer 2 (i.e., the barrier layer) to form a Schottky contact with the aluminum nitride layer of the second structural layer 2 (i.e., the barrier layer). The first gate 72 layer is generally made of metals with high work functions, such as Pt, Ni, Au, and Ti. Their work functions are 5.65 eV, 5.15 eV, 5.1 eV, and 4.33 eV, respectively. The metal layer can consist of a single metal layer or two to four metal layers, such as Pt / Au or Ni / Au, with a thickness ranging from 10 nm to 50 nm or 50 nm to 250 nm.

[0082] It can be understood that in some other embodiments, part of the first source electrode is located on the surface of the second structure layer away from the first structure layer, and another part passes through the second structure layer and contacts the surface of the first structure layer; part of the first drain electrode is located on the surface of the second structure layer away from the first structure layer, and another part passes through the second structure layer and contacts the surface of the first structure layer 1.

[0083] Furthermore, the first gate may be partially located on a surface of the second structural layer facing away from the first structural layer 1, and another portion may penetrate partially through the thickness of the second structural layer 2. When the first gate penetrates partially through the second structural layer, the distance between the bottom end of the first gate and the bottom surface of the second structural layer is 2 nm to 15 nm, thereby improving the gate's ability to control the two-dimensional electron gas while ensuring sufficient two-dimensional electron gas can be formed in the second structural layer.

[0084] It should also be noted that, in other embodiments, the region in the second structural layer used to set the first source and the first drain may also be N-type doped to form an N-type doped region to further reduce the ohmic contact resistance.

[0085] In this embodiment, the first structural layer 1 in the second region S2 is hydrogen-terminated, i.e., the first structural layer 1 in the second region S2 is hydrogen-terminated using a hydrogen-terminated (H-Terminated) technique. The second electrode structure includes a second source 74, a second gate 75, and a second drain 76. The second electrode structure is disposed on the first structural layer 1 in the second region S2 and is located on the same side of the first structural layer 1 as the first electrode structure. The second source 74 and the second drain 76 can be fabricated using a method similar to that used for the first source 71 and the first drain 73. The second gate 75 can be fabricated using a method similar to that used for the first gate 72.

[0086] Here, hydrogen termination technology is used to hydrogen-terminate the first structural layer 1 (i.e., diamond material) of the second region S2, so that a P-type semiconductor can be formed on the surface of the material. This technology utilizes the principles of electron exchange between materials and the use of surface acceptor doping with high electron affinity (such as water molecules). By performing hydrogen plasma treatment on the surface of diamond, for example, a higher two-dimensional hole concentration and mobility can be generated. Transistors made by this mechanism are called hydrogen-terminated diamond field-effect transistors (H-Terminated Diamond FETs). There are currently a variety of hydrogen termination technologies, generally using microwave plasma generated in H2 (hydrogen) or D2 (deuterium). In the process of diamond hydrogen termination, the adjustable parameters are gas pressure, microwave power and time, for example, the pressure range is 50-300 Torr, the microwave power is 1-10kW, and the time is 1-20min. The production steps can also be carried out step by step, for example, first under low pressure and low power conditions, and then under high pressure and high power conditions. By optimizing the process parameters, a diamond surface with a high two-dimensional hole concentration and a high hole rate can be obtained.

[0087] After the hydrogen termination treatment, two-dimensional vacancy gas is formed on the surface of the first structural layer 1 in the second region S2 , and the two-dimensional vacancy gas has a relatively high concentration and mobility.

[0088] 1 , in the second region S2 , a gate dielectric layer 3 may be provided on the surface of the first structure layer 1 at least between the second gate 75 and the first structure layer 1 .

[0089] The gate dielectric layer 3 may be made of one or more materials such as Al2O3, SiO2, MoO3, WO3, ZrO2, AlN, TiOx, HfO2, LaAlO3, and Ta2O5. The gate dielectric layer 3 may be formed by atomic layer deposition, metal organic chemical vapor deposition, or magnetron sputtering.

[0090] These oxides pull electrons out of the diamond, forming a two-dimensional gas of holes.

[0091] 1 , in some embodiments, the first drain 73 is connected to the second source 74 , and the first gate 72 is connected to the second gate 75 , forming an integrated circuit that includes an N-type transistor based on a two-dimensional electron gas and a P-type transistor based on a two-dimensional hole gas.

[0092] 1 , in some embodiments, an isolation zone 101 is provided on a portion of the first structural layer 1 that is not covered by the second structural layer 2. The isolation zone 101 is used to electrically isolate the first region S1 from the second region S2.

[0093] In some embodiments, the isolation zone 101 extends inward from the surface of the first structural layer 1 (i.e., the surface in contact with the second structural layer 2), and the depth h of the isolation zone 101 is, for example, 2 nm to 20 nm. The width w of the isolation zone 101 is, for example, 0.1 μm to 5 μm.

[0094] The isolation zone 101 can be formed by etching, oxygen plasma treatment, or ion implantation.

[0095] Based on the above description of semiconductor device 100, first region S1 forms an N-type transistor based on the two-dimensional electron gas. This N-type transistor formed in first region S1 is similar to an NMOS transistor. Second region S2 forms a P-type transistor based on the two-dimensional hole gas. This P-type transistor formed entirely in second region S2 is similar to a PMOS transistor. Semiconductor device 100 as a whole forms a CMOS device or integrated circuit that integrates an N-type transistor formed by the two-dimensional electron gas in the first region and a P-type transistor formed by the two-dimensional hole gas in the second region.

[0096] FIG2 is a cross-sectional view of another semiconductor device 200 provided in accordance with an embodiment of the present application. Referring to FIG2 , compared to the semiconductor device 100 shown in FIG1 , the semiconductor device 200 includes, in addition to a first structure layer 1, a second structure layer 2, a first electrode structure, a second electrode structure, and the like, a cap layer 4 located in a first region S1 to protect the second structure layer 2. The cap layer 4 is disposed on (i.e., grown on) a surface of the second structure layer 2 facing away from the first structure layer 1.

[0097] It can be understood that the cap layer 4 can cover part or all of the surface of the second structural layer 2 .

[0098] The material of cap layer 4 can be GaN. The following description uses GaN as an example. Of course, other materials are also possible, such as silicon nitride or AlGaN with a low Al content (AlGaN with an Al content of less than 0.2). Combinations of GaN and silicon nitride, or AlGaN and silicon nitride, are also possible. The thickness of cap layer 4 can be, for example, 2 nm to 20 nm.

[0099] In this embodiment, the cap layer 4 covers a portion of the surface of the second structure layer 2 in the first region S1. Specifically, the cap layer 4 is absent from the areas where the first source electrode 71 and the first drain electrode 73 are located. A portion of the first source electrode 71 is located on the surface of the second structure layer 2 facing away from the first structure layer 1, while another portion penetrates the second structure layer 2 and contacts the surface of the first structure layer 1. The first drain electrode 73 is similarly configured. The first gate electrode penetrates the cap layer 4 and contacts the surface of the second structure layer 2.

[0100] Of course, in other embodiments, the regions where the first source electrode 71 and the first drain electrode 73 are disposed have a cap layer 4, with a portion of the first source electrode 71 located on the surface of the cap layer facing away from the first structural layer 1, and another portion penetrating the cap layer and extending into the second structural layer 2; a portion of the first drain electrode 73 located on the surface of the cap layer facing away from the first structural layer 1, and another portion penetrating the cap layer and extending into the second structural layer 2. Alternatively, in still other embodiments, a portion of the first source electrode 71 located on the surface of the cap layer facing away from the first structural layer 1, and another portion penetrating the cap layer and the second structural layer 2, contacting the surface of the first structural layer 1; a portion of the first drain electrode 73 located on the surface of the cap layer facing away from the first structural layer 1, and another portion penetrating the cap layer and the second structural layer 2.

[0101] The other structures of the semiconductor device 200 can refer to the above corresponding description.

[0102] FIG3 is a cross-sectional view of another semiconductor device 300 provided in accordance with an embodiment of the present application. Referring to FIG2 , the semiconductor device 300 differs from the semiconductor device 200 shown in FIG2 in that, in this embodiment, a portion of the first gate 72 is disposed on a surface of the cap layer 4 facing away from the first structural layer 1 , a portion extends through the cap layer 4 , and another portion extends partially through the second structural layer 2 .

[0103] In this embodiment, the first gate 72 penetrates a portion of the depth of the second structural layer 2, so that there is a certain distance between the first gate 72 and the bottom surface of the second structural layer 2. For example, as shown in Figure 3, the distance between the bottom end of the first gate 72 and the bottom surface of the second structural layer 2 is, for example, 2nm-15nm, so as to improve the gate's control ability over the two-dimensional electron gas while being able to form sufficient two-dimensional electron gas in the second structural layer.

[0104] FIG4 is a cross-sectional view of another semiconductor device 400 provided in accordance with an embodiment of the present application. Referring to FIG4 , compared to the semiconductor device 100 shown in FIG1 , the semiconductor device 400 includes, in addition to the first structure layer 1 and the second structure layer 2, a substrate (i.e., a substrate layer) 5. The substrate 5 is located on a surface of the first structure layer 1 facing away from the second structure layer 2.

[0105] The material of the substrate 5 can be silicon (including SOI), silicon carbide, sapphire, etc.

[0106] In this embodiment, the thickness of the first structural layer 1 is, for example, 0.2 um to 10 um.

[0107] The thickness of the second structural layer 2 is, for example, 2 nm to 30 nm. The specific thicknesses of the first structural layer 1 and the second structural layer 2 can be set according to specific circumstances.

[0108] The present application further provides a semiconductor wafer, which includes a plurality of chips arranged in an array, each chip integrating a plurality of the semiconductor devices described above. For example, please refer to FIG6 , the semiconductor wafer 1000 shown in FIG6 , and the semiconductor wafer 1000 has a plurality of chips 1001 arranged in an array. A certain number of the aforementioned device units (i.e., the aforementioned semiconductor devices) are integrated on the chip 1001 to form an integrated circuit, i.e., a CMOS integrated circuit formed by the aforementioned N-type transistors based on two-dimensional electron gas and the P-type transistors based on two-dimensional hole gas, to realize various different logic functions and meet different product performance and application requirements. As shown in FIG6 , the figure also illustrates a schematic diagram of a CMOS logic circuit unit fabricated on the chip 1001.

[0109] Referring to FIG. 7 , and in combination with FIG. 1 to FIG. 4 when necessary, the present application further provides a method for manufacturing a semiconductor device, which includes the following steps S101 to S109:

[0110] In step S101, a first structural layer is formed; the material of the first structural layer includes single crystal diamond;

[0111] In step S103, a second structural layer is formed, wherein the second structural layer is located on the first structural layer and in the first region, and forms a heterojunction structure with the first structural layer located in the first region; wherein the material of the second structural layer includes a single crystal AlN thin film or a doped single crystal AlN thin film;

[0112] In step S105, hydrogen termination treatment is performed on the first structural layer located in the second region;

[0113] In step S107, electrically isolating the portion of the first structural layer located in the first area and the portion located in the second area;

[0114] In step S109, a first electrode structure and a second electrode structure are generated; wherein the first electrode structure includes a first source, a first gate and a first drain, and the first electrode structure is arranged in the first region and at least partially located on a side of the second structure layer away from the first structure layer; the second electrode structure includes a second source, a second gate and a second drain, and the second electrode structure is arranged on the first structure layer and located in the second region, and is located on the same side of the first structure layer as the first electrode structure.

[0115] First, referring to FIG. 8 to FIG. 17 , the formation of a semiconductor device 100 is described as an example.

[0116] As shown in FIG. 8 , in step S101 , a first structure layer 1 is formed.

[0117] In some embodiments, the first structural layer 1 is formed using a high pressure and high temperature (HPHT) method.

[0118] In some other embodiments, the first structure layer 1 is formed by a chemical vapor deposition (CVD) method, such as a PECVD method or a MPCVD method.

[0119] As shown in FIG9 to FIG11 , step S103 can be implemented by the following steps S1031 and S1032:

[0120] As shown in FIG. 9 , in step S1031 , a second structural material layer 20 is formed on the surface of the first structural layer 1 .

[0121] The thickness of the second structural material layer 20 is, for example, in the range of 2 nm to 30 nm.

[0122] There are many methods for generating the second structural material layer 20, the most commonly used method being metal organic chemical vapor deposition (MOCVD). Generally, trimethylaluminum (TMAl, C3H9Al) and ammonia (NH3) are used as aluminum source and nitrogen source, respectively, and hydrogen is used as carrier gas. High-quality single-crystal aluminum nitride thin films can be grown by adjusting the pressure, temperature, and gas flow rate of the reactor. In order to reduce the stress and dislocation caused by the lattice mismatch between the diamond material and the aluminum nitride material, a layer of amorphous thin film, such as silicon oxide, silicon nitride, silicon oxynitride, etc., can be grown before growing the AlN film. Growth methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical deposition (PVD), etc., with a thickness of 0.5-5nm. In order to further increase the two-dimensional electron gas concentration and mobility, AlN can be doped to increase the piezoelectric coefficient of the material and thereby enhance the piezoelectric polarization effect. The production method involves adding a Sc-containing MO source gas, tris(cyanodifenyl)scandium (chemical formula: C15H15Sc), to the AlN film during the aforementioned AlN growth process. This allows for simultaneous scandium doping, forming a ScAlN film. The doping concentration can range from 5% to 50%, or even higher, depending on the specific application requirements.

[0123] The second structural material layer 20 can also be generated by molecular beam epitaxy (MBE) or plasma induced molecular beam (PIMBE), using a conventional evaporation source for Al and a radio frequency plasma source to generate nitrogen radicals, thereby growing a high-quality single-crystal AlN film on the diamond surface. In order to further improve the concentration and mobility of the two-dimensional electron gas, AlN can be doped to increase the piezoelectric coefficient of the material and thereby enhance the piezoelectric polarization effect. The production method is that, in the above-mentioned process of growing AlN, in addition to the Al source, an Sc evaporation source is added to form a ScAlN material. It is also possible to use only one evaporation source, that is, to use an ScAl alloy that has been prepared in a certain proportion, and react with the nitrogen radicals generated by the radio frequency plasma source to form a ScAlN film, that is, a Sc-doped AlN film. The doping concentration can be 5-50%, or even higher, depending on the ratio of the ScAl alloy material.

[0124] In step S1032 , the portion of the second structural material layer 20 located in the second region S2 is removed to form the second structural layer 2 .

[0125] Specifically, as shown in FIG. 10 and FIG. 11 , a photolithography process may be performed on the surface of the second structural material layer 20 located in the first region S1 , and then the second structural material layer 20 located in the second region S2 may be etched to form the second structural layer 2 .

[0126] Referring to FIG. 12 , in step S105 , the first structural layer 1 located in the second region S2 is subjected to hydrogen termination treatment.

[0127] Here, hydrogen termination technology is used to hydrogen-terminate the first structural layer 1 (i.e., diamond material) of the second region S2, so that a P-type semiconductor can be formed on the surface of the material. This technology utilizes the principles of electron exchange between materials and the use of surface acceptor doping with high electron affinity (such as water molecules). By performing hydrogen plasma treatment on the surface of diamond, for example, a high two-dimensional hole concentration and mobility can be generated. Transistors made by this mechanism are called hydrogen-terminated diamond field-effect transistors (H-Terminated Diamond FETs). There are currently a variety of hydrogen termination technologies, generally achieved using microwave plasma generated in H2 (hydrogen) or D2 (deuterium). In the diamond hydrogen termination process, the adjustable parameters are gas pressure, microwave power, and time, for example, the pressure range is 50-300 Torr, the microwave power is 1-10kW, and the time is 1-20 min. The production steps can also be carried out step by step, for example, first under low pressure and low power conditions, and then under high pressure and high power conditions. By optimizing the process parameters, a diamond surface with a high two-dimensional hole concentration and a high hole rate can be obtained.

[0128] Referring to FIG. 13 , for a semiconductor device having a gate dielectric layer 3 , after step S105 , the method further includes step S106 :

[0129] A gate dielectric layer 3 is formed on the surface of the first structure layer 1 located in the second region S2 .

[0130] The gate dielectric layer 3 may be made of one or more materials such as Al2O3, SiO2, MoO3, WO3, ZrO2, AlN, TiOx, HfO2, LaAlO3, and Ta2O5. The gate dielectric layer 3 may be formed by atomic layer deposition, metal organic chemical vapor deposition, or magnetron sputtering.

[0131] In step S107 , the portion of the first structural layer 1 located in the first area S1 and the portion located in the second area S2 are electrically isolated.

[0132] 14 , specifically, in this step, an isolation tape 101 may be provided on the portion of the first structural layer 1 not covered by the second structural layer 2. The isolation tape 101 is used to electrically isolate the first region S1 from the second region S2.

[0133] In some embodiments, the isolation zone 101 extends inward from the surface of the first structural layer 1 (i.e., the surface in contact with the second structural layer 2), and the depth h of the isolation zone 101 is 2 nm to 20 nm. The width w of the isolation zone 101 is 0.1 μm to 5 μm.

[0134] The isolation zone 101 can be formed by etching, oxygen plasma treatment, or ion implantation.

[0135] Please refer to Figures 15 and 16. In step S109, a first electrode structure and a second electrode structure are generated; wherein, the first electrode structure includes a first source 71, a first gate 72 and a first drain 73, and the first electrode structure is arranged in the first region S1 and is at least partially located on the side of the second structure layer 2 away from the first structure layer 1; the second electrode structure includes a second source 74, a second gate 75 and a second drain 76, and the second electrode structure is arranged on the first structure layer 1 and is located in the second region S2, and is located on the same side of the first structure layer 1 as the first electrode structure.

[0136] In this embodiment, the first electrode structure is generated first and then the second electrode structure is generated. In other embodiments, the order of the first electrode structure and the second electrode structure can be reversed, or they can be generated simultaneously.

[0137] The specific generation of the first electrode structure and the second electrode structure can refer to the relevant description of the above structural embodiment, which will not be repeated here.

[0138] Referring to FIG. 17 , after generating the first electrode structure and the second electrode structure in step S109, the method further includes step S110:

[0139] The first drain electrode 73 is connected to the second source electrode 74 , and the first gate electrode 72 is connected to the second gate electrode 75 .

[0140] Metal wires may be used to connect the first drain 73 to the second source 74 , and the first gate 72 to the second gate 75 .

[0141] For a semiconductor device having a cap layer, such as shown in FIG. 2 and FIG. 3 , correspondingly, after forming the second structure layer 2 in step S103 , the method includes the following step S104 :

[0142] In step S104 , a cap layer 4 is formed on a surface of the second structural layer 2 facing away from the first structural layer 1 .

[0143] The cap layer 4 can be, for example, gallium nitride or silicon nitride. The cap layer 4 can also be AlGaN with a low Al content, such as AlGaN with an Al content of less than 0.2. The thickness of the cap layer 4 can range from 2 nm to 20 nm, for example.

[0144] Cap layer 4 can be formed using a variety of methods. For example, a commonly used method for forming a GaN-based cap layer is Metal Organic Chemical Vapor Deposition (MOCVD). Trimethylgallium (TMGa, C3H9Ga) and ammonia (NH3) are typically used as the gallium and nitrogen sources, respectively, with hydrogen as the carrier gas. High-quality single-crystalline gallium nitride thin films can be grown by adjusting the reactor pressure, temperature, and gas flow rates.

[0145] It should be noted that, in this embodiment, the first structural layer 1 serves as a substrate.

[0146] Referring to FIG. 4 , in some other embodiments, for a semiconductor device in which the first structure layer 1 does not serve as a substrate, before forming the first structure layer 1 , the method includes the following step S1001:

[0147] In step S1001, a substrate 5 is provided;

[0148] The step S101 of forming the first structural layer 1 includes:

[0149] A first structural layer 1 is formed on the substrate 5 .

[0150] By optimizing the process variables for preparing the first structural layer 1 (including the reaction gas pressure and concentration, substrate temperature, and sample stage), the growth quality of the first structural layer 1 (e.g., diamond) can be optimized and its growth rate increased. The inventors have found that the thickness of the generated first structural layer 1 is 0.2um-10um. Preferably, the MPCVD method can be used, with the following process conditions: power of 1kW-10kW, pressure of 5kPa-200kPa, gas ratio of 1-5% (N2 / CH4), and temperature of 1000°C-1500°C.

[0151] When forming the first structural layer 1 , the substrate 5 may preferably be mounted on a molybdenum substrate holder to ensure that the temperature of the entire substrate is uniform, so that the thickness of different regions of the formed first structural layer 1 is relatively consistent.

[0152] For a semiconductor device having a substrate 5, after providing the substrate 5, the method may optionally include:

[0153] Polishing and cleaning the surface of the substrate 5;

[0154] The forming of the first structural layer 1 on the substrate 5 includes:

[0155] A first structural layer 1 is formed on the surface of the polished and cleaned substrate 5 .

[0156] The polishing methods here include mechanical polishing, thermochemical polishing, electrospark polishing, laser polishing, ion beam polishing and the like.

[0157] Here, cleaning can be performed by ultrasonic cleaning with acetone or other solutions.

[0158] Since the material of the substrate 5 and the material of the first structure layer 1 have different lattice constants and thermal expansion coefficients, the difference in lattice constants will cause lattice mismatch between the substrate 5 and the first structure layer 1, resulting in dislocation defects; at the same time, lattice mismatch will also cause stress in the film layer and cause problems such as film warping and cracking. In addition, the material of the substrate 5 and the material of the first structure layer 1 have different thermal expansion coefficients. During the preparation of the semiconductor device 30, residual stress is easily generated in the film. Specifically, a buffer layer can be set on the substrate to eliminate or reduce defects such as film dislocation, warping and cracking caused by the different lattice constants and thermal expansion coefficients of the substrate 5 and the first structure layer 1, which helps to improve the performance of the semiconductor device.

[0159] For a semiconductor device having a substrate 5 , a buffer layer may be further provided between the substrate 5 and the first structure layer 1 .

[0160] Accordingly, after providing the substrate 5 and before forming the first structure layer 1, the method may further include:

[0161] A buffer layer is formed on the substrate 5 .

[0162] In this application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0163] Those skilled in the art will appreciate that the embodiments described above in conjunction with the accompanying drawings are merely preferred embodiments, and the implementation of this application is not limited to these embodiments. Any changes or substitutions conceived by those skilled in the art based on the disclosure of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: The method has a first region and a second region, comprising: A first structural layer, wherein the material of the first structural layer comprises single crystal diamond, and a portion of the first structural layer located in the first region and a portion of the first structural layer located in the second region are electrically isolated; wherein the portion of the first structural layer located in the second region is subjected to hydrogen termination treatment; A second structural layer is provided on the first structural layer and is located in the first region, and the second structural layer and a portion of the first structural layer located in the first region form a heterojunction structure; wherein the material of the second structural layer is a single crystal AlN film or a doped single crystal AlN film; A first electrode structure, comprising a first source, a first gate and a first drain, wherein the first electrode structure is disposed in the first region and at least partially located on a side of the second structure layer away from the first structure layer; The second electrode structure includes a second source, a second gate and a second drain. The second electrode structure is disposed on the first structure layer and located in the second region, and is located on the same side of the first structure layer as the first electrode structure.

2. The semiconductor device according to claim 1, wherein The first drain is connected to the second source, and the first gate is connected to the second gate.

3. The semiconductor device according to claim 1, wherein The first structural layer serves as a substrate; or, The semiconductor device includes a substrate, which is located on a surface of the first structure layer facing away from the second structure layer.

4. The semiconductor device according to claim 1, wherein If the first structural layer is used as a substrate, the thickness of the first structural layer is 100 μm-500 μm; if the semiconductor device includes other layers in contact with the first structural layer as a substrate, the thickness of the first structural layer is 0.2 um-10 um; and / or, The thickness of the second structural layer is 2nm-30nm.

5. The semiconductor device according to claim 1, wherein: The first structure layer is used as a channel layer of the first region, the second structure layer is used as a barrier layer of the first region, and the semiconductor device includes: The cap layer disposed in the first region is disposed on a surface of the second structural layer away from the first structural layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The semiconductor device is not provided with a cap layer, Wherein, the first source electrode and the first drain electrode are both arranged on a surface of the second structural layer away from the first structural layer; or, A portion of the first source electrode is located on a surface of the second structure layer away from the first structure layer, another portion of the first source electrode penetrates the second structure layer and contacts the surface of the first structure layer, and a portion of the first drain electrode is located on a surface of the second structure layer away from the first structure layer. on a surface of the second structural layer facing away from the first structural layer, and another portion penetrates through the second structural layer and contacts with a surface of the first structural layer; or The semiconductor device is provided with a cap layer, Wherein, the first source electrode and the first drain electrode are both arranged on a surface of the cap layer away from the first structural layer; or, A portion of the first source electrode is located on a surface of the cap layer away from the first structural layer, and another portion thereof penetrates through a portion of the cap layer and the second structural layer; a portion of the first drain electrode is located on a surface of the cap layer away from the first structural layer, and another portion thereof penetrates through a portion of the cap layer and the second structural layer; or, Part of the first source electrode is located on the surface of the cap layer away from the first structural layer, and another part penetrates the cap layer and the second structural layer and contacts with the surface of the first structural layer; part of the first drain electrode is located on the surface of the cap layer away from the first structural layer, and another part penetrates the cap layer and the second structural layer.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The semiconductor device is not provided with a cap layer, Wherein, the first gate is arranged on a surface of the second structure layer away from the first structure layer; or, A portion of the first gate is located on a surface of the second structure layer away from the first structure layer, and another portion thereof penetrates a portion of the depth of the second structure layer; The semiconductor device is provided with a cap layer, The first gate penetrates the cap layer and contacts the surface of the second structure layer; or A portion of the first gate is disposed on a surface of the cap layer away from the first structural layer, and another portion thereof penetrates through a portion of the cap layer and the second structural layer.

8. The semiconductor device according to claim 7, characterized in that If the first gate penetrates a portion of the depth of the second structure layer, the distance between the bottom end of the first gate and the bottom surface of the second structure layer is 2 nm-15 nm.

9. The semiconductor device according to claim 1, wherein: An isolation zone is provided at a portion of the first structural layer not covered by the second structural layer, and the isolation zone is used to electrically isolate the first region from the second region.

10. The semiconductor device according to claim 9, wherein: The isolation zone extends from the surface of the first structural layer in contact with the second structural layer into the first structural layer, the extension depth of the isolation zone is 2nm-20nm, and the width of the isolation zone is 0.1μm-5μm; and / or The isolation zone is formed by etching, oxygen plasma treatment or ion implantation.

11. The semiconductor device according to claim 1, wherein A two-dimensional electron gas is formed at an interface between the first structure layer and the second structure layer in the first region, and the first region forms an N-type transistor based on the two-dimensional electron gas; Two-dimensional hole gas is formed on the surface of the first structure layer in the second region, and the second region forms a P-type transistor based on the two-dimensional hole gas; The semiconductor device is a CMOS device or an integrated circuit which integrates an N-type transistor formed based on the two-dimensional electron gas in the first region and a P-type transistor formed based on the two-dimensional hole gas in the second region.

12. A semiconductor wafer, characterized in that: The invention comprises a plurality of chips arranged in an array, each chip integrating a plurality of semiconductor devices according to any one of claims 1 to 11.

13. A method for preparing a semiconductor device, characterized in that: include: forming a first structural layer; The material of the first structural layer includes single crystal diamond; forming a second structural layer, wherein the second structural layer is located on the first structural layer and in the first region, and forms a heterojunction structure with a portion of the first structural layer located in the first region; wherein the material of the second structural layer is a single crystal AlN film or a doped AlN film; Performing hydrogen termination treatment on a portion of the first structural layer located in the second region; Electrically isolating a portion of the first structural layer located in the first area from a portion located in the second area; A first electrode structure and a second electrode structure are generated; wherein the first electrode structure includes a first source, a first gate and a first drain, and is arranged in the first region and at least partially located on a side of the second structure layer away from the first structure layer; the second electrode structure includes a second source, a second gate and a second drain, and the second electrode structure is arranged on the first structure layer and located in the second region, and is located on the same side of the first structure layer as the first electrode structure.

14. The method for preparing a semiconductor device according to claim 13, wherein: After generating the first electrode structure and the second electrode structure, the method includes: The first drain is connected to the second source, and the first gate is connected to the second gate.

15. The method for preparing a semiconductor device according to claim 13, wherein: Before forming the first structural layer, the method includes: providing a substrate; The forming of the first structural layer comprises: The first structure layer is formed on the substrate.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: After providing the substrate, the method includes: Polishing and cleaning the surface of the substrate; The forming the first structural layer on the substrate comprises: The first structural layer is formed on the surface of the substrate after polishing and cleaning.

17. The method for preparing a semiconductor device according to claim 13, wherein: After forming the second structural layer, the method includes: A cap layer is formed on a surface of the second structural layer facing away from the first structural layer.

18. The method for preparing a semiconductor device according to claim 13, wherein: The electrically isolating a portion of the first structural layer located in the first area from a portion located in the second area includes: An isolation zone is provided on a portion of the first structural layer not covered by the second structural layer, and the isolation zone is used to electrically isolate the first region from the second region.

19. The method for preparing a semiconductor device according to claim 18, wherein: The isolation zone extends inward from the surface of the first structural layer in contact with the second structural layer, the extension depth of the isolation zone is 2nm-20nm, and the width of the isolation zone is 0.1μm-5μm; and / or The isolation zone is formed by etching, oxygen plasma treatment or ion implantation.

20. The method for preparing a semiconductor device according to claim 13, wherein: The forming of the second structural layer comprises: forming a second structural material layer on the first structural layer; The portion of the second structural material layer located in the second region is removed to form the second structural layer.

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