Repair circuit, repair cancellation method, and memory

Abstract

Embodiments of the present disclosure provide a repair circuit, a repair cancellation method, and a memory. The repair circuit comprises: an input circuit used for carrying out sampling processing on a current address signal on the basis of an activation signal to obtain a target address signal; an enable circuit used for carrying out sampling processing on the current address signal on the basis of the activation signal and a repair signal to obtain a first enable signal; a selection circuit used for selecting one of the first enable signal and a preset signal on the basis of a repair cancellation signal and outputting the selected signal as a second enable signal; and a matching circuit used for: when the second enable signal is the first enable signal, comparing a preset address signal with the target address signal and outputting a matching signal, and when the second enable signal is the preset signal, fixing the matching signal in a non-enabled state.

Description

Repair circuit, repair undo method and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application number 202310896798.1, application date July 20, 2023, and invention name “Repair Circuit, Repair Undo Method and Memory”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a repair circuit, a repair undo method, and a memory. Background Art

[0004] During normal use of a memory, some storage rows and / or columns may fail. In order to extend the life of the memory in the event of a failure of a storage row and / or column, a post-package repair (PPR) method is used to repair the storage rows and / or columns of the memory. Specifically, redundant storage rows and / or columns can be used to replace the failed storage rows and / or columns. The PPR method includes soft post-package repair (SPPR) and hard post-package repair (HPPR), where SPPR is a temporary repair and HPPR is a permanent repair.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a repair circuit, a repair undo method, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a repair circuit, comprising:

[0008] An input circuit, configured to receive an activation signal and a current address signal, and sample the current address signal according to the activation signal to obtain a target address signal;

[0009] an enabling circuit, configured to receive the current address signal, the activation signal, and the repair signal, and sample the current address signal according to the activation signal and the repair signal to obtain a first enabling signal;

[0010] a selection circuit configured to receive a repair cancellation signal, the first enable signal, and a preset signal, and select one of the first enable signal and the preset signal according to the repair cancellation signal and output it as a second enable signal;

[0011] A matching circuit is configured to receive the target address signal and the second enable signal, compare a preset address signal with the target address signal when the second enable signal is the first enable signal, and output a matching signal; and fix the matching signal in a non-enabled state when the second enable signal is the preset signal.

[0012] In some embodiments, the input circuit includes a first sampling circuit, an input terminal of the first sampling circuit is used to receive the current address signal, and a clock terminal of the first sampling circuit is used to receive the activation signal; wherein:

[0013] The first sampling circuit is configured to sample the current address signal according to the activation signal to generate the target address signal when the activation signal is in an enabled state;

[0014] The target address signal includes an n-bit target address, where n is an integer greater than 0.

[0015] In some embodiments, the enabling circuit includes a first logic circuit and a second sampling circuit, the output terminal of the first logic circuit is connected to the clock terminal of the second sampling circuit, and the input terminal of the second sampling circuit is used to receive the current address signal; wherein:

[0016] The first logic circuit is configured to receive the activation signal and the repair signal, perform logic processing on the activation signal and the repair signal, and generate a trigger signal; wherein, when both the activation signal and the repair signal are in an enabled state, the trigger signal is in an enabled state;

[0017] The second sampling circuit is configured to receive the trigger signal and the current address signal, sample the current address signal according to the trigger signal, and generate the first enable signal.

[0018] In some embodiments, the first logic circuit includes a first AND gate; wherein:

[0019] The first input terminal of the first AND gate is used to receive the activation signal;

[0020] The second input terminal of the first AND gate is used to receive the repair signal;

[0021] The output terminal of the first AND gate is connected to the clock terminal of the second sampling circuit for outputting the trigger signal.

[0022] In some embodiments, the selection circuit includes a selector, wherein a first input terminal of the selector is used to receive the preset signal; a second input terminal of the selector is connected to the output terminal of the enable circuit, and is used to receive the first enable signal; a control terminal of the selector is used to receive the repair cancellation signal; and an output terminal of the selector is connected to the matching circuit; wherein:

[0023] The selector is configured to select the first enable signal as the second enable signal when the repair cancel signal has a first value, or to select the preset signal as the second enable signal when the repair cancel signal has a second value.

[0024] In some embodiments, the matching circuit includes a third sampling circuit, a latch circuit, a comparison circuit, and a second logic circuit; wherein:

[0025] The third sampling circuit is configured to receive the target clock signal and the second enable signal, sample and latch the second enable signal according to the target clock signal, and generate a third enable signal;

[0026] The latch circuit is configured to receive the target clock signal, sample and latch the preset address signal according to the target clock signal, and generate a first address signal;

[0027] The comparison circuit is configured to receive the target address signal and the first address signal, compare the target address signal with the first address signal, and generate a comparison signal;

[0028] The second logic circuit is used to receive the third enable signal and the comparison signal, and generate the matching signal according to the comparison signal when the third enable signal is in an enabled state; and fix the matching signal in a disabled state when the third enable signal is in a disabled state.

[0029] In some embodiments, the preset address signal includes an n-bit preset address, the first address signal includes an n-bit first address, the comparison signal includes an n-bit comparison sub-signal, the latch circuit includes n sampling sub-circuits, and the comparison circuit includes n comparison sub-circuits; wherein:

[0030] The i-th sampling sub-circuit is configured to receive the target clock signal and the i-th preset address, sample and latch the i-th preset address according to the target clock signal, and generate the i-th first address;

[0031] The i-th comparison sub-circuit is used to receive the i-th target address and the i-th first address, compare the i-th target address with the i-th first address, and generate an i-th comparison sub-signal, where i is an integer greater than 0 and less than or equal to n.

[0032] In some embodiments, the i-th comparison sub-circuit comprises an i-th XNOR gate; wherein:

[0033] The first input terminal of the i-th XNOR gate is connected to the output terminal of the input circuit, and is used for receiving the i-th target address;

[0034] The second input terminal of the i-th XNOR gate is connected to the output terminal of the i-th sampling sub-circuit, and is used to receive the i-th first address;

[0035] The output terminal of the i-th XNOR gate is used to output the i-th comparison sub-signal.

[0036] In some embodiments, the second logic circuit includes a second AND gate, the second AND gate including a first input terminal and n second input terminals; wherein:

[0037] The first input terminal of the second AND gate is used to receive the third enable signal;

[0038] The i-th second input terminal of the second AND gate is used to receive the i-th comparison sub-signal;

[0039] The output terminal of the second AND gate is used to output the matching signal.

[0040] In some embodiments, the repair circuit further includes a third logic circuit, wherein:

[0041] The third logic circuit is configured to receive the first clock signal and the second clock signal, perform logic processing based on the first clock signal and the second clock signal, and generate the target clock signal;

[0042] The first clock signal is generated according to the repair signal and the initial clock signal, and the second clock signal is generated according to the repair cancellation signal and the initial clock signal.

[0043] In some embodiments, the repair signal is a soft-encapsulated repair signal.

[0044] In some embodiments, the third logic circuit includes a first OR gate, wherein:

[0045] The first input terminal of the first OR gate is used to receive the first clock signal;

[0046] The second input terminal of the first OR gate is used to receive the second clock signal;

[0047] The output end of the first OR gate is used to output the target clock signal.

[0048] In some embodiments, a level state of the preset signal is opposite to a level state of the first enable signal in the enabled state.

[0049] In a second aspect, an embodiment of the present disclosure provides a repair and undo method, comprising:

[0050] receiving an activation signal and a current address signal through an input circuit, sampling and processing the current address signal according to the activation signal to obtain a target address signal;

[0051] receiving the current address signal, the activation signal, and the repair signal through an enabling circuit, and sampling and processing the current address signal according to the activation signal and the repair signal to obtain a first enabling signal;

[0052] receiving a repair cancellation signal, the first enable signal, and a preset signal through a selection circuit, and selecting one of the first enable signal and the preset signal to output as a second enable signal according to the repair cancellation signal;

[0053] The target address signal and the second enable signal are received through a matching circuit, and when the second enable signal is the first enable signal, the preset address signal is compared with the target address signal to output a matching signal; and when the second enable signal is the preset signal, the matching signal is fixed in a non-enabled state.

[0054] In a third aspect, an embodiment of the present disclosure provides a memory comprising a repair circuit as described in any one of the first aspects.

[0055] The present disclosure provides a repair circuit, a repair reversal method, and a memory. The repair circuit includes: an input circuit for receiving an activation signal and a current address signal, and sampling and processing the current address signal according to the activation signal to obtain a target address signal; an enable circuit for receiving the current address signal, the activation signal, and the repair signal, and sampling and processing the current address signal according to the activation signal and the repair signal to obtain a first enable signal; a selection circuit for receiving a repair reversal signal, the first enable signal, and a preset signal, and selecting one of the first enable signal and the preset signal to output as a second enable signal according to the repair reversal signal; a matching circuit for receiving the target address signal and the second enable signal, and comparing the preset address signal with the target address signal when the second enable signal is the first enable signal, and outputting a match signal; and fixing the match signal in a disabled state when the second enable signal is the preset signal. Thus, by adding a selection circuit to the repair circuit, when repair reversal is required, the preset signal is used as the enable signal of the matching circuit, fixing the match signal in a disabled state, thereby preventing redundant rows from being used to replace failed rows. Ultimately, the repair reversal function is achieved without making significant changes to the circuit, meeting standard requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 is a schematic diagram of the structure of an SPPR circuit provided by an embodiment of the present disclosure;

[0057] FIG2 is a schematic diagram of the structure of a repair circuit provided by an embodiment of the present disclosure;

[0058] FIG3 is a detailed structural diagram of a repair circuit provided by an embodiment of the present disclosure;

[0059] FIG4 is a schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

[0060] FIG5 is a flow chart of a repair and undo method provided by an embodiment of the present disclosure;

[0061] FIG6 is a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0064] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0065] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0066] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0067] Post Package Repair (PPR)

[0068] Soft Post Package Repair (SPPR);

[0069] Hard Post Package Repair (HPPR);

[0070] Dynamic Random Access Memory (DRAM);

[0071] D flip-flop (DFF);

[0072] Standard (SPEC);

[0073] Activation (ACT);

[0074] Row Address (RA);

[0075] Double Data Rate (DDR).

[0076] Referring to Figure 1 , a schematic diagram illustrating the structure of an SPPR circuit according to an embodiment of the present disclosure is shown. As shown in Figure 1 , the SPPR circuit 10 includes an AND gate A1, a flip-flop DFF_1, a flip-flop DFF_2, a fuse latch X, n fuse latches (fuse latch 0 to fuse latch n-1), n ​​XNOR gates (XNOR gate X0 to XN-1), and an AND gate A2. Where n is an integer greater than 0.

[0077] It should be noted that a memory (such as a DRAM) includes a memory array and a redundant memory array. When a row in the memory array fails, a redundant row in the redundant memory array can be used to replace the failed row. This replacement can be non-permanent (SPPR) or permanent (HPPR). In the embodiments of this disclosure, the focus is on SPPR.

[0078] As shown in Figure 1, fuse latches 0 through n-1 are used to latch the addresses of the failed row, FzRA 0 through FzRA n-1 (collectively referred to as FzRA<0:n-1>). Address FzRA<0:n-1> can be sent to fuse latches 0 through n-1 by another circuit or device. Alternatively, as shown in Figure 1, the input terminal D of each fuse latch is connected to the output terminal of flip-flop DFF_2. Flip-flop DFF_2 samples the address signal corresponding to the failed row to obtain address FzRA<0:n-1>, which is then sent to fuse latches 0 through n-1 for latching.

[0079] The flip-flop DFF_1 is used to sample the address RA of the accessed row according to the activation signal ACT to obtain n-bit address sampling signals RA0 to RAn-1 (collectively denoted as RA<0:n-1>). The address RA comes from the activation signal ACT, that is, the address RA is the address information carried by the activation signal ACT.

[0080] AND gate A1 performs an AND logic operation on the activation signal ACT and the post-soft package repair signal SPPR. The output signal of AND gate A1 serves as the clock signal for flip-flop DFF_2. DFF_2 samples the address RA and generates the enable signal EN only when both the activation signal ACT and the post-soft package repair signal SPPR are enabled.

[0081] As shown in Figure 1, the input terminal of each fuse latch is represented by D, and the output terminal is represented by Q. Fuse latch X samples the enable signal EN according to the latch clock signal LatClk, generating a repair enable signal FzEN, which is sent to AND gate A2. Fuse latch i-1 samples the address FzRA i-1 according to the latch clock signal LatClk, outputs the sampled signal from the output terminal Q, and sends it to the XNOR gate Xi-1. Here, i is an integer greater than 0 and less than or equal to n. The latch clock signal LatClk is generated based on the post-soft package repair signal SPPR. That is, when the post-soft package repair signal SPPR is enabled, the latch clock signal LatClk is valid, allowing fuse latch X and fuse latches 0 through n-1 to sample the signal received at the input terminal D according to the latch clock signal LatClk.

[0082] The EXCLUSIVE-OR gate Xi-1 compares the address RA i-1 output by the flip-flop DFF_1 with the signal sampled and latched by the fuse latch i-1 from the address FzRA i-1. If the two are the same, the EXCLUSIVE-OR gate Xi-1 outputs a logic 1; if the two are different, the EXCLUSIVE-OR gate Xi-1 outputs a logic 0. The output signal of each EXCLUSIVE-OR gate Xi-1 is transmitted to the AND gate A2, which also receives the address enable signal FzEN output by the fuse latch X.

[0083] Thus, if every FzRA i-1 and RA i-1 match (i.e., the two signals received by each XNOR gate Xi i-1 are identical), the outputs of all n XNOR gates are logic 1, indicating that the row corresponding to address RA is the failed row. Simultaneously, if the signal output by fuse latch X is also logic 1, a repair operation is required. Consequently, the match signal Ma output by AND gate A2 is logic 1, indicating that the redundant row should be used instead of the failed row to ensure normal operation of the memory.

[0084] That is, in the SPPR circuit 10 shown in FIG1 , the SPPR command can be used to generate a latch clock signal LatClk. This latch clock signal LatClk can be sent to the fuse latch of the corresponding memory bank to retain the repaired failed row address FzRA 0 to FzRA n-1. Subsequently, when the chip activates the row address, it will be compared with the retained failed row address FzRA 0 to FzRA n-1. If a match is successful, the row decoder will access the redundant row instead of the failed row. In addition, the fuse latch X retains the fuse enable information (EN). Therefore, only when EN = logic 1 is the retained address valid and address matching is performed when activated. Otherwise, the Ma (Match) signal will always remain low (logic 0).

[0085] The SPPR Undo SPEC standard was released later than SPPR. How to integrate SPPR Undo into the SPPR circuit while meeting the standard is a problem that needs to be solved.

[0086] Based on this, an embodiment of the present disclosure provides a repair circuit, comprising: an input circuit for receiving an activation signal and a current address signal, and sampling and processing the current address signal according to the activation signal to obtain a target address signal; an enable circuit for receiving the current address signal, the activation signal, and the repair signal, and sampling and processing the current address signal according to the activation signal and the repair signal to obtain a first enable signal; a selection circuit for receiving a repair override signal, a first enable signal, and a preset signal, and selecting one of the first enable signal and the preset signal to output as a second enable signal according to the repair override signal; a matching circuit for receiving the target address signal and a second enable signal, and when the second enable signal is the first enable signal, comparing the preset address signal with the target address signal and outputting a match signal; and when the second enable signal is the preset signal, fixing the match signal in a disabled state. Thus, by adding a selection circuit to the repair circuit, when repair override is required, the preset signal is used as the enable signal of the matching circuit, fixing the match signal in a disabled state, thereby preventing redundant rows from replacing failed rows. Ultimately, the repair override function is achieved without making significant changes to the circuit, meeting standard requirements.

[0087] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0088] In one embodiment of the present disclosure, referring to FIG2 , a schematic diagram of the structure of a repair circuit provided by the present disclosure is shown. As shown in FIG2 , the repair circuit 20 includes:

[0089] The input circuit 21 is used to receive the activation signal and the current address signal, and sample the current address signal according to the activation signal to obtain the target address signal;

[0090] The enabling circuit 22 is configured to receive a current address signal, an activation signal, and a repair signal, and sample and process the current address signal according to the activation signal and the repair signal to obtain a first enabling signal;

[0091] The selection circuit 23 is configured to receive a repair cancellation signal, a first enable signal, and a preset signal, and select one of the first enable signal and the preset signal according to the repair cancellation signal to output as a second enable signal;

[0092] The matching circuit 24 is used to receive the target address signal and the second enable signal, compare the preset address signal with the target address signal when the second enable signal is the first enable signal, and output a matching signal; and fix the matching signal in a non-enabled state when the second enable signal is the preset signal.

[0093] It should be noted that the repair circuit 20 may be an SPPR circuit, and correspondingly, the repair signal may be an SPPR repair signal (which may be denoted as SPPR CMD), and the repair undo signal may be a signal indicating the undoing of the SPPR operation (which may be denoted as SPPR Undo CMD). The disclosed embodiment improves the SPPR circuit 10 shown in FIG. 1 , adding a function of undoing the SPPR operation without significantly changing the SPPR circuit 10 to meet the requirements of the standard.

[0094] In this embodiment, SPPR is a method for quickly but temporarily repairing the row address of each bank group on a memory device (such as DDR5 DRAM), compared to HPPR, which takes longer but can permanently repair the row address.

[0095] SPPR Undo is a method of returning an SPPR resource to its unused state, much like a reset. The SPPR Undo command (repair undo command) undoes the previous SPPR and returns the SPPR resource to its unused state. After an SPPR Undo, the original row in the storage array appears in the memory map at its original location; if a repair was made, the memory was mapped to the redundant row used for the repair. After the repair is undone, the memory is mapped to the original failed row.

[0096] As shown in FIG2 , the activation signal is used to activate the corresponding storage address in the memory (such as a storage unit, row, column, memory bank, etc., with a row being used as an example in this embodiment), and the current address signal is used to locate the storage address. In other words, the activation signal and the current address signal correspond to each other.

[0097] The input circuit 21 is a circuit with sampling and latching functions. When receiving the activation signal and the current address signal, if the activation signal and the current address signal are valid signals, that is, the activation signal and the current address signal can successfully locate the row (or storage row) in the storage array, then the input circuit 21 will sample the current address signal according to the activation signal to obtain the target address signal.

[0098] The activation signal and the current address signal are also transmitted to the enable circuit 22, which also receives the repair signal. The enable circuit 22 also has sampling and latching functions. Thus, when the repair signal is enabled, the repair circuit 20 enters the repair operating state. The enable circuit 22 samples the current address signal based on the activation signal to generate a first enable signal.

[0099] The repair override signal indicates whether to cancel a repair operation. This signal controls the output of selection circuit 23, causing repair circuit 20 to perform a repair operation or a repair override operation. If the repair override signal is enabled, selection circuit 23 outputs a preset signal as the second enable signal. If the repair override signal is disabled, selection circuit 23 outputs the first enable signal as the second enable signal. The preset address signal corresponds to the failed address in the memory array that needs to be repaired (using a failed row as an example).

[0100] When the second enable signal is equal to the first enable signal, the repair operation is being performed normally. If the first enable signal is in the enabled state, the matching circuit 24 compares the preset address signal with the target address signal and outputs a match signal based on the comparison result. Specifically, if the preset address signal is the same as the current address signal, indicating that the row corresponding to the current address signal is a failed row, the matching signal is enabled, and the failed row is replaced by a redundant row for operation. If the preset address signal is different from the current address signal, indicating that the row corresponding to the current address signal is not a failed row, the matching signal is disabled, and the row corresponding to the current address signal operates normally.

[0101] The preset signal is always in the disabled state. When the second enable signal is the preset signal, it indicates that a repair undo operation is required, meaning that a redundant row does not need to be substituted for the failed row. At this time, the second enable signal is in the disabled state, and the match signal is always fixed in the disabled state, regardless of whether the preset address signal and the current address signal are identical. This way, even if the preset address signal and the current address signal are identical, indicating that the row corresponding to the current address signal is a failed row, the redundant row will not be substituted for the failed row, thus achieving the repair undo function.

[0102] It should also be noted that in the embodiment of the present disclosure, a high-level logic 1 is used as an enabled state and a low-level logic 0 is used as a disabled state. However, a high-level logic 1 may be used as a disabled state and a low-level logic 0 may be used as an enabled state. This is not limited to the above and is set in combination with the circuit.

[0103] In this way, for the first enable signal and the preset signal, since the preset signal is always in the disabled state, the level state of the preset signal is opposite to the level state of the first enable signal in the enabled state.

[0104] In a specific circuit implementation, see FIG3 , which shows a detailed structural diagram of a repair circuit provided by an embodiment of the present disclosure. As shown in FIG3 , the input circuit 21 includes a first sampling circuit 211 . The input terminal of the first sampling circuit 211 is used to receive the current address signal RA, and the clock terminal of the first sampling circuit 211 is used to receive the activation signal ACT.

[0105] The first sampling circuit 211 is configured to sample the current address signal RA according to the activation signal ACT to generate a target address signal RA<0:n-1> when the activation signal ACT is enabled;

[0106] The target address signal RA<0:n-1> includes an n-bit target address RA i-1, where n is an integer greater than 0, and i is an integer greater than 0 and less than or equal to n.

[0107] It should be noted that in the embodiment of the present disclosure, the first sampling circuit 211 can be implemented by a DFF (or other devices with sampling latch and other functions). Therefore, as shown in Figure 3, the first sampling circuit 211 is represented by DFF_1. The input terminal and clock terminal of the first sampling circuit 211 serve as the two input terminals of the input circuit 21, respectively, and the output terminal of the first sampling circuit 211 serves as the output terminal of the input circuit 21.

[0108] Wherein, RA represents the current address signal, and ACT represents the activation signal. When the activation signal ACT is in the enabled state, it indicates that it carries valid address information, that is, the current address signal RA is valid and can indicate a row in the memory array (here, the row address is used as an example. In other embodiments, it can also be a specific memory cell, column address, or even a memory bank, etc.). When the activation signal ACT is converted from the disabled state to the enabled state, it can form a rising edge, which is used to trigger the first sampling circuit 211. The first sampling circuit 211 samples the current address signal RA according to the activation signal ACT to obtain the target address signal RA<0:n-1>. The target address signal RA<0:n-1> includes an n-bit target address: RA0 to RAn-1.

[0109] Correspondingly, the current address signal may include an n-bit current address, and the first sampling circuit 211 may include n DFFs, each DFF receiving the activation signal ACT and a current address, performing sampling according to the activation signal ACT and the current address to generate a corresponding target address.

[0110] As shown in FIG3 , the enabling circuit 22 includes a first logic circuit 221 and a second sampling circuit 222 . The output of the first logic circuit 221 is connected to the clock terminal of the second sampling circuit 222 , and the input of the second sampling circuit 222 is used to receive the current address signal RA.

[0111] The first logic circuit 221 is configured to receive the activation signal ACT and the repair signal SPPR, perform logic processing on the activation signal ACT and the repair signal SPPR, and generate a trigger signal; wherein, when both the activation signal ACT and the repair signal SPPR are in an enabled state, the trigger signal is in an enabled state;

[0112] The second sampling circuit 222 is configured to receive a trigger signal and a current address signal RA, sample the current address signal RA according to the trigger signal, and generate a first enable signal EN1.

[0113] It should be noted that, as shown in FIG3 , in the embodiment of the present disclosure, the second sampling circuit 222 may also be implemented by a DFF (or other devices having functions such as sampling latching), and the repair signal may specifically be a repair signal after soft packaging. Therefore, as shown in FIG3 , the second sampling circuit 222 is represented by DFF_2, the repair signal is represented by SPPR, and EN1 represents the first enable signal.

[0114] Specifically, as shown in FIG3 , the first logic circuit 221 includes a first AND gate A1 ; wherein:

[0115] The first input terminal of the first AND gate A1 is used to receive the activation signal ACT;

[0116] The second input terminal of the first AND gate A1 is used to receive the repair signal SPPR;

[0117] The output terminal of the first AND gate A1 is connected to the clock terminal of the second sampling circuit 222 for outputting a trigger signal.

[0118] It should be noted that, as shown in FIG. 3 , the first input terminal and the second input terminal of the first AND gate A1 serve as two input terminals of the enabling circuit 22 , and the output terminal of the second sampling circuit 222 serves as the output terminal of the enabling circuit 22 .

[0119] The first logic circuit 221 is used to perform an AND logic operation on the activation signal ACT and the repair signal SPPR. The first logic circuit 221 can be implemented by an AND gate A1. Thus, when the activation signal ACT and the repair signal SPPR are both in the enabled state (logic 1), the trigger signal output by the first AND gate A1 is also in the enabled state; otherwise, the trigger signal is in the disabled state.

[0120] When the trigger signal transitions from the disabled state to the enabled state, a rising edge is generated, triggering the second sampling circuit 222. The second sampling circuit 222 can then sample the valid current address signal RA according to the trigger signal, obtain the first enable signal EN1, and latch the first enable signal EN1. Thus, the first enable signal EN1 maintains its state until the next rising edge of the trigger signal. Here, when the second sampling circuit 222 is sampling, if the current address signal RA is valid for indicating a row in the memory array, the second sampling circuit 222 can output the first enable signal EN1 in the enabled state; otherwise, the first enable signal EN1 is in the disabled state.

[0121] In this way, the embodiment of the present disclosure uses the result of the AND logic operation of the activation signal ACT and the repair signal SPPR as the clock of DFF_2, samples the current address signal RA to obtain the first enable signal EN1, and ensures that subsequent operations are performed only when the activation signal ACT and the current address signal RA are valid signals and can indicate a certain row, thereby avoiding the adverse effects of erroneous signals on the circuit.

[0122] As shown in FIG3 , the selection circuit 23 includes a selector MUX, wherein a first input terminal of the selector MUX is used to receive a preset signal GND; a second input terminal of the selector MUX is connected to an output terminal of the enable circuit 22 for receiving a first enable signal EN1; a control terminal of the selector MUX is used to receive a repair undo signal SPPR Undo; and an output terminal of the selector MUX is connected to a matching circuit 24.

[0123] The selector MUX is configured to select the first enable signal EN1 as the second enable signal EN2 when the repair undo signal SPPR Undo has a first value, or select the preset signal GND as the second enable signal EN2 when the repair undo signal SPPR Undo has a second value.

[0124] It should be noted that in the disclosed embodiment, the preset signal GND is always in the disabled state. Therefore, when the preset signal GND is selected as the second enable signal EN2, the second enable signal EN2 is in the disabled state. When a high-level logic 1 (represented as the first level state) represents the enable state and a low-level logic 0 (represented as the second level state) represents the disabled state, the preset signal is always in the logic 0 state. Therefore, the first input terminal of the selector MUX can be connected to the ground, and the preset signal can be represented by GND. In addition, SPPR Undo is used to represent the repair undo signal.

[0125] The first value may be a high-level logic 1, and the second value may be a low-level logic 0; or the first value may be a low-level logic 0, and the second value may be a high-level logic 1, which is not specifically limited.

[0126] In this way, when the repair undo signal SPPR Undo is effective (i.e., it is the first value, or in the enabled state), the preset signal GND is output as the second enable signal EN2, so that the second enable signal EN2 is maintained in the disabled state, thereby controlling the matching signal output by the matching circuit 24 to be fixed in the disabled state.

[0127] As shown in FIG3 , the matching circuit 24 includes a third sampling circuit 241 , a latch circuit 242 , a comparison circuit 243 and a second logic circuit 244 ; wherein:

[0128] The third sampling circuit 241 is configured to receive the target clock signal LatClk and the second enable signal EN2, sample and latch the second enable signal EN2 according to the target clock signal LatClk, and generate a third enable signal EN3;

[0129] The latch circuit 242 is configured to receive a target clock signal LatClk, sample and latch a preset address signal FzRA<0:n-1> according to the target clock signal LatClk, and generate a first address signal FA<0:n-1>;

[0130] The comparison circuit 243 is configured to receive the target address signal RA<0:n-1> and the first address signal FA<0:n-1>, compare the target address signal RA<0:n-1> with the first address signal FA<0:n-1>, and generate a comparison signal Com<0:n-1>.

[0131] The second logic circuit 244 is configured to receive the third enable signal EN3 and the comparison signal Com<0:n-1>, and to generate a match signal Ma according to the comparison signal Com<0:n-1> when the third enable signal EN3 is in an enabled state; and to fix the match signal Ma in a disabled state when the third enable signal EN3 is in a disabled state.

[0132] It should be noted that the third sampling circuit 241 is a circuit with sampling and latching functions. The third sampling circuit 241 samples and latches the second enable signal EN2 according to the target clock signal LatClk to obtain the third enable signal EN3. The third sampling circuit 241 can be a fuse latch (Fuse Latch), denoted as Fuse Latch X in FIG3 . The input terminal D of Fuse Latch X serves as the input terminal of the third sampling circuit 241 and is connected to the output terminal of the selector MUX for receiving the second enable signal EN2. The clock terminal of Fuse Latch X serves as the clock terminal of the third sampling circuit 241 for receiving the target clock signal LatClk. The output terminal Q of Fuse Latch X serves as the output terminal of the third sampling circuit 241 for outputting the third enable signal EN3.

[0133] It should also be noted that latch circuit 242 also has sampling and latching functions. Here, the preset address signal FzRA<0:n-1> includes n-bit preset addresses FzRA0 through FzRAn-1. The preset address signal FzRA<0:n-1> corresponds to a failed row in the memory array. These n-bit preset addresses can be sent to latch circuit 242 by another circuit or device and then latched by latch circuit 242. Alternatively, as shown in FIG3 , latch circuit 242 is connected to the output of second sampling circuit 222. In this case, the input of second sampling circuit 222 receives the address signal corresponding to the failed row (which, as can be appreciated, also consists of n bits). Second sampling circuit 222 samples the address signal of the failed row, obtains the n-bit preset addresses, and sends them to latch circuit 242 for latching.

[0134] It should also be noted that the preset address signal latched by the latch circuit 242 is not fixed but variable. For example, the latch circuit 242 latches the preset address signal corresponding to the first failed row. After the first failed row is repaired, the latch circuit 242 may also latch the preset address signal corresponding to the second failed row.

[0135] As shown in FIG3 , the latch circuit 242 and the comparison circuit 243 have the following characteristics: the preset address signal FzRA<0:n-1> includes an n-bit preset address FzRA i-1, the first address signal FA<0:n-1> includes an n-bit first address FA i-1, the comparison signal Com<0:n-1> includes an n-bit comparison sub-signal Com i-1, the latch circuit 242 includes n sampling sub-circuits 2421, and the comparison circuit 243 includes n comparison sub-circuits 2431; wherein:

[0136] The i-th sampling sub-circuit 2421 is configured to receive the target clock signal LatClk and the i-th preset address FzRA i-1, sample and latch the i-th preset address FzRA i-1 according to the target clock signal LatClk, and generate the i-th first address FA i-1;

[0137] The i-th comparison sub-circuit 2431 is used to receive the i-th target address RA i-1 and the i-th first address FA i-1, compare the i-th target address RA i-1 with the i-th first address FA i-1, and generate an i-th comparison sub-signal Com i-1, where i is an integer greater than 0 and less than or equal to n.

[0138] It should be noted that, as shown in Figure 3, the sampling sub-circuit 2421 is a circuit with sampling and latching functions. The input terminal D of the i-th sampling sub-circuit 2421 receives the i-th preset address FzRA i-1, the clock terminal of each sampling sub-circuit 2421 receives the target clock signal LatClk, and the output terminal Q of the i-th sampling sub-circuit 2421 outputs the i-th first address FA i-1.

[0139] The i-th sampling subcircuit 2421 samples and latches the corresponding i-th preset address FzRA i-1 according to the target clock signal LatClk, thereby obtaining the corresponding i-th first address FA i-1. Sampling subcircuit 2421 may be a fuse latch. In FIG3 , the fuse latch in the i-th sampling subcircuit 2421 is denoted as fuse latch i-1, and the n fuse latches in latch circuit 242 are denoted as fuse latch 0 through fuse latch n-1, respectively.

[0140] The comparison sub-circuit 2431 is a circuit with a comparison function. The i-th comparison sub-circuit 2431 receives the i-th target address RA i-1 and the i-th first address FA i-1. When the i-th target address RA i-1 and the i-th first address FA i-1 are the same, the comparison sub-signal Com i-1 output by the i-th comparison sub-circuit 2431 is a first value. When the i-th target address RA i-1 and the i-th first address FA i-1 are different, the comparison sub-signal Com i-1 output by the i-th comparison sub-circuit 2431 is a second value.

[0141] As shown in FIG3 , for the comparison circuit 243 and the second logic circuit 244 , in one implementation, the i-th comparison sub-circuit 2431 includes the i-th XNOR gate Xi-1; wherein:

[0142] A first input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal of the input circuit 21 for receiving the i-th target address RA i-1;

[0143] The second input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal Q of the i-th sampling sub-circuit 2421, for receiving the i-th first address FA i-1;

[0144] The output terminal of the i-th XNOR gate Xi-1 is used to output the i-th comparison sub-signal Com i-1.

[0145] The second logic circuit 244 includes a second AND gate A2, which includes a first input terminal and n second input terminals; wherein:

[0146] The first input terminal of the second AND gate A2 is used to receive the third enable signal EN3;

[0147] The i-th second input terminal of the second AND gate A2 is used to receive the i-th comparison sub-signal Com i-1;

[0148] The output terminal of the second AND gate A2 is used to output a matching signal Ma.

[0149] It should be noted that, as shown in FIG3 , taking the first sampling sub-circuit 2421 and the first comparison sub-circuit 2431 as an example, the output terminal Q of the fuse latch 0 is connected to the second input terminal of the X-OR gate X0, and the first input terminal of the X-OR gate X0 is connected to the output terminal of the input circuit 21. Thus, the first input terminal and the second input terminal of the X-OR gate X0 receive the first target address RA0 and the first first address FA0, respectively. If the first first address FA0 and the first target address RA0 are the same, the first comparison sub-signal Com0 output by the X-OR gate X0 is logic 1. If the first first address RA10 and the first target address RA0 are different, the first comparison sub-signal Com0 output by the X-OR gate X0 is logic 0.

[0150] The same applies to the remaining sampling sub-circuit 2421 and comparison sub-circuit 2431 , which will not be described in detail here.

[0151] If the first enable signal EN1 is in the enabled state and the first enable signal EN1 is output as the second enable signal EN2, the third enable signal EN3 is in the enabled state (logical 1). At the same time, if each first address and target address are identical, indicating that the first address signal and the target address signal are identical, then the n comparison sub-signals Com 0 to Com n-1 are all logical 1, and the n+1 signals received by the second AND gate A2 are all logical 1, so that the match signal Ma output by the second AND gate A2 is logical 1 (enabled state), and then the repair operation is performed, that is, the redundant row is used to replace the row corresponding to the current address signal. If the first address and target address are different, indicating that the first address signal and the target address signal are different, then the match signal Ma output by the second AND gate A2 is logical 0 (disabled state), and the row corresponding to the current address signal operates normally.

[0152] If the preset signal GND is output as the second enable signal EN2, the third enable signal EN3 is in the non-enabled state (logic 0); at this time, regardless of whether the first address signal and the target address signal are the same, in the signal received by the second AND gate A2, the third enable signal EN3 is always logic 0, so that the matching signal Ma output by the second AND gate A2 is always logic 0 (fixed in the non-enabled state); in this way, even if the first address signal and the target address signal are the same, the redundant row will not be used to replace the row corresponding to the current address signal, thereby realizing repair cancellation.

[0153] For the comparison circuit 243 and the second logic circuit 244, in another implementation, the i-th comparison sub-circuit includes the i-th XOR gate; wherein:

[0154] A first input terminal of the i-th XOR gate is connected to the output terminal of the input circuit for receiving the i-th target address;

[0155] The second input terminal of the i-th XOR gate is connected to the output terminal of the i-th sampling sub-circuit, and is used to receive the i-th first address;

[0156] The output terminal of the i-th XOR gate is used to output the i-th comparison sub-signal.

[0157] The second logic circuit includes a second NAND gate, and the second NAND gate includes a first input terminal and n second input terminals; wherein:

[0158] The first input terminal of the second NAND gate is used to receive a third enable signal;

[0159] The i-th second input terminal of the second NAND gate is used to receive the i-th comparison sub-signal;

[0160] The output terminal of the second NAND gate is used for outputting a matching signal.

[0161] It should be noted that the comparison sub-circuit can also be implemented by an XOR gate. In this case, the second logic circuit is implemented by a NAND gate, which can also achieve the same function as FIG3 , and will not be described in detail here.

[0162] Furthermore, for the target clock signal LatClk, in some embodiments, as shown in FIG3 , the repair circuit 20 further includes a third logic circuit 25 , wherein:

[0163] The third logic circuit 25 is configured to receive the first clock signal Clk1 and the second clock signal Clk2, perform logic processing on the first clock signal Clk1 and the second clock signal Clk2, and generate a target clock signal LatClk;

[0164] The first clock signal Clk1 is generated according to the repair signal SPPR and the initial clock signal, and the second clock signal Clk2 is generated according to the repair undo signal SPPR Undo and the initial clock signal.

[0165] Specifically, as shown in FIG3 , the third logic circuit 25 includes a first OR gate OR, wherein:

[0166] The first input terminal of the first OR gate OR is used to receive the first clock signal Clk1;

[0167] The second input terminal of the first OR gate OR is used to receive the second clock signal Clk2;

[0168] The output terminal of the first OR gate OR is used to output the target clock signal LatClk.

[0169] It should be noted that the third logic circuit 25 performs an OR logic operation on the first clock signal Clk1 and the second clock signal Clk2 to obtain the target clock signal LatClk. The third logic circuit 25 can be implemented by a first OR gate OR. The first input terminal and the second input terminal of the first OR gate OR serve as the two input terminals of the third logic circuit 25, respectively, and the output terminal of the first OR gate OR serves as the output terminal of the third logic circuit 25.

[0170] Here, the initial clock signal can be a system clock or other signal, the first clock signal Clk1 can be generated by performing an AND logic operation on the repair signal SPPR and the initial clock signal, and the second clock signal Clk2 can be generated by performing an AND logic operation on the repair undo signal SPPR Undo and the initial clock signal. Therefore, the first clock signal Clk1 can also be recorded as SPPR Clk, and the second clock signal Clk2 can also be recorded as SPPR Undo Clk. For the first clock signal Clk1, it will generate a short pulse when the repair signal SPPR is in the enabled state, which is used to trigger each fuse latch; for the second clock signal Clk2, it will generate a short pulse when the repair undo signal SPPR Undo is in the enabled state, which is used to trigger each fuse latch.

[0171] It should also be noted that the repair signal SPPR and the repair undo signal SPPR Undo are not enabled at the same time, so that when the repair signal SPPR is in the enabled state, the target clock signal LatClk output by the first OR gate OR is the same as the first clock signal Clk1; when the repair undo signal SPPR Undo is in the enabled state, the target clock signal LatClk output by the first OR gate OR is the same as the second clock signal Clk2.

[0172] Based on the circuit shown in FIG3 , refer to FIG4 , which shows a signal timing diagram provided by an embodiment of the present disclosure. As shown in FIG4 , a high-level logic 1 represents an enabled state, and a low-level logic 0 represents a disabled state. After the rising edge of the first clock signal Clk1 arrives and a certain delay time passes, the third enable signal EN3 becomes enabled, causing the circuit to perform a repair operation; thereafter, after the rising edge of the second clock signal Clk2 arrives and a certain delay time passes, the third enable signal EN3 becomes disabled, causing the circuit to cancel the repair operation. That is, between the rising edge of the first clock signal Clk1 and the rising edge of the second clock signal Clk2 (due to the influence of the device, there is a certain delay), the third enable signal EN3 is in an enabled state; after the rising edge of the second clock signal Clk2 arrives, the third enable signal EN3 is in a disabled state (due to the influence of the device, there is a certain delay).

[0173] 4 , the repair signal SPPR and the repair undo signal SPPR Undo are not in the enabled state at the same time. That is, the repair operation is either performed or, after the repair operation, the repair operation is undone using the repair undo signal SPPR Undo.

[0174] The simulation results show that the repair circuit 20 can implement the repair operation and repair undo functions.

[0175] In short, the disclosed embodiments relate to DRAM, and more specifically, to SPPR design. Using this solution, SPPR Undo can be applied to existing DDR5 products. Since SPPR Undo SPEC was released later than SPPR, it was necessary to add this new functionality to the existing SPPR functionality without significantly changing the structure and logic that would affect the existing SPPR. This solution introduces a method for implementing the SPPR Undo functionality and adapting it to current SPPR designs.

[0176] The disclosed embodiment combines SPPR with SPPR Undo to implement the "Undo" function without changing the current design, thereby reducing the risk of changes and resource consumption. Specifically: on the one hand, the repair signal SPPR and the repair undo signal SPPR Undo are combined to generate the target clock signal LatClk as the clock of the fuse latch; on the other hand, when undoing SPPR or executing SPPR, the selector is used to select the preset signal GND or the first enable signal EN1 as the second enable signal EN2 to be sent to the fuse latch X. This solution introduces a simple but efficient design to implement the SPPR Undo function of DDR5, which can meet the SPEC requirements with limited circuit implementation, thereby reducing design time and size cost.

[0177] In another embodiment of the present disclosure, see FIG5 , which shows a flowchart of a repair and undo method provided by an embodiment of the present disclosure. As shown in FIG5 , the method may include:

[0178] S501: receiving an activation signal and a current address signal through an input circuit, sampling and processing the current address signal according to the activation signal, and obtaining a target address signal.

[0179] S502: receiving a current address signal, an activation signal, and a repair signal through an enabling circuit, and sampling and processing the current address signal according to the activation signal and the repair signal to obtain a first enabling signal.

[0180] S503: receiving a repair cancellation signal, a first enable signal, and a preset signal through a selection circuit, and selecting one of the first enable signal and the preset signal according to the repair cancellation signal to output as a second enable signal.

[0181] S504: Receive a target address signal and a second enable signal through a matching circuit, compare the preset address signal with the target address signal when the second enable signal is the first enable signal, and output a matching signal; and fix the matching signal in a non-enabled state when the second enable signal is the preset signal.

[0182] It should be noted that the repair undo method provided in the embodiment of the present disclosure is applied to the repair circuit 20 in the aforementioned embodiment. For details not disclosed in this embodiment, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0183] In another embodiment of the present disclosure, referring to Figure 6, a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure is shown. As shown in Figure 6, the memory 60 at least includes the repair circuit 20 in the above embodiment.

[0184] It should be noted that the memory 60 can be a semiconductor memory such as DRAM. For DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0185] Since the memory 60 includes the repair circuit 20, it can implement a repair undo function, which meets the standard requirements.

[0186] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0187] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0188] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0189] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0190] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0191] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0192] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0193] The disclosed embodiment adds a selection circuit to the repair circuit. When repair reversal is required, a preset signal is used as an enable signal for the matching circuit, so that the matching signal is fixed in a non-enabled state, thereby preventing redundant rows from replacing failed rows. Ultimately, the repair reversal function is achieved without making too many changes to the circuit, meeting the requirements of the standard.

Claims

1. A repair circuit (20), comprising: An input circuit (21) is used to receive an activation signal (ACT) and a current address signal (RA), and to sample the current address signal (RA) according to the activation signal (ACT) to obtain a target address signal (RA<0:n-1>); An enabling circuit (22) is used to receive the current address signal (RA), the activation signal (ACT) and the repair signal (SPPR), and to sample the current address signal (RA) according to the activation signal (ACT) and the repair signal (SPPR) to obtain a first enabling signal (EN1); A selection circuit (23) is used to receive a repair undo signal (SPPR Undo), the first enable signal (EN1) and a preset signal (GND), and select one of the first enable signal (EN1) and the preset signal (GND) according to the repair undo signal (SPPR Undo) to output as a second enable signal (EN2); A matching circuit (24) is used to receive the target address signal (RA<0:n-1>) and the second enable signal (EN2), compare a preset address signal (FzRA<0:n-1>) with the target address signal (RA<0:n-1>) when the second enable signal (EN2) is the first enable signal (EN1), and output a matching signal (Ma); and fix the matching signal (Ma) in a non-enabled state when the second enable signal (EN2) is the preset signal (GND).

2. The repair circuit (20) according to claim 1, wherein: The input circuit (21) comprises a first sampling circuit (211), the input end of the first sampling circuit (211) is used to receive the current address signal (RA), and the clock end of the first sampling circuit (211) is used to receive the activation signal (ACT); wherein: The first sampling circuit (211) is used for sampling the current address signal (RA) according to the activation signal (ACT) to generate the target address signal (RA<0:n-1>) when the activation signal (ACT) is in an enabled state; The target address signal (RA<0:n-1>) includes an n-bit target address, where n is an integer greater than 0.

3. The repair circuit (20) according to claim 1 or 2, wherein: The enabling circuit (22) comprises a first logic circuit (221) and a second sampling circuit (222), the output end of the first logic circuit (221) is connected to the clock end of the second sampling circuit (222), and the input end of the second sampling circuit (222) is used to receive the current address signal (RA); wherein: The first logic circuit (221) is used to receive the activation signal (ACT) and the repair signal (SPPR), perform logic processing on the activation signal (ACT) and the repair signal (SPPR), and generate a trigger signal; wherein, when the activation signal (ACT) and the repair signal (SPPR) are both in an enabled state, the trigger signal is in an enabled state; The second sampling circuit (222) is used to receive the trigger signal and the current address signal (RA), perform sampling processing on the current address signal (RA) according to the trigger signal, and generate the first enable signal (EN1).

4. The repair circuit (20) according to claim 3, wherein: The first logic circuit (221) comprises a first AND gate (A1); wherein: The first input terminal of the first AND gate (A1) is used to receive the activation signal (ACT); The second input terminal of the first AND gate (A1) is used to receive the repair signal (SPPR); The output end of the first AND gate (A1) is connected to the clock end of the second sampling circuit (222) for outputting the trigger signal.

5. The repair circuit (20) according to any one of claims 1 to 4, wherein: The selection circuit (23) comprises a selector (MUX), wherein a first input end of the selector (MUX) is used to receive the preset signal (GND); a second input end of the selector (MUX) is connected to an output end of the enable circuit (22) and is used to receive the first enable signal (EN1); a control end of the selector (MUX) is used to receive the repair undo signal (SPPR Undo); and an output end of the selector (MUX) is connected to the matching circuit (24); wherein: The selector (MUX) is used to select the first enable signal (EN1) as the second enable signal (EN2) when the repair undo signal (SPPR Undo) is a first value, or to select the preset signal (GND) as the second enable signal (EN2) when the repair undo signal (SPPR Undo) is a second value.

6. The repair circuit (20) according to claim 2, wherein: The matching circuit (24) comprises a third sampling circuit (241), a latch circuit (242), a comparison circuit (243) and a second logic circuit (244); wherein: The third sampling circuit (241) is used to receive the target clock signal (LatClk) and the second enable signal (EN2), sample and latch the second enable signal (EN2) according to the target clock signal (LatClk), and generate a third enable signal (EN3); The latch circuit (242) is used to receive the target clock signal (LatClk), sample and latch the preset address signal (FzRA<0:n-1>) according to the target clock signal (LatClk), and generate a first address signal (FA<0:n-1>); The comparison circuit (243) is used to receive the target address signal (RA<0:n-1>) and the first address signal (FA<0:n-1>), compare the target address signal (RA<0:n-1>) and the first address signal (FA<0:n-1>), and generate a comparison signal (Com<0:n-1>); The second logic circuit (244) is used to receive the third enable signal (EN3) and the comparison signal (Com<0:n-1>), and when the third enable signal (EN3) is in an enabled state, generate the match signal (Ma) according to the comparison signal (Com<0:n-1>); and when the third enable signal (EN3) is in a disabled state, fix the match signal (Ma) in a disabled state.

7. The repair circuit (20) according to claim 6, wherein: The preset address signal (FzRA<0:n-1>) includes an n-bit preset address, the first address signal (FA<0:n-1>) includes an n-bit first address (FA i-1), the comparison signal (Com<0:n-1>) includes an n-bit comparison sub-signal (Com i-1), the latch circuit (242) includes n sampling sub-circuits (2421), and the comparison circuit (243) includes n comparison sub-circuits (2431); wherein: The i-th sampling subcircuit (2421) is used to receive the target clock signal (LatClk) and the i-th preset address, sample and latch the i-th preset address according to the target clock signal (LatClk), and generate the i-th first address (FA i-1); The i-th comparison sub-circuit (2431) is used to receive the i-th target address (RA i-1) and the i-th first address (FA i-1), compare the i-th target address (RA i-1) with the i-th first address (FA i-1), and generate the i-th comparison sub-signal (Com i-1), wherein i is an integer greater than 0 and less than or equal to n.

8. The repair circuit (20) according to claim 7, wherein the i-th comparison subcircuit (2431) comprises an i-th XNOR gate (X0); wherein: The first input terminal of the i-th XNOR gate (X0) is connected to the output terminal of the input circuit (21) for receiving the i-th target address (RA i-1); The second input terminal of the i-th XNOR gate (X0) is connected to the output terminal of the i-th sampling subcircuit (2421) for receiving the i-th first address (FA i-1); The output terminal of the i-th XNOR gate (X0) is used to output the i-th comparison sub-signal (Com i-1).

9. The repair circuit (20) according to claim 7 or 8, wherein: The second logic circuit (244) comprises a second AND gate (A2), wherein the second AND gate (A2) comprises a first input terminal and n second input terminals; wherein: The first input terminal of the second AND gate (A2) is used to receive the third enable signal (EN3); The i-th second input terminal of the second AND gate (A2) is used to receive the i-th comparison sub-signal (Com i-1); The output end of the second AND gate (A2) is used to output the matching signal (Ma).

10. The repair circuit (20) according to any one of claims 6 to 9, wherein: The repair circuit (20) further comprises a third logic circuit (25), wherein: The third logic circuit (25) is used for receiving the first clock signal (Clk1) and the second clock signal (Clk2), performing logic processing according to the first clock signal (Clk1) and the second clock signal (Clk2), and generating the target clock signal (LatClk); The first clock signal (Clk1) is generated according to the repair signal (SPPR) and the initial clock signal, and the second clock signal (Clk2) is generated according to the repair undo signal (SPPR Undo) and the initial clock signal.

11. The repair circuit (20) according to any one of claims 1 to 10, wherein: The repair signal (SPPR) is a soft package post repair signal.

12. The repair circuit (20) according to claim 10, wherein: The third logic circuit (25) comprises a first OR gate (OR), wherein: The first input terminal of the first OR gate (OR) is used to receive the first clock signal (Clk1); The second input terminal of the first OR gate (OR) is used to receive the second clock signal (Clk2); The output terminal of the first OR gate (OR) is used to output the target clock signal (LatClk).

13. The repair circuit (20) according to any one of claims 1 to 12, wherein: The level state of the preset signal (GND) is opposite to the level state of the first enable signal (EN1) in the enable state.

14. A repair and undo method, comprising: An activation signal (ACT) and a current address signal (RA) are received through an input circuit (21), and the current address signal (RA) is sampled according to the activation signal (ACT) to obtain a target address signal (RA<0:n-1>); Receiving the current address signal (RA), the activation signal (ACT) and the repair signal (SPPR) through an enabling circuit (22), sampling the current address signal (RA) according to the activation signal (ACT) and the repair signal (SPPR), and obtaining a first enabling signal (EN1); receiving a repair undo signal (SPPR Undo), the first enable signal (EN1) and a preset signal (GND) through a selection circuit (23), and selecting one of the first enable signal (EN1) and the preset signal (GND) to output as a second enable signal (EN2) according to the repair undo signal (SPPR Undo); The target address signal (RA<0:n-1>) and the second enable signal (EN2) are received through a matching circuit (24); when the second enable signal (EN2) is the first enable signal (EN1), a preset address signal (FzRA<0:n-1>) is compared with the target address signal (RA<0:n-1>) to output a matching signal (Ma); and when the second enable signal (EN2) is the preset signal (GND), the matching signal (Ma) is fixed in a non-enabled state.

15. A memory (60) comprising the repair circuit (20) according to any one of claims 1 to 13.

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