Controllable line-commutated converter forced commutation test circuit and method, computer device, storage medium, and product

Abstract

The present disclosure discloses a controllable line-commutated converter forced commutation test circuit and method, a computer device, and a storage medium. The controllable line-commutated converter forced commutation test circuit comprises: a steady-state power supply and a multi-wave harmonic current source. The steady-state power supply and the controllable line-commutated converter are connected in parallel, and the steady-state power supply is used to provide a voltage and a current that meet an actual stable operating condition of the controllable line-commutated converter. The multi-wave harmonic current source and the controllable line-commutated converter are connected in parallel, and the multi-wave harmonic current source is configured to periodically inject a fault current into the controllable line-commutated converter when a primary branch and an auxiliary branch in the controllable line-commutated converter are continuously alternately turned on and off over a plurality of cycles, so as to perform periodic forced commutation testing on the controllable line-commutated converter. In the present disclosure, the test circuit for synthesizing multi-source injection is used, and by means of using the multi-wave harmonic current source, an adjustable half-wave multi-wave sub-current is injected and is superposed on a test current of the steady-state power supply, to form a test current capable of verifying a controllable turning-off function of the converter.

Description

Controllable phase-changing valve forced commutation test circuit, method, computer equipment, storage medium and product

[0001] Cross-references to related publications

[0002] The embodiments of the present disclosure are based on Chinese patent application number 202310891724.9, application date July 19, 2023, and application name “Controllable Phase-Change Converter Valve Forced Commutation Test Circuit and Method” and claim the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of direct current transmission technology, and in particular to a controllable phase-changing valve forced commutation test circuit, method, computer equipment, storage medium and product. Background Art

[0004] my country's DC transmission system is characterized by a high number of feed-in DC systems at the receiving end of power grids in central and eastern China, with close coupling between stations. This interlocking of multiple stations can lead to more severe commutation failures, posing a more severe challenge to the safe and stable operation of the power grid. Therefore, controllable commutation valves that can withstand commutation failures are becoming a research hotspot.

[0005] To verify the controllable commutation valve's ability to withstand commutation failures caused by AC faults, it's necessary to verify the valve's ability to controllably shut off the AC fault current flowing through it, ensuring it can shut off the fault current and complete forced commutation. Therefore, the controlled shutoff capability test is a crucial test to ensure the design and manufacturing level of the controllable commutation valve and its ability to withstand commutation failures. This test not only verifies the voltage, current, and thermal stresses to which the valve's components are subjected during forced commutation, but also demonstrates that each component can withstand the transient stresses of high current change rates (di / dt) and voltage change rates (du / dt) during current shutoff.

[0006] Summary of the Invention

[0007] In view of this, the present disclosure provides a controllable phase-changing valve forced commutation test circuit, method, computer equipment, storage medium and product to solve the problem of how to construct an equivalent test circuit for the controllable phase-changing valve.

[0008] In a first aspect, the present disclosure provides a forced commutation test circuit for a controllable phase-changing valve, the circuit comprising: a steady-state power supply and a multi-wave harmonic current source, wherein the steady-state power supply is connected in parallel with the controllable phase-changing valve, and is used to provide a voltage and current that conforms to the actual stable operating conditions of the controllable phase-changing valve; the multi-wave harmonic current source is connected in parallel with the controllable phase-changing valve, and is used to periodically inject a fault current into the controllable phase-changing valve when the main branch and the auxiliary branch in the controllable phase-changing valve are alternately opened and closed for multiple cycles continuously, so as to perform a periodic forced commutation test on the controllable phase-changing valve.

[0009] The controlled-commutation valve forced commutation test circuit disclosed herein can be a synthetic multi-source injection test circuit, comprising a steady-state power supply and a multi-wave harmonic current source. By employing the multi-wave harmonic current source, a half-wave multi-wave current with adjustable period and amplitude is injected. This current is superimposed on the test current from the steady-state power supply to form a test current capable of verifying the controlled shutdown function of the controlled-commutation valve. This effectively simulates the controlled-commutation valve operating under AC fault conditions in the system, effectively verifying the voltage, current, and thermal stresses experienced by various components of the controlled-commutation valve under actual operating conditions, as well as the high di / dt and du / dt transient stresses caused by the high shutdown current during the shutdown process.

[0010] In an optional embodiment, the multi-wave subharmonic current source includes: a plurality of resonant branches connected in parallel; wherein, within one cycle, one resonant branch is turned on to inject a fault current into the controllable phase-changing valve.

[0011] In an optional implementation, the resonant branch includes: a resonant inductor, a resonant capacitor, and a thyristor valve connected in series in sequence.

[0012] In an optional embodiment, the controllable phase-changing valve forced commutation test circuit further includes: a charging circuit, the charging circuit being connected to the multi-wave harmonic current source and being used to charge the multi-wave harmonic current source.

[0013] In an optional embodiment, the forced commutation test circuit of the controllable phase-changing valve also includes: a control background, which is connected to the controllable phase-changing valve, a steady-state power supply and a multi-wave harmonic current source, and is used to control the steady-state power supply to provide a voltage and current that meets the actual steady-state operating conditions of the controllable phase-changing valve; control the main branch and the auxiliary branch of the controllable phase-changing valve to be alternately opened and closed for multiple cycles; when the main branch and the auxiliary branch are alternately opened and closed for multiple cycles, control the multi-wave harmonic current source to periodically inject a fault current into the controllable phase-changing valve.

[0014] In a second aspect, the present disclosure provides a forced commutation test method for a controllable phase-changing converter valve, the method comprising: controlling a steady-state power supply to provide a voltage and current that conforms to the actual stable operating conditions of the controllable phase-changing converter valve; controlling a main branch and an auxiliary branch of the controllable phase-changing converter valve to be alternately opened and closed for multiple cycles; when the main branch and the auxiliary branch are alternately opened and closed for multiple cycles, controlling a multi-wave harmonic current source to periodically inject a fault current into the controllable phase-changing converter valve to perform a periodic forced commutation test on the controllable phase-changing converter valve.

[0015] In an optional embodiment, when a single valve of a controllable phase-changing valve is composed of two main branches and multiple auxiliary branches connected in parallel, the process of periodically injecting fault current into the controllable phase-changing valve includes: controlling the first main branch to be turned on; when a logic timing turn-on instruction is received, controlling the first main branch to be turned off and the second main branch to be turned on; after the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave harmonic current source to be continuously turned on for a second preset time; when a first logic timing turn-off instruction is received, controlling the second main branch to be turned off and the multiple auxiliary branches to be turned on in sequence; after the second main branch is turned off for a third preset time, controlling the multiple auxiliary branches to be turned off in sequence, and returning to the above-mentioned step of "controlling the first main branch to be turned on".

[0016] In an optional embodiment, when a single valve of a controllable phase-changing valve is composed of a main branch and multiple auxiliary branches connected in parallel, the process of periodically injecting fault current into the controllable phase-changing valve includes: controlling the first main branch to be turned on; after the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave harmonic current source to be continuously turned on for a second preset time; when a second logic timing shutdown instruction is received, controlling the first main branch to be turned off and the multiple auxiliary branches to be turned on in sequence; after the first main branch is closed for a third preset time, controlling the multiple auxiliary branches to be turned off in sequence, and returning to the above-mentioned step of "controlling the first main branch to be turned on".

[0017] In a third aspect, the present disclosure provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute the controllable phase-changing valve forced commutation test method of the second aspect or any corresponding embodiment thereof.

[0018] In a fourth aspect, the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the controlled phase-changing valve forced commutation test method of the second aspect or any corresponding embodiment thereof.

[0019] In a fifth aspect, the present disclosure provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements the forced commutation test method for a controllable phase-changing valve according to the second aspect or any corresponding embodiment thereof.

[0020] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] FIG1 is a structural block diagram of a test circuit according to an embodiment of the present disclosure;

[0023] FIG2 is a structural block diagram of another test circuit according to an embodiment of the present disclosure;

[0024] FIG3 is a specific circuit topology diagram of a test circuit according to an embodiment of the present disclosure;

[0025] FIG4 is a flow chart of a test method according to an embodiment of the present disclosure;

[0026] FIG5 is a single valve structure of a controllable phase-changing valve according to an embodiment of the present disclosure;

[0027] FIG6 is a control timing diagram when the current shutoff branch a has two branches according to an embodiment of the present disclosure;

[0028] FIG7 is a control timing diagram when the current shutoff branch a has one branch according to an embodiment of the present disclosure;

[0029] FIG8 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present disclosure.

[0031] The embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure and are not to be construed as limiting the present disclosure.

[0032] Since DC transmission devices generally have the characteristics of high voltage, large current and large capacity, it is difficult to construct a full-load circuit with the same operating conditions as the actual operating conditions in a test environment for testing. Therefore, it becomes an inevitable choice to construct an equivalent test circuit and conduct tests with the same intensity as the actual operating conditions.

[0033] To verify the controllable commutation valve's ability to withstand commutation failures caused by AC faults, it's necessary to verify the valve's ability to controllably shut off the AC fault current flowing through it, ensuring it can shut off the fault current and complete forced commutation. Therefore, the controlled shutoff capability test is a crucial test to ensure the design and manufacturing quality of the controllable commutation valve and its ability to withstand commutation failures. This test not only verifies the voltage, current, and thermal stresses to which the valve's components are subjected during forced commutation, but also demonstrates that each component can withstand the high di / dt and du / dt transient stresses experienced when shutting off the current.

[0034] This embodiment provides a controllable phase-changing valve forced commutation test circuit, as shown in FIG1 , the circuit includes: a steady-state power supply 11 and a multi-wave harmonic current source 12 .

[0035] As shown in Figure 1, a steady-state power supply 11 is connected in parallel with the controllable phase-change valve test assembly 10 to provide voltage and current consistent with the actual stable operating conditions of the controllable phase-change valve test assembly 10. It should be noted that the controllable phase-change valve test assembly 10 is the smallest unit of the controllable phase-change valve. During implementation, due to limitations in test equipment capabilities and conditions, the controllable shutoff capability of the controllable phase-change valve test assembly can be verified to determine the controllable shutoff capability of the controllable phase-change valve test assembly.

[0036] As shown in FIG1 , a multi-wave harmonic current source 12 is connected in parallel to the controllable commutation valve test assembly 10, and is used to periodically inject a fault current into the controllable commutation valve test assembly 10 when the main branch and the auxiliary branch in the controllable commutation valve test assembly 10 are alternately opened and closed for multiple cycles continuously, so as to perform a periodic forced commutation test on the controllable commutation valve test assembly 10.

[0037] Specifically, this embodiment employs a synthetic multi-source injection test method. By employing a multi-wave harmonic current source, an adjustable half-wave multi-wave current is injected. This current is superimposed on the steady-state power supply's test current to generate a test current capable of verifying the controlled shutdown function of the controllable commutation valve. The test is completed by coordinating the timing of the power electronic components within the controllable commutation valve with the timing of the current injected by the multi-wave harmonic current source. This method can meet the forced commutation test requirements of various DC transmission system projects.

[0038] In some optional embodiments, as shown in FIG2 , the multi-wave harmonic current source 12 includes: a plurality of resonant branches connected in parallel; wherein, within one cycle, one resonant branch is turned on to inject a fault current into the controllable commutation valve test assembly 10 .

[0039] In some embodiments, the resonant branch includes: a resonant inductor, a resonant capacitor and a thyristor valve connected in series. As shown in FIG3 , the resonant inductor is L 61 ~L 6n , the resonant capacitor is C 61 ~C 6n , the thyristor valve is V 61 ~V 6n , where k (k = 1, 2, ..., n) groups of parallel circuit resonant capacitors are charged, and each group of resonant capacitors C 6k With the resonant inductor L 6k Through the thyristor valve V 6k The triggering and shutting-off are coordinated under the corresponding logic timing to form a controllable additional fault current. This controllable additional fault current is superimposed on the above-mentioned test current to form a fault current with k cycles that can simulate an AC fault. It should be noted that a thyristor valve comprises multiple thyristors connected in series. During implementation, the choice of using a thyristor valve or a thyristor can be based on the actual voltage required by the circuit. For example, when the actual voltage required by the circuit is relatively low, a thyristor can be used; when the actual voltage required by the circuit is relatively high, a thyristor valve can be used.

[0040] In some optional embodiments, as shown in FIG3 , the controllable phase-change valve forced commutation test circuit further includes a charging circuit 13 connected to the multi-wave harmonic current source for charging the multi-wave harmonic current source. The charging circuit charges the resonant capacitors of k (k=1, 2, ..., n) parallel circuits.

[0041] In some optional embodiments, as shown in FIG3 , the forced commutation test circuit of the controllable commutation valve further includes: a control background 14, which is connected to the controllable commutation valve test component, the steady-state power supply and the multi-wave harmonic current source, and is used to control the steady-state power supply to provide a voltage and current that meets the actual stable operating conditions of the controllable commutation valve test component; control the main branch and the auxiliary branch of the controllable commutation valve test component to be alternately opened and closed for multiple cycles; when the main branch and the auxiliary branch are alternately opened and closed for multiple cycles, control the multi-wave harmonic current source to periodically inject a fault current into the controllable commutation valve test component.

[0042] This embodiment provides a forced commutation test method for a controllable phase-changing valve, as shown in FIG4 , and the method includes:

[0043] Step S11: controlling the steady-state power supply to provide a voltage and current that conforms to the actual stable operating conditions of the controllable phase-commutation valve;

[0044] Step S12: Control the main branch and the auxiliary branch of the controllable phase-changing valve to be alternately opened and closed for multiple cycles;

[0045] Step S13: When the main branch and the auxiliary branch are alternately opened and closed for multiple cycles, the multi-wave harmonic current source is controlled to periodically inject fault current into the controllable commutation valve to perform a forced commutation test on the controllable commutation valve.

[0046] Specifically, a synthetic multi-source injection test method is adopted. By using a multi-wave harmonic current source, an adjustable half-wave multi-wave current is injected, which is superimposed with the test current of the steady-state power supply to form a test current that can verify the controllable phase-changing and controllable shutdown function of the converter valve.

[0047] Specifically, this embodiment controls the on and off of the power electronic devices inside the controllable commutation valve according to the forced commutation timing, and injects an adjustable half-wave multi-wave current during the on-state of the power electronic devices.

[0048] In some optional embodiments, when a single controllable phase-changing valve is composed of two main branches and multiple auxiliary branches connected in parallel, the process of periodically injecting a fault current into the controllable phase-changing valve includes:

[0049] (1) Control the conduction of the first main branch;

[0050] (2) When receiving a logic timing conduction instruction, the first main branch is controlled to be turned off and the second main branch is controlled to be turned on;

[0051] (3) after the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave subharmonic current source to be turned on continuously for a second preset time;

[0052] (4) When receiving the first logic timing shutdown instruction, controlling the second main branch to be shut down and the plurality of auxiliary branches to be turned on in sequence;

[0053] (5) After the second main branch is turned off for a third preset time, the plurality of auxiliary branches are controlled to be turned off in sequence, and the process returns to the above step of “controlling the first main branch to be turned on”.

[0054] Specifically, as shown in Figure 5, the controllable commutation valve is composed of a current shutoff branch a and an auxiliary commutation branch b connected in parallel, wherein the current shutoff branch a (a=1, 2, ..., p) contains power electronic devices with current shutoff and forward and reverse voltage blocking capabilities, such as one or more devices such as an insulated gate bipolar transistor (IGBT), an integrated gate-commutated thyristor (IGCT), an injection enhanced gate transistor (IEGT), a gate turn-off thyristor (GTO) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and the auxiliary commutation branch b (b=1, 2, ..., q) is used to establish the commutation voltage of the controllable commutation valve, and this branch does not contain power electronic devices.

[0055] Specifically, the control logic timing of the converter valve with controlled shutoff or controlled commutation capabilities must ensure that the AC fault current flowing through the bridge arm during the simulated bridge arm commutation is shut off during the test. By shutting off the current, the commutation voltage is established to achieve the forced commutation function of the bridge arm. The forced commutation test is conducted under stable operating conditions of the converter valve. For example, the current shutoff branch a includes two branches a1 and a2, and the auxiliary commutation branch b includes b1 to bq:

[0056] The steady-state power supply needs to provide the controllable phase-commutation valve with voltage and current that meet the actual stable operating conditions of the controllable phase-commutation valve. On this basis:

[0057] ① The power electronic devices in branch a1 (i.e. the first branch mentioned above) are in the first cycle t 11 Always open first,

[0058] ②When receiving the logic timing conduction instruction from the control background, t 12 At this moment, the power electronic device in branch a1 is turned off, and the power electronic device in branch a2 (i.e., the second branch) is turned on, and the current is transferred from branch a1 to branch a2.

[0059] ③ At time t13, the power electronic devices in branch 2 receive a logic-sequential shutdown command from the control background, and the current is transferred to the auxiliary commutation branch b (i.e., the auxiliary branch mentioned above). The auxiliary commutation branch b is controlled to conduct b1 to bq in sequence (i.e., b1 is turned on, b2 is turned on when b1 is turned off, b3 is turned on when b2 is turned off, and so on). This establishes the shutdown voltage of the controllable commutation valve (Valve Type Converter, VT), achieving forced commutation.

[0060] The trigger pulse ft of the multi-wave harmonic current source in this process n In t 1n -t 2n At any point in the process, harmonic currents of the appropriate order and width are injected according to the test requirements. These harmonic currents are superimposed on the test current provided by the steady-state power supply to form the fault current required by the controllable commutation valve. The multi-order harmonic current source and the trigger pulses for the power electronics within the controllable commutation valve are shown in Figure 6.

[0061] In some optional embodiments, when a single valve of a controllable phase-changing valve is composed of a main branch and multiple auxiliary branches connected in parallel, the process of periodically injecting a fault current into the controllable phase-changing valve includes:

[0062] (1) Control the conduction of the first main branch;

[0063] (2) after the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave subharmonic current source to be turned on continuously for a second preset time;

[0064] (3) When receiving the second logic timing shutdown instruction, the first main branch is controlled to be shut down and the plurality of auxiliary branches are turned on in sequence;

[0065] (4) After the first main branch is closed for a third preset time, the plurality of auxiliary branches are controlled to be turned off in sequence, and the process returns to the above step of “controlling the first main branch to be turned on”.

[0066] The steady-state power supply needs to provide the controllable phase-commutation valve with voltage and current that meet the actual stable operating conditions of the controllable phase-commutation valve. On this basis:

[0067] ① The branch of the power electronic device in the controllable phase-changing valve (i.e. the first main branch mentioned above) is at t 11 Always open,

[0068] ② When receiving the logic timing shutdown command from the control background, t 12The AC fault current is transferred to the branch without power electronic devices (i.e. the auxiliary branch mentioned above), and b1 to bq in the auxiliary commutation branch b are controlled to be turned on in sequence (i.e. b1 is turned on, b2 is turned on while b1 is turned off, b3 is turned on while b2 is turned off, etc.), completing the forced commutation.

[0069] The trigger pulse ft of the multi-wave harmonic current source in this process n In t 1n -t 2n At any point in the process, harmonic currents of the appropriate order and width are injected according to the test requirements. These harmonic currents are superimposed on the test current provided by the steady-state power supply to form the fault current required by the controllable commutation valve. The trigger pulses for the power electronic devices within the controllable commutation valve are shown in Figure 7.

[0070] In some embodiments, the multi-wave harmonic current source assists the valve V 6k The trigger pulse is an equally spaced pulse, that is, ft1=ft2=ft3=···=ft n However, when there is a special requirement, the auxiliary valve V 6k The trigger pulses can be set to be unequal, i.e. ft1≠ft2≠ft3≠···≠ft n .

[0071] In addition, the half-wave width of the fault current of the multi-wave harmonic current source, the width of each current source group is: Among them, L K Represents the resonant inductance value, C K Indicates the resonant capacitance value.

[0072] The embodiment of the present disclosure further provides a computer device having the control background shown in FIG3 .

[0073] It should be noted that, in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0074] Please refer to Figure 8, which is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present disclosure. As shown in Figure 8, the computer device 800 includes: one or more processors 810, a memory 820, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of a graphical user interface (GUI) on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, with each device providing some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 takes a processor 810 as an example.

[0075] Processor 810 may be a central processing unit, a network processor, or a combination thereof. Processor 810 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0076] The memory 820 stores instructions that can be executed by at least one processor 810, so as to enable the at least one processor 810 to implement the method shown in the above embodiment.

[0077] The memory 820 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created based on the use of a computer device for displaying a small program landing page, etc. In addition, the memory 820 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 820 may optionally include a memory remotely located relative to the processor 810, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0078] The memory 820 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory 820 may also include a combination of the above types of memory.

[0079] The computer device further includes a communication interface 830 for the computer device to communicate with other devices or a communication network.

[0080] The embodiments of the present disclosure also provide a computer-readable storage medium. The above-mentioned method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0081] The present disclosure also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement some or all of the steps in the above method. The computer program product can be implemented in hardware, software, or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium. In other embodiments, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0082] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between the embodiments, and reference can be made to the similarities or similarities between them. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above-mentioned method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product disclosed herein, please refer to the description of the method embodiments disclosed herein for understanding.

[0083] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0084] It should be noted that, in the application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0086] The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the functional units in the various embodiments of the present application may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0087] The above description is merely a preferred embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A controllable phase-changing valve forced commutation test circuit, the circuit comprising: Steady-state power supply and multi-wave harmonic current source, among which, The steady-state power supply is connected in parallel with the controllable phase-changing valve to provide a voltage and current that meets the actual stable operating conditions of the controllable phase-changing valve; The multi-wave harmonic current source is connected in parallel with the controllable phase-changing valve, and is used to periodically inject fault current into the controllable phase-changing valve when the main branch and the auxiliary branch in the controllable phase-changing valve are alternately opened and closed for multiple cycles continuously, so as to perform periodic forced commutation tests on the controllable phase-changing valve.

2. The controllable phase-changing valve forced commutation test circuit according to claim 1, wherein: The multi-wave harmonic current source comprises: a plurality of resonant branches connected in parallel; Wherein, within one cycle, one resonant branch is turned on to inject a fault current into the controllable phase-changing valve.

3. The controllable phase-changing valve forced commutation test circuit according to claim 1 or 2, wherein: The resonant branch includes: a resonant inductor, a resonant capacitor and a thyristor valve which are connected in series in sequence.

4. The controllable phase-changing valve forced commutation test circuit according to any one of claims 1 to 3, wherein: Also includes charging circuit: The charging circuit is connected to the multi-wave harmonic current source and is used for charging the multi-wave harmonic current source.

5. The controllable phase-changing valve forced commutation test circuit according to any one of claims 1 to 4, wherein: Also includes: Control the backend, The control backend is connected to the controllable phase-changing valve, the steady-state power supply and the multi-wave harmonic current source, and is used to control the steady-state power supply to provide a voltage and current that meets the actual stable operating conditions of the controllable phase-changing valve; and to control the main branch and the auxiliary branch of the controllable phase-changing valve to be opened and closed alternately for multiple cycles continuously; When the main branch and the auxiliary branch are alternately opened and closed for multiple cycles in succession, the multi-wave harmonic current source is controlled to periodically inject fault current into the controllable phase-changing valve.

6. A method for testing forced commutation of a controllable phase-changing commutation valve, the method comprising: Control the steady-state power supply to provide voltage and current that meet the actual stable operating conditions of the controllable phase-changing converter valve; Control the main branch and the auxiliary branch of the controllable phase-changing valve to be opened and closed alternately for multiple cycles; When the main branch and the auxiliary branch are alternately opened and closed for multiple cycles in a row, the multi-wave harmonic current source is controlled to periodically inject fault current into the controllable phase-changing valve to perform a periodic forced commutation test on the controllable phase-changing valve.

7. The forced commutation test method of a controllable phase-changing valve according to claim 6, wherein: When a single valve of the controllable phase-changing valve is composed of two main branches and a plurality of auxiliary branches connected in parallel, the process of periodically injecting a fault current into the controllable phase-changing valve includes: Controlling the first main branch to be turned on; When receiving a logic timing conduction instruction, controlling the first main branch to be turned off and the second main branch to be turned on; After the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave harmonic current source to be turned on for a second preset time; When receiving the first logic timing shutdown instruction, controlling the second main branch to be shut down and the plurality of auxiliary branches to be turned on in sequence; After the second main branch is turned off for a third preset time, the plurality of auxiliary branches are controlled to be turned off in sequence, and the process returns to the above step of "controlling the first main branch to be turned on".

8. The forced commutation test method of a controllable phase-changing valve according to claim 6 or 7, wherein: When a single valve of the controllable phase-changing valve is composed of a main branch and a plurality of auxiliary branches connected in parallel, the process of periodically injecting a fault current into the controllable phase-changing valve includes: Controlling the first main branch to be turned on; After the first main branch is turned on for a first preset time, controlling a resonant branch of the multi-wave harmonic current source to be turned on for a second preset time; When receiving a second logic timing shutdown instruction, controlling the first main branch to be shut down and the plurality of auxiliary branches to be turned on in sequence; After the first main branch is closed for a third preset time, the plurality of auxiliary branches are controlled to be turned off in sequence, and the process returns to the above step of "controlling the first main branch to be turned on".

9. A computer device comprising: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the forced commutation test method for a controllable phase-changing valve according to any one of claims 6 to 8 by executing the computer instructions.

10. A computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions are used to enable a computer to execute the forced commutation test method for a controllable phase-changing valve according to any one of claims 6 to 8.

11. A computer program product, comprising a computer program or an instruction, which, when executed by a processor, implements the forced commutation test method for a controllable phase-changing valve according to any one of claims 6 to 8.

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