Semiconductor structure and forming method therefor

Abstract

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate; and forming several discrete interdigital electrode structures on the surface of the substrate. Each interdigital electrode comprises: a seed layer, which is located on the surface of the substrate; and a first metal layer, which is located on the surface of the seed layer, wherein the material of the first metal layer is a metal in a crystalline state, and the crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer. The semiconductor structure and the forming method therefor reduce the resistivity of an interdigital electrode, and improve the power tolerance of a device.

Description

Semiconductor structure and method for forming the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 18, 2023, with application number 202310886448.7 and invention name “Semiconductor structure and method for forming the same”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0003] The radio frequency (RF) front-end chips for wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low-noise amplifiers. RF filters include piezoelectric surface acoustic wave (SAW) filters, piezoelectric bulk acoustic wave (BAW) filters, micro-electro-mechanical system (MEMS) filters, and integrated passive device (IPD) filters.

[0004] Existing piezoelectric surface acoustic wave filters consist of a piezoelectric substrate and interdigitated electrodes located on its surface. However, current technologies struggle to achieve both low resistivity and high power tolerance, leaving device performance to be improved.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the resistivity of the interdigital electrodes and improves the power tolerance of the device.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of discrete interdigitated electrode structures located on the surface of the substrate, the interdigitated electrode structures including: a seed layer located on the surface of the substrate; a first metal layer located on the surface of the seed layer, the material of the first metal layer is a crystalline metal, and the crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer.

[0008] Optionally, the lattice type of the seed layer is the same as the lattice type of the first metal layer.

[0009] Optionally, the material of the seed layer includes tungsten, chromium, vanadium or α iron.

[0010] Optionally, the material of the first metal layer includes molybdenum.

[0011] Optionally, the atomic arrangement of at least one cross section of the first metal layer is the same as the atomic arrangement on the surface of the seed layer.

[0012] Optionally, the lattice type of the seed layer is a face-centered cubic lattice, and the lattice type of the first metal layer is a close-packed hexagonal lattice; or the lattice type of the seed layer is a close-packed hexagonal lattice, and the lattice type of the first metal layer is a face-centered cubic lattice.

[0013] Optionally, the material of the substrate includes lithium niobate.

[0014] Optionally, the thickness of the seed layer is less than 15 nanometers.

[0015] Optionally, a ratio H / (H+D) of the thickness H of the seed layer to the sum of the thickness H of the seed layer and the thickness D of the first metal layer is in a range of 1% to 5%.

[0016] Optionally, the interdigitated electrode structure further includes: a second metal layer located on the surface of the first metal layer, and the resistivity of the second metal layer is smaller than the resistivity of the first metal layer.

[0017] Optionally, the material of the second metal layer includes aluminum or aluminum alloy.

[0018] Optionally, it further includes: a temperature compensation layer located on the surface of the substrate and the surface of the interdigital electrode structure.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a number of discrete interdigitated electrode structures on the surface of the substrate, the interdigitated electrode structures including: a seed layer located on the surface of the substrate; a first metal layer located on the surface of the seed layer, the material of the first metal layer is a crystalline metal, and the crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer.

[0020] Optionally, the method for forming the interdigitated electrode structure includes: forming an initial seed layer on the surface of the substrate; forming a first interdigitated material layer on the surface of the initial seed layer; etching the first interdigitated material layer and the initial seed layer to form a first metal layer and a seed layer.

[0021] Optionally, the process of forming the initial seed layer includes a sputtering deposition process.

[0022] Optionally, the parameters of the sputtering deposition process include: a temperature of less than 100 degrees Celsius; a DC power of 1000W to 6000W; an argon gas; an argon gas flow rate of 20sccm to 240sccm; and a rotation speed of 10 rpm to 150 rpm.

[0023] Optionally, the formation process of the first interdigital material layer includes a sputtering deposition process.

[0024] Optionally, the parameters of the sputtering deposition process include: a temperature of less than 100 degrees Celsius; a DC power of 1000W to 6000W; an argon gas; an argon gas flow rate of 20sccm to 240sccm; and a rotation speed of 10 rpm to 150 rpm.

[0025] Optionally, the method for forming the interdigitated electrode structure further includes: forming a second metal layer on the surface of the first metal layer, wherein the resistivity of the second metal layer is smaller than the resistivity of the first metal layer.

[0026] Optionally, the method further includes: forming a temperature compensation layer on the surface of the substrate and the surface of the interdigital electrode structure.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first metal layer is formed on the surface of the seed layer, and the crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer. The seed layer can crystallize at a lower temperature and become crystalline, thereby guiding the growth of the first metal layer along the lattice structure of the seed layer, and thus making the metal of the first metal layer have a certain lattice morphology, making the lattice arrangement more orderly, with fewer grain boundaries, reducing the number of scattering centers for electron transmission in the first metal layer, making the resistivity of the first metal layer lower, reducing insertion loss, and also reducing the energy consumed and heat generated when the device is working, thereby improving the power tolerance of the device.

[0029] Furthermore, a second metal layer is formed on the surface of the first metal layer, and the resistivity of the second metal layer is lower than that of the first metal layer, thereby further reducing the insertion loss of the device.

[0030] In the semiconductor structure provided by the technical solution of the present invention, since the first metal layer is located on the surface of the seed layer, the presence of the seed layer can make the metal of the first metal layer have a certain lattice morphology, making the lattice arrangement of the first metal layer more orderly, thereby making the resistivity of the first metal layer lower, reducing the insertion loss, and also improving the power tolerance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] 1 to 5 are schematic cross-sectional views of the formation process of a semiconductor structure according to a first embodiment of the present invention;

[0032] 6 to 8 are schematic cross-sectional views of the semiconductor structure during the formation process according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, it is difficult for piezoelectric surface acoustic wave filters to simultaneously meet the requirements of low resistivity and high power tolerance, resulting in the need to improve device performance.

[0034] In one embodiment of a piezoelectric surface acoustic wave filter, the structure includes a piezoelectric substrate and interdigitated electrodes located on the surface of the piezoelectric substrate. The interdigitated electrodes are typically made of molybdenum, a metal with a non-fixed lattice structure. However, molybdenum with a non-fixed lattice structure has strong scattering properties and a high resistivity, resulting in high insertion loss in the filter.

[0035] In another embodiment, the piezoelectric surface acoustic wave filter structure further includes aluminum electrodes located on the surfaces of the interdigitated electrodes. The addition of aluminum improves resistivity and reduces the filter's insertion loss, but it also reduces the filter's power tolerance. Therefore, it is difficult to simultaneously achieve both low resistivity and high power tolerance, resulting in a need for improved filter performance.

[0036] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein a first metal layer is formed on the surface of a seed layer, and the crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer. The seed layer can crystallize at a lower temperature and become crystalline, thereby guiding the first metal layer to grow along the lattice structure of the seed layer, so that the metal of the first metal layer has a certain lattice morphology, reduces electron scattering, makes the resistivity of the first metal layer lower, reduces insertion loss, and also improves the power tolerance of the device.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] 1 to 5 are schematic cross-sectional views of a semiconductor structure forming process according to a first embodiment of the present invention.

[0039] Referring to FIG. 1 , a substrate 100 is provided.

[0040] In this embodiment, the substrate 100 is made of lithium niobate.

[0041] In other embodiments, the substrate may be made of other piezoelectric materials.

[0042] Referring to FIG. 2 , an initial seed layer 110 is formed on the surface of the substrate 100 .

[0043] In this embodiment, the lattice type of the initial seed layer 110 is similar to the lattice type of the substrate 100, that is, the atomic arrangement of at least one cross section of the substrate 100 is the same as the atomic arrangement on the surface of the initial seed layer 110, so that the initial seed layer 110 can grow along the surface of the substrate 100.

[0044] Specifically, the material of the initial seed layer 110 includes tungsten.

[0045] In other embodiments, the initial seed layer may be made of other materials, provided that: the lattice type of the initial seed layer is the same as that of the substrate, or the atomic arrangement of at least one cross-section of the initial seed layer is the same as that of the substrate surface, thereby enabling the initial seed layer to grow along the substrate surface. Specifically, the initial seed layer may be made of chromium, vanadium, or α-iron.

[0046] In this embodiment, the initial seed layer 110 is formed by a sputtering deposition process.

[0047] Specifically, the parameters of the sputtering deposition process include: a temperature of less than 100 degrees Celsius; a DC power of 1000W to 6000W; an argon gas; an argon gas flow rate of 20sccm to 240sccm; and a rotation speed of 10 rpm to 150 rpm.

[0048] The initial seed layer 110 can crystallize at the process temperature and become crystalline, thereby guiding the first metal layer subsequently formed thereon to grow along the lattice structure of the initial seed layer 110 , thereby making the metal of the first metal layer also have a certain lattice morphology.

[0049] 3 , a first interdigital material layer 111 is formed on the surface of the initial seed layer 110 . The material of the first interdigital material layer 111 is a crystalline metal, wherein the crystallization temperature of the material of the initial seed layer 110 is lower than that of the material of the first interdigital material layer 111 .

[0050] In this embodiment, the lattice type of the initial seed layer 110 is the same as the lattice type of the first interdigital material layer 111, so that the first interdigital material layer 111 can grow along the surface of the initial seed layer 110. Specifically, the material of the initial seed layer 110 includes tungsten, and the material of the first interdigital material layer 111 includes molybdenum.

[0051] Since the crystallization temperature of the material of the initial seed layer 110 is lower than the crystallization temperature of the material of the first interdigitated material layer 111, the initial seed layer 110 can crystallize at a relatively low temperature and become crystalline, and the first interdigitated material layer 111 can grow along its lattice structure on the surface of the crystalline initial seed layer 110, thereby making the metal of the first interdigitated material layer 111 also have a certain lattice morphology.

[0052] In this embodiment, the formation process of the first interdigital material layer 111 includes a sputtering deposition process. Specifically, the parameters of the sputtering deposition process include: a temperature of less than 100 degrees Celsius; a DC power of 1000W to 6000W; an argon gas; an argon gas flow rate of 20sccm to 240sccm; and a rotation speed of 10 rpm to 150 rpm.

[0053] The formation of the first interdigitated material layer 111 requires a relatively low process temperature. This is because the lithium niobate material of the substrate 100 exhibits a pyroelectric effect, which polarizes when heated, causing deformation of the substrate 100. Furthermore, excessively high process temperatures can significantly deform the wafer supporting the device, affecting film deposition uniformity. Furthermore, due to uneven forces applied to different parts of the wafer, the wafer is more susceptible to fragmentation.

[0054] Since the process temperature of the first interdigital material layer 111 is relatively low, the first interdigital material layer 111 itself is not easily crystallized. By pre-forming an initial seed layer 110 having a lower crystallization temperature before forming the first interdigital material layer 111, the initial seed layer 110 is more easily crystallized than the first interdigital material layer 111. As a result, the crystalline initial seed layer 110 can guide the metal growth of the first interdigital material layer 111 to a crystalline state.

[0055] In another embodiment, the atomic arrangement of at least one cross-section of the first interdigital material layer is the same as the atomic arrangement on the surface of the initial seed layer, thereby enabling the first interdigital material layer to grow along the surface of the initial seed layer. Specifically, the lattice type of the initial seed layer is a face-centered cubic lattice, and the lattice type of the first interdigital material layer is a close-packed hexagonal lattice. The material of the initial seed layer includes tungsten, chromium, vanadium, or α-iron, and the material of the first interdigital material layer includes molybdenum.

[0056] In another embodiment, the lattice type of the initial seed layer is a close-packed hexagonal lattice, the lattice type of the first interdigital material layer is a face-centered cubic lattice, the material of the initial seed layer includes tungsten, chromium, vanadium or α-iron, and the material of the first interdigital material layer includes molybdenum.

[0057] Referring to FIG. 4 , the first interdigital material layer 111 and the initial seed layer 110 are etched to form a first metal layer 131 and a seed layer 130 .

[0058] The first metal layer 131 and the seed layer 130 together form a plurality of interdigitated electrode structures 140, each of which is separate from the others. Specifically, the interdigitated electrodes include: a seed layer 130 located on the surface of the substrate 100; and a first metal layer 131 located on the surface of the seed layer 130. The material of the first metal layer 131 is a crystalline metal. The crystallization temperature of the material of the seed layer 130 is lower than that of the material of the first metal layer 131.

[0059] Since the material of the first metal layer 131 is a crystalline metal, the lattice arrangement of the first metal layer 131 is more orderly and has fewer grain boundaries, which reduces the number of scattering centers for electron transmission in the first metal layer 131, making the resistivity of the first metal layer 131 and the overall interdigitated electrode structure 140 lower, reducing insertion loss, and also reducing the energy consumed and heat generated when the device is working, thereby improving the power tolerance of the device.

[0060] More specifically, the larger the grains of the first metal layer 131, the fewer the grain boundaries, the lower the resistivity of the first metal layer 131, and the better the power tolerance of the device. If the substrate 100 material and the stability of the previous process allow, the higher the process temperature and the lower the deposition rate during sputtering deposition of the initial seed layer 110 and the first interdigitated material layer 111, the larger the grains of the formed seed layer 130 and the first metal layer 131, and the higher the degree of crystallization.

[0061] In this embodiment, the temperature of the sputter-deposited initial seed layer 110 and the temperature of the sputter-deposited first interdigitated material layer 111 are both less than 100 degrees Celsius, and both are sputter-deposited at a relatively low temperature. Since the initial seed layer 110 is easier to crystallize than the first interdigitated material layer 111, it is possible to guide the first metal layer 131 to become crystalline by first forming a crystalline initial seed layer 110 without affecting the previous process.

[0062] Furthermore, in this embodiment, the thickness of the seed layer 130 is less than 15 nanometers, and the ratio (H / (H+D)) of the seed layer thickness H to the sum of the seed layer 130 thickness H and the first metal layer 131 thickness D is in the range of 1% to 5%. Within this thickness range for the seed layer 130, the resistivity of the interdigitated electrode structure 140 decreases most rapidly, and the presence of the seed layer 130 is most effective in reducing the resistivity of the interdigitated electrode structure 140.

[0063] In other embodiments, the ratio H / (H+D) of the thickness H of the seed layer to the sum of the thickness H of the seed layer 130 and the thickness D of the first metal layer 131 may also be less than 1% or greater than 5%.

[0064] In other embodiments, the method for forming the interdigitated electrode structure includes: forming an initial seed layer on the surface of the substrate; etching the initial seed layer to form several discrete seed layers; forming a first interdigitated material layer on the seed layer and the surface of the substrate; etching the first interdigitated material layer to form a first metal layer on the surfaces of various sub-layers.

[0065] Referring to FIG. 5 , a temperature compensation layer 150 is formed on the surface of the substrate 100 and the surface of the interdigital electrode structure 140 .

[0066] The temperature compensation layer 150 covers the substrate 100 and the top surface of the interdigital electrode structure 140. The temperature compensation layer 150 is used to adjust the frequency temperature coefficient of the device and improve the stability of the device.

[0067] The semiconductor structure described in this embodiment can be applied to a temperature-compensated surface acoustic wave resonator.

[0068] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method.

[0069] Please continue to refer to Figure 5. The semiconductor structure includes: a substrate 100; a plurality of discrete interdigitated electrode structures 140 located on the surface of the substrate 100, and the interdigitated electrode structure 140 includes: a seed layer 130 located on the surface of the substrate 100; a first metal layer 131 located on the surface of the seed layer 130, wherein the material of the first metal layer 131 is a crystalline metal, and the crystallization temperature of the material of the seed layer 130 is lower than the crystallization temperature of the material of the first metal layer 131; and a temperature compensation layer 150 located on the surface of the substrate 100 and the surface of the interdigitated electrode structure 140.

[0070] Since the first metal layer 131 is located on the surface of the seed layer 130, the presence of the seed layer 130 can make the metal of the first metal layer 131 have a certain lattice morphology, making the lattice arrangement of the first metal layer 131 more orderly, thereby making the resistivity of the first metal layer 131 and the overall interdigitated electrode structure 140 lower, reducing the insertion loss, and also improving the power tolerance of the device.

[0071] In this embodiment, the lattice type of the seed layer 130 is the same as the lattice type of the first metal layer 131 ; the material of the seed layer 130 includes tungsten.

[0072] In other embodiments, the material of the seed layer further includes chromium, vanadium or α iron.

[0073] In other embodiments, the atomic arrangement of at least one cross-section of the first metal layer is the same as the atomic arrangement of the surface of the seed layer. Specifically, the lattice type of the seed layer is a face-centered cubic lattice, and the lattice type of the first metal layer is a close-packed hexagonal lattice. In another embodiment, the lattice type of the seed layer is a close-packed hexagonal lattice, and the lattice type of the first metal layer is a face-centered cubic lattice.

[0074] In this embodiment, the material of the first metal layer 131 includes molybdenum.

[0075] In this embodiment, the substrate 100 is made of lithium niobate.

[0076] In this embodiment, the thickness of the seed layer 130 is less than 15 nanometers.

[0077] In this embodiment, the ratio H / (H+D) of the thickness H of the seed layer 130 to the sum of the thickness H of the seed layer 130 and the thickness D of the first metal layer 131 is in the range of 1% to 5%.

[0078] 6 to 8 are schematic cross-sectional views of the semiconductor structure during the formation process according to the second embodiment of the present invention.

[0079] 6 , a substrate 200 is provided; an initial seed layer 210 is formed on the surface of the substrate 200 ; a first interdigitated material layer 211 is formed on the surface of the initial seed layer 210 ; and a second interdigitated material layer 212 is formed on the surface of the first interdigitated material layer 211 .

[0080] Among them, the materials and formation process of the substrate 200, the initial seed layer 210 and the first interdigitated material layer 211 are the same as the materials and formation process of the substrate 100, the initial seed layer 110 and the first interdigitated material layer 111 in the first embodiment in Figures 1 to 5, and will not be repeated here.

[0081] In this embodiment, the second interdigital material layer 212 is formed by a sputtering deposition process.

[0082] Please refer to Figure 7, the initial seed layer 210, the first interdigitated material layer 211 and the second interdigitated material layer 212 are etched to form a number of discrete interdigitated electrode structures 240 located on the surface of the substrate 200, and the interdigitated electrode structure 240 includes: a seed layer 230 located on the surface of the substrate 200; a first metal layer 231 located on the surface of the seed layer 230, the material of the first metal layer 231 is a crystalline metal, and the crystallization temperature of the material of the seed layer 230 is lower than the crystallization temperature of the material of the first metal layer 231; and a second metal layer 232 located on the surface of the first metal layer 231.

[0083] The resistivity of the second metal layer 232 is lower than that of the first metal layer 231 , thereby further reducing the insertion loss of the device.

[0084] Specifically, the material of the second metal layer 232 includes aluminum or an aluminum alloy, wherein the aluminum alloy includes aluminum copper (AlCu) or aluminum magnesium copper alloy (AlMgCu).

[0085] Referring to FIG. 8 , a temperature compensation layer 250 is formed on the surface of the substrate 200 and the surface of the interdigital electrode structure 240 .

[0086] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method.

[0087] Please continue to refer to Figure 8. The semiconductor structure includes: a substrate 200; a plurality of discrete interdigitated electrode structures 240 located on the surface of the substrate 200, the interdigitated electrode structures 240 including: a seed layer 230 located on the surface of the substrate 200; a first metal layer 231 located on the surface of the seed layer 230, the material of the first metal layer 231 being a crystalline metal, and the crystallization temperature of the material of the seed layer 230 is lower than the crystallization temperature of the material of the first metal layer 231; a second metal layer 232 located on the surface of the first metal layer 231, the resistivity of the second metal layer 232 being lower than the resistivity of the first metal layer 231; and a temperature compensation layer 250 located on the surface of the substrate 200 and the surface of the interdigitated electrode structure 240.

[0088] The material of the second metal layer 232 includes aluminum or aluminum alloy.

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of discrete interdigitated electrode structures located on the surface of the substrate, the interdigitated electrode structures comprising: a seed layer located on the surface of the substrate; A first metal layer is located on the surface of the seed layer. The material of the first metal layer is a crystalline metal. The crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer.

2. The semiconductor structure according to claim 1, wherein: The lattice type of the seed layer is the same as the lattice type of the first metal layer.

3. The semiconductor structure according to claim 2, wherein: The material of the seed layer includes tungsten, chromium, vanadium or α iron.

4. The semiconductor structure according to claim 2, wherein: The material of the first metal layer includes molybdenum.

5. The semiconductor structure according to claim 1, wherein: The atomic arrangement of at least one cross section of the first metal layer is the same as the atomic arrangement of the surface of the seed layer.

6. The semiconductor structure according to claim 5, characterized in that The lattice type of the seed layer is a face-centered cubic lattice, and the lattice type of the first metal layer is a close-packed hexagonal lattice; or the lattice type of the seed layer is a close-packed hexagonal lattice, and the lattice type of the first metal layer is a face-centered cubic lattice.

7. The semiconductor structure according to claim 1, wherein: The material of the substrate includes lithium niobate.

8. The semiconductor structure according to claim 1, wherein: The seed layer has a thickness less than 15 nanometers.

9. The semiconductor structure according to claim 1, wherein: The value range of the ratio H / (H+D) of the thickness H of the seed layer to the sum of the thickness H of the seed layer and the thickness D of the first metal layer is 1% to 5%.

10. The semiconductor structure according to claim 1, wherein: The interdigitated electrode structure further includes: a second metal layer located on the surface of the first metal layer, wherein the resistivity of the second metal layer is smaller than the resistivity of the first metal layer.

11. The semiconductor structure according to claim 10, characterized in that The material of the second metal layer includes aluminum or aluminum alloy.

12. The semiconductor structure according to claim 1, wherein: Also includes: A temperature compensation layer is located on the surface of the substrate and the surface of the interdigital electrode structure.

13. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A plurality of discrete interdigital electrode structures are formed on the surface of the substrate, wherein the interdigital electrode structures include: a seed layer located on the surface of the substrate; A first metal layer is located on the surface of the seed layer. The material of the first metal layer is a crystalline metal. The crystallization temperature of the material of the seed layer is lower than the crystallization temperature of the material of the first metal layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the interdigitated electrode structure includes: forming an initial seed layer on the surface of the substrate; forming a first interdigitated material layer on the surface of the initial seed layer; etching the first interdigitated material layer and the initial seed layer to form a first metal layer and a seed layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The initial seed layer formation process includes a sputtering deposition process.

16. The method for forming a semiconductor structure according to claim 15, wherein: The parameters of the sputtering deposition process include: the temperature used is less than 100 degrees Celsius; the DC power is 1000W to 6000W; the gas used is argon; the argon gas flow rate is 20sccm to 240sccm; and the rotation speed is 10 rpm to 150 rpm.

17. The method for forming a semiconductor structure according to claim 14, wherein: The formation process of the first interdigital material layer includes a sputtering deposition process.

18. The method for forming a semiconductor structure according to claim 17, wherein: The parameters of the sputtering deposition process include: the temperature used is less than 100 degrees Celsius; the DC power is 1000W to 6000W; the gas used is argon; the argon gas flow rate is 20sccm to 240sccm; and the rotation speed is 10 rpm to 150 rpm.

19. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the interdigital electrode structure further includes: forming a second metal layer on the surface of the first metal layer, wherein the resistivity of the second metal layer is smaller than the resistivity of the first metal layer.

20. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: A temperature compensation layer is formed on the surface of the substrate and the surface of the interdigital electrode structure.

Images