Crystalline silicon film layer and preparation method therefor, and solar cell and preparation method therefor

Abstract

A crystalline silicon film layer and a preparation method therefor, and a solar cell and a preparation method therefor, relating to the technical field of photovoltaics. The crystalline silicon film layer comprises at least one first polycrystalline silicon part; the crystallization rate of the first polycrystalline silicon part is 50-60%; the hydrogen content in the first polycrystalline silicon part is 1-20%; and the porosity of the first polycrystalline silicon part is 0.1-10%. The first polycrystalline silicon part has relatively appropriate crystallization rate, hydrogen content and porosity, and has good film layer quality which facilitates improvement the photoelectric conversion efficiency of photovoltaic devices. Moreover, during wet etching, the etching rate of the first polycrystalline silicon part with good quality is low in both an alkaline wet etching agent and an acidic wet etching agent, and the etching of the first polycrystalline silicon part can be basically ignored, such that a mask layer does not need to be arranged on the first polycrystalline silicon part, thereby reducing steps, simplifying the wet etching process, and improving the production efficiency.

Description

Crystalline silicon film layer and preparation method thereof, solar cell and preparation method thereof Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a crystalline silicon film layer and a preparation method thereof, a solar cell and a preparation method thereof. Background Art

[0002] Polysilicon is widely used in the photovoltaic industry. The quality of polysilicon film plays an important role in the photoelectric conversion efficiency of photovoltaic devices.

[0003] However, the quality of the existing polysilicon film is poor, resulting in a relatively complicated process during the wet etching process.

[0004] Summary of the Invention

[0005] The present invention provides a crystalline silicon film layer and a preparation method thereof, a solar cell and a preparation method thereof, aiming to solve the problem that the existing polycrystalline silicon film layer has poor quality, resulting in a complex process during wet etching.

[0006] A first aspect of the present invention provides a crystalline silicon film layer, the crystalline silicon film layer comprising: a first polysilicon portion; the first polysilicon portion penetrates the crystalline silicon film layer in a thickness direction of the crystalline silicon film layer;

[0007] The crystallization rate of the first polysilicon portion is 50% to 60%;

[0008] The hydrogen content in the first polysilicon portion is 1% to 20%;

[0009] The porosity of the first polysilicon portion is 0.1% to 10%.

[0010] In the embodiment of the present invention, the first polysilicon portion penetrates the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer, the crystallization rate of the first polysilicon portion is relatively suitable, the hydrogen content is also relatively suitable, and the porosity of the first polysilicon portion is relatively suitable. The film quality of the first polysilicon portion is relatively good, which is conducive to improving the photoelectric conversion efficiency of the photovoltaic device. Moreover, during the wet etching process, the etching rate of the first polysilicon portion with relatively good quality in both alkaline wet etchants and acidic wet etching agents is very slow, and the etching effect of the alkaline wet etchants and acidic wet etching agents on it is basically negligible. Therefore, it is unnecessary to set a mask layer on the first polysilicon portion, reducing the step of setting the mask layer on the first polysilicon portion and reducing the step of removing the mask layer after wet etching, thereby simplifying the wet etching process and improving production efficiency.

[0011] Optionally, the first polysilicon portion is a doped polysilicon portion, and the doping concentration of the doped polysilicon portion is: 5×10 18 cm-3 to 1×10 20 cm -3 .

[0012] Optionally, the thickness variability of the crystalline silicon film layer is less than 5%.

[0013] Optionally, the crystalline silicon film layer also includes: an amorphous silicon portion; the amorphous silicon portion penetrates the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer; in the crystalline silicon film layer, the first polycrystalline silicon portion and the amorphous silicon portion are alternately distributed; the crystallization rate of the amorphous silicon portion is lower than the crystallization rate of the first polycrystalline silicon portion, and the hydrogen content and porosity of the amorphous silicon portion are both greater than the hydrogen content and porosity of the first polycrystalline silicon portion.

[0014] A second aspect of the present invention provides a method for preparing any of the aforementioned crystalline silicon film layers, comprising:

[0015] providing an amorphous silicon film layer;

[0016] The amorphous silicon film layer is heated by infrared light until the temperature of the amorphous silicon film layer reaches a preset temperature, and at least a portion of the amorphous silicon film layer is hydrogenated and crystallized by laser, with the portion acted upon by the laser forming a first polycrystalline silicon portion; the preset temperature is 5%-30% of the temperature of the laser; wherein the infrared light heating and the laser action are performed simultaneously, or the infrared light heating is performed first and then the laser action.

[0017] Optionally, the power of the laser is 20W to 200W;

[0018] The preset temperature is 100°C to 300°C.

[0019] Optionally, the spot shape of the laser is triangular.

[0020] Optionally, providing the amorphous silicon film layer includes:

[0021] providing a substrate;

[0022] On the first surface of the substrate, forming the amorphous silicon film layer with a crystallization rate of 5%-40% and a porosity of 0.1%-20% by LPCVD;

[0023] Alternatively, forming the amorphous silicon film layer having a crystallization rate of 5%-30% and a porosity of 0.1%-20% on the substrate by PECVD;

[0024] Optionally, in the PECVD method, the process parameters include at least one of the following five process parameters:

[0025] The RF power switch ratio is 1 / 5-4 / 5;

[0026] Discharge times are 20,000-50,000 times;

[0027] The discharge gas is a mixed gas formed by hydrogen, nitrogen and argon; in the mixed gas, the volume concentration of hydrogen is 5%-70%, and the volume concentration of argon is 10%-80%;

[0028] The power of RF power supply is 5000w-15000w;

[0029] The process temperature is 300℃-500℃.

[0030] Optionally, providing a substrate includes:

[0031] The first surface of the substrate is polished to obtain a first surface with a reflectivity of 30%-50%.

[0032] A third aspect of the present invention provides a solar cell comprising:

[0033] A silicon substrate, a tunneling oxide layer located on the silicon substrate, and a doped crystalline silicon film layer located on the tunneling oxide layer; the doped crystalline silicon film layer is the crystalline silicon film layer described in the first aspect of the present invention or the crystalline silicon film layer obtained by the method for preparing the crystalline silicon film layer described in the second aspect of the present invention; the doped crystalline silicon film layer includes: a second polycrystalline silicon portion; the second polycrystalline silicon portion penetrates the doped crystalline silicon film layer in a thickness direction of the doped crystalline silicon film layer;

[0034] The crystallization rate of the second polysilicon portion is greater than or equal to 60%;

[0035] The hydrogen content in the second polysilicon portion is 1% to 20%;

[0036] The porosity of the second polysilicon portion is 0.1% to 10%.

[0037] Optionally, the doped crystalline silicon film layer is entirely composed of the second polysilicon portion;

[0038] The surface of the silicon substrate away from the doped crystalline silicon film layer has a textured structure.

[0039] Optionally, the thickness variability of the doped crystalline silicon film layer is less than 5%.

[0040] A fourth aspect of the present invention provides a back-contact solar cell, comprising:

[0041] Silicon substrate;

[0042] The projection falls on a first area and a second area on the silicon substrate; the first area and the second area are alternately distributed; the first area includes: a tunneling oxide layer and a first transmission layer arranged in a stacked manner; the first transmission layer comes from the crystalline silicon film layer described in the first aspect of the present invention or the crystalline silicon film layer obtained by the preparation method of the crystalline silicon film layer described in the second aspect of the present invention; the crystallization rate of the first transmission layer is greater than or equal to 60%; the hydrogen content of the first transmission layer is 1% to 20%; the porosity of the first transmission layer is 0.1% to 10%; the second area includes a second transmission layer, and the second transmission layer is located on the exposed tunneling oxide layer or the silicon substrate; the doping types of the first transmission layer and the second transmission layer are different.

[0043] Optionally, the thickness variability of the first transmission layer is less than 5%.

[0044] A fifth aspect of the present invention provides a method for preparing the aforementioned back-contact solar cell, comprising:

[0045] A conductive substrate is provided; the conductive substrate comprises: a silicon substrate, a tunneling oxide layer sequentially stacked on the silicon substrate, and a crystalline silicon film layer; the crystalline silicon film layer is the crystalline silicon film layer described in the first aspect of the present invention, or the crystalline silicon film layer is prepared by the method for preparing a crystalline silicon film layer described in the second aspect of the present invention; the crystalline silicon film layer comprises: a first polycrystalline silicon portion and an amorphous silicon portion; the first polycrystalline silicon portion and the amorphous silicon portion extend through the crystalline silicon film layer in a thickness direction of the crystalline silicon film layer; and the first polycrystalline silicon portion and the amorphous silicon portion are alternately distributed in the crystalline silicon film layer;

[0046] When the first polysilicon portion is not covered by the mask layer, wet etching is performed on the conductive substrate, wherein the first polysilicon portion is retained in the wet etching, the amorphous silicon portion is removed in the wet etching, and the tunnel oxide layer or the second region of the silicon substrate is exposed;

[0047] A second transmission layer is formed on the exposed second area. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] FIG1 shows a schematic planar structural diagram of a crystalline silicon film layer according to some embodiments of the present invention;

[0050] FIG2 shows a schematic planar structure diagram of another crystalline silicon film layer according to some embodiments of the present invention;

[0051] FIG3 shows a partially enlarged schematic diagram of a first polysilicon portion according to some embodiments of the present invention;

[0052] FIG4 is a schematic diagram showing a partial enlargement of a polysilicon film layer in the prior art;

[0053] FIG5 shows a schematic diagram of crystallization and hydrogenation according to some embodiments of the present invention;

[0054] FIG6 shows a schematic diagram of crystallization and hydrogenation in the prior art;

[0055] FIG7 shows a schematic diagram of a laser according to some embodiments of the present invention;

[0056] FIG8 shows a schematic diagram of a laser in the prior art;

[0057] FIG9 is a schematic diagram showing the distribution of hydrogen content and crystallization rate of the first polysilicon portion according to various examples of some embodiments of the present invention.

[0058] Description of the accompanying figures:

[0059] 1-crystalline silicon film layer, 11-first polycrystalline silicon portion, 12-amorphous silicon portion, 111-hole, 2-amorphous silicon film layer, 31-infrared light, 32-laser. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0061] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0062] As used herein, the term "located on" means that a first feature and a second feature are in direct contact, or the first feature and the second feature are in indirect contact via an intermediary.

[0063] As used herein, the term "hydrogenation" refers to a change in hydrogen content, ie, a process in which hydrogen in a polycrystalline silicon thin film is released to the outside in the form of hydrogen gas.

[0064] As used herein, the term "throughout," for example, a polycrystalline silicon portion "throughout" the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer means that there is at least one three-dimensional structure in the polycrystalline silicon portion, and the three-dimensional structure includes, for example, at least one point and at least one surface, and the point and the surface are respectively located on two opposite surfaces in the thickness direction of the crystalline silicon film layer, or includes, for example, at least two points, and the two points are respectively located on two opposite surfaces in the thickness direction of the crystalline silicon film layer, or includes, for example, at least two surfaces, and the two surfaces are respectively located on two opposite surfaces in the thickness direction of the crystalline silicon film layer.

[0065] As used herein, the term "hydrogen content" refers to, for example, the ratio of the total number of hydrogen bonds in a polysilicon portion to the total number of all bonds in the polysilicon portion. In this context, hydrogen content is measured by Fourier transform infrared spectroscopy.

[0066] As used herein, the term "crystallization rate" refers to the ratio of crystals in, for example, a polycrystalline silicon portion, indicating the degree of crystallization, and is typically calculated as follows: obtaining the crystalline silicon Gaussian peak, amorphous silicon Gaussian peak, and grain boundary Gaussian peak from Raman spectroscopy testing; the crystallization rate is equal to the sum of the integral areas of the crystalline silicon peak and the amorphous peak divided by the sum of the integrals of the three.

[0067] As used herein, the term "porosity" refers to, for example, the percentage of the pore volume in a polycrystalline silicon portion to the total volume of the polycrystalline silicon portion. Typically, porosity is determined by measuring the porosity of at least two fields of view under a microscope and then calculating the arithmetic mean. The porosity within a single field of view is typically calculated by dividing the sum of the areas of the pores within that field of view by the area of ​​the single field of view. The microscope typically has a magnification of 20x and a field of view of 400 x 400. If the field of view is too large, the area is limited to 400 x 400.

[0068] In this document, for example, regarding the calculation of the crystallinity and porosity of a polycrystalline silicon portion, a predetermined number of points can be selected in the polycrystalline silicon portion, each of which is located at a different position in the polycrystalline silicon portion. The crystallinity and porosity at each point are measured, and then the crystallinity at all points is calculated as the arithmetic average to obtain the crystallinity of the polycrystalline silicon portion, and the porosity at all points is calculated as the arithmetic average to obtain the porosity of the polycrystalline silicon portion. For example, when calculating the crystallinity and porosity of a polycrystalline silicon portion, the number of points selected can be the same or different, and each point can be representative of the polycrystalline silicon portion. For example, if the polycrystalline silicon portion is rectangular, for both calculations of the crystallinity and porosity, five points can be selected, with the five points located at the four vertices of the rectangle and the geometric center of the rectangle. For another example, when calculating the crystallinity and porosity of a polycrystalline silicon portion, 30 points can be selected, with the 30 points evenly distributed in the polycrystalline silicon portion.

[0069] As used herein, "thickness variability" refers to, for example, a first quotient obtained by dividing a first difference obtained by subtracting an average value of multiple thicknesses at multiple locations in a crystalline silicon film layer from a maximum value of the multiple thicknesses by the average value of the multiple thicknesses. Alternatively, the thickness variability of a crystalline silicon film layer is: a second quotient obtained by subtracting a second difference obtained by subtracting a minimum value of the multiple thicknesses from an average value of the multiple thicknesses at multiple locations in the crystalline silicon film layer by the average value of the multiple thicknesses. In this application, thickness variability is measured using the first method.

[0070] As used herein, the term "projection" refers to an orthographic projection.

[0071] Figure 1 shows a schematic diagram of the planar structure of a crystalline silicon film layer according to some embodiments of the present invention. Figure 2 shows a schematic diagram of the planar structure of another crystalline silicon film layer according to some embodiments of the present invention. The present invention provides a crystalline silicon film layer 1, which includes a first polycrystalline silicon portion 11, and the first polycrystalline silicon portion 11 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1. In the present invention, the number of first polycrystalline silicon portions included in the crystalline silicon film layer 1 is not limited. For example, the number of the first polycrystalline silicon portions can be 1, 2, 3, 4, 5, 6, 7, 9, 10, 12, 13, 14, etc. In the present invention, the number of amorphous silicon portions included in the crystalline silicon film layer 1 is not limited. For example, the number of the amorphous silicon portions can be 1, 2, 3, 4, 5, 6, 7, 9, 10, 12, 13, 14, etc. The crystalline silicon film layer 1 can be entirely composed of the first polycrystalline silicon portion 11, or the crystalline silicon film layer 1 can be composed of the first polycrystalline silicon portion 11 and the amorphous silicon portion 12. In the embodiment of the present invention, this is not specifically limited. For example, as shown in Figure 1, the crystalline silicon film layer 1 is entirely composed of the first polycrystalline silicon portion 11, or it can be considered that the crystalline silicon film layer 1 is composed of one first polycrystalline silicon portion 11, and the first polycrystalline silicon portion 11 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1. Figures 1 and 2 are schematic diagrams of the planar structure of the crystalline silicon film layer. Therefore, in Figures 1 and 2, the thickness direction of the crystalline silicon film layer 1 is perpendicular to the paper surface. For another example, referring to Figure 2, the crystalline silicon film layer 1 includes: 8 first polycrystalline silicon portions 11, and 7 amorphous silicon portions 12, each of the first polycrystalline silicon portions 11 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1, and each of the amorphous silicon portions 12 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1. Here, the first polycrystalline silicon portions 11 penetrate the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1 can be: at least one three-dimensional structure exists in the first polycrystalline silicon portion 11, and the three-dimensional structure includes: at least one point and at least one surface, and the point and the surface are respectively located on two opposite surfaces of the crystalline silicon film layer 1 in the thickness direction.

[0072] Figure 3 shows a partially enlarged schematic diagram of a first polysilicon portion according to some embodiments of the present invention. Figure 4 shows a partially enlarged schematic diagram of a polysilicon film layer in the prior art. Referring to Figures 3 and 4, compared to the prior art, the present invention has fewer holes 111 in the first polysilicon portion 11 and a smaller volume of holes 111. Therefore, the porosity of the first polysilicon portion 11 in the present invention is lower and the film is more dense.

[0073] More specifically, the crystallization rate of the first polycrystalline silicon portion 11 is 50% to 60%, the hydrogen content of the first polycrystalline silicon portion 11 is 1% to 20%, and the porosity of the first polycrystalline silicon portion 11 is 0.1% to 10%. When the crystallization rate, hydrogen content, and porosity of the first polycrystalline silicon portion 11 are within the above ranges, the film layer formed by the first polycrystalline silicon portion 11 is of high quality, which is conducive to improving the photoelectric conversion efficiency of the photovoltaic device. Moreover, during the wet etching process, the etching rate of the first polycrystalline silicon portion 11 with high quality is very slow in both alkaline wet etchants and acidic wet etchants, and the etching effect of the alkaline wet etchants and acidic wet etchants on the first polycrystalline silicon portion 11 is basically negligible. Therefore, it is unnecessary to set a mask layer on the first polycrystalline silicon portion 11, reducing the steps of setting a mask layer on each first polycrystalline silicon portion 11 and reducing the steps of removing the mask layer after wet etching, simplifying the wet etching process and improving production efficiency.

[0074] For example, in an embodiment in which the crystalline silicon film layer 1 is entirely composed of a first polycrystalline silicon portion 11 as shown in Figure 1, the photovoltaic device includes the stacked crystalline silicon film layer 1 and component A. In the process of setting the texture surface on the surface of component A away from the crystalline silicon film layer 1, since the crystallization rate, hydrogen content and porosity of the first polycrystalline silicon portion 11 are respectively within the above-mentioned ranges, the film layer formed by the first polycrystalline silicon portion 11 has a better quality. During the texture making process, the etching rate of the above-mentioned first polycrystalline silicon portion 11 with better quality is very slow in the texture making liquid, and the etching effect of the texture making liquid on it can be basically ignored. Therefore, there is no need to set a mask layer on the crystalline silicon film layer 1, which reduces the step of setting the mask layer on the crystalline silicon film layer 1 and the step of removing the mask layer after wet etching, thereby simplifying the texture making process and improving production efficiency.

[0075] For another example, in the embodiment of the crystalline silicon film layer 1 shown in FIG2 , which is composed of 8 first polycrystalline silicon parts 11 and 7 amorphous silicon parts 12, wherein each first polycrystalline silicon part 11 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1, and each amorphous silicon part 12 also penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1, in the process of patterning the crystalline silicon film layer 1, since the crystallization rate, hydrogen content and porosity of the first polycrystalline silicon part 11 are respectively within the above ranges, the film layer quality of the first polycrystalline silicon part 11 is better, and in the patterning process, the first polycrystalline silicon part 11 with better quality is better. The etching rate of the polysilicon part 11 in the etching solution is very slow, and the etching effect of the etching solution on it can be basically ignored. However, compared with the first polysilicon part 11, the film quality of the amorphous silicon part 12 is poor. In this etching solution, the 7 amorphous silicon parts 12 will be completely etched away, leaving only 8 first polysilicon parts 11, thereby realizing patterning. This makes it unnecessary to set a mask layer on each first polysilicon part 11, reduces the step of setting a mask layer on each first polysilicon part 11, and reduces the step of removing the mask layer after patterning, simplifies the patterning process, and improves production efficiency.

[0076] In some embodiments, the crystallinity of the first polysilicon portion 11 can be 50%, 50.2%, 52%, 52.9%, 53.7%, 54.9%, 55%, 55.3%, 57%, 59%, or 60%. In some embodiments, the hydrogen content of the first polysilicon portion 11 is 1%, 2.3%, 4%, 7%, 9.7%, 10.4%, 10.5%, 10.9%, 12%, 15%, or 20%. In some embodiments, the porosity of the first polysilicon portion 11 is 0.1%, 1%, 3%, 4.7%, 5.05%, 6%, 7.5%, 8%, 9%, 9.5%, or 10%.

[0077] It should be noted that the hydrogen content of a first polycrystalline silicon portion 11 herein may refer to the ratio of the total number of hydrogen bonds in the first polycrystalline silicon portion 11 to the total number of all bonds in the first polycrystalline silicon portion 11. The crystallization rate of a first polycrystalline silicon portion 11 may refer to the ratio of crystals in the first polycrystalline silicon portion 11. The porosity of a first polycrystalline silicon portion 11 may refer to the percentage of the total volume of pores in the first polycrystalline silicon portion 11 to the total volume of the first polycrystalline silicon portion 11. Regarding the crystallization rate and porosity, a predetermined number of points may be selected in the first polycrystalline silicon portion 11, each of which is located at a different position in the first polycrystalline silicon portion 11. The crystallization rate and porosity at each point may then be measured. The crystallization rate of the first polycrystalline silicon portion 11 may then be calculated as the arithmetic average of the crystallization rates at all points, and the porosity of the first polycrystalline silicon portion 11 may then be calculated as the arithmetic average of the porosity at all points. The number of points selected for the crystallinity and porosity can be the same or different, and each point can be representative of the first polysilicon portion 11. For example, if the first polysilicon portion 11 is rectangular, 5 points can be selected for both the crystallinity and porosity, with the 5 points located at the four vertices and the geometric center of the rectangle. For another example, 30 points can be selected for both the crystallinity and porosity, with the 30 points evenly distributed throughout the first polysilicon portion 11.

[0078] Optionally, the first polysilicon portion 11 is a doped polysilicon portion, wherein the doping concentration of the doped polysilicon portion is: 5×10 18 cm -3 to 1×10 20 cm -3 Since the film quality of the first polysilicon portion 11 is relatively good, the first polysilicon portion 11 can obtain a relatively wide range of doping concentrations and can be applied to a wider range of scenarios. For example, the first polysilicon portion 11 is a doped polysilicon portion, and the doping concentration of the doped polysilicon portion can be: 5×10 18 cm -3 , or 8×10 18 cm -3 , or 9.3×10 18 cm -3 , or 1×10 19 cm -3 , or 4×10 19 cm -3 , or 5×10 19 cm -3 , or 5.25×10 19 cm -3 , or 6×10 19 cm -3 , or 8×10 19 cm -3, or 9×10 19 cm -3 , or 1×10 20 cm -3 .

[0079] It should be noted that the first polysilicon portion 11 may be N-type doped or P-type doped, which is not limited.

[0080] Optionally, the thickness variability of the crystalline silicon film layer 1 is less than 5%. The thickness variability of the crystalline silicon film layer 1 is: a first quotient obtained by subtracting a first difference obtained by dividing the average value of the multiple thicknesses at multiple locations in the crystalline silicon film layer 1 by the average value of the multiple thicknesses. The thickness variability of the crystalline silicon film layer 1 is less than 5%, indicating that the thickness uniformity of the crystalline silicon film layer 1 is good. This ensures that during the etching process of the crystalline silicon film layer 1, the thickest part of the crystalline silicon film layer 1 is not too thick, and the etching time is not too long, which can save etching time and improve etching efficiency. Each first polysilicon portion is a portion of the crystalline silicon film layer, and each first polysilicon portion penetrates the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer. Therefore, the thickness difference of each first polysilicon portion is basically equal to the thickness difference of the crystalline silicon film layer. The thickness difference of each first polysilicon portion is less than 5%, indicating that the thickness uniformity of each first polysilicon portion is good. In the process of etching each first polysilicon portion, the thickest part of each first polysilicon portion will not be too thick, and the etching time will not be too long, which can also save etching time and improve etching efficiency. In the case where the crystalline silicon film layer includes an amorphous silicon part, each amorphous silicon part is a part of the crystalline silicon film layer, and each amorphous silicon part penetrates the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer. Therefore, the thickness difference of each amorphous silicon part is basically equal to the thickness difference of the crystalline silicon film layer, and the thickness difference of each amorphous silicon part is less than 5%, indicating that the thickness uniformity of each amorphous silicon part is good. In the process of etching the each amorphous silicon part, the thickest part of each amorphous silicon part will not be too thick, and the etching time will not be too long, which can also save etching time and improve etching efficiency.

[0081] Optionally, referring to FIG2 , the crystalline silicon film layer 1 further includes: at least one amorphous silicon portion 12, and the amorphous silicon portion 12 penetrates the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1. In the crystalline silicon film layer 1, the first polycrystalline silicon portion 11 and the amorphous silicon portion 12 are alternately distributed, wherein the crystallization rate of the amorphous silicon portion 12 is lower than the crystallization rate of the first polycrystalline silicon portion 11, and the hydrogen content and porosity of the amorphous silicon portion 12 are both greater than the hydrogen content and porosity of the first polycrystalline silicon portion 11. That is, compared with the first polycrystalline silicon portion 11, the film layer quality of the amorphous silicon portion 12 is relatively poor. When it is necessary to remove the amorphous silicon portion 12 in the crystalline silicon film layer 1 and retain the first polycrystalline silicon portion 11, on the one hand, the film layer quality of the amorphous silicon portion 12 is relatively poor, and the removal speed is faster, which reduces the process time. On the other hand, the first polycrystalline silicon portion 11 is removed. The polycrystalline silicon portion 11 has a better film quality than the amorphous silicon portion 12. When it is necessary to remove the amorphous silicon portion 12 from the crystalline silicon film layer 1 and retain the first polycrystalline silicon portion 11, the etching rate of the first polycrystalline silicon portion 11 in both alkaline and acidic wet etching agents is very slow, and the etching effect of both alkaline and acidic wet etching agents on it is essentially negligible. Therefore, it is not necessary to form a mask layer on each first polycrystalline silicon portion 11, thereby reducing the steps of setting a mask layer on each first polycrystalline silicon portion 11 and the step of removing the mask layer after wet etching, simplifying the wet etching process and improving production efficiency. It should be noted that the hydrogen content of an amorphous silicon portion 12 herein may refer to the ratio of the total number of hydrogen bonds in the amorphous silicon portion 12 to the total number of all bonds in the amorphous silicon portion 12. The crystallization rate of an amorphous silicon portion 12 may refer to the ratio of crystals in the amorphous silicon portion 12. The porosity of an amorphous silicon portion 12 may refer to the percentage of the total volume of pores in the amorphous silicon portion 12 to the total volume of the amorphous silicon portion 12 .

[0082] It should be noted that there is no specific limitation on how much lower the crystallization rate of the amorphous silicon portion 12 is than that of the first polycrystalline silicon portion 11, or how much greater the hydrogen content and porosity of the amorphous silicon portion 12 are than those of the first polycrystalline silicon portion 11. The method for determining the hydrogen content, crystallization rate, and porosity of the amorphous silicon portion 12 herein can refer to the method for determining the hydrogen content, crystallization rate, and porosity of the first polycrystalline silicon portion 11 described above. To avoid repetition, these details are not repeated here.

[0083] The present invention also provides a method for preparing any of the aforementioned crystalline silicon film layers 1. The method may include the following steps:

[0084] Step 101, providing an amorphous silicon film layer. The crystallization rate of the amorphous silicon film layer is lower than the crystallization rate of the first polycrystalline silicon portion 11, and the hydrogen content and porosity of the amorphous silicon film layer are both greater than the hydrogen content and porosity of the first polycrystalline silicon portion 11. The hydrogen content in the amorphous silicon film layer here may refer to the ratio of the total number of hydrogen bonds in the amorphous silicon film layer to the total number of all bonds in the amorphous silicon film layer. The crystallization rate in the amorphous silicon film layer may refer to the ratio of crystals in the amorphous silicon film layer. The porosity in the amorphous silicon film layer may refer to the percentage of the total volume of pores in the amorphous silicon film layer to the total volume of the amorphous silicon film layer. The method for determining the hydrogen content, crystallization rate, and porosity of the amorphous silicon film layer here can refer to the method for determining the hydrogen content, crystallization rate, and porosity in the aforementioned first polycrystalline silicon portion 11. In order to avoid repetition, it will not be repeated here.

[0085] Step 102: Infrared light is used to heat the amorphous silicon film layer until the temperature of the amorphous silicon film layer reaches a preset temperature. Laser light is then used to hydrogenate and crystallize at least a portion of the amorphous silicon film layer. The portion subjected to the laser light treatment forms a first polycrystalline silicon portion. The preset temperature is 5%-30% of the laser light temperature. The laser light temperature refers to the temperature of the surface of an object when the laser light is applied to the surface, which can be measured using an infrared temperature measuring gun. Infrared light heating and laser light application may be performed simultaneously, or infrared light heating may be performed first, followed by laser application.

[0086] Figure 5 shows a schematic diagram of crystallization and hydrogenation according to some embodiments of the present invention. Figure 6 shows a schematic diagram of a prior art crystallization and hydrogenation process. In the present invention, the primary purpose of using infrared light 31 to heat the amorphous silicon film layer 2 is: first, infrared light 31 causes virtually no damage, and infrared light 31 provides a sufficient heat base for the amorphous silicon film layer 2, thereby reducing the energy of laser light 32 and, in turn, minimizing laser damage. Second, hydrogen has a high absorption rate for infrared light 31, facilitating the slow release of hydrogen, which can significantly reduce porosity. Third, infrared light 31 can easily raise the temperature of the amorphous silicon film layer 2 to the preset temperature. Compared to the prior art method shown in Figure 6, which uses only laser light 32 for crystallization and hydrogenation, the present invention utilizes the auxiliary heating provided by infrared light 31, reducing the energy of laser light 32 and minimizing laser damage. Furthermore, hydrogen has a high absorption rate for infrared light 31, facilitating the slow release of hydrogen. Furthermore, infrared light 31 can easily raise the temperature of the amorphous silicon film layer 2 to the preset temperature.

[0087] It should be noted that in the present invention, infrared light 31 is used to heat the entire amorphous silicon film layer 2. Compared to using infrared light 31 to heat only the portion that requires crystallization and hydrogenation, this method, on the one hand, eliminates the need for alignment, simplifying the heating process, and on the other hand, heats the entire amorphous silicon film layer 2 more evenly, resulting in a more uniform stress distribution, which can reduce warping. For example, the amorphous silicon film layer 2 can be placed on an auxiliary table, and infrared light can be used to heat the auxiliary table to a predetermined temperature.

[0088] The preset temperature is 5%-30% of the temperature of the laser. At this preset temperature, the laser and the infrared light work well together, which is conducive to the slow release of hydrogen. The slow release of hydrogen can greatly reduce the porosity. At the same time, the preset temperature of the infrared light is easy to reach. When combined with the laser, it can achieve good crystallization and hydrogenation effects, and the laser damage caused by the laser is smaller. In the present invention, the main purpose of the combination of the laser and the infrared light is to facilitate the slow release of hydrogen, the slow release of hydrogen, and reduce laser damage. There is no excessive limit on the improvement of the crystallization rate. For example, the temperature can be 5%, or 8%, or 9%, or 10%, or 13.5%, or 17%, or 17.5%, or 18%, or 21%, or 28%, or 30% of the temperature of the laser.

[0089] The portion of the amorphous silicon film layer 2 that is acted upon by the laser beam 32 forms the first polysilicon portion 11. The portion that is not acted upon by the laser beam 32 serves as the amorphous silicon portion.

[0090] In some embodiments, the infrared light 31 heating and the laser 32 action are performed simultaneously, that is, while the infrared light 31 heats the amorphous silicon film layer 2, the laser 32 is used to hydrogenate and crystallize at least a portion of the amorphous silicon film layer 2. The infrared light 31 heats the amorphous silicon film layer 2 in order to heat the amorphous silicon film layer 2 to the aforementioned preset temperature.

[0091] In some embodiments, infrared light 31 is used for heating first, followed by laser 32. Heating with infrared light 31 first and then laser 32 means that infrared light 31 is first used to heat the amorphous silicon film layer 2 to the aforementioned preset temperature, and then laser 32 is used to hydrogenate and crystallize at least a portion of the amorphous silicon film layer 2.

[0092] Optionally, in the present invention, the power of laser 32 is 20W to 200W. Lasers at this power facilitate the slow release of hydrogen, which can significantly reduce porosity and cause less laser damage. At the same time, the degree of crystallization and hydrogenation is more appropriate. The preset temperature is 100°C to 300°C. The infrared light 31 can easily raise the temperature of the amorphous silicon film layer 2 to this preset temperature. Moreover, with the assistance of this preset temperature, laser damage is reduced, the hydrogen release rate is more appropriate, and the porosity can be further reduced.

[0093] For example, in the present invention, the power of the laser 32 is 20 W, or 30 W, or 50 W, or 60 W, or 90 W, or 105 W, or 110 W, or 113 W, or 140 W, or 170 W, or 200 W. The preset temperature can be 100° C., or 110° C., or 140° C., or 160° C., or 190° C., or 197° C., or 200° C., or 210° C., or 260° C., or 290° C., or 300° C.

[0094] It should be noted that, in the present invention, there is no limitation on the wavelength of infrared light 31, nor on the wavelength of laser light 32. For example, the wavelength of infrared light 31 can be 50 nm to 3000 nm. Laser light 32 can be a nanosecond laser of 500 to 600 nm. Alternatively, laser light 32 can be green light with a pulse width of 10 ns to 100 ns, a spot size of 20 μm to 300 μm (micrometers), and a wavelength of 492 nm to 577 nm.

[0095] Figure 7 shows a schematic diagram of a laser according to some embodiments of the present invention. In Figure 7, the black and white triangles distributed above and below are both triangular laser spots. Figure 8 shows a schematic diagram of a laser in the prior art. Referring to Figure 8, in the prior art, heptagonal laser spots are often used in the photovoltaic field. However, the inventors found that the square laser spot has more sides, and each side inevitably has burrs, etc., which makes it difficult to splice into a regular pattern during the splicing process. Moreover, due to the large number of burrs, the laser damage area is large, and the distribution is irregular, making it difficult to remove the damage caused by the laser. Optionally, to address this problem, the inventors creatively adjusted the spot shape of the laser 32 to a triangle, as shown in Figure 7. Compared with the square, the triangle has fewer sides and fewer burrs. During the splicing process, it is easier to splice into a regular pattern. Moreover, due to the fewer burrs, the laser damage area is smaller, and the distribution is more regular, making it easier to remove the damage caused by the laser.

[0096] More specifically, the triangular laser spot can be an equilateral triangle laser spot, which is easier to splice into a regular pattern during the splicing process. Moreover, there are fewer burrs, fewer laser damage areas, and a more regular distribution, making it easier to remove the damage caused by the laser.

[0097] Optionally, step 101 may include providing a substrate. On a first surface of the substrate, gaseous silicon is deposited onto the substrate using LPCVD (Low Pressure Chemical Vapor Deposition) to form an amorphous silicon film layer 2 having a crystallization ratio of 5% to 40% and a porosity of 0.1% to 20%. Alternatively, gaseous silicon is deposited onto the substrate using PECVD (Plasma Enhanced Chemical Vapor Deposition) to form an amorphous silicon film layer 2 having a crystallization ratio of 5% to 30% and a porosity of 0.1% to 20%. In the PECVD method, the process parameters include at least one of the following five process parameters: the RF power supply switching ratio is 1 / 5-4 / 5; the number of discharges is 20,000-50,000 times; the discharge gas is a mixed gas formed by hydrogen, nitrogen and argon; in the mixed gas, the volume concentration of hydrogen is 5%-70%, and the volume concentration of argon is 10%-80%; the power of the RF power supply is 5000w-15000w; and the process temperature is 300℃-500℃.

[0098] Specifically, the substrate serves as the deposition carrier for the amorphous silicon film layer 2, and the substrate material is not specifically limited. LPCVD is used. Due to the constant temperature during the LPCVD deposition process, the amorphous silicon film layer 2 undergoes a certain degree of crystallization, with a crystallization rate between 5% and 40% and a porosity between 0.1% and 20%. Due to the lower deposition temperature of PECVD, the crystallization rate of the amorphous silicon film layer 2 is also lower, ranging from 5% to 30%, and a porosity between 0.1% and 20%. In the PECVD method, the RF power supply on-off ratio is adjusted, using a smaller on-off ratio and a more frequent on-off frequency to achieve high-quality film deposition. Specifically, the on-off ratio ranges from 1 / 5 to 4 / 5, and the number of discharges is between 20,000 and 50,000. By adjusting the RF power supply on-off ratio and the number of discharges, a high-quality amorphous silicon film layer 2 with a thickness variability within 5% is obtained. And / or, in the PECVD method, the discharge gas is a mixture of hydrogen, nitrogen, and argon. In this mixed gas, the volume concentration of hydrogen is 5%-70%, and the volume concentration of argon is 10%-80%. The present invention uses a mixed discharge of nitrogen, argon, and hydrogen. Hydrogen molecules are small and are more easily ionized and enter the amorphous silicon film layer 2. The above-mentioned nitrogen and argon gases assist in ionization. The molecules of these nitrogen and argon gases are larger than those of hydrogen, and are less likely to ionize and enter the amorphous silicon film layer 2, which can reduce porosity. The above-mentioned nitrogen and argon gases can also ensure the ionization effect. At the same time, when the substrate is a silicon base, nitrogen easily reacts with the silicon base, while argon is relatively expensive. Using nitrogen and argon with a volume concentration of 10%-80% can reduce costs and reduce reactions with the silicon base compared to using only one of the two. And / or, in the PECVD method, the power of the RF power supply is 5000W-15000W. The relatively low power of the RF power supply can reduce power consumption and appropriately reduce the crystallization rate of the amorphous silicon film layer 2, thereby reducing the thickness variability of the amorphous silicon film layer 2. And / or, in the PECVD method, the process temperature is 300°C-500°C, which can reduce power consumption and appropriately reduce the crystallization rate of the amorphous silicon film layer 2, thereby reducing the thickness variability of the amorphous silicon film layer 2. Because the thickness variability of the amorphous silicon film layer 2 is small, the thickest part is not too thick, and the cleaning time for the amorphous silicon film layer 2 can be reduced by 10% to 50%.

[0099] For example, the substrate can be a silicon substrate, and in the PECVD method: the RF power switch ratio can be 1 / 5, or 1 / 4, or 1 / 3, or 2 / 5, or 1 / 2, or 3 / 5, or 2 / 3, or 3 / 4, or 4 / 5. The number of discharges can be 20,000 times, or 22,000 times, or 29,000 times, or 33,000 times, or 34,000 times, or 35,000 times, or 37,000 times, or 40,000 times, or 50,000 times; the discharge gas is a mixed gas formed by hydrogen, nitrogen and argon, in which the volume concentration of hydrogen can be 5%, or 10%, or 19%, or 26%, or 35%, or 37.5%, or 50%, or 70%, and the volume concentration of argon can be 10%, or 30%, or 40%, or 50%. 0%, or 60%, or 67.5%, or 70%, or 80%; the power of the RF power supply can be 5000W, or 6000W, or 7000W, or 9000W, or 9600W, or 10000W, or 11000W, or 13000W, or 14000W, or 15000W; the process temperature can be 300℃, or 310℃, or 360℃, or 390℃, or 400℃, or 405℃, or 430℃, or 480℃, or 500℃.

[0100] Optionally, providing the substrate may include polishing the first surface of the substrate to obtain a first surface with a reflectivity of 30%-50%, so that the first surface of the substrate is flatter. On a flatter first surface, it is easier to obtain an amorphous silicon film layer 2 with better film quality.

[0101] For example, the first surface of the substrate is polished to obtain a first surface with a reflectivity of 30%, or 32%, or 39%, or 40%, or 41%, or 46%, or 49%, or 50%.

[0102] It should be noted that the polishing etchant is not specifically limited. For example, the polishing etchant may include an alkali solution and an etching additive, wherein the mass concentration of the alkali in the polishing etchant is 1%-20%, and the mass concentration of the etching additive is 1%-20%.

[0103] The present invention also provides a solar cell, comprising: a silicon substrate, a tunneling oxide layer located on the silicon substrate, and a doped crystalline silicon film layer located on the tunneling oxide layer, wherein the doped crystalline silicon film layer comes from any of the aforementioned crystalline silicon film layers 1 or comes from a crystalline silicon film layer 1 prepared by any of the aforementioned preparation methods of the crystalline silicon film layer 1. In the present invention, "the doped crystalline silicon film layer comes from any of the aforementioned crystalline silicon film layers 1" can be understood as the doped crystalline silicon film layer being obtained by doping only the crystalline silicon film layer 1, or by first doping the crystalline silicon film layer 1 and then being affected by subsequent steps in the process of forming a solar cell. In the present application, the doping of the crystalline silicon film layer can be performed while the crystalline silicon film layer is being formed, or can be performed after the crystalline silicon film layer is formed. Similarly, in the present invention, "the doped crystalline silicon film layer comes from a crystalline silicon film layer 1 prepared by any of the aforementioned preparation methods of the crystalline silicon film layer 1" can also be understood in the same way. In some embodiments, the doped crystalline silicon film layer here is: a film layer formed under the influence of a subsequent step after any of the aforementioned crystalline silicon film layers 1 are formed in the process of forming a solar cell. In some embodiments, the doped crystalline silicon film layer here is: a film layer formed under the influence of a subsequent step after the crystalline silicon film layer 1 is prepared by any of the aforementioned preparation methods of the crystalline silicon film layer 1 in the process of forming a solar cell. Therefore, the structure of the doped crystalline silicon film layer in the solar cell is similar to the structure of the aforementioned crystalline silicon film layer, and the doped crystalline silicon film layer in the solar cell may include a second polycrystalline silicon portion, and the second polycrystalline silicon portion penetrates the doped crystalline silicon film layer in the thickness direction of the doped crystalline silicon film layer. In the preparation of the solar cell, there is a high probability that other preparation processes after the crystalline silicon film layer 1 is set will also include a heating process, and the heating process may bring thermal effects to the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1. For example, the sintering of the electrode may cause certain thermal effects on the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1. This thermal effect is primarily reflected in an increase in the crystallization rate, which may in turn increase the crystallization rate of the first polycrystalline silicon portion 11. Therefore, the crystallization rate of the doped crystalline silicon film layer in the solar cell is greater than or equal to 60%. In some embodiments, the crystallization rate of the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1 is 50% to 60%, while the crystallization rate of the second polycrystalline silicon portion in the solar cell is 60% to 80%. The hydrogen content and porosity of the first polycrystalline silicon portion 11 are less affected by thermal effects. Therefore, in the solar cell, the hydrogen content and porosity of the second polycrystalline silicon portion are substantially the same as those of the first polycrystalline silicon portion 11. Therefore, in the solar cell, the hydrogen content of the second polycrystalline silicon portion is 1% to 20%, and the porosity of the second polycrystalline silicon portion is 0.1% to 10%.

[0104] As understood by those skilled in the art, the tunneling oxide layer refers to an ultra-thin oxide layer of 1-2 nm, which is generally formed of a material having a channel effect and a passivation effect, and a commonly used material is silicon oxide.

[0105] The doped crystalline silicon film layer is: in the process of forming a solar cell, after the crystalline silicon film layer 1 is prepared by any of the aforementioned preparation methods of the crystalline silicon film layer 1, a film layer is formed under the influence of its subsequent steps. In the aforementioned preparation method of the crystalline silicon film layer 1, the substrate may include a silicon base and a tunneling oxide layer located on the silicon base.

[0106] In this solar cell, the second polycrystalline silicon portion has a higher crystallization rate, a suitable hydrogen content, and a suitable porosity, resulting in a higher film quality and greater benefits for improving the solar cell's photoelectric conversion efficiency. Other advantages of this solar cell can be found in the aforementioned description of the crystalline silicon film layer 1 or the method for preparing the crystalline silicon film layer 1, and similar or similar beneficial effects are achieved. These advantages are not further detailed here to avoid repetition. The specific type of this solar cell is not limited.

[0107] Optionally, the doped crystalline silicon film layer is entirely composed of the second polycrystalline silicon part, that is, referring to Figure 1, the crystalline silicon film layer 1 is entirely composed of the first polycrystalline silicon part 11, and the surface of the silicon substrate away from the crystalline silicon film layer 1 is a velvet structure. For the preparation of the solar cell, after the crystalline silicon film layer 1 is set, the surface of the silicon substrate away from the crystalline silicon film layer 1 can be textured. During the texture process, since the crystalline silicon film layer 1 is entirely composed of the first polycrystalline silicon part 11, the quality of the crystalline silicon film layer 1 is better, and the crystalline silicon film layer 1 will basically not be etched in the texture liquid. Therefore, there is no need to set a mask layer on the crystalline silicon film layer 1, which reduces the steps of setting the mask layer and removing the mask layer. The solar cell has fewer production steps and higher production efficiency.

[0108] Optionally, the thickness variability of the doped crystalline silicon film layer is less than 5%. Specifically, the doped crystalline silicon film layer herein is: a film layer formed under the influence of a subsequent step after any of the aforementioned crystalline silicon film layers 1 are formed during the formation of a solar cell. Or, the doped crystalline silicon film layer herein is: a film layer formed under the influence of a subsequent step after a crystalline silicon film layer 1 is prepared by any of the aforementioned methods for preparing a crystalline silicon film layer 1 during the formation of a solar cell. The influence of the subsequent steps described herein mainly refers to thermal influence, which has little effect on the variability of its thickness. Therefore, the thickness variability of the doped crystalline silicon film layer is also less than 5%. The thickness variability of the doped crystalline silicon film layer is also less than 5%, indicating that the thickness uniformity of the doped crystalline silicon film layer is good. During the processing of each doped crystalline silicon film layer, the thickest part will not be too thick, and the processing time will not be too long, which can also save process time and improve production efficiency. The method for determining the thickness variability of the doped crystalline silicon film layer can refer to the method for determining the thickness variability of the crystalline silicon film layer described above. To avoid repetition, it will not be described here.

[0109] The present invention also provides a method for preparing the aforementioned solar cell, comprising forming the aforementioned solar cell structure on one or both surfaces of a silicon substrate, and forming an antireflection layer and electrodes on a doped crystalline silicon film. This method can be used to form, for example, TOPCon cells and partial TOPCon cells. Those skilled in the art can prepare different types of cells based on actual needs. The specific process steps can refer to known procedures in the industry and are not further described in this application.

[0110] The present invention also provides a back-contact solar cell, comprising: a silicon substrate; a first region and a second region projected onto the silicon substrate. The first and second regions are alternately arranged. The relative sizes of the first and second regions are not limited. The first region may include a stacked tunneling oxide layer and a first transport layer. The relative positions of the first transport layer and the tunneling oxide layer may be: the first transport layer is located on the surface of the silicon substrate near the tunneling oxide layer; the first transport layer is located on the silicon substrate and the tunneling oxide layer is located on the first transport layer; or the tunneling oxide layer is located on the silicon substrate and the first transport layer is located on the tunneling oxide layer, i.e., the tunneling oxide layer is located between the silicon substrate and the first transport layer. The first transport layer has a crystallinity greater than or equal to 60%, a hydrogen content of 1% to 20%, and a porosity of 0.1% to 10%. The first transport layer herein is a layer formed in the back-contact solar cell process after any of the aforementioned crystalline silicon film layers 1 are formed, and after the amorphous silicon portion is removed, and in the subsequent steps. Alternatively, the first transmission layer herein is a layer formed in the back-contact solar cell by removing the amorphous silicon portion after the crystalline silicon film layer 1 is prepared by any of the aforementioned methods for preparing the crystalline silicon film layer 1, and then undergoing subsequent steps. In the preparation of this back-contact solar cell, other preparation processes after the crystalline silicon film layer 1 is provided are likely to involve heating processes, which may thermally impact the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1. For example, electrode sintering and other processes may thermally impact the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1. This thermal impact is primarily reflected in an increase in the crystallization rate, which in turn may increase the crystallization rate of the first polycrystalline silicon portion 11. Therefore, the crystallization rate of the first transmission layer in the back-contact solar cell is greater than or equal to 60%. For example, the crystallization rate of the first polycrystalline silicon portion 11 of the crystalline silicon film layer 1 is 50% to 60%, while the crystallization rate of the first transmission layer in this back-contact solar cell is 60% to 80%. The hydrogen content and porosity of the first polysilicon part 11 are less affected by heat. Therefore, in the back-contact solar cell, the hydrogen content and porosity of the first transmission layer are basically the same as the hydrogen content and porosity of the first polysilicon part 11. Therefore, in the back-contact solar cell, the hydrogen content of the first transmission layer is 1% to 20%, and the porosity of the second polysilicon part is 0.1% to 10%.

[0111] The second region may include a second transport layer. The first transport layer and the second transport layer have different doping types, i.e., one of the first transport layer and the second transport layer is P-type doped and the other is N-type doped. It should be noted that the presence of a tunneling oxide layer in the second region is not limited. For example, the second region may not have a tunneling oxide layer. Even if the second region has a tunneling oxide layer, the relative position of the second transport layer and the tunneling oxide layer is not specifically limited.

[0112] As understood by those skilled in the art, the "second transmission layer" refers to a doped semiconductor layer such as doped polycrystalline silicon, doped amorphous silicon, etc., and the semiconductor layer can be doped by in-situ doping or non-in-situ doping, for example: non-in-situ doping through LPCVD combined with a doping process, or in-situ doping through PECVD.

[0113] The back contact solar cell has similar or similar beneficial effects as the aforementioned crystalline silicon film layer or crystalline silicon film layer, and will not be described in detail here to avoid repetition.

[0114] Optionally, the thickness variability of the first transmission layer is less than 5%. Specifically, the first transmission layer here is: in the process of forming a back-contact solar cell, after any of the aforementioned crystalline silicon film layers 1 are formed, the amorphous silicon portion is removed, and a film layer is formed under the influence of its subsequent steps. Or, the first transmission layer here is: in the process of forming a back-contact solar cell, after the crystalline silicon film layer 1 is prepared by any of the aforementioned preparation methods of the crystalline silicon film layer 1, the amorphous silicon portion is removed, and a film layer is formed under the influence of its subsequent steps. The influence of the subsequent steps described herein mainly refers to thermal influence, which has basically no effect on the variability of its thickness. Therefore, the thickness variability of the first transmission layer is also less than 5%. The thickness uniformity of the first transmission layer is good. In the process of processing the first transmission layer, the thickest part is not too thick, and the processing time is not too long. It can also save process time and improve production efficiency. The method for determining the thickness variability of the first transmission layer can refer to the method for determining the thickness variability of the aforementioned crystalline silicon film layer. In order to avoid repetition, it will not be repeated here.

[0115] The present invention also provides a method for preparing the aforementioned back-contact solar cell, comprising the following steps:

[0116] Step S1, providing a conductive substrate; the conductive substrate includes: a silicon substrate, a tunneling oxide layer sequentially stacked on the silicon substrate, and a crystalline silicon film layer, wherein the crystalline silicon film layer is any of the aforementioned crystalline silicon film layers, or the crystalline silicon film layer is prepared by any of the aforementioned crystalline silicon film layer preparation methods; the crystalline silicon film layer includes a first polycrystalline silicon portion and an amorphous silicon portion, and the first polycrystalline silicon portion and the amorphous silicon portion penetrate the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer; in the crystalline silicon film layer, the first polycrystalline silicon portion and the amorphous silicon portion are alternately distributed.

[0117] The silicon substrate, tunnel oxide layer, and crystalline silicon film layer may each include: a first region whose projection falls within the silicon substrate, and a second region whose projection falls within the silicon substrate, with the first and second regions being alternately distributed. In the crystalline silicon film layer, a first polycrystalline silicon portion is located within the first region, and an amorphous silicon portion is located within the second region. Both the amorphous silicon portion and the first polycrystalline silicon portion extend through the crystalline silicon film layer in the thickness direction, and the first polycrystalline silicon portion and the amorphous silicon portion are alternately distributed. That is, the crystalline silicon film layer may be the crystalline silicon film layer 1 shown in FIG. 2 .

[0118] Step S2, when each of the first polysilicon parts is not covered by the mask layer, wet etching is performed on the conductive substrate, each of the first polysilicon parts is retained in the wet etching, each of the amorphous silicon parts is removed in the wet etching, and the tunneling oxide layer or the second area of ​​the silicon substrate is exposed.

[0119] In step S2, the first polysilicon portion retained in the wet etching forms a first transmission layer under the influence of subsequent steps.

[0120] Step S3: forming a second transmission layer on the exposed second area.

[0121] In some embodiments, the crystalline silicon film layer can be the crystalline silicon film layer 1 shown in Figure 2. During the wet etching process of step S2, since the quality of the first polycrystalline silicon portion 11 is relatively good, the first polycrystalline silicon portion 11 is basically not etched in the wet etching solution. Therefore, there is no need to set a mask layer on each first polycrystalline silicon portion 11, reducing the steps of setting a mask layer on each first polycrystalline silicon portion 11 and reducing the step of removing the mask layer. The production steps of the back contact solar cell are fewer and the production efficiency is higher. It should be noted that in the process of wet etching to remove the amorphous silicon portion in the crystalline silicon film layer, the tunnel oxide layer underneath may also be etched away. Therefore, the portion of the silicon substrate located in the second region may also be exposed. If the tunnel oxide layer in the second region is not etched away, the second region of the tunnel oxide layer is exposed, and a second transmission layer is formed on the second region of the tunnel oxide layer. If the second region of the tunnel oxide layer is etched away, the second region of the silicon substrate is exposed, and a second transmission layer can be formed here on the second region of the tunnel oxide layer.

[0122] Optionally, the first transmission layer may be a P-type doped transmission layer, and the second transmission layer may be an N-type doped transmission layer, which can reduce thermal effects.

[0123] The present application is further explained below with reference to specific embodiments.

[0124] Example 1

[0125] A tunneling oxide layer is disposed on a silicon substrate. Both the tunneling oxide layer and the silicon substrate include a portion located in a first region and a portion located in a second region, with the first and second regions alternating. A first surface of the tunneling oxide layer, distal from the silicon substrate, includes a portion located in the first region and a portion located in the second region. A P-type doped amorphous silicon film layer 2 with a crystallization ratio of 5%-30%, a porosity of 0.1% to 20%, and a hydrogen content of 30%-40% is formed on the tunneling oxide layer using PECVD. The amorphous silicon film layer 2 is heated using infrared light until it reaches a preset temperature of 100°C and maintained at that temperature. A 20W laser is then used at a preset temperature of 100°C to hydrogenate and crystallize multiple portions of the amorphous silicon film layer 2 located in the first region. The portions exposed to the laser light form first polycrystalline silicon portions 11, while the portions not exposed to the laser light form amorphous silicon portions 12. Specifically, the portions of the amorphous silicon film layer 2 located in the second region form amorphous silicon portions 12, thereby forming a conductive substrate. The first polysilicon portion 11 and the amorphous silicon portion 12 both penetrate the crystalline silicon film layer 1 in the thickness direction of the crystalline silicon film layer 1. In the crystalline silicon film layer 1, the first polysilicon portion 11 and the amorphous silicon portion 12 are alternately distributed, and the resulting crystalline silicon film layer 1 is shown in Figure 2. In the PECVD method: the RF power switching ratio is 3 / 5, the number of discharges is 40,000 times, and the discharge gas is a mixed gas formed by hydrogen, nitrogen, and argon. In the mixed gas, the volume concentration of hydrogen is 40%, the volume concentration of argon is 43%, and the volume concentration of nitrogen is 17%. The power of the RF power supply is 10,000w, and the process temperature is 400°C.

[0126] Without a mask layer covering each first polysilicon portion 11, the conductive substrate is wet-etched using a wet etchant comprising an alkali and an additive. The etching time is 15 to 20 minutes. Each first polysilicon portion 11 is substantially not etched during the wet etching and remains substantially intact. Each amorphous silicon portion 12 is removed during the wet etching, exposing the second region of the tunnel oxide layer. The substrate is then cleaned with a mixed acid for another 15 to 20 minutes. The mixed acid may include HF, HNO3, H2SO4, etc. The purpose of the mixed acid is to neutralize the alkali in the wet etchant and etch away the portion of the tunnel oxide layer located in the second region, exposing the second region of the silicon substrate.

[0127] An N-type doped second transmission layer is formed on the exposed second area of ​​the silicon substrate.

[0128] Compared with the prior art, in which a polysilicon film layer with a relatively uniform texture is formed and then the polysilicon film layer on the second area is removed by laser, on the one hand, in Example 1, the laser only plays the role of hydrogenation and crystallization, and with the assistance of infrared light, the laser power is relatively small, and the laser damage is relatively small. On the other hand, in Example 1, the laser action area is shown in Figure 2, which is only the first polysilicon part 11. However, in the prior art, laser is used to remove the second area. Since in addition to forming another doped second transmission layer in the second area, an insulating area that mainly plays an insulating role needs to be left. The second area is larger, that is, the laser action area is larger. That is to say, compared with the prior art, the laser action area in this application is also smaller, and the laser damage is further greatly reduced.

[0129] Example 2

[0130] The infrared light heats the amorphous silicon film layer 2 until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 130°C and is kept warm. Then, a 30W laser is used, at a preset temperature of 12% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0131] The rest of Example 2 is the same as Example 1.

[0132] Example 3

[0133] The amorphous silicon film layer 2 is heated by infrared light until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 170°C and is kept warm. Then, a 40W laser is used, at which the preset temperature is 16% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0134] The rest of Example 3 is the same as Example 1.

[0135] Example 4

[0136] Infrared light heats the amorphous silicon film layer 2 until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 200°C and is kept warm. Then, a 50W laser is used, at a preset temperature of 19% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0137] The rest of Example 4 is the same as Example 1.

[0138] Example 5

[0139] The amorphous silicon film layer 2 is heated by infrared light until the temperature of the amorphous silicon film layer reaches a preset temperature of 230°C and is kept warm. Then, a 60W laser is used, at a preset temperature of 22% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0140] The rest of Example 5 is the same as Example 1.

[0141] Example 6

[0142] The amorphous silicon film layer 2 is heated by infrared light until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 270°C and is kept warm. Then, a 70W laser is used, at which the preset temperature is 26% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0143] The rest of Example 6 is the same as that of Example 1.

[0144] Example 7

[0145] The amorphous silicon film layer 2 is heated by infrared light until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 100°C and is kept warm. Then, a 100W laser is used, at which the preset temperature is 10% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0146] The rest of Example 7 is the same as that of Example 1.

[0147] Example 8

[0148] Infrared light heats the amorphous silicon film layer 2 until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 100°C and is kept warm. Then, a 120W laser is used, at which the preset temperature is 10% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0149] The rest of Example 8 is the same as that of Example 1.

[0150] Example 9

[0151] Infrared light heats the amorphous silicon film layer 2 until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 100°C and is kept warm. Then, a 150W laser is used, at which the preset temperature is 10% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0152] The rest of Example 9 is the same as that of Example 1.

[0153] Example 10

[0154] Infrared light heats the amorphous silicon film layer 2 until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 100°C and is kept warm. Then, an 180W laser is used, at a preset temperature of 10% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0155] The rest of Example 10 is the same as that of Example 1.

[0156] Example 11

[0157] The amorphous silicon film layer 2 is heated by infrared light until the temperature of the amorphous silicon film layer 2 reaches a preset temperature of 100°C and is kept warm. Then, a 200W laser is used, at which the preset temperature is 10% of the laser temperature, to hydrogenate and crystallize multiple parts of the amorphous silicon film layer 2.

[0158] The rest of Example 11 is the same as that of Example 1.

[0159] FIG9 shows a schematic diagram of the hydrogen content and crystallization rate distribution of the first polysilicon portion of various examples according to some embodiments of the present invention. In Examples 1 to 6, the amorphous silicon film layer 2 formed by PECVD is not subjected to laser crystallization and hydrogenation, and is directly cleaned using the wet etchant in Examples 1 to 6 under the same etching conditions. The cleaning parameters are shown in the second row of Table 1 below. The crystallization rate and hydrogen content of the first polysilicon portion 11 in the crystalline silicon film layer 1 formed after laser crystallization and hydrogenation in Examples 1 to 6 are measured. The measurement results are shown in Table 1 and FIG9. In FIG9, G1 represents Example 1, G2 represents Example 2, G3 represents Example 3, G4 represents Example 4, G5 represents Example 5, and G6 represents Example 6.

[0160] Table 1: Some process parameters and measurement results

[0161] Referring to the second row of Table 1, the amorphous silicon film layer 2 formed by PECVD in Examples 1 to 11 is not subjected to laser crystallization and hydrogenation, and is directly cleaned using the wet etchant described in Examples 1 to 11 under the same etching conditions. Cleaning is essentially complete in 6-12 minutes. As can be seen from Examples 1 to 11 and Table 1, the crystalline silicon film layer 1 formed after laser crystallization and hydrogenation in Examples 1 to 11 is cleaned using the wet etchant described in Examples 1 to 11 under the same etching conditions for 15-20 minutes. The first polysilicon portions 11 are essentially not etched during the wet etching process and are essentially retained. The specific reason is that, in the present invention, through the cooperation of infrared light assisted heating and laser, the temperature of the auxiliary heating and the laser power are perfectly coordinated, and the crystallization rate of the formed first polysilicon part 11 is more appropriate, and is conducive to the slow release of hydrogen. The slow release of hydrogen can greatly reduce the porosity, specifically reduce the porosity from 5%-35% to 0.1%-20%, and thus obtain the first polysilicon part 11 with excellent film quality. When there is no need to set a mask layer for each first polysilicon part 11, in the etchant, the first polysilicon part 11 with excellent film quality will basically not be etched and basically retained, thereby reducing the steps of setting a mask layer and removing the mask layer on each first polysilicon part 11, fewer process steps, and higher production efficiency.

[0162] In addition, it can be seen from Examples 7-11 in Table 1 and FIG. 9 that as long as the laser power is within the range defined by the present invention, changes in laser power will not substantially affect the properties of the crystalline silicon film layer, such as the crystallization rate and hydrogen content.

[0163] As can be seen from Table 1 and Figure 9, in the present invention, through the combination of infrared light-assisted heating and laser light, the auxiliary heating temperature and laser power are perfectly coordinated, and the crystallization rate of the first polycrystalline silicon portion 11 formed remains basically stable, rather than increasing continuously with increasing laser power. The hydrogen content is slowly released, reducing the hydrogen content and porosity. The cell efficiency of the BC battery produced from this crystalline silicon film layer is also improved.

[0164] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0165] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0166] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0167] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A crystalline silicon film layer, characterized in that: The crystalline silicon film layer comprises: a first polysilicon portion; wherein the first polysilicon portion penetrates the crystalline silicon film layer in a thickness direction of the crystalline silicon film layer; The crystallization rate of the first polysilicon portion is 50% to 60%; The hydrogen content in the first polysilicon portion is 1% to 20%; The porosity of the first polysilicon portion is 0.1% to 10%.

2. The crystalline silicon film layer according to claim 1, characterized in that: The first polysilicon portion is a doped polysilicon portion, and the doping concentration of the doped polysilicon portion is: 5×10 18 cm -3 Up to 1×10 20 cm -3 .

3. The crystalline silicon film layer according to claim 1, characterized in that: The thickness variability of the crystalline silicon film layer is less than 5%.

4. The crystalline silicon film layer according to any one of claims 1 to 3, characterized in that: The crystalline silicon film layer also includes: an amorphous silicon part; the amorphous silicon part penetrates the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer; in the crystalline silicon film layer, the first polycrystalline silicon part and the amorphous silicon part are alternately distributed; the crystallization rate of the amorphous silicon part is lower than the crystallization rate of the first polycrystalline silicon part, and the hydrogen content and porosity of the amorphous silicon part are both greater than the hydrogen content and porosity of the first polycrystalline silicon part.

5. A method for preparing a crystalline silicon film layer according to any one of claims 1 to 4, characterized in that: include: providing an amorphous silicon film layer; The amorphous silicon film layer is heated by infrared light until the temperature of the amorphous silicon film layer reaches a preset temperature, and at least a portion of the amorphous silicon film layer is hydrogenated and crystallized by laser, and the portion acted upon by the laser forms a first polycrystalline silicon portion; the preset temperature is 5%-30% of the temperature of the laser; wherein the infrared light heating and the laser action are performed simultaneously, or the infrared light heating is performed first and then the laser action.

6. The method for preparing a crystalline silicon film layer according to claim 5, characterized in that: The power of the laser is 20W to 200W; The preset temperature is 100°C to 300°C.

7. The method for preparing a crystalline silicon film layer according to claim 5 or 6, characterized in that: The spot shape of the laser is a triangle.

8. The method for preparing a crystalline silicon film layer according to claim 5 or 6, characterized in that: The providing of an amorphous silicon film layer comprises: providing a substrate; On the first surface of the substrate, the amorphous silicon film layer having a crystallization rate of 5%-40% and a porosity of 0.1%-20% is formed by LPCVD; Alternatively, the amorphous silicon film layer having a crystallization rate of 5%-30% and a porosity of 0.1%-20% is formed on the substrate by using a PECVD method.

9. The method for preparing a crystalline silicon film layer according to claim 8, characterized in that: In the PECVD method, the process parameters include at least one of the following five process parameters: The RF power switch ratio is 1 / 5-4 / 5; Discharge times: 20,000-50,000 times; The discharge gas is a mixed gas formed by hydrogen, nitrogen and argon; in the mixed gas, the volume concentration of hydrogen is 5%-70%, and the volume concentration of argon is 10%-80%; The power of RF power supply is 5000w-15000w; The process temperature is 300℃-500℃.

10. The method for preparing a crystalline silicon film layer according to claim 8, characterized in that: The providing of the substrate comprises: The first surface of the substrate is polished to obtain a first surface with a reflectivity of 30%-50%.

11. A solar cell, characterized in that: include: A silicon substrate, a tunneling oxide layer located on the silicon substrate, and a doped crystalline silicon film layer located on the tunneling oxide layer; the doped crystalline silicon film layer is a crystalline silicon film layer according to any one of claims 1 to 4 or a crystalline silicon film layer obtained by the method for preparing a crystalline silicon film layer according to any one of claims 5 to 10; The doped crystalline silicon film layer comprises: a second polysilicon portion; the second polysilicon portion penetrates the doped crystalline silicon film layer in a thickness direction of the doped crystalline silicon film layer; The crystallization rate of the second polysilicon portion is greater than or equal to 60%; The hydrogen content in the second polysilicon portion is 1% to 20%; The porosity of the second polysilicon portion is 0.1% to 10%.

12. The solar cell according to claim 11, characterized in that: The doped crystalline silicon film layer is entirely composed of the second polysilicon portion; The surface of the silicon substrate away from the doped crystalline silicon film layer is a velvet structure.

13. The solar cell according to claim 11 or 12, characterized in that: The thickness variability of the doped crystalline silicon film layer is less than 5%.

14. A back contact solar cell, characterized in that: include: Silicon substrate; The projection falls on a first area and a second area on the silicon substrate; The first region and the second region are alternately distributed; the first region includes: a tunneling oxide layer and a first transmission layer arranged in stacked layers; The first transmission layer comes from the crystalline silicon film layer described in any one of claims 1 to 4 or the crystalline silicon film layer obtained by the preparation method of the crystalline silicon film layer described in any one of claims 5 to 10; the crystallization rate of the first transmission layer is greater than or equal to 60%; the hydrogen content of the first transmission layer is 1% to 20%; the porosity of the first transmission layer is 0.1% to 10%; the second region includes a second transmission layer, and the second transmission layer is located on the exposed tunneling oxide layer or the silicon substrate; The first transmission layer and the second transmission layer have different doping types.

15. The back contact solar cell according to claim 14, characterized in that: The thickness variability of the first transmission layer is less than 5%.

16. A method for preparing a back contact solar cell according to claim 14 or 15, characterized in that: include: providing a conductive substrate; The conductive substrate comprises: a silicon substrate, a tunneling oxide layer sequentially stacked on the silicon substrate, and a crystalline silicon film layer; the crystalline silicon film layer is the crystalline silicon film layer described in any one of claims 1 to 4, or the crystalline silicon film layer is prepared by the method for preparing a crystalline silicon film layer described in any one of claims 5 to 10; the crystalline silicon film layer comprises: a first polycrystalline silicon portion and an amorphous silicon portion; the first polycrystalline silicon portion and the amorphous silicon portion penetrate the crystalline silicon film layer in the thickness direction of the crystalline silicon film layer; in the crystalline silicon film layer, the first polycrystalline silicon portion and the amorphous silicon portion are alternately distributed; In a case where the first polysilicon portion is not covered by a mask layer, wet etching is performed on the conductive substrate, wherein the first polysilicon portion is retained in the wet etching, the amorphous silicon portion is removed in the wet etching, and the tunneling oxide layer or the second region of the silicon substrate is exposed; A second transmission layer is formed on the exposed second area.

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