Semiconductor device and method of producing semiconductor device

Abstract

Provided is a semiconductor device having a narrow occupation area. The semiconductor device has a vertical transistor, a TGSA transistor, a first insulating layer, and a second insulating layer. Each of both of both the transistors has two gate electrodes (a gate electrode and a back gate electrode) provided such as to sandwich a semiconductor layer. The first insulating layer is positioned between one of a source electrode and a drain electrode and the back gate electrode of the vertical transistor and the second insulating layer is positioned between the back gate electrode and the other one of the source electrode and the drain electrode of the vertical transistor. A back gate insulating layer, the semiconductor layer, a gate insulating layer, and the gate electrode of the vertical transistor are provided, in the stated order, along an opening-portion sidewall provided to the first insulating layer, the back gate electrode, the second insulating layer, and the other one of the source electrode and the drain electrode. The TGSA transistor is provided on the second insulating layer. Back gate insulating layers of both of the transistors have a function of supplying oxygen to the semiconductor layers.

Description

Semiconductor device and method for manufacturing the same

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of the above, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely applied to electronic devices. In recent years, the applications of display devices have been diversified, and display devices are used in, for example, mobile information terminals, television devices (also referred to as television receivers), digital signage, and public information displays (PIDs). Examples of display devices include display devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs), display devices having liquid crystal elements, and electronic paper that displays using an electrophoretic method.

[0005] In a display device, by reducing the area occupied by a transistor, the pixel size can be reduced and the resolution can be increased. In addition, by reducing the area occupied by a transistor, the aperture ratio can be increased. Therefore, there is a demand for miniaturized transistors.

[0006] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] As described above, miniaturization of transistors and reduction of the area occupied by the transistors can realize high-definition display devices. However, as transistors are miniaturized, the so-called short channel effect (also referred to as SCE) becomes more likely to become apparent, which may lead to deterioration of transistor characteristics, such as a shift in threshold voltage to the normally-on side, an increase in off-current, and an increase in subthreshold swing value (Svalue).

[0010] Furthermore, display devices have other issues to be improved besides high definition, such as increasing operating speed and suppressing display unevenness, and these cannot be solved simply by uniformly miniaturizing transistors.

[0011] For example, in order to realize high-speed operation of a display device, a transistor included in a driver circuit is required to have a large on-state current. In this case, the on-state current can be increased by increasing the channel width of the transistor (more precisely, by increasing the channel width relative to the channel length), thereby enabling the display device to operate at a high speed.

[0012] Furthermore, for example, in order to suppress display unevenness in a display device, the transistors included in the pixel circuits are required to be transistors with small changes in drain current in the saturation region (hereinafter, sometimes referred to as "high saturation"). In this case, by increasing the channel length of the transistor (more precisely, by increasing the channel length relative to the channel width), the saturation can be increased, thereby suppressing display unevenness in the display device.

[0013] In order to achieve a display device that satisfies various requirements, it is preferable to arrange transistors having characteristics suited to the respective requirements in appropriate locations for each circuit constituting the display device. For example, it is preferable to use transistors with a short channel length and a large on-state current for the driver circuit. It is also preferable to use transistors with a long channel length and high saturation for the pixel circuit.

[0014] In view of the above, an object of one embodiment of the present invention is to provide a semiconductor device or a display device including a transistor with high on-state current and a transistor with high saturation. Another object is to provide a semiconductor device or a display device including a transistor with a short channel length and a transistor with a long channel length. Another object is to provide a semiconductor device or a display device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device or a display device with a small occupation area. Another object is to provide a semiconductor device or a display device with low power consumption. Another object is to provide a semiconductor device or a display device including a highly reliable transistor. Another object is to provide a semiconductor device or a display device with high definition. Another object is to provide a method for manufacturing a semiconductor device or a display device with high productivity. Another object is to provide a semiconductor device or a display device including a novel transistor, or a manufacturing method thereof.

[0015] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0016] One embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, a third insulating layer, and a fourth insulating layer. The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided on the first insulating layer with a region overlapping with the first conductive layer, the second insulating layer is provided on the first insulating layer and the second conductive layer, the third conductive layer is provided on the second insulating layer with a region overlapping with the second conductive layer, and a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, and the third insulating layer is provided with a first opening reaching the first conductive layer, and the third insulating layer is provided with a first opening extending from the first conductive layer to the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the the first semiconductor layer contacts a side surface of the insulating layer and a side surface of the third conductive layer, the first semiconductor layer contacts a top surface of the third conductive layer, a side surface of the third insulating layer, and a top surface of the first conductive layer in the first opening, the fifth conductive layer is provided on the second insulating layer in a region different from the third conductive layer, the fifth insulating layer is provided in contact with a top surface and a side surface of the fifth conductive layer, the second semiconductor layer is provided on the fifth insulating layer and has a region overlapping with the fifth conductive layer, the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer, a fourth conductive layer is provided on the fourth insulating layer, having a region overlapping with the first semiconductor layer; a sixth conductive layer is provided in the second opening and in contact with an upper surface of the second semiconductor layer; a seventh conductive layer is provided in the third opening and in contact with an upper surface of the second semiconductor layer; and an eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, having a region overlapping with the second semiconductor layer.

[0017] In the above, it is preferable that the first semiconductor layer and the second semiconductor layer contain metal oxide, the third insulating layer contains one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the fifth insulating layer contains one or both of silicon oxide and silicon oxynitride.

[0018] In the above, the third conductive layer and the fifth conductive layer preferably have a first material, and the first material is preferably one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0019] In the above, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the seventh insulating layer and the tenth insulating layer each preferably have one or both of silicon oxide and silicon oxynitride.

[0020] Another embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, the third insulating layer, and a fourth insulating layer. The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, the fourth insulating layer, and the fifth insulating layer. The first insulating layer is a first conductive layer. a fifth conductive layer and a fifth insulating layer, the second conductive layer being provided on the first insulating layer and having an area overlapping with the first conductive layer, the second insulating layer being provided on the first insulating layer and the second conductive layer, the third conductive layer being provided on the second insulating layer and having an area overlapping with the second conductive layer, and a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, and the third insulating layer is provided in the first opening and overlaps with the upper surface of the first conductive layer and the first the first semiconductor layer contacts a side surface of the insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer; the first semiconductor layer contacts a top surface of the third conductive layer, a side surface of the third insulating layer, and a top surface of the first conductive layer in the first opening; the fifth insulating layer is provided on the second insulating layer to have a region overlapping with the fifth conductive layer; the second semiconductor layer is provided on the fifth insulating layer to have a region overlapping with the fifth conductive layer; the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer; the fourth conductive layer is provided on the fourth insulating layer, having a region overlapping with the first semiconductor layer, the sixth conductive layer is provided in the second opening and in contact with the upper surface of the second semiconductor layer, the seventh conductive layer is provided in the third opening and in contact with the upper surface of the second semiconductor layer, and the eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, having a region overlapping with the second semiconductor layer.

[0021] In the above, it is preferable that the first semiconductor layer and the second semiconductor layer contain metal oxide, the third insulating layer contains one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the fifth insulating layer contains one or both of silicon oxide and silicon oxynitride.

[0022] In the above, the first conductive layer and the fifth conductive layer preferably have a first material, and the first material is preferably one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0023] In the above, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the seventh insulating layer and the tenth insulating layer each preferably have one or both of silicon oxide and silicon oxynitride.

[0024] Another embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, the third insulating layer, and a fourth insulating layer. The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, the fourth insulating layer, and a fifth insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided on the first insulating layer in a region overlapping with the first conductive layer, the fifth conductive layer is provided on the first insulating layer in a region different from the second conductive layer, the second insulating layer is provided on the first insulating layer, the second conductive layer, and the fifth conductive layer, the third conductive layer is provided on the second insulating layer in a region overlapping with the second conductive layer, and a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, and the third insulating layer is provided in the first opening. the first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer; the first semiconductor layer is in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and an upper surface of the first conductive layer in the first opening; the fifth insulating layer is provided on the second insulating layer to have a region overlapping with the fifth conductive layer; the second semiconductor layer is provided on the fifth insulating layer to have a region overlapping with the fifth conductive layer; and the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer. a fourth conductive layer is provided on the fourth insulating layer, having a region overlapping with the first semiconductor layer, a sixth conductive layer is provided in the second opening and in contact with an upper surface of the second semiconductor layer, a seventh conductive layer is provided in the third opening and in contact with an upper surface of the second semiconductor layer, and an eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, having a region overlapping with the second semiconductor layer.

[0025] In the above, it is preferable that the first semiconductor layer and the second semiconductor layer contain metal oxide, the third insulating layer contains one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the fifth insulating layer contains one or both of silicon oxide and silicon oxynitride.

[0026] In the above, the second conductive layer and the fifth conductive layer preferably have a first material, and the first material is preferably one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, niobium, and a metal oxide.

[0027] In the above, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide, and the seventh insulating layer and the tenth insulating layer each preferably have one or both of silicon oxide and silicon oxynitride.

[0028] Another embodiment of the present invention includes forming a first conductive layer, forming a first insulating film over the first conductive layer, forming the first conductive film over the first insulating film, processing the first conductive film to form a second conductive layer over the first insulating film to have a region overlapping with the first conductive layer, forming a second insulating film over the second conductive layer and the first insulating film, forming a third conductive layer in a region on the second insulating film that does not overlap with the first conductive layer and the second conductive layer, and forming a third conductive layer over the third conductive layer and the second insulating film. a first insulating layer having an area overlapping with the third conductive layer; a second conductive layer being formed on the first insulating layer and the second insulating layer; a second insulating layer having a first opening reaching the first conductive layer, a fourth conductive layer, a third insulating layer, and a fifth conductive layer being formed by removing parts of the first insulating layer, the second conductive layer, the second insulating layer, and the second conductive layer; a fourth insulating layer in contact with a side surface of the third insulating layer in the first opening and a side surface of the fifth conductive layer in the first opening, the fifth conductive layer being processed to form a sixth conductive layer having an area overlapping with the first conductive layer and the fourth conductive layer; a first semiconductor layer in contact with an upper surface of the first conductive layer in the first opening, a side surface of the fourth insulating layer in the first opening, and an upper surface of the sixth conductive layer; and a second semiconductor layer on the first insulating layer having an area overlapping with the third conductive layer. A method for manufacturing a semiconductor device includes forming a conductor layer, forming a third insulating film over a first semiconductor layer and a second semiconductor layer, processing the third insulating film to form a fifth insulating layer having a second opening and a third opening that reach the second semiconductor layer, and forming, over the fifth insulating layer, a seventh conductive layer overlapping with the first semiconductor layer, an eighth conductive layer overlapping with the second semiconductor layer and the third conductive layer, a ninth conductive layer overlapping with the second opening, and a tenth conductive layer overlapping with the third opening.

[0029] According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a transistor with high saturation current can be provided. Alternatively, a semiconductor device or display device including a transistor with a short channel length and a transistor with a long channel length can be provided. Alternatively, a semiconductor device or display device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device or display device with a small occupation area can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a semiconductor device or display device including a highly reliable transistor can be provided. Alternatively, a semiconductor device or display device with high definition can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a semiconductor device or display device including a novel transistor, or a manufacturing method thereof can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0031] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a cross-sectional view showing an example of a semiconductor device. FIG. 2A is a plan view showing an example of a semiconductor device. FIG. 2B is a cross-sectional view showing an example of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIG. 3B is a cross-sectional view showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 11A to 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 12A to 12C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 13A to 13C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 14A to 14C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 15A to 15C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a perspective view illustrating an example of a display device. FIG. 17B is a block diagram illustrating an example of a display device. FIG. 18A is a circuit diagram of a latch circuit. FIG. 18B is a circuit diagram of an inverter circuit. FIGS. 19A and 19B are circuit diagrams of pixel circuits. FIG. 19C is a cross-sectional view illustrating an example of a pixel circuit. FIG. 20 is a circuit diagram of a pixel circuit. FIGS. 21A and 21B are cross-sectional views illustrating an example of a display device. FIG. 22 is a cross-sectional view illustrating an example of a display device. FIGS. 23A to 23C are cross-sectional views illustrating an example of a display device. FIGS. 24A and 24B are cross-sectional views illustrating an example of a display device. FIG. 25 is a cross-sectional view illustrating an example of a display device. FIGS. 26A to 26D are views illustrating examples of electronic devices. FIGS. 27A to 27F are views illustrating examples of electronic devices. FIGS. 28A to 28G are views illustrating examples of electronic devices.

[0032] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0033] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0034] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0035] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0036] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0037] It should be noted that the terms "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0039] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as a source terminal and a drain terminal, a source electrode and a drain electrode, or the like, depending on the situation.

[0040] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0041] In addition, in this specification, "connection" includes "electrical connection."

[0042] "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when exchange of electrical signals or interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time when exchange of electrical signals or interaction of potentials does not occur between A and B during circuit operation, it can be said that "A and B are electrically connected" as long as there is a time when exchange of electrical signals or interaction of potentials occurs between A and B.

[0043] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0044] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, or when A and B are connected via the source and drain of one or more transistors. However, this is premised on the fact that there is a timing when an electrical signal is exchanged or an interaction of potential occurs between A and B.

[0045] An example in which it cannot be said that "A and B are electrically connected" because A and B are connected via an insulator is when a dielectric of a capacitive element, a gate insulating film of a transistor, etc. is interposed between A and B.

[0046] Examples of cases where A and B are connected without an insulator between them, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power supply, signal source, etc. (however, this does not include a case where the potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, but there is no timing at which both the transistor TrP and the transistor TrQ are turned on simultaneously.

[0047] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0048] In this specification, the phrase "top surface shapes are approximately the same" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are the same or approximately the same, or that the edges are aligned or approximately aligned.

[0049] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0050] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution resulting from the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0051] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0052] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0053] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0054] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0055] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0056] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0057] Embodiment 1 In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 9B. FIG.

[0058] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor.

[0059] The first transistor is a vertical transistor in which the source electrode and the drain electrode are provided at different heights relative to the substrate surface, and the second transistor is a planar transistor in which the source electrode and the drain electrode are provided on the same plane. Each of the first transistor and the second transistor has two gate electrodes provided to sandwich a semiconductor layer.

[0060] In the first transistor (vertical transistor), the channel length direction corresponds to the height direction (vertical direction) relative to the substrate surface, so the channel length can be determined by controlling the film thickness of the insulating layer sandwiched between the source electrode and the drain electrode. Therefore, a transistor with an extremely short channel length equal to or less than the minimum dimension (hereinafter also referred to as the minimum dimension) that can be exposed by an exposure apparatus used for manufacturing the transistor can be realized. Therefore, a miniaturized transistor with a large on-state current can be realized with high precision. Furthermore, since the first transistor has two gate electrodes sandwiching the semiconductor layer, it is easier to control the threshold voltage than when only one gate electrode is provided. Therefore, even when the channel length is extremely short, the adverse effects of the short channel effect can be suppressed.

[0061] The channel length of the second transistor (planar transistor) corresponds to a direction substantially parallel to the substrate surface, and therefore the channel length can be determined by the exposure performance of an exposure apparatus used for fabricating the transistor. Therefore, the channel length can be set to a length equal to or longer than the minimum dimension of the exposure apparatus, and a transistor with high saturation can be realized. Furthermore, since the second transistor has two gate electrodes disposed so as to sandwich the semiconductor layer, the saturation can be further improved compared to a transistor having only one gate electrode.

[0062] As described above, the semiconductor device of one embodiment of the present invention includes two transistors each having different characteristics over the same substrate. For example, when the semiconductor device of one embodiment of the present invention is a display device, the first transistor can be used as a transistor constituting a driver circuit of the display device, and the second transistor can be used as a transistor constituting a pixel circuit. Alternatively, both the first transistor and the second transistor can be used as transistors constituting the pixel circuit. This makes it possible to realize a high-performance display device that has a driver circuit portion with a narrow frame and high operating speed, and a high-definition display portion with little display unevenness.

[0063] A specific structural example of a semiconductor device according to one embodiment of the present invention will be described below.

[0064] <Configuration Example 1> Fig. 1A shows a plan view (also referred to as a top view) of a semiconductor device 10. Fig. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 1A. Note that Fig. 1A omits some of the components of the semiconductor device 10 (insulating layers, etc.). As with Fig. 1A , some of the components will also be omitted from plan views of semiconductor devices in the following drawings.

[0065] The semiconductor device 10 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The transistor 100 and the transistor 200 are provided over a substrate 102. The transistor 100 and the transistor 200 have different structures. The transistor 100 and the transistor 200 can be formed using some common steps.

[0066] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 116, an insulating layer 110s, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode), and part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 116 functions as a back gate electrode (also referred to as a second gate electrode), and part of the insulating layer 110s functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. Each layer constituting the transistor 100 can have a single-layer structure or a stacked-layer structure.

[0067] The transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202. In the transistor 200, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode), and another part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 202 functions as a back gate electrode (also referred to as a second gate electrode), and a part of the insulating layer 120 functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode. Each layer constituting the transistor 200 can have a single-layer structure or a stacked-layer structure. Note that the transistor 200 may not include the conductive layer 202.

[0068] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer for the transistor 100 and the transistor 200.

[0069] First, a description will be given of the structure of the transistor 100. Enlarged views of the transistor 100 shown in FIGS. 1A and 1B are shown in FIGS. 2A and 2B, respectively.

[0070] The conductive layer 112a is provided over the substrate 102. An insulating layer 110a, an insulating layer 110b, and an insulating layer 110c are stacked in this order over the conductive layer 112a. The insulating layer 110a has a region in contact with the top surface and side surfaces of the conductive layer 112a and the top surface of the substrate 102. It can also be said that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are provided so as to cover the top surface and side surfaces of the conductive layer 112a.

[0071] A conductive layer 116 is provided over the insulating layer 110c. The conductive layer 116 has a region overlapping with the conductive layer 112a with the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c interposed therebetween.

[0072] An insulating layer 110d, an insulating layer 110e, and an insulating layer 110f are stacked in this order on the insulating layer 110c and the conductive layer 116. The insulating layer 110d has a region in contact with the top surface and side surfaces of the conductive layer 116 and the top surface of the insulating layer 110c. It can also be said that the insulating layers 110d, 110e, and 110f are provided so as to cover the top surface and side surfaces of the conductive layer 116. It can also be said that the conductive layer 116 is sandwiched between the insulating layers 110a, 110b, and 110c and the insulating layers 110d, 110e, and 110f.

[0073] In this specification and the like, the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, the insulating layer 110e, and the insulating layer 110f may be collectively referred to as the insulating layer 110.

[0074] A conductive layer 112b is provided on the insulating layer 110f. The conductive layer 112b has a region overlapping with the conductive layer 116 with the insulating layers 110d, 110e, and 110f interposed therebetween. The conductive layer 112b also has a region overlapping with the conductive layer 112a with the insulating layer 110 and the conductive layer 116 interposed therebetween. It can also be said that the insulating layer 110 and the conductive layer 116 have a region sandwiched between the conductive layer 112a and the conductive layer 112b. The insulating layer 110, the conductive layer 116, and the conductive layer 112b have an opening 143 reaching the conductive layer 112a in the region overlapping with the conductive layer 112a. The conductive layer 112a is exposed in the opening 143.

[0075] The insulating layer 110s is provided so as to cover the sidewall of the opening 143. The insulating layer 110s has regions in contact with the side surfaces of the insulating layer 110, the conductive layer 116, and the conductive layer 112b within the opening 143. In addition, in a cross-sectional view, the upper end of the insulating layer 110s has a curved shape. The insulating layer 110s may be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0076] The semiconductor layer 108 is provided to cover the opening 143 via the insulating layer 110s. The semiconductor layer 108 has regions in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s, and the curved portion of the insulating layer 110s within the opening 143, and has a region in contact with the top surface of the conductive layer 112b outside the opening 143. The semiconductor layer 108 has a shape that follows the shapes of the top surface of the conductive layer 112b, the curved portion of the insulating layer 110s, the side surface of the insulating layer 110s, and the top surface of the conductive layer 112a. The semiconductor layer 108 has a region that overlaps with the conductive layer 112a via the conductive layer 112b, the conductive layer 116, and the insulating layer 110. It can also be said that the semiconductor layer 108 faces the side surface of the insulating layer 110, the side surface of the conductive layer 116, and the side surface of the conductive layer 112b within the opening 143 via the insulating layer 110s.

[0077] The semiconductor layer 108 has a region in contact with the conductive layer 112a and a region in contact with the conductive layer 112b, and is connected to these regions. The region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other of the source region and the drain region. In the semiconductor layer 108, a channel formation region is provided between the source region and the drain region.

[0078] 1B and the like show an example in which the end of the semiconductor layer 108 is located inside the end of the conductive layer 112b on the side that does not face the opening 143 in a plan view (also referred to as a top view); however, one embodiment of the present invention is not limited to this. A structure in which the semiconductor layer 108 extends to and covers the side surface of the conductive layer 112b on the side that does not face the opening 143 can also be used. This increases the contact area between the semiconductor layer 108 and the conductive layer 112b, thereby reducing the contact resistance between the semiconductor layer 108 and the conductive layer 112b and increasing the on-state current of the transistor 100. Alternatively, a structure in which the end of the semiconductor layer 108 extends further outward than the above and contacts the top surface of the insulating layer 110 can also be used.

[0079] The insulating layer 106 is provided to cover the opening 143 with the insulating layer 110s and the semiconductor layer 108 interposed therebetween. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110.

[0080] The conductive layer 104 is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween in the opening 143. FIG. 1B and other figures show an example in which part of the conductive layer 104 is provided to be embedded in the opening 143. The conductive layer 104 may have a shape that follows the shape of the top surface of the insulating layer 106.

[0081] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows in the vertical direction or approximately vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a vertical field effect transistor (VFET).

[0082] The channel length of the transistor 100 can be controlled by the thickness of the conductive layer 116 and the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length smaller than the minimum dimension of an exposure device used to manufacture the transistor can be manufactured with high accuracy. This also reduces the variation in characteristics among multiple transistors 100. Therefore, the operation of a semiconductor device including the transistor 100 can be stabilized and the reliability can be improved. Furthermore, the reduced variation in characteristics increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0083] The transistor 100 can have a source electrode, a layer having a channel formation region, and a drain electrode that are stacked, and therefore can occupy a significantly smaller area than a so-called planar transistor in which a layer having a channel formation region is arranged in a planar shape.

[0084] The conductive layer 112a, the conductive layer 112b, the conductive layer 116, and the conductive layer 104 can each function as a wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0085] 1B and the like illustrate an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 143 in the transistor 100; however, one embodiment of the present invention is not limited to this. A structure in which a step is formed by the conductive layer 116, the insulating layer 110, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step may also be used.

[0086] In the opening 143 of the transistor 100, one surface of the semiconductor layer 108 faces the conductive layer 104 with the insulating layer 106 interposed therebetween, and the other surface of the semiconductor layer 108 faces the conductive layer 116 with the insulating layer 110s interposed therebetween. As described above, in the transistor 100, the conductive layer 104 functions as a gate electrode, and the conductive layer 116 functions as a backgate electrode.

[0087] The potential of the back gate electrode (conductive layer 116) can be the same as that of the gate electrode (conductive layer 104). By applying a potential to the back gate electrode that turns on the transistor 100, the field-effect mobility of the transistor 100 can be increased. Furthermore, by changing the potential of the back gate electrode, the threshold voltage of the transistor 100 can be changed. Alternatively, the potential of the back gate electrode can be set to ground potential or any arbitrary potential. In this way, the potential of the region of the semiconductor layer 108 facing the back gate electrode can be fixed, thereby suppressing variations in the electrical characteristics of the transistor 100.

[0088] Alternatively, the potential of the back gate electrode can be set to the same potential as the source or drain electrode (the conductive layer 112a or the conductive layer 112b).

[0089] When the same potential as that of the gate electrode is applied to the back gate electrode, the back gate electrode and the gate electrode may be connected to each other to provide electrical continuity. When the same potential as that of the source electrode or the drain electrode is applied to the back gate electrode, the back gate electrode and the source electrode or the drain electrode may be connected to each other to provide electrical continuity. For example, by connecting the gate electrode or the back gate electrode to the source electrode, the reliability of the transistor 100 can be improved. Furthermore, by connecting the gate electrode or the back gate electrode to the drain electrode, the transistor 100 can function as a diode, for example.

[0090] Note that in the case where the potential of the back gate electrode is set to the ground potential or an arbitrary potential, a common wiring connected to the back gate electrodes of the plurality of transistors 100 may be provided and the potential may be applied to the common wiring.

[0091] As described above, the transistor 100 can have an extremely short channel length. Therefore, it can be said that the transistor 100 is a transistor in which the short-channel effect is likely to become apparent. The transistor 100 having a back gate electrode makes it easier to control the threshold voltage than a transistor without a back gate electrode, and thus can suppress the short-channel effect from becoming apparent.

[0092] Furthermore, by providing a backgate electrode, it may be possible to reduce variations in characteristics among the plurality of transistors 100. For example, it may be possible to reduce variations in threshold voltage among the plurality of transistors 100.

[0093] Next, the structure of the transistor 200 will be described. Enlarged views of the transistor 200 shown in FIGS. 1A and 1B are shown in FIGS. 3A and 3B, respectively. An enlarged cross-sectional view taken along dashed line B1-B2 in FIG. 1A is shown in FIG. 4.

[0094] The insulating layer 109 is provided on the insulating layer 110. The conductive layer 202 is provided on the insulating layer 109. The insulating layer 109 is provided over the entire region where the conductive layer 202 is provided. In a plan view, the insulating layer 109 preferably includes the conductive layer 202. An end of the conductive layer 202 contacts the upper surface of the insulating layer 109.

[0095] The insulating layer 120 is provided on the conductive layer 202. The insulating layer 120 has a region in contact with the upper surface and side surfaces of the conductive layer 202 and the upper surface of the insulating layer 109. In other words, the conductive layer 202 is surrounded by the insulating layer 109 and the insulating layer 120.

[0096] As shown in FIGS. 1B , 3B , and 4 , the edge of the insulating layer 120 preferably coincides with or substantially coincides with the edge of the insulating layer 109. It can also be said that the top surface shape of the insulating layer 120 coincides with or substantially coincides with the top surface shape of the insulating layer 109. For example, a first insulating film to be the insulating layer 109 is formed, a conductive layer 202 is formed on the first insulating film, and a second insulating film to be the insulating layer 120 is formed on the first insulating film and the conductive layer 202. Then, by processing the first insulating film and the second insulating film, the insulating layer 120 and the insulating layer 109 can be formed whose edge portions coincide with or substantially coincide with each other. Forming the insulating layer 109 and the insulating layer 120 in the same process can improve productivity of the semiconductor device 10 and reduce manufacturing costs. Here, a structure in which the first insulating film and the second insulating film are processed in the same process is shown, but one embodiment of the present invention is not limited thereto. The first insulating film and the second insulating film can also be processed in different processes. The end of the insulating layer 120 and the end of the insulating layer 109 may be aligned or not aligned substantially.

[0097] 1B and the like show an example in which the thickness of the insulating layer 110 is uniform regardless of location, but one embodiment of the present invention is not limited to this. A configuration in which the thickness of a region of the insulating layer 110 that overlaps with one or more of the insulating layer 120 and the insulating layer 109 is different from that of a region that does not overlap with either the insulating layer 120 or the insulating layer 109 may be employed. For example, when the insulating film that becomes the insulating layer 120 and the insulating layer 109 are processed to form the insulating layer 120 and the insulating layer 109, part of the insulating layer 110 is removed, so that the thickness of the region of the insulating layer 110 that does not overlap with either the insulating layer 120 or the insulating layer 109 may become thinner than the thickness of the region that overlaps with one or more of the insulating layer 120 and the insulating layer 109.

[0098] A semiconductor layer 208 is provided over the insulating layer 120. The semiconductor layer 208 has a region overlapping with the conductive layer 202 with the insulating layer 120 interposed therebetween. The same material as that of the semiconductor layer 108 can be used for the semiconductor layer 208. The semiconductor layer 208 can be formed in the same process as that of the semiconductor layer 108. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming films to be the semiconductor layer 108 and the semiconductor layer 208 and processing the films.

[0099] The insulating layer 120 is preferably provided in at least a region overlapping with the channel formation region of the transistor 200. Furthermore, as described above, it is preferable that the edge of the insulating layer 120 coincides or substantially coincides with the edge of the insulating layer 109. FIG. 1B and other figures illustrate a structure in which the edge of the insulating layer 109 is in contact with the top surface of the insulating layer 110. The semiconductor layer 208 covers the side surfaces of the insulating layer 120 and the insulating layer 109. That is, the semiconductor layer 208 has portions that protrude beyond the edges of the insulating layer 120 and the insulating layer 109. The edge of the semiconductor layer 208 is in contact with the top surface of the insulating layer 110. It can also be said that part of the bottom surface of the semiconductor layer 208 is in contact with the top surface of the insulating layer 110. Note that the insulating layer 120 may be provided over the entire region where the semiconductor layer 208 is provided, and the entire bottom surface of the semiconductor layer 208 may be in contact with the top surface of the insulating layer 120.

[0100] An insulating layer 106 is provided over the semiconductor layer 208. A portion of the insulating layer 106 (a region overlapping with the opening 143) functions as a gate insulating layer of the transistor 100, and another portion of the insulating layer 106 (a region overlapping with the conductive layer 202) functions as a gate insulating layer of the transistor 200. The insulating layer 106 has an opening 147a and an opening 147b in a region overlapping with the semiconductor layer 208. The opening 147a and the opening 147b are provided to sandwich a region of the insulating layer 106 that functions as a gate insulating layer of the transistor 200.

[0101] A conductive layer 204, a conductive layer 212a, and a conductive layer 212b are provided over the insulating layer 106. The conductive layer 204 has a region overlapping with the semiconductor layer 208 through the insulating layer 106 located in a region between the openings 147a and 147b. The conductive layer 204 also has a region overlapping with the conductive layer 202 through the semiconductor layer 208. The conductive layers 212a and 212b are provided so as to cover parts of the openings 147a and 147b, respectively. The conductive layer 212a has a region in contact with the top surface of the semiconductor layer 208 in the opening 147a, and the conductive layer 212b has a region in contact with the top surface of the semiconductor layer 208 in the opening 147b. The semiconductor layer 208 is connected to the conductive layers 212a and 212b. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed using the same material as the conductive layer 104. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process as the conductive layer 104. For example, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by forming films to be the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and processing the films.

[0102] The conductive layer 202 functioning as the back gate electrode of the transistor 200 preferably extends beyond the end of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction (see FIG. 3B ). That is, the size of the conductive layer 202 is preferably larger than the size of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction. Specifically, the conductive layer 202 preferably has a portion that protrudes beyond the end of the conductive layer 204 in the channel length direction.

[0103] A portion of the semiconductor layer 208 that overlaps with at least one of the conductive layer 204 and the conductive layer 202 functions as a channel formation region. The semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region and a pair of regions 208D that are located outside the pair of regions 208L. Note that, for ease of explanation, the portion of the semiconductor layer 208 that overlaps with the conductive layer 204 may be referred to as a channel formation region; however, a portion that does not overlap with the conductive layer 204 and overlaps with the conductive layer 202 (a portion including the region 208L and the region 208D) can also function as a channel formation region.

[0104] The regions 208L and 208D contain impurity elements. The impurity elements may be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity elements.

[0105] Using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks, an impurity element is supplied (also referred to as adding or injecting) to the semiconductor layer 208. As a result, a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106.

[0106] In the semiconductor layer 208, a region in contact with the conductive layer 212a and a region 208D adjacent to the region function as one of a source region and a drain region. In the semiconductor layer 208, a region in contact with the conductive layer 212b and a region 208D adjacent to the region function as the other of the source region and the drain region.

[0107] The transistor 200 is a planar transistor in which the semiconductor layer 208 is arranged in a planar shape. The transistor 200 is also a so-called top-gate transistor having a gate electrode above the semiconductor layer 208. For example, by supplying an impurity element to the semiconductor layer 208 using the conductive layer 204 functioning as the gate electrode as a mask, regions 208D functioning as source and drain regions can be formed in a self-aligned manner. The transistor 200 can be called a TGSA (Top Gate Self-Aligned) transistor.

[0108] The channel length of the transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of the transistor 200 is equal to or greater than the minimum dimension of an exposure apparatus used to manufacture the transistor. That is, the channel length of the transistor 200 can be made longer than the channel length of the transistor 100. By increasing the channel length, the transistor can have high saturation properties.

[0109] The transistor 100 having a short channel length and the transistor 200 having a long channel length can be formed over the same substrate by sharing some of the steps. For example, by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation, a high-performance semiconductor device can be obtained.

[0110] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0111] The detailed structures of the transistor 100 and the transistor 200 will be described.

[0112] The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0113] The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0114] Silicon can be used for each of the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for a channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for a channel formation region has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for a channel formation region has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0115] The semiconductor layer 108 and the semiconductor layer 208 each preferably include a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0116] The band gap of each of the metal oxides used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0117] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS: X-ray photoelectron spectrometry or ESCA: Electron spectrometry for chemical analysis), or X-ray absorption fine structure (XAFS: X-ray absorption fine structure). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the difference in energy between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0118] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0119] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0120] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0121] The insulating layer 110 preferably has a stacked structure. Figure 1B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, an insulating layer 110d on the insulating layer 110c, an insulating layer 110e on the insulating layer 110d, and an insulating layer 110f on the insulating layer 110e. The insulating layers 110a, 110b, 110c, 110d, 110e, and 110f can each be made of a material that can be used for the insulating layer 110.

[0122] The insulating layers 110a, 110b, 110c, 110d, 110e, and 110f can be preferably formed by, for example, sputtering or plasma-enhanced chemical vapor deposition (PECVD). It is preferable that the flow rate of a hydrogen-containing gas (e.g., hydrogen gas and ammonia gas) relative to the total deposition gas used in the formation of these layers is low, or that the partial pressure of the gas in the processing chamber of the deposition apparatus is low. This can reduce the amount of hydrogen contained in the insulating layers 110a, 110b, 110c, 110d, 110e, and 110f. Furthermore, by forming these layers by a method that does not use a hydrogen-containing gas, the amount of hydrogen contained in these layers can be significantly reduced. Sputtering can be preferably used in the formation of these layers. By reducing the hydrogen content in the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the insulating layer 110d, the insulating layer 110e, and the insulating layer 110f, the supply of hydrogen to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical characteristics of the transistor 100 can be stabilized.

[0123] The insulating layer 110s has a region in contact with the semiconductor layer 108. The region of the semiconductor layer 108 in contact with the insulating layer 110s can function as a channel formation region. Therefore, when a metal oxide is used for the semiconductor layer 108, the insulating layer 110s preferably contains oxygen. This can improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110s. Furthermore, it is more preferable to use a film that releases oxygen when heated for the insulating layer 110s. The insulating layer 110s releases oxygen due to heat applied during the manufacturing process of the transistor 100, and oxygen can be supplied to the semiconductor layer 108. Supplying oxygen from the insulating layer 110s to the semiconductor layer 108, particularly to the channel formation region, can eliminate oxygen vacancies (V Ｏ The oxygen vacancy (V) is repaired and the oxygen vacancy (V Ｏ ) can be reduced. Therefore, the transistor 100 can have favorable electrical characteristics and high reliability. For the insulating layer 110s, for example, one or more of an oxide and an oxynitride that can be used for the insulating layer 110 can be preferably used. Specifically, the insulating layer 110s preferably contains silicon and oxygen, and one or both of silicon oxide and silicon oxynitride can be preferably used.

[0124] Of the insulating layers 110, the insulating layer 110b sandwiched between the insulating layers 110a and 110c and the insulating layer 110e sandwiched between the insulating layers 110d and 110f preferably contain oxygen. Furthermore, it is more preferable to use a film that releases oxygen when heated for the insulating layers 110b and 110e. That is, it is preferable to use the same material for the insulating layers 110b and 110e as for the insulating layer 110s. This allows oxygen contained in the insulating layers 110b and 110e to be supplied to the channel formation region of the semiconductor layer 108 through the insulating layer 110s. Furthermore, since both the oxygen contained in the insulating layer 110s and the oxygen contained in the insulating layers 110b and 110e can be supplied to the channel formation region of the semiconductor layer 108, the reliability of the transistor 100 can be further improved.

[0125] For example, oxygen can be supplied to the insulating layer 110s, the insulating layer 110b, or the insulating layer 110e by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere on the insulating layer 110s, the insulating layer 110b, or the insulating layer 110e. Alternatively, oxygen can be supplied to the insulating layer 110b or the insulating layer 110e by forming an oxide film on the top surface of the insulating layer 110b or the insulating layer 110e by a sputtering method in an oxygen-containing atmosphere. The oxide film may then be removed. A method for supplying oxygen to the insulating layer 110b or the like will be described in Embodiment 2.

[0126] It is preferable that substances (e.g., atoms, molecules, and ions) diffuse easily in the insulating layer 110s, the insulating layer 110b, and the insulating layer 110e. It can also be said that the diffusion coefficient of substances in the insulating layer 110s, the insulating layer 110b, and the insulating layer 110e is preferably large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110s, the insulating layer 110b, and the insulating layer 110e. That is, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110s, the insulating layer 110b, and the insulating layer 110e is large. Oxygen contained in the insulating layer 110s diffuses in the insulating layer 110s and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s and the semiconductor layer 108. Oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the insulating layer 110s, and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110s and the semiconductor layer 108. Similarly, oxygen contained in the insulating layer 110e diffuses through the insulating layer 110e and is supplied to the insulating layer 110s, and then is supplied to the semiconductor layer 108 through the interface between the insulating layer 110s and the semiconductor layer 108. In this way, by making the insulating layer 110s, the insulating layer 110b, and the insulating layer 110e into which oxygen easily diffuses, the oxygen contained in the insulating layer can be efficiently supplied to the semiconductor layer 108 (particularly, the channel formation region).

[0127] A region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other of the source and drain regions. The source and drain regions have lower electrical resistance than the channel formation region. The source and drain regions can also be said to have a higher carrier concentration and a higher oxygen defect density than the channel formation region.

[0128] Of the insulating layers 110, the insulating layer 110a is provided between the conductive layer 112a and the insulating layer 110b. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 116. The insulating layer 110d is provided between the conductive layer 116 and the insulating layer 110e. The insulating layer 110f is provided between the insulating layer 110e and the conductive layer 112b. The insulating layers 110a, 110c, 110d, and 110f preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layers 110a, 110c, 110d, and 110f preferably are impermeable to substances. The insulating layers 110a, 110c, 110d, and 110f can also be said to function as barrier films. Specifically, the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110f preferably have a low impurity permeability, which can prevent impurities contained in the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110f from diffusing into the channel formation region of the semiconductor layer 108. Therefore, the transistor 100 can have favorable electrical characteristics and high reliability.

[0129] It is preferable that the insulating layers 110a, 110c, 110d, and 110f are made of a material that is less permeable to oxygen. This can prevent oxygen contained in the insulating layer 110b and oxygen contained in the insulating layer 110e from diffusing toward the conductive layer 112a via the insulating layer 110a and the insulating layer 110d, respectively. Similarly, it can prevent oxygen contained in the insulating layer 110b and oxygen contained in the insulating layer 110e from diffusing toward the conductive layer 112b via the insulating layer 110c and the insulating layer 110f, respectively. This increases the amount of oxygen supplied from the insulating layer 110b and the insulating layer 110e to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies (V Ｏ ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ H). Therefore, the transistor 100 can have favorable electrical characteristics and high reliability. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110b and oxygen contained in the insulating layer 110e, and the electrical resistance of the conductive layer 112a can be prevented from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b and oxygen contained in the insulating layer 110e, and the electrical resistance of the conductive layer 112b can be prevented from being increased. Therefore, the transistor 100 can have a large on-state current.

[0130] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of suppressing the diffusion of a target substance (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0131] The insulating layers 110a, 110c, 110d, and 110f, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layers 110a, 110c, 110d, and 110f can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. The insulating layers 110a, 110c, 110d, and 110f can each be made of the same material. Using the same material allows the insulating layers to be formed using the same equipment, thereby improving productivity and reducing manufacturing costs. Alternatively, different materials may be used for the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110f.

[0132] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0133] The insulating layers 110a, 110c, 110d, and 110f are preferably formed by a method that does not use a gas containing hydrogen. For example, sputtering can be suitably used to form the insulating layers 110a, 110c, 110d, and 110f. For the insulating layers 110a, 110c, 110d, and 110f, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly suitably used, respectively.

[0134] The insulating layer 110c provided over the insulating layer 110b and the insulating layer 110f provided over the insulating layer 110e are preferably formed in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110b when the insulating layer 110c is formed. Similarly, oxygen can be supplied to the insulating layer 110e when the insulating layer 110f is formed. Materials containing oxygen are particularly suitable for use for the insulating layers 110c and 110f. The higher the ratio of the flow rate of oxygen gas to the total flow rate of the film formation gas used to form the insulating layer 110c (hereinafter also referred to as the oxygen flow ratio) or the oxygen partial pressure in the treatment chamber of the film formation apparatus, the more efficiently oxygen can be supplied to the insulating layer 110b. By performing the same process as above for the insulating layer 110f, oxygen can be efficiently supplied to the insulating layer 110e.

[0135] The thickness of each of the insulating layer 110a and the insulating layer 110d (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 50 nm or more and 300 nm or less, even more preferably 100 nm or more and 300 nm or less, even more preferably 100 nm or more and 250 nm or less, even more preferably 150 nm or more and 250 nm or less.

[0136] If the insulating layer 110a is thin, oxygen contained in the insulating layer 110b may diffuse toward the conductive layer 112a through the insulating layer 110a, thereby reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110d is thin, oxygen contained in the insulating layer 110e may diffuse toward the conductive layer 112a through the insulating layer 110d, thereby reducing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. On the other hand, if the insulating layer 110a is thick, the amount of impurities released from the insulating layer 110a may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110d is thick, the amount of impurities released from the insulating layer 110d may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. By setting the thickness of each of the insulating layers 110a and 110d within the above-mentioned range, the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the conductive layer 112a from being oxidized by the oxygen contained in the insulating layer 110b and the insulating layer 110e, which would otherwise increase the electrical resistance of the conductive layer 112a. Note that the thicknesses of the insulating layer 110a and the insulating layer 110d are not limited to the above-mentioned ranges.

[0137] The thickness of each of the insulating layer 110c and the insulating layer 110f (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 20 nm or more and 200 nm or less, even more preferably 30 nm or more and 200 nm or less, even more preferably 50 nm or more and 200 nm or less, even more preferably 50 nm or more and 150 nm or less.

[0138] If the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110f is thick, the amount of impurities released from the insulating layer 110f may increase, resulting in a larger amount of impurities diffusing into the channel formation region of the semiconductor layer 108. On the other hand, if the insulating layer 110c is thin, oxygen contained in the insulating layer 110b may diffuse toward the conductive layer 112b via the insulating layer 110c, resulting in a smaller amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Similarly, if the insulating layer 110f is thin, oxygen contained in the insulating layer 110e may diffuse toward the conductive layer 112b via the insulating layer 110f, resulting in a smaller amount of oxygen supplied to the channel formation region of the semiconductor layer 108. By setting the thicknesses of the insulating layer 110c and the insulating layer 110f within the above-mentioned ranges, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the conductive layer 112b from being oxidized by oxygen contained in the insulating layer 110b and the insulating layer 110e, which would otherwise increase the electrical resistance of the conductive layer 112b. Note that the thicknesses of the insulating layer 110c and the insulating layer 110f are not limited to the above-described ranges.

[0139] Note that when the channel length of the transistor 100 is short, the impurities diffusing into the channel formation region have a greater effect on the electrical characteristics of the transistor 100. Therefore, it is preferable to use materials that release less impurities (especially hydrogen) from the insulating layers 110a, 110c, 110d, and 110f. Furthermore, it is more preferable that the thicknesses of the insulating layers 110a, 110c, 110d, and 110f are thin. This reduces the amount of impurities diffusing into the channel formation region, and the transistor 100 can exhibit good electrical characteristics and high reliability even when the channel length is short. For example, when the channel length is 500 nm or less, the thickness of each of the insulating layers 110a, 110c, 110d, and 110f is preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less, further preferably 3 nm or more and 30 nm or less, further preferably 3 nm or more and 20 nm or less, further preferably 3 nm or more and 10 nm or less, and further preferably 5 nm or more and 10 nm or less.

[0140] Note that although the insulating layer 110 has a six-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a single layer, a two-layer structure, a three-layer structure, a four-layer structure, a five-layer structure, or a seven or more layer structure.

[0141] The insulating layer 109 (see FIG. 4 ) provided between the conductive layer 112 b and the conductive layer 202 has a function of insulating the conductive layer 112 b from the conductive layer 202. The insulating layer 109 can be formed using the same material as that used for the insulating layer 110.

[0142] The insulating layer 109, which has a region in contact with the conductive layer 112b and the conductive layer 202, is preferably formed using a material that releases impurities that reduce the electrical resistance of the conductive layer 112b and the conductive layer 202. When a metal oxide is used for the conductive layer 112b, the impurity preferably contains hydrogen. Examples of the impurity include water and hydrogen. This increases the carrier concentration of the conductive layer 112b, thereby reducing the electrical resistance. Therefore, the transistor 100 can have a large on-state current. Furthermore, the conductive layer 112b can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Similarly, when a metal oxide is used for the conductive layer 202, the impurity preferably contains hydrogen. Note that the impurities that reduce the electrical resistance of the conductive layer 112b and the conductive layer 202 may be the same or may be partially or entirely different. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 109.

[0143] The insulating layer 110f is provided between the insulating layer 109 and the insulating layer 110e. The insulating layer 110f functions as a barrier film, which can prevent impurities contained in the insulating layer 109 from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layer 110f. The insulating layer 109 preferably has a region containing more impurities than the insulating layer 110f. Specifically, the insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110f. The impurity contents of the insulating layer 109 and the insulating layer 110f can be analyzed by, for example, secondary ion mass spectrometry (SIMS). The insulating layer 120 preferably has a barrier insulating layer. This can prevent impurities contained in the insulating layer 109 from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layer 120.

[0144] The top surface shape of the opening 143 is not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or any other polygonal shape, or a shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other figures, "circular" is not limited to a perfect circle.

[0145] In this specification and the like, the top surface shape of the opening 143 refers to the shape of the top surface edge of the conductive layer 112b on the opening 143 side.

[0146] 2A and 2B, the channel length and the channel width of the transistor 100 will be described. Here, the case where a region of the semiconductor layer 108 in contact with the insulating layer 110s functions as a channel formation region will be described as an example.

[0147] 2B, the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the distance along the insulating layer 110s between the top surface of the conductive layer 112a and the top surface of the conductive layer 112b in the semiconductor layer 108.

[0148] Note that the channel length L100 of the transistor 100 may be a sum of the thicknesses of the insulating layers 110a, 110b, 110c, 116, 110d, 110e, and 110f in the region of the semiconductor layer 108 sandwiched between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b (in FIG. 2B , the thickness T110 is indicated by a dashed-dotted double-headed arrow). Alternatively, the channel length L100 of the transistor 100 may be a sum of the thickness T110 and the thickness of the conductive layer 112b.

[0149] The channel length L100 is determined by the thickness T110, the thickness of the conductive layer 112b, and the angle (angle θ110) between the surface on which the insulating layer 110s is to be formed (here, the side surfaces of the insulating layer 110a, the side surfaces of the insulating layer 110b, the side surfaces of the insulating layer 110c, the side surfaces of the conductive layer 116, the side surfaces of the insulating layer 110d, the side surfaces of the insulating layer 110e, the side surfaces of the insulating layer 110f, and the side surfaces of the conductive layer 112b) and the surface on which the insulating layer 110a is to be formed (here, the top surface of the conductive layer 112a), and is not affected by the performance of the exposure equipment used to fabricate the transistor. Therefore, the channel length L100 can be made smaller than the minimum dimension of the exposure equipment, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized with conventional exposure equipment used in the mass production of flat panel displays (e.g., a minimum dimension of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0150] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can be 100 nm or more and 1 μm or less.

[0151] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0152] The channel length L100 can be controlled by adjusting the thickness T110, the angle θ110, and the like.

[0153] The thickness T110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 200 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0154] The side surface of the insulating layer 110 on the opening 143 side is preferably tapered. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of a layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0155] The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less.

[0156] 2B and the like, the angle θ110 is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. The angle θ110 can also be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0157] 2B and other drawings show an example in which the sidewalls of the opening 143 (the side surfaces of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, the conductive layer 116, the insulating layer 110d, the insulating layer 110e, the insulating layer 110f, and the conductive layer 112b) are formed in a straight line, but one embodiment of the present invention is not limited to this. For example, the angles formed by the side surfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c and the top surface of the conductive layer 112a, the angles formed by the side surfaces of the conductive layer 116 and the top surface of the insulating layer 110c, the angles formed by the side surfaces of the insulating layer 110d, the insulating layer 110e, and the insulating layer 110f and the top surface of the conductive layer 116, and the angle formed by the side surface of the conductive layer 112b and the top surface of the insulating layer 110f may be different from each other.

[0158] 2A and 2B, the channel width W100 of the transistor 100 is indicated by a solid double-headed arrow. The channel width W100 is the perimeter of the opening 143 in a plan view. The width D143 of the opening 143 is indicated by a two-dot chain double-headed arrow. If the top surface shape of the opening 143 is circular, the width D143 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the perimeter of the circle. In other words, the channel width W100 is π×D143. In this way, if the top surface shape of the opening 143 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0159] The width D143 of the opening 143 may vary in the depth direction. For example, the width D143 of the opening 143 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these points in a cross-sectional view.

[0160] When the opening 143 is formed using photolithography, the width D143 of the opening 143 is equal to or larger than the minimum dimension of the exposure device. The width D143 can be, for example, 200 nm to less than 5 μm, 300 nm to 4.5 μm, 400 nm to 4 μm, 500 nm to 3.5 μm, 500 nm to 3 μm, 500 nm to 2.5 μm, 500 nm to 2 μm, 500 nm to 1.5 μm, or 500 nm to 1 μm.

[0161] 3A to 4, the channel length and the channel width of the transistor 200 will be described. For ease of description, a portion of the semiconductor layer 208 that overlaps with the conductive layer 204 will be described as a channel formation region.

[0162] The channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between the pair of regions 208D. In FIGS. 3A and 3B , the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200 of the transistor 200 is determined by the length of the conductive layer 204 and is equal to or greater than the minimum dimension of an exposure device used to fabricate the transistor. For example, the channel length L200 can be 1.5 μm or greater. Increasing the channel length allows the transistor to have high saturation properties.

[0163] The channel width of the transistor 200 is the width of the region in the direction perpendicular to the channel length direction where the semiconductor layer 208 and the conductive layer 204 overlap. In Figures 3A and 4, the channel width W200 of the transistor 200 is indicated by a dashed line with a double-headed arrow.

[0164] As described above, the channel length L100 of the transistor 100 can be smaller than the minimum dimension of the exposure tool, and the channel length L200 of the transistor 200 can be equal to or greater than the minimum dimension of the exposure tool. For example, by applying the transistor 100 to a transistor requiring a large on-state current and the transistor 200 to a transistor requiring high saturation, a high-performance semiconductor device can be achieved by utilizing the advantages of each transistor. Furthermore, the transistors 100 and 200 can be formed using some common processes. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same process. A portion of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another portion of the insulating layer 106 functions as a gate insulating layer for the transistor 200. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process. Therefore, the productivity of the semiconductor device can be improved and the manufacturing cost can be reduced.

[0165] 3A and 4, the conductive layers 204 and 202 preferably protrude outward beyond the end portions of the semiconductor layer 208 in the channel width direction of the transistor 200. In this case, as shown in Fig. 4, the entire semiconductor layer 208 in the channel width direction is covered with the conductive layers 204 and 202 via the insulating layers 106 and 120. With this structure, the semiconductor layer 208 can be electrically surrounded by an electric field generated by the pair of gate electrodes.

[0166] 3A and 4 show a structure in which the conductive layer 204 and the conductive layer 202 are not connected. A constant potential can be applied to one of a pair of gate electrodes, and a signal for driving the transistor 200 can be applied to the other. In this case, the threshold voltage when the transistor 200 is driven by the other gate electrode can be controlled by the potential applied to one gate electrode.

[0167] The conductive layer 204 and the conductive layer 202 can also be connected to each other. By applying the same potential to the conductive layer 204 and the conductive layer 202, an electric field for inducing a channel in the semiconductor layer 208 can be effectively applied, thereby increasing the on-state current of the transistor 200. Therefore, the transistor 200 can be miniaturized. For example, openings reaching the conductive layer 202 can be formed in the insulating layer 106 and the insulating layer 120, and the conductive layer 204 can be formed to cover the openings.

[0168] The conductive layer 202 can also be connected to the conductive layer 212a or the conductive layer 212b. For example, openings reaching the conductive layer 202 can be provided in the insulating layer 106 and the insulating layer 120, and the conductive layer 212a or the conductive layer 212b can be formed to cover the openings.

[0169] The insulating layer 120 can be made of the same material as that used for the insulating layer 110 .

[0170] The insulating layer 120 preferably has a stacked structure. In Fig. 3B and other figures, the insulating layer 120 has a stacked structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a. The insulating layer 120a and the insulating layer 120b can each be made of a material that can be used for the insulating layer 110.

[0171] It is more preferable to use a film that releases oxygen by heating for the insulating layer 120b having a region in contact with the channel formation region of the semiconductor layer 208. When the insulating layer 120b releases oxygen due to heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 208, particularly to the channel formation region. The oxygen contained in the insulating layer 120b diffuses in the insulating layer 120b and is supplied to the semiconductor layer 208 through the interface between the insulating layer 120b and the semiconductor layer 208. By supplying oxygen from the insulating layer 120b to the semiconductor layer 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Therefore, the transistor 200 can have favorable electrical characteristics and high reliability.

[0172] The insulating layer 120a preferably releases a small amount of impurities (for example, hydrogen and water) from itself and is less permeable to impurities, thereby preventing the impurities contained in the insulating layer 120a from diffusing into the channel formation region of the semiconductor layer 208. Therefore, the transistor 200 can have favorable electrical characteristics and high reliability.

[0173] The insulating layer 120a is preferably a film that is difficult for oxygen to permeate. The insulating layer 120a can also be said to function as a barrier film. By providing the insulating layer 120a that functions as a barrier film, oxygen contained in the insulating layer 120b can be prevented from diffusing to the conductive layer 202 side through the insulating layer 120a. This can prevent the conductive layer 202 from being oxidized and its electrical resistance from increasing. At the same time, since the oxygen contained in the insulating layer 120b is prevented from diffusing to the insulating layer 120a side, the amount of oxygen supplied from the insulating layer 120b to the channel formation region of the semiconductor layer 208 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0174] The insulating layer 120a located on the conductive layer 202 side is preferably made of a material that does not easily diffuse metal elements contained in the conductive layer 202. This can prevent the metal elements contained in the conductive layer 202 from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layer 120.

[0175] The insulating layer 120a is preferably made of a material that can be used for the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110f. The insulating layer 120a preferably contains nitrogen, and one or more of a nitride and a nitride oxide can be suitably used. Specifically, for example, one or both of silicon nitride and silicon nitride oxide can be suitably used for the insulating layer 120a. Alternatively, one or more of an oxide and an oxynitride can be used for the insulating layer 120a. For example, aluminum oxide can be suitably used for the insulating layer 120a. Note that the same material can be used for the insulating layer 120a, the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, and the insulating layer 110f. Alternatively, different materials can be used for some or all of these layers.

[0176] Note that the insulating layer 120a and the insulating layer 120b can each have a stacked-layer structure. Although the insulating layer 120 has a two-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 120 can also have a stacked-layer structure of three or more layers or a single-layer structure.

[0177] 1B and the like show a structure in which the semiconductor layer 208 has a region in contact with the side surface of the insulating layer 120, but one embodiment of the present invention is not limited to this. For example, a structure in which the semiconductor layer 208 does not have a region in contact with the side surface of the insulating layer 120, an end of the semiconductor layer 208 is located on the upper surface of the insulating layer 120, and the entire lower surface of the semiconductor layer 208 is in contact with the upper surface of the insulating layer 120. In this case, the insulating layer 120 encompasses the semiconductor layer 208 in a plan view. This can reduce the step on the surface where the semiconductor layer 208 is formed, thereby improving the coverage of the semiconductor layer 208.

[0178] In the semiconductor layer 208, the region 208D has a lower electrical resistance than the channel formation region. The region 208D can also be said to have a higher carrier concentration, a higher oxygen defect density, or a higher impurity concentration than the channel formation region.

[0179] The region 208L has electrical resistance that is similar to or lower than that of the channel formation region. The region 208L can also be referred to as a region with a carrier concentration that is similar to or higher than that of the channel formation region, a region with an oxygen defect density that is similar to or higher than that of the channel formation region, or a region with an impurity concentration that is similar to or higher than that of the channel formation region. Furthermore, the region 208L has electrical resistance that is similar to or higher than that of the region 208D. The region 208L can also be referred to as a region with a carrier concentration that is similar to or lower than that of the region 208D, a region with an oxygen defect density that is similar to or lower than that of the region 208D, or a region with an impurity concentration that is similar to or lower than that of the region 208D.

[0180] The region 208L functions as a buffer region for reducing the drain electric field. Since the region 208L does not overlap with the conductive layer 204, a channel is hardly formed in the region 208L even when a gate voltage is applied to the conductive layer 204. The region 208L preferably has a higher carrier concentration than the channel formation region. This allows the region 208L to function as an LDD (lightly doped drain) region. By providing the region 208L functioning as an LDD region between the channel formation region and the region 208D, the transistor 200 can have a high drain breakdown voltage.

[0181] The carrier concentration in the semiconductor layer 208 is preferably lowest in the channel formation region and increases in the order of the region 208L and the region 208D. By providing the region 208L between the channel formation region and the region 208D, the carrier concentration in the channel formation region can be kept extremely low even if impurities such as hydrogen diffuse from the region 208D during the manufacturing process, for example.

[0182] Note that the carrier concentration in the region 208L is not uniform, and there may be a gradient in which the carrier concentration decreases from the region 208D side toward the channel formation region. For example, the hydrogen concentration or oxygen vacancy (V Ｏ ) may have a gradient in concentration that decreases from the region 208D side to the channel formation region side.

[0183] As shown in FIG. 1B and other figures, partial ends of the conductive layer 212a and the conductive layer 212b are preferably located inside the openings 147a and 147b, respectively. In other words, partial ends of the conductive layer 212a and the conductive layer 212b preferably have regions in contact with the semiconductor layer 208 within the openings 147a and 147b. This allows the region of the semiconductor layer 208 in contact with the conductive layer 212a to be adjacent to one of the pair of regions 208D, and similarly, the region of the semiconductor layer 208 in contact with the conductive layer 212b to be adjacent to the other of the pair of regions 208D. The region of the semiconductor layer 208 in contact with the conductive layer 212a and one of the pair of regions 208D function as one of the source region or drain region of the transistor 200. The region of the semiconductor layer 208 in contact with the conductive layer 212b and the other of the pair of regions 208D function as the other of the source region or drain region of the transistor 200.

[0184] Note that the top surface shapes of the openings 147a and 147b are not particularly limited. The top surface shapes of the openings 147a and 147b can be any shape that can be applied to the opening 143. Although FIG. 1A and other drawings show a configuration in which the top surface shapes of the openings 147a and 147b are rectangular with rounded corners, which is different from the top surface shape of the opening 143, one embodiment of the present invention is not limited thereto. The top surface shapes of the openings 147a and 147b can also be the same as the top surface shape of the opening 143.

[0185] In the transistor 200, when an impurity element is supplied to the semiconductor layer 208 to form the regions 208L and 208D, in the transistor 100, the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask. As a result, the region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as a source region or a drain region. The region 108L is formed in a part of the source region or drain region. Note that the concentration of the impurity element in the region 108L may be different from the concentration of the impurity element in the region 208L. Alternatively, the region 108L may not be formed. For example, when the conductive layer 104 extends to cover the end of the semiconductor layer 108, the entire semiconductor layer 108 is masked by the conductive layer 104, and therefore the impurity element is not supplied to the semiconductor layer 108, and the region 108L is not formed.

[0186] Here, the structure in which the conductive layer 212a and the conductive layer 212b are formed in the same process as the conductive layer 204 is described; however, one embodiment of the present invention is not limited to this. The conductive layer 212a and the conductive layer 212b can be formed in a process different from that of the conductive layer 204. For example, the conductive layer 104 and the conductive layer 204 are formed over the insulating layer 106, and an impurity element is supplied to the semiconductor layer 208 using the conductive layer 204 as a mask, thereby forming a source region and a drain region. After that, the insulating layer 195 is formed over the conductive layer 104 and the conductive layer 204, and openings reaching the source region and the drain region are formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 212a and the conductive layer 212b can be formed so as to cover these openings.

[0187] 1B and the like show an example in which the thickness of the semiconductor layer 208 is uniform regardless of location, but one embodiment of the present invention is not limited to this. The thickness of the semiconductor layer 208 may be different between a region that overlaps with the insulating layer 106 and a region that does not overlap with the insulating layer 106. For example, when forming the openings 147a and 147b, part of the semiconductor layer 208 may be removed, so that the thickness of the region that does not overlap with the insulating layer 106 may be thinner than the thickness of the overlapping region. Alternatively, the thickness of the semiconductor layer 208 may be different between a region that overlaps with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b and a region that does not overlap with any of these layers. For example, when forming the conductive layers 212a and 212b, part of the semiconductor layer 208 may be removed, so that the thickness of the region that does not overlap with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b may be thinner than the thickness of the region that overlaps with any of these layers. Alternatively, a structure can be adopted in which the thickness is different between a region of the semiconductor layer 208 that overlaps with the insulating layer 106, a region that overlaps with either the conductive layer 212a or the conductive layer 212b of the semiconductor layer 208, and a region that does not overlap with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b.

[0188] The semiconductor device 10 can have a capacitor. FIGS. 1A and 4 show a structure in which the semiconductor device 10 includes a capacitor 150. As shown in FIG. 4 , the capacitor 150 has a structure in which a conductive layer 112b, an insulating layer 109, and a conductive layer 202 are stacked in this order. The conductive layer 112b and the conductive layer 202 function as a pair of electrodes of the capacitor 150. The conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 100 and also functions as one of the pair of electrodes of the capacitor 150. The conductive layer 202 functions as a backgate electrode of the transistor 200 and also functions as the other of the pair of electrodes of the capacitor 150. A region of the insulating layer 109 sandwiched between the conductive layer 112b and the conductive layer 202 functions as a dielectric of the capacitor 150. By forming the conductive layer 112b and the conductive layer 202 in different processes, the capacitor 150 including these conductive layers as a pair of electrodes can be formed. Furthermore, by forming the conductive layer 112b and the conductive layer 202 in different processes, different materials can be used for the conductive layer 112b and the conductive layer 202, thereby widening the range of material selection. The thickness of the insulating layer 109 can be set depending on the capacitance of the capacitor 150, the area of ​​the capacitor 150, and the relative dielectric constant of the material used for the insulating layer 109. Note that the area of ​​the capacitor 150 refers to the area of ​​a region in the capacitor 150 where the conductive layer 112b, the conductive layer 202, and the insulating layer 109 overlap with each other.

[0189] 1A and the like, an example has been described in which the capacitor 150 includes the conductive layer 112b, the conductive layer 202, and the insulating layer 109, but the structure of the capacitor 150 is not particularly limited. In addition, although the structure in which the other of the source electrode and the drain electrode of the transistor 100 is connected to one of the pair of electrodes of the capacitor 150 and the backgate electrode of the transistor 200 is connected to the other of the pair of electrodes of the capacitor 150 has been shown, the connection relationship between the transistor 100, the transistor 200, and the capacitor 150 is not particularly limited. Note that the semiconductor device may have a structure without a capacitor.

[0190] [Semiconductor Layer 108, Semiconductor Layer 208] Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0191] The semiconductor layer 108 and the semiconductor layer 208 may each be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (A), or the like. Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0192] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0193] The metal oxide may contain one or more nonmetallic elements. The presence of a nonmetallic element in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0194] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0195] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0196] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0197] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and the transistor can be a normally-off transistor. In addition, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0198] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0199] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Examples of the composition include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0200] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0201] By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0202] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the unevenness of the surfaces of the semiconductor layer 108 and the semiconductor layer 208 may increase. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 and the semiconductor layer 208 is formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily forms a polycrystalline structure is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 and the semiconductor layer 208 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 and the semiconductor layer 208 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0203] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less. Specifically, metal oxides of In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that ITSO have crystallinity. Note that the semiconductor layer 108 and the semiconductor layer 208 may have an amorphous region or may be amorphous.

[0204] A metal oxide that does not contain element M can be applied to the semiconductor layer 108 and the semiconductor layer 208. When the metal oxide is an In—Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, the atomic ratio of In is more preferably equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0205] The compositions of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Furthermore, a combination of these techniques can be used for analysis. It is preferable to separate peaks in the spectrum obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0206] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that in the sputtering target.

[0207] It is preferable to use a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208. Examples of the structure of a crystalline metal oxide include a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. The CAAC structure has fewer crystal grain boundaries and grains in the a-b plane than a polycrystalline structure, and therefore a highly reliable semiconductor device can be realized.

[0208] The semiconductor layer 108 and the semiconductor layer 208 are preferably formed using a CAAC-OS or an nc-OS.

[0209] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 and the semiconductor layer 208 are formed. The semiconductor layer 108 and the semiconductor layer 208 preferably have layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b, and layered crystals parallel or approximately parallel to the side surface of the insulating layer 110s in a region in contact with the side surface of the insulating layer 110s. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110s, which is the surface where the semiconductor layer 108 is formed, in the opening 143. With this structure, the layered crystals of the semiconductor layer 108 are formed approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current. Similarly, the semiconductor layer 208 preferably has layered crystals that are parallel or approximately parallel to the surface where it is to be formed (here, the top surface and side surfaces of the insulating layer 120 and the top surface of the insulating layer 110). In particular, the semiconductor layer 208 preferably has layered crystals that are parallel or approximately parallel to the top surface of the insulating layer 120, which is the surface where it is to be formed, in a region that overlaps with the conductive layer 204.

[0210] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0211] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0212] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Furthermore, the analysis can be performed by combining a plurality of these techniques.

[0213] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which defects such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0214] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0215] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0216] The semiconductor layer 108 and the semiconductor layer 208 may each include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0217] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0218] The semiconductor layer 108 and the semiconductor layer 208 can each have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 are the same or approximately the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0219] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 104, Conductive Layer 116, Conductive Layer 204, Conductive Layer 212a, Conductive Layer 212b, and Conductive Layer 202] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each have a single-layer structure or a stacked-layer structure. Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals. A conductive material with low electrical resistivity, including one or more of copper, silver, gold, and aluminum, can be preferably used for each of the conductive layers 112a, 112b, 104, 116, 204, 212a, 212b, and 202. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0220] A conductive metal oxide (oxide conductor) can be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, or ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, oxide conductors containing indium are preferable because of their high conductivity.

[0221] Oxygen deficiency (V) in metal oxides with semiconducting properties Ｏ ) and the oxygen vacancy (V Ｏ When hydrogen is added to a metal oxide, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive. A metal oxide that has become electrically conductive can be called an oxide conductor.

[0222] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each have a stacked structure of a conductive film containing the oxide conductor and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0223] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0224] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 116, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can be formed using the same material, or different materials can be used for some or all of these layers.

[0225] The conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a and the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material is preferably used.

[0226] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, which are conductive materials that are difficult to oxidize or materials that maintain low electrical resistance even when oxidized, and are therefore preferable.

[0227] The conductive layer 112 a and the conductive layer 112 b can each be formed using the above-described oxide conductors. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0228] The conductive layer 112a and the conductive layer 112b may each be made of a nitride conductor, such as tantalum nitride or titanium nitride.

[0229] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, and the conductive layer 116 can each have a stacked-layer structure. When the conductive layer 112a has a stacked-layer structure, a conductive material that is not easily oxidized is preferably used for at least a layer in contact with the semiconductor layer 108. The same applies to the conductive layer 112b.

[0230] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as can be used for the insulating layer 110 and the insulating layer 110s.

[0231] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0232] In a miniaturized transistor, a thinner gate insulating layer may result in a larger leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Furthermore, a material that can have ferroelectricity can be used for the gate insulating layer. Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms may be 1:1 or close to that. Examples of materials that can have ferroelectricity include materials in which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. For example, the ratio of the number of zirconium atoms to the number of element J2 ... lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, can be used.

[0233] 1B and the like, the insulating layer 106 has a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked-layer structure.

[0234] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer, is preferably made of a material that does not easily diffuse impurities. By providing the insulating layer 195, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0235] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating films can be stacked. The insulating layer 195 can have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0236] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102. Furthermore, the substrate 102 may be configured to include a semiconductor element. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0237] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0238] The following describes a configuration example that has some configurations different from the above-described configuration example 1. Note that, in the following, descriptions of parts that overlap with the above-described configuration example 1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-described configuration example 1 may be hatched with the same pattern and may not be assigned reference numerals.

[0239] 5A is a cross-sectional view of a semiconductor device 10A according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0240] The semiconductor device 10A includes a transistor 100 and a transistor 200A. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG.

[0241] The transistor 200A includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120b, an insulating layer 110, and a conductive layer 202a.

[0242] The conductive layer 202a is provided in a region different from the conductive layer 112a on the substrate 102. An insulating layer 110 (insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, insulating layer 110e, and insulating layer 110f) is provided over the conductive layer 202a. An insulating layer 120b is provided over the insulating layer 110 to have a region overlapping with the conductive layer 202a. The description of the transistor 200 can be referred to for the structure of layers above the insulating layer 120b.

[0243] In the transistor 200A, the conductive layer 204 functions as a gate electrode, and part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 202a functions as a back gate electrode, and part of the insulating layer 120b and part of the insulating layer 110 function as a back gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode.

[0244] That is, the transistor 200A and the transistor 200 differ in the structure of the back gate electrode and the structure of the back gate insulating layer. Since the transistor 200A has the above structure, the conductive layer 112a functioning as one of the source electrode and the drain electrode of the transistor 100 and the conductive layer 202a functioning as the back gate electrode of the transistor 200A can be formed using the same material and in the same process. Furthermore, the transistor 200A does not include the insulating layer 109 and the insulating layer 120a included in the transistor 200. Therefore, the number of steps involved in manufacturing the semiconductor device 10A can be reduced compared to the semiconductor device 10 shown in FIG. 1B.

[0245] With respect to the semiconductor device 10A, the contents described for the semiconductor device 10 can be referred to for other matters.

[0246] 5B is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0247] The semiconductor device 10B includes a transistor 100, a transistor 200B, an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c. The semiconductor device 10B differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10B includes a transistor 200B instead of the transistor 200.

[0248] The transistor 200B includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120b, an insulating layer 110d, an insulating layer 110e, an insulating layer 110f, and a conductive layer 202b.

[0249] The conductive layer 202b is provided in a region over the insulating layer 110c that is different from the conductive layer 116. The insulating layers 110d, 110e, and 110f are provided over the conductive layer 202b. The insulating layer 120b is provided over the insulating layer 110f to have a region overlapping with the conductive layer 202b. The description of the transistor 200 can be referred to for the structure of layers above the insulating layer 120b.

[0250] In the transistor 200B, the conductive layer 204 functions as a gate electrode, and part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 202b functions as a back gate electrode, and part of the insulating layer 120b, part of the insulating layer 110f, part of the insulating layer 110e, and part of the insulating layer 110d function as a back gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode.

[0251] That is, the transistor 200B differs from the transistor 200 in the structure of the back gate electrode and the structure of the back gate insulating layer. Since the transistor 200B has the above structure, the conductive layer 116 functioning as the back gate electrode of the transistor 100 and the conductive layer 202b functioning as the back gate electrode of the transistor 200B can be formed using the same material and in the same process. Furthermore, the transistor 200B does not include the insulating layer 109 and the insulating layer 120a included in the transistor 200. Therefore, the number of steps required for manufacturing the semiconductor device 10B can be reduced compared to the semiconductor device 10 shown in FIG. 1B.

[0252] With regard to the semiconductor device 10B, the contents described for the semiconductor device 10 can be referred to for other aspects than those described above.

[0253] 6A is a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0254] The semiconductor device 10C includes a transistor 100, a transistor 200C, and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG.

[0255] The transistor 200C includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202c.

[0256] The conductive layer 202c is provided in a region different from the conductive layer 112b over the insulating layer 110. The insulating layer 120 (insulating layers 120a and 120b) is provided over the conductive layer 202c. The insulating layer 120 has a region in contact with the top surface of the conductive layer 202c, the side surface of the conductive layer 202c, and the top surface of the insulating layer 110. For the structure of layers above the insulating layer 120, the description of the transistor 200 can be referred to.

[0257] In the transistor 200C, the conductive layer 204 functions as a gate electrode, and part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 202c functions as a back gate electrode, and part of the insulating layer 120 functions as a back gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode.

[0258] That is, the transistor 200C has a different back gate electrode structure from the transistor 200. Since the transistor 200C has the above structure, the conductive layer 112b, which functions as the other of the source electrode and the drain electrode of the transistor 100, and the conductive layer 202c, which functions as the back gate electrode of the transistor 200C, can be formed using the same material and in the same process. Furthermore, the transistor 200C does not include the insulating layer 109 included in the transistor 200. Therefore, the number of steps involved in manufacturing the semiconductor device 10C can be reduced compared to the semiconductor device 10 shown in FIG. 1B.

[0259] With respect to the semiconductor device 10C, the contents described in connection with the semiconductor device 10 can be referred to for other aspects than those described above.

[0260] 6B is a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0261] The semiconductor device 10D includes a transistor 100A, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10D includes a transistor 100A instead of the transistor 100.

[0262] The transistor 100A differs from the transistor 100 in that the insulating layer 110s has a stacked structure of an insulating layer 110s1 and an insulating layer 110s2 over the insulating layer 110s1. The insulating layer 110s1 is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116, and the side surface of the conductive layer 112b. The insulating layer 110s2 is provided to face the top surface of the conductive layer 112a, the side surface of the insulating layer 110, the side surface of the conductive layer 116, and the side surface of the conductive layer 112b with the insulating layer 110s1 interposed therebetween.

[0263] For example, the materials, manufacturing methods, etc. used for the insulating layers 110a, 110c, 110d, and 110f can be applied to the insulating layer 110s1. For example, the materials, manufacturing methods, etc. used for the insulating layers 110b and 110e can be applied to the insulating layer 110s2. That is, the insulating layer 110s1 can be made of a material that is difficult for oxygen to permeate, and the insulating layer 110s2 can be made of a material that contains oxygen and releases oxygen when heated.

[0264] In a structure in which the insulating layer 110s that releases oxygen is in contact with the conductive layer 112a and the conductive layer 112b, as in the transistor 100, there is a concern that the conductive layer 112a and the conductive layer 112b may be oxidized by the oxygen released from the insulating layer 110s, thereby reducing the amount of oxygen supplied from the insulating layer 110s to the semiconductor layer 108. By forming the insulating layer 110s as a stacked structure of the insulating layer 110s1 and the insulating layer 110s2 as in the transistor 100A, the insulating layer 110s2 that releases oxygen can be prevented from being in contact with the conductive layer 112a and the conductive layer 112b. This can prevent the conductive layer 112a and the conductive layer 112b from being oxidized by the oxygen released from the insulating layer 110s2. Furthermore, a reduction in the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108 can be suppressed.

[0265] With respect to the semiconductor device 10D, the contents described for the semiconductor device 10 can be referred to for other aspects than those described above.

[0266] 7A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0267] The semiconductor device 10E includes a transistor 100B, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10E differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10E includes a transistor 100B instead of the transistor 100.

[0268] The transistor 100B differs from the transistor 100 in that an insulating layer 110g is provided between the conductive layer 116 and the insulating layer 110s.

[0269] The insulating layer 110g contains, for example, an oxide of an element contained in the conductive layer 116. When the conductive layer 116 is a metal, the insulating layer 110g is, for example, an oxide of the metal. When the conductive layer 116 is silicon, the insulating layer 110g is, for example, a silicon oxide. For example, a metal oxide such as aluminum oxide or tantalum oxide can be used as the insulating layer 110g, and aluminum oxide is particularly preferable.

[0270] 7A , for example, the stacked structure of the insulating layer 110s and the insulating layer 110g functions as the back gate insulating layer of the transistor 100B.

[0271] In addition, since the transistor 100B uses a stacked structure of the insulating layer 110s and the insulating layer 110g as the back gate insulating layer, even if the insulating property of the insulating layer 110g is lower than that of the insulating layer 110s, if sufficient insulating property can be obtained by stacking it with the insulating layer 110s, the electrical characteristics and reliability of the transistor 100B can be sufficiently ensured.

[0272] The transistor 100B includes the insulating layer 110g, which may allow the thickness of the insulating layer 110s to be thin. Reducing the thickness of the insulating layer 110s can increase the electric field strength applied from the back gate electrode (conductive layer 116) of the transistor 100B to the semiconductor layer 108. For example, a material having a higher dielectric constant than the material used for the insulating layer 110s can be suitably used for the insulating layer 110g.

[0273] The insulating layer 110g can be formed in a self-aligned manner, for example, by depositing a layer capable of supplying oxygen in contact with the surface of the conductive layer 116 and oxidizing the surface of the conductive layer 116 with oxygen supplied from the insulating layers 110b and 110e through the layer. If the height of the upper end of the insulating layer 110s becomes lower than the height of the upper surface of the conductive layer 116 during etching during the formation of the insulating layer 110s, or if the height of the upper end of the insulating layer 110s is higher than the height of the upper surface of the conductive layer 116 but the difference is small, leakage current may flow between the semiconductor layer 108 and the conductive layer 116, potentially degrading the electrical characteristics of the transistor 100B. Even in such cases, the transistor 100B can suppress leakage current between the semiconductor layer 108 and the conductive layer 116 by including the insulating layer 110g.

[0274] With regard to the semiconductor device 10E, the contents described in the semiconductor device 10 can be referred to for other aspects than those described above.

[0275] 7B is a cross-sectional view of a semiconductor device 10F according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0276] The semiconductor device 10F includes a transistor 100C, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10F includes a transistor 100C instead of the transistor 100.

[0277] The transistor 100C differs from the transistor 100 in the configuration of the insulating layer 110s.

[0278] Specifically, in the transistor 100C, the bottom surface of the insulating layer 110s is in contact with the top surface of the insulating layer 110a, and the side surface of the insulating layer 110a is in contact with the semiconductor layer 108. That is, in the transistor 100C, the insulating layer 110s is not in contact with the conductive layer 112a.

[0279] As described above, the insulating layer 110s, together with the insulating layer 110b and the insulating layer 110e, can have a function of supplying oxygen to the semiconductor layer 108. Therefore, in a structure in which the bottom surface of the insulating layer 110s is in contact with the conductive layer 112a, as in the transistor 100, oxygen diffused from the insulating layer 110s may oxidize part of the top surface of the conductive layer 112a, increasing its resistance and causing a problem of reducing the on-state current of the transistor. In contrast, by using a structure in which the insulating layer 110s and the conductive layer 112a are not in contact with each other, as in the transistor 100C, the risk of causing the above problem can be reduced.

[0280] With regard to the semiconductor device 10F, the contents described in connection with the semiconductor device 10 can be referred to for other matters than those described above.

[0281] 8A is a cross-sectional view of a semiconductor device 10G according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0282] The semiconductor device 10G includes a transistor 100D, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10F includes a transistor 100D instead of the transistor 100.

[0283] The transistor 100D differs from the transistor 100 in that the transistor 100D does not include the conductive layer 112b and that the end portions of the semiconductor layer 108 extend to the outside of the conductive layer 116 and the conductive layer 112a.

[0284] In the transistor 100D, the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s, the curved portion of the insulating layer 110s, and the top surface of the insulating layer 110. In the transistor 100D, the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and also as the other of the source electrode and the drain electrode. For example, a region of the semiconductor layer 108 that overlaps with the insulating layer 110s can function as the channel formation region. A region located outside the opening 143 can function as the other of the source electrode and the drain electrode.

[0285] For example, the resistance of the semiconductor layer 108 can be reduced by supplying impurities such as boron to the semiconductor layer 108 from a direction perpendicular to the substrate surface using ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Alternatively, when an oxide semiconductor is used for the semiconductor layer 108, a silicon nitride film or the like can be formed on a region of the semiconductor layer 108 that does not overlap with the opening 143 to make the region an oxide conductor (OC), thereby forming a low-resistance region in the semiconductor layer 108. In this manner, the resistance of the regions corresponding to the source and drain regions of the semiconductor layer 108 can be made lower than that of the channel formation region. Therefore, the channel formation region and the source and drain regions having lower resistance than the channel formation region can be separately formed in the semiconductor layer 108. As a result, in the transistor 100D, regions corresponding to the source and drain electrodes can be formed in the semiconductor layer 108 without providing the conductive layer 112b. Therefore, the number of steps required for manufacturing the transistor 100D can be reduced by the absence of the conductive layer 112b.

[0286] With respect to the semiconductor device 10G, the contents described in the semiconductor device 10 can be referred to for other aspects than those described above.

[0287] 8B is a cross-sectional view of a semiconductor device 10H according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0288] The semiconductor device 10H includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10H differs from the semiconductor device 10 shown in FIG.

[0289] Specifically, in the semiconductor device 10H, the insulating layers corresponding to the insulating layers 110a, 110b, and 110c are composed only of the insulating layer 110h, and the insulating layers corresponding to the insulating layers 110d, 110e, and 110f are composed only of the insulating layer 110i. That is, the semiconductor device 10H differs from the semiconductor device 10 in that the insulating layer 110 is composed of only two layers: the insulating layer 110h and the insulating layer 110i on the insulating layer 110h. For the insulating layers 110h and 110i, it is preferable to use materials that can be used for the insulating layers 110a, 110c, 110d, and 110f. That is, it is preferable to use materials that have high blocking properties against oxygen and hydrogen. This prevents the conductive layer 116 from being oxidized by oxygen diffusion from outside the insulating layers 110h and 110i. Furthermore, oxygen in the semiconductor layer 108 diffuses toward the insulating layer 110h and the insulating layer 110i, and oxygen vacancies (V Ｏ ) can be suppressed from being formed. As described above, since the insulating layer 110s has the function of releasing oxygen, even if the insulating layer 110 has the above-described configuration, oxygen can be supplied to the semiconductor layer 108. In the semiconductor device 10H, the number of insulating layers constituting the insulating layer 110 can be significantly reduced, and therefore the number of steps involved in forming the insulating layer 110 can be reduced compared to the semiconductor device 10 and the like.

[0290] With respect to the semiconductor device 10H, the contents described for the semiconductor device 10 can be referred to for other aspects than those described above.

[0291] 9A is a cross-sectional view of a semiconductor device 10I according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0292] The semiconductor device 10I includes a transistor 100, a transistor 200D, an insulating layer 110, and an insulating layer 109. The semiconductor device 10I differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10I includes a transistor 200D instead of the transistor 200.

[0293] The transistor 200D differs from the transistor 200 in that the transistor 200D does not include the conductive layer 202 functioning as a backgate electrode.

[0294] As described above, the transistor 200, which is a TGSA transistor, can have a longer channel length than the transistor 100, which is a vertical transistor. Therefore, even if the transistor 200 does not have a back gate electrode, it may be possible to achieve higher saturation than the transistor 100. By configuring the transistor 200 without a back gate electrode (transistor 200D), the number of steps required to manufacture the semiconductor device 10I can be reduced compared to the semiconductor device 10 shown in FIG. 1B.

[0295] With respect to the semiconductor device 10I, the contents described for the semiconductor device 10 can be referred to for other aspects than those described above.

[0296] 9B is a cross-sectional view of a semiconductor device 10J according to one embodiment of the present invention, taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 10 shown in FIG.

[0297] The semiconductor device 10J includes a transistor 100E, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 10J differs from the semiconductor device 10 shown in FIG. 1B mainly in that the semiconductor device 10J includes a transistor 100E instead of the transistor 100.

[0298] The transistor 100E differs from the transistor 100 in that it does not include the conductive layer 104. That is, the transistor 100E can be said to be a transistor including only one conductive layer (conductive layer 116) that functions as a gate electrode. By providing only the conductive layer 116 with the function of a gate electrode as in the transistor 100E, it is not necessary to provide the conductive layer 104 in the opening 143. Therefore, the diameter of the top surface of the opening 143 can be reduced compared to when the conductive layer 104 is provided. Therefore, the transistor 100E can occupy a smaller area in the substrate plane than the transistor 100, and a semiconductor device 10J that occupies a smaller area than the semiconductor device 10 shown in FIG. 1B can be realized.

[0299] With respect to the semiconductor device 10J, the contents described in connection with the semiconductor device 10 can be referred to for other matters than those described above.

[0300] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0301] In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Note that with regard to materials and formation methods of elements, descriptions of the same parts as those described in Embodiment 1 may be omitted.

[0302] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include PECVD and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0303] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating.

[0304] When processing a thin film constituting a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0305] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0306] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0307] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0308] 1A and 1B will be described with reference to Fig. 10A to Fig. 16C. Each figure shows a cross-sectional view taken along dashed line A1-A2 in Fig. 1A.

[0309] First, a conductive film to be the conductive layer 112a is formed over the substrate 102, and then processed to form the conductive layer 112a. A sputtering method can be suitably used to form the conductive film.

[0310] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed in this order on the conductive layer 112a (FIG. 10A).

[0311] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the interface between the insulating films 110af and 110bf. Examples of such impurities include water and organic substances. For example, it is preferable to form the insulating film 110af and then the insulating film 110bf consecutively using the same device.

[0312] When the insulating films 110af and 110bf are formed by PECVD, the substrate temperature during formation is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during formation of the insulating films 110af and 110bf within the above-described ranges, the release of impurities (e.g., water and hydrogen) from the insulating films can be reduced, and the diffusion of the impurities into the semiconductor layer 108 to be formed later can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained. Furthermore, when the insulating films 110af and 110bf are formed by sputtering without using hydrogen gas as a deposition gas, the substrate temperature during formation can also be room temperature.

[0313] Since the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

[0314] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. Examples of methods for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic.

[0315] The plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0316] Subsequently, a film 137 is preferably formed over the insulating film 110bf (FIG. 10B). The film 137 preferably contains oxygen. By forming the film 137, oxygen can be supplied to the insulating film 110bf.

[0317] The conductivity of the film 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 137.

[0318] The film 137 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferably made of a metal oxide material that can be used for the semiconductor layer 108 and the semiconductor layer 208.

[0319] When forming the film 137, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0320] In this way, by forming the film 137 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 137, and oxygen can be prevented from being desorbed from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0321] Heat treatment can be performed after the film 137 is formed. By performing heat treatment after the film 137 is formed, oxygen can be effectively supplied from the film 137 to the insulating film 110bf.

[0322] The temperature of the heat treatment is preferably, for example, 150° C. or higher and lower than the strain point of the substrate, 200° C. or higher and 450° C. or lower, 230° C. or higher and 400° C. or lower, 250° C. or higher and 350° C. or lower, or 250° C. or higher and 300° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating film 110af and the insulating film 110bf as much as possible. For the heat treatment, an oven, a rapid thermal annealing (RTA) apparatus, or the like can be used. By using an RTA apparatus, the heat treatment time can be shortened.

[0323] After the film 137 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 137. The above description can be referred to for the method of supplying oxygen, and therefore detailed description thereof will be omitted.

[0324] Next, the film 137 is removed. There is no particular limitation on the method for removing the film 137, but a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when removing the film 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating film 110bf uniform.

[0325] After removing the film 137, oxygen can be further supplied to the insulating film 110bf. The above description can be referred to for the method of supplying oxygen. For example, as shown in FIG. 10C , a film 139 can be formed on the insulating film 110bf, and oxygen can be supplied to the insulating film 110bf through the film 139. The treatment for supplying oxygen can be plasma treatment in an atmosphere containing oxygen. In FIG. 10C , arrows are used to schematically show how oxygen is supplied to the insulating film 110bf through the film 139.

[0326] A conductive film or a semiconductor film is preferably used as the film 139. A metal oxide film, a metal film, or an alloy film can be used as the film 139. When a metal oxide film is used as the film 139 and formed by a sputtering method or the like in an atmosphere containing oxygen, oxygen can be preferably supplied to the insulating film 110bf even during the formation of the film 139.

[0327] The thickness of the film 139 is preferably small. Specifically, the thickness of the film 139 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. Typically, the thickness can be about 5 nm.

[0328] The substrate temperature during the formation of the film 139 is preferably 350° C. or less, more preferably 340° C. or less, further preferably 330° C. or less, and further preferably 300° C. or less, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0329] By providing the film 139, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, the film 139 tends to attract ionized oxygen, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0330] A dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used as the processing apparatus for supplying oxygen. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage may be set to, for example, 10 V or more and 1 kV or less. Alternatively, the bias power density may be set to, for example, 1 W / cm. ２ More than 5W / cm ２ The following would suffice.

[0331] Next, the film 139 is removed. The film 139 can be preferably removed by wet etching.

[0332] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, after a film that suppresses oxygen desorption is formed over the insulating film 110bf, oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0333] It is preferable that a large amount of oxygen be released from the insulating layer 110b through the insulating layer 110s to the channel formation region of the transistor 100. By supplying oxygen to the insulating film 110bf that becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b is increased, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 through the insulating layer 110s can be increased. As a result, even the transistor 100 with a short channel length can exhibit favorable electrical characteristics.

[0334] Next, an insulating film 110cf, which will become the insulating layer 110c, is formed on the insulating film 110bf (FIG. 10D). The description of the formation of the insulating film 110af can be referred to for the formation of the insulating film 110cf, and therefore a detailed description thereof will be omitted.

[0335] Subsequently, a conductive film 116f that will become the conductive layer 116 is formed on the insulating film 110cf (FIG. 11A). The conductive film 116f can be formed by, for example, a sputtering method.

[0336] Next, the conductive film 116f is processed to form a conductive layer 116s on the insulating film 110cf so as to have a region overlapping with the conductive layer 112a (FIG. 11B). For example, wet etching can be suitably used to form the conductive layer 116s.

[0337] Subsequently, the insulating films 110df, 110ef, and 110ff are formed in this order on the conductive layer 116s and the insulating film 110cf. The description of the formation of the insulating films 110af, 110bf, and 110cf can be referred to for the formation of the insulating films 110df, 110ef, and 110ff, and therefore detailed description thereof will be omitted.

[0338] Note that after the insulating film 110ef is formed, oxygen can be supplied to the insulating film 110ef. For the supply of oxygen to the insulating film 110ef, the description of the supply of oxygen to the insulating film 110bf can be referred to, and therefore detailed description thereof will be omitted.

[0339] Subsequently, an insulating film 109f that will become the insulating layer 109 is formed over the insulating film 110ff. The formation of the insulating film 109f can be performed by referring to the description of the formation of the insulating films 110af, 110bf, and 110cf, and therefore detailed description thereof will be omitted.

[0340] Subsequently, a conductive film 202f that will become the conductive layer 202 is formed over the insulating film 109f (FIG. 11C). The conductive film 202f can be formed by, for example, a sputtering method.

[0341] Next, the conductive film 202f is processed to form a conductive layer 202 over the insulating film 109f (FIG. 12A). The conductive layer 202 is provided in a region that does not overlap with the conductive layer 112a and the conductive layer 116s. The conductive layer 202 can be formed by, for example, wet etching.

[0342] Subsequently, an insulating film 120af that will become the insulating layer 120a and an insulating film 120bf that will become the insulating layer 120b are formed in this order on the conductive layer 202 and the insulating film 109f (FIG. 12B).

[0343] The insulating films 120af and 120bf can be preferably formed by sputtering or PECVD. After forming the insulating film 120af, it is preferable to form the insulating film 120bf without exposing the surface of the insulating film 120af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the interface between the insulating films 120af and 120bf. Examples of such impurities include water and organic substances. For example, it is preferable to form the insulating film 120af and then the insulating film 120bf consecutively using the same device.

[0344] The substrate temperature during the formation of the insulating films 120af and 120bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 120af and 120bf within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating films 120af and 120bf, and to suppress the diffusion of the impurities into the semiconductor layer 108 to be formed later. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0345] Since the insulating films 120af and 120bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 120af and 120bf.

[0346] After the insulating film 120bf is formed, oxygen can be supplied to the insulating film 120bf. The above description can be referred to for the method of supplying oxygen.

[0347] Subsequently, the insulating films 109f, 120af, and 120bf are processed to form the insulating layer 109, and the insulating layer 120 including the insulating layers 120a and 120b is formed ( FIG. 12C ). By forming the insulating layers 109 and 120 in the same process, their edges can be aligned or approximately aligned. This also improves productivity of the semiconductor device 10 and reduces manufacturing costs. The insulating layers 109 and 120 are formed at least in the region where the conductive layer 202 is to be formed. Furthermore, the formation of the insulating layers 109 and 120 exposes a portion of the insulating layer 110. For example, dry etching can be suitably used to process the insulating films 109f, 120af, and 120bf.

[0348] When the insulating layer 109 and the insulating layer 120 are formed, a part of the insulating film 110ff (later insulating layer 110f) in a region that does not overlap with either the insulating layer 109 or the insulating layer 120 may be etched, resulting in a thinning of the insulating film 110ff in that region. The insulating film 110ff preferably has a high etching selectivity with respect to the insulating layer 109 and the insulating layer 120 in the etching of the insulating layer 109 and the insulating layer 120. This is preferable because it can prevent the thickness of the insulating film 110ff from being thinned.

[0349] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating layer 120 and the insulating film 110ff (FIG. 13A). The conductive film 112bf can be formed by, for example, a sputtering method.

[0350] Next, portions of the conductive film 112bf, the insulating film 110ff, the insulating film 110ef, the insulating film 110df, the conductive layer 116s, the insulating film 110cf, the insulating film 110bf, and the insulating film 110af are removed to form the conductive layer 112B, the conductive layer 116, and the insulating layer 110 (insulating layer 110f, insulating layer 110e, insulating layer 110d, insulating layer 110c, insulating layer 110b, and insulating layer 110a) having openings 143 ( FIG. 13B ). The openings 143 are provided in regions overlapping with the conductive layer 112a. The formation of the openings 143 exposes portions of the conductive layer 112a. For example, dry etching can be suitably used to form the conductive layer 112B and the insulating layer 110.

[0351] The conductive layer 112B and the insulating layer 110 can be formed at the same time by using the same resist mask. Alternatively, the conductive layer 112B and the insulating layer 110 can be formed separately. For example, after the conductive layer 112B is formed using a first resist mask, the first resist mask can be removed, and then the insulating layer 110 can be formed using a second resist mask.

[0352] 1B and other drawings show an example in which the bottom of the opening 143 coincides with the top surface of the conductive layer 112a, but this is not limited to this embodiment of the present invention. For example, the conductive layer 112a may have a recess in a region overlapping with the opening 143. This allows the semiconductor layer 108 and the conductive layer 104 to be provided even in the recess, thereby strengthening the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a. This increases the on-state current of the transistor 100. For example, when forming the opening 143, etching is performed to remove part of the top surface of the conductive layer 112a, thereby forming the conductive layer 112a having the recess.

[0353] Next, an insulating film 110sf that will become the insulating layer 110s is formed so as to cover the opening 143 ( FIG. 13C ). The insulating film 110sf is provided in contact with the top surface of the conductive layer 112B, the side surface of the conductive layer 112B in the opening 143, the side surface of the insulating layer 110 in the opening 143, the side surface of the conductive layer 116 in the opening 143, and the top surface of the conductive layer 112a in the opening 143.

[0354] Subsequently, a portion of the insulating film 110sf is removed by etching to form the insulating layer 110s ( FIG. 14A ). Specifically, the region of the insulating film 110sf that contacts the upper surface of the conductive layer 112a and the region that contacts the upper surface of the conductive layer 112B is removed by etching, while the region that contacts the side surface of the conductive layer 112B in the opening 143, the side surface of the insulating layer 110 in the opening 143, and the side surface of the conductive layer 116 in the opening 143 remains, thereby forming the insulating layer 110s. The upper end of the insulating layer 110s has a curved shape.

[0355] The insulating film 110sf can be etched by, for example, anisotropic etching. More specifically, the insulating layer 110s can be formed by, for example, performing highly anisotropic etching using a dry etching method.

[0356] Although not shown, depending on the etching conditions for the insulating film 110sf, a part of the insulating film 110sf may remain on the side surface of the step portion of the conductive layer 112B outside the opening 143.

[0357] Next, a part of the conductive layer 112B is removed to form a conductive layer 112b (FIG. 14B). The conductive layer 112b is formed to have a region overlapping with the conductive layer 116 and the conductive layer 112a. For example, a wet etching method can be suitably used to form the conductive layer 112b.

[0358] Next, a metal oxide film 108f to become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 143 ( FIG. 14C ). The metal oxide film 108f is provided in contact with the upper surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110s in the opening 143, the curved portion of the insulating layer 110s, the upper surface of the conductive layer 112b, the side surface of the conductive layer 112b, the upper surface of the insulating layer 110, the side surface of the insulating layer 109, the side surface of the insulating layer 120, and the upper surface of the insulating layer 120.

[0359] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. The ALD method has high coverage and is therefore suitable for forming the metal oxide film 108f that covers the opening 143. By using the ALD method, a metal oxide film can be formed with good coverage also on the side surfaces of the insulating layer 110s. Furthermore, the ALD method allows for easy control of the film formation rate, making it possible to form a thin film with a high yield.

[0360] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0361] Oxygen gas is preferably used when the metal oxide film 108f is formed. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110s and the insulating layer 120. For example, when an oxide or an oxynitride is used for the insulating layer 110s, oxygen can be suitably supplied to the insulating layer 110s. Similarly, when an oxide or an oxynitride is used for the insulating layer 120b, oxygen can be suitably supplied to the insulating layer 120b.

[0362] By supplying oxygen to the insulating layer 110s, oxygen is supplied to the channel formation region of the semiconductor layer 108 in a later process, and oxygen vacancies (V Ｏ ) and V ＯFurthermore, by supplying oxygen to the insulating layer 120b, oxygen is supplied to the channel formation region of the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0363] When forming the metal oxide film 108f, oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be mixed. Note that, as the oxygen flow rate ratio of the deposition gas or the oxygen partial pressure in the processing chamber when forming the metal oxide film increases, the crystallinity of the metal oxide film can be improved, and a highly reliable transistor can be realized. On the other hand, as the oxygen flow rate ratio or the oxygen partial pressure decreases, the crystallinity of the metal oxide film can be reduced and the electrical conductivity of the metal oxide film can be increased, resulting in a transistor with a large on-state current.

[0364] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, the oxygen flow rate ratio or oxygen partial pressure may be adjusted depending on the composition of the metal oxide film 108f.

[0365] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the resulting metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the resulting metal oxide film.

[0366] The substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by forming the metal oxide film 108f at room temperature or without heating the substrate, the crystallinity can be reduced.

[0367] If the substrate temperature is high, the metal oxide film may have a polycrystalline structure. It is preferable to adjust the substrate temperature so that the metal oxide film 108f does not have a polycrystalline structure. The substrate temperature may be adjusted depending on the composition applied to the metal oxide film 108f.

[0368] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0369] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0370] For example, when forming an In—Ga—Zn oxide, three precursors, an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor, or two precursors, an indium-containing precursor, and a gallium- and zinc-containing precursor, can be used.

[0371] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0372] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0373] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0374] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0375] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0376] Oxidizing agents include, for example, ozone, oxygen, and water.

[0377] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, a film whose composition changes continuously can be formed. A configuration in which the composition of the metal oxide film 108f changes continuously can also be achieved.

[0378] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surfaces of the insulating layer 110s, the insulating layer 109, and the insulating layer 120, and a treatment for supplying oxygen to the insulating layer 110s and the insulating layer 120. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110s and the insulating layer 120. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied to the insulating layer 110s and the insulating layer 120 while suitably removing organic substances from the surfaces of the insulating layer 110s, the insulating layer 109, and the insulating layer 120. After such treatment, it is preferable to form the metal oxide film 108f in succession without exposing the surfaces of the insulating layer 110s, the insulating layer 109, and the insulating layer 120 to the air.

[0379] In addition, when the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0380] When the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same deposition method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0381] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 15A). The semiconductor layer 108 is formed to have a region overlapping with the conductive layer 112a and the conductive layer 112b. The semiconductor layer 208 is formed to have a region overlapping with the conductive layer 202.

[0382] A wet etching method can be suitably used for forming the semiconductor layer 108 and the semiconductor layer 208. At this time, parts of the insulating layer 110 and the conductive layer 112b in regions that do not overlap with either the semiconductor layer 108 or the semiconductor layer 208 may be etched and become thin. Note that in etching the metal oxide film 108f, using materials with high selectivity for the insulating layer 110 and the conductive layer 112b can prevent the insulating layer 110 and the conductive layer 112b from becoming thin, which is preferable.

[0383] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove hydrogen and water contained in or adsorbed to the surfaces of the metal oxide film 108f, or the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f, or the semiconductor layer 108 and the semiconductor layer 208 (for example, defects are reduced or crystallinity is improved).

[0384] By the heat treatment, oxygen can also be supplied from the insulating layer 110s and the insulating layer 120b to the metal oxide film 108f, or from the insulating layer 110s to the semiconductor layer 108, or from the insulating layer 120b to the semiconductor layer 208. As a result, oxygen vacancies (V Ｏ ) can be reduced. In this case, it is more preferable to perform heat treatment before processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208. The above description can be referred to for the heat treatment, and detailed description thereof will be omitted. Note that oxygen may be supplied to the channel formation region in a step in which heat is applied after the formation of the metal oxide film 108f (for example, a step in which the insulating layer 106 is formed).

[0385] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a high-temperature treatment in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0386] Subsequently, an insulating film 106f that will become the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 110 (FIG. 15B). The insulating film 106f can be formed by, for example, a PECVD method or an ALD method.

[0387] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is suppressed from diffusing above the insulating layer 106, and oxygen vacancies (V Ｏ As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0388] By increasing the temperature during the formation of the insulating film 106f, the insulating layer 106 can be formed with fewer defects. However, if the temperature during the formation of the insulating film 106f is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating film 106f is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0389] Before forming the insulating film 106f, plasma treatment can be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities (e.g., water) adsorbed to the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, thereby realizing a highly reliable transistor. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating film 106f. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. The plasma treatment and the formation of the insulating film 106f are preferably performed successively without exposure to the air.

[0390] Next, the insulating film 106f is processed to form the insulating layer 106 ( FIG. 15C ). The insulating layer 106 is provided with openings 147a and 147b that reach the semiconductor layer 208. A portion of the insulating layer 106 is provided so as to have a region overlapping with the semiconductor layer 108 and the conductive layer 112b, and another portion of the insulating layer 106 (a region sandwiched between the openings 147a and 147b) is provided so as to have a region overlapping with the conductive layer 202. A dry etching method can be suitably used to form the insulating layer 106.

[0391] Next, a conductive film 104f to be the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is formed over the insulating layer 106 (FIG. 16A). The conductive film 104f can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0392] Next, the conductive film 104f is processed to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b ( FIG. 16B ). The conductive layer 104 is formed to have a region overlapping with the opening 143. The conductive layer 204 is formed to have a region overlapping with the conductive layer 202 and the insulating layer 106. The conductive layer 212a is formed to have a region overlapping with the opening 147a. The conductive layer 212b is formed to have a region overlapping with the opening 147b.

[0393] Next, using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks, impurities are supplied (also referred to as addition or injection) to the semiconductor layer 208. As a result, a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106 ( FIG. 16C ). At this time, it is preferable to determine the conditions for supplying the impurities in consideration of the material and thickness of the conductive layer 204 that serves as the mask so that the impurities are not supplied to the region of the semiconductor layer 208 that overlaps with the conductive layer 204 as much as possible. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 208 that overlaps with the conductive layer 204. Similarly, impurities may be supplied to the semiconductor layer 108 using the conductive layer 104 as a mask. By supplying the impurities, a region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104 and overlaps with the insulating layer 106.

[0394] The impurity can be supplied preferably by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc. The use of plasma ion doping can increase productivity. Furthermore, the use of ion implantation using mass separation can increase the purity of the supplied impurity.

[0395] In supplying the impurity, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 208 or in a portion close to the surface.

[0396] The source material used for supplying the impurity may be, for example, a gas containing the above-mentioned impurity element. ２ H ６ Gas or BF ３ In addition, when phosphorus is supplied, one or more of the following gases can be used: PH ３Furthermore, gases obtained by diluting these source gases with noble gases can also be used.

[0397] As a raw material used for supplying impurities, for example, CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. Note that the raw material is not limited to gas, and a solid or liquid can also be heated and vaporized for use.

[0398] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 106 and the semiconductor layer 208 .

[0399] For example, when boron is supplied by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0400] When phosphorus is supplied by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV. The dose can be, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0401] The method of supplying the impurities is not limited to this, and for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of the plasma treatment method, the impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing the plasma treatment. As the apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0402] For example, by performing plasma treatment using a plasma CVD apparatus in an atmosphere containing a gas containing hydrogen, hydrogen can be supplied as an impurity to a region of the semiconductor layer 208 that does not overlap with the conductive layer 204. Furthermore, by using a plasma CVD apparatus for supplying the impurity and forming the insulating layer 195, the supply of the impurity and the formation of the insulating layer 195 can be performed successively in the same apparatus, thereby improving productivity.

[0403] As a result, the transistor 100 and the transistor 200 are formed.

[0404] Subsequently, an insulating layer 195 is formed to cover the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, the insulating layer 106, and the semiconductor layer 208 (FIG. 1B). The insulating layer 195 can be preferably formed by a PECVD method.

[0405] If the deposition temperature of the insulating layer 195 is too high, impurities contained in the regions 108L, 208L, and 208D may diffuse to the peripheral portions including the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208. In addition, the electrical resistance of the regions 108L, 208L, and 208D may increase. Therefore, the deposition temperature of the insulating layer 195 may be determined in consideration of the diffusion of impurities.

[0406] The deposition temperature of the insulating layer 195 can be, for example, 150° C. to 400° C., preferably 180° C. to 360° C., and more preferably 200° C. to 250° C. By depositing the insulating layer 195 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0407] After the insulating layer 195 is formed, heat treatment can be performed. The heat treatment can sometimes reduce the electrical resistance of the region 108L, the region 208L, and the region 208D. For example, the heat treatment can appropriately diffuse impurities, forming the regions 208L and 208D with ideal impurity concentration gradients. The above description can be referred to for the heat treatment, and therefore a detailed description thereof will be omitted. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), impurities may diffuse into the channel formation region, which may result in deterioration of the electrical characteristics and reliability of the transistor.

[0408] Note that this heat treatment does not necessarily have to be performed. Alternatively, the heat treatment may be omitted here and may serve as a heat treatment to be performed in a later step. Furthermore, if there is a high-temperature treatment (for example, a film formation step) in a later step, this heat treatment may serve as the heat treatment.

[0409] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0410] This embodiment mode can be combined with other embodiment modes as appropriate.

[0411] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 17A to 25. FIG.

[0412] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0413] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0414] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0415] The display device of this embodiment can have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0416] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0417] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0418] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that the in-cell type touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also referred to as a display device) and an opposing substrate.

[0419] <Configuration Example of Display Device> FIG. 17A shows a perspective view of a display device 50A.

[0420] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 17A, the substrate 152 is indicated by a dashed line.

[0421] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Fig. 17A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 17A can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0422] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one or more sides of the display portion 162. There can be one or more connection portions 140. Fig. 17A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0423] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). The circuit portion 164 can also include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0424] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0425] 17A shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may be configured without an IC. The IC can also be mounted on an FPC by a COF method, or the like.

[0426] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, it is possible to reduce manufacturing costs.

[0427] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0428] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 17A shows an enlarged view of one pixel 210.

[0429] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0430] The pixel 210 shown in FIG. 17A includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. A full-color display can be achieved by configuring one pixel 210 with the pixels 230R, 230G, and 230B. The pixels 230R, 230G, and 230B each function as a subpixel. The display device 50A shown in FIG. 17A illustrates an example in which the pixels 230 functioning as subpixels are arranged in a stripe array. The number of subpixels constituting one pixel 210 is not particularly limited. For example, the pixel 210 may have four subpixels that emit R, G, B, and white (W) light. Alternatively, the pixel 210 may have four subpixels that emit R, G, B, and Y light.

[0431] Each of the pixel 230R, the pixel 230G, and the pixel 230B includes a display element and a circuit that controls the driving of the display element.

[0432] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials can be used.

[0433] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0434] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0435] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0436] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, OLEDs (organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0437] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0438] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0439] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0440] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0441] In this embodiment, a case where a light-emitting element is used as a display element will be mainly described as an example.

[0442] 17B is a block diagram illustrating a display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or greater). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

[0443] The circuit included in the first drive circuit unit 231 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit can be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit can be provided at a position facing the second drive circuit unit 232 across the display unit 162.

[0444] The circuit portion 164 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. A transistor, a capacitor, or the like can be used for the circuit portion 164. The transistor included in the circuit portion 164 can be formed in the same process as the transistor included in the pixel 230.

[0445] The display device 50A has wirings 236 that are arranged substantially parallel to each other and whose potential is controlled by a circuit included in a first drive circuit unit 231, and wirings 238 that are arranged substantially parallel to each other and whose potential is controlled by a circuit included in a second drive circuit unit 232. Note that Fig. 17B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

[0446] In the semiconductor device of one embodiment of the present invention, a vertical transistor (VFET) with a short channel length and high on-state current and a TGSA transistor with a long channel length and high saturation property can be formed by some common processes. An oxide semiconductor (OS) can be suitably used for the channel formation region of these transistors, thereby enabling the transistors to have low off-state current. The semiconductor device of one embodiment of the present invention can be suitably used for one or both of the display portion 162 and the circuit portion 164. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device, it is possible to reduce manufacturing costs.

[0447] <Configuration Example of Driver Circuit> A configuration example will be described using a latch circuit as an example of a circuit that can be used as a driver circuit.

[0448] 18A is a circuit diagram showing an example of the configuration of a latch circuit LAT. The latch circuit LAT shown in FIG. 18A includes transistors Tr31, Tr33, Tr35, Tr36, a capacitance element C31, and an inverter circuit INV. In FIG. 18A, a node N is defined as a node where one of the source or drain of transistor Tr33, the gate (first gate) of transistor Tr35, and one electrode of capacitance element C31 are connected.

[0449] In the latch circuit LAT shown in FIG. 18A , when a high-potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After the data is written to the latch circuit LAT, if the potential of the terminal SMP is set to a low potential, the transistor Tr33 is turned off. As a result, the potential of the node N is maintained, and the data written to the latch circuit LAT is maintained. Specifically, for example, when the potential of the node N is low, it can be assumed that data with a value of "0" is held in the latch circuit LAT, and when the potential of the node N is high, it can be assumed that data with a value of "1" is held in the latch circuit LAT.

[0450] The transistor Tr33 is preferably a transistor with low off-state current. An OS transistor can be suitably used for the transistor Tr33. This allows the latch circuit LAT to retain data for a long period of time. Therefore, the frequency of rewriting data to the latch circuit LAT can be reduced.

[0451] In this specification and the like, writing data into the latch circuit LAT such that a signal input from the terminal SP2 is output to the terminal LIN may be simply referred to as "writing data into the latch circuit LAT." In other words, for example, writing data with a value of "1" into the latch circuit LAT may be simply referred to as "writing data into the latch circuit LAT."

[0452] The semiconductor device according to one embodiment of the present invention can be suitably used in the latch circuit LAT. For example, the transistor 100 or the transistor 200 illustrated in FIG. 1B and the like can be used as one or more of the transistors Tr31, Tr33, Tr35, and Tr36.

[0453] 18A does not explicitly show where the back gates (second gates) of the transistors Tr31, Tr33, Tr35, and Tr36 are connected. As described in Embodiment 1, the back gates of the transistors of one embodiment of the present invention can be connected to a wiring to which a ground potential or any potential is applied, or can be connected to another terminal (gate (first gate), source, or drain) of the transistor.

[0454] 18B shows an example of the configuration of the inverter circuit INV. The inverter circuit INV includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitive element C41.

[0455] 18A and the inverter circuit INV has the configuration shown in FIG. 18B, all the transistors included in the latch circuit LAT can be transistors of the same polarity, for example, n-channel transistors. As a result, for example, the transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47, in addition to the transistor Tr33, can be OS transistors. Therefore, all the transistors included in the latch circuit LAT can be manufactured using the same process.

[0456] The semiconductor device according to one embodiment of the present invention can be suitably used for the inverter circuit INV. For example, the transistor 100 or the transistor 200 illustrated in FIG. 1B and the like can be used for one or more of the transistors Tr41, Tr43, Tr45, and Tr47.

[0457] 18B does not explicitly show where the back gates of the transistors Tr41, Tr43, Tr45, and Tr47 are connected. As described in Embodiment 1, the back gates of the transistors of one embodiment of the present invention can be connected to a wiring to which a ground potential or any potential is applied, or can be connected to another terminal (gate, source, or drain) of the transistor.

[0458] For example, the occupation area can be reduced and a display device with a narrow frame can be obtained by using one or more of the transistors 100 and 100A to 100E described in Embodiment 1. Furthermore, a high-performance display device can be obtained by preferably using one or more of the transistors 100 and 100A to 100E described in Embodiment 1 as transistors that require a large on-state current and one or more of the transistors 200 and 200A to 200D described in Embodiment 1 as transistors that require high saturation properties.

[0459] 19A shows a configuration example of a pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0460] 19A includes a transistor 52A, a transistor 52B, and a capacitor 53. The pixel circuit 51 is a 2Tr1C pixel circuit including two transistors (Tr) and one capacitor (C). Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

[0461] The anode of the light-emitting device 61 is connected to one of the source or drain of the transistor 52B and one electrode of the capacitor 53. The other of the source or drain of the transistor 52B is connected to a wiring ANO. The gate of the transistor 52B is connected to one of the source or drain of the transistor 52A and the other electrode of the capacitor 53. The other of the source or drain of the transistor 52A is connected to a wiring SL. The gate of the transistor 52A is connected to a wiring GL. The cathode of the light-emitting device 61 is connected to a wiring VCOM.

[0462] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0463] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting device 61. The capacitor 53 has a function of maintaining the gate potential of the transistor 52B. The intensity of light emitted from the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor 52B.

[0464] A back gate can be provided in some or all of the transistors included in the pixel circuit 51. In the pixel circuit 51 shown in FIG. 19A , the transistor 52A has a back gate connected to the other of the source and the drain of the transistor 52A. The pixel circuit 51 also shows a configuration in which the transistor 52B has a back gate connected to the source and the drain of the transistor 52B. Note that the back gate of the transistor 52A may also be connected to the gate of the transistor 52A. The back gate of the transistor 52B may also be connected to the gate of the transistor 52B.

[0465] The above-described semiconductor device can be suitably used in the pixel circuit 51. Compared with the transistor 52A functioning as a selection transistor for controlling the selection state of the pixel 230, the transistor 52B functioning as a driving transistor for controlling the current flowing through the light-emitting device 61 preferably has high saturation. By using one of the transistors 200 and 200A to 200D, which have a long channel length, as the transistor 52B, a highly reliable display device can be obtained. Furthermore, by using one of the transistors 100 and 100A to 100E as the transistor 52A, the area occupied by the pixel circuit 51A can be reduced, and a high-resolution display device can be obtained.

[0466] Note that the transistor 52B can also be one of the transistors 100 and 100A to 100E. By using a transistor with a short channel length as the transistor 52B, a display device with high luminance can be provided. Furthermore, the area occupied by the pixel circuit 51 can be reduced, and a high-resolution display device can be provided.

[0467] 19B shows an example of a configuration different from that of the pixel 230 shown in FIG.

[0468] 19B differs from the pixel circuit 51 shown in Fig. 19A mainly in that it includes a transistor 52C. The pixel circuit 51A includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51A is a 3Tr1C type pixel circuit including three transistors (Tr) and one capacitor (C).

[0469] One of the source and the drain of the transistor 52C is connected to one of the source and the drain of the transistor 52B. The other of the source and the drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0. The gate of the transistor 52C is connected to a wiring GL.

[0470] The transistor 52C has a function of controlling conduction or non-conduction between the wiring V0 and one of the source electrode and the drain electrode of the transistor 52B based on the potential of the wiring GL. The reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0471] The wiring V0 can be used to acquire a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit and output to the outside, or converted into a digital signal by an AD converter and output to the outside.

[0472] The above-described semiconductor device can be suitably used in the pixel circuit 51A. By using one of the transistors 200 and 200A to 200D, which have a long channel length, as the transistor 52B, a highly reliable display device can be obtained. By using one or more of the transistors 100 and 100A to 100E as the transistors 52A and 52C, the area occupied by the pixel circuit 51A can be reduced, resulting in a high-resolution display device. Note that the transistor 52B can also be one of the transistors 100 and 100A to 100E.

[0473] 19C shows a configuration example of the pixel circuit 51. Fig. 19C is a cross-sectional view of the pixel circuit 51. Fig. 19C excerpts the transistor 52A, the transistor 52B, the capacitor 53, and the pixel electrode of the light-emitting device 61. Note that the connection between the transistor 52A and the transistor 52B is omitted.

[0474] The transistor 52A includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 116, an insulating layer 110s, a conductive layer 112a, and a conductive layer 112b. The transistor 52B includes a conductive layer 202, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. The above descriptions can be referred to for the transistors 52A and 52B, and detailed descriptions thereof will be omitted.

[0475] The capacitor 53 includes a conductive layer 212a, a conductive layer 112p, and an insulating layer 106 sandwiched between them. The conductive layer 112p is provided over the insulating layer 120. The conductive layer 112p can be formed, for example, in the same process as the conductive layer 112b. The insulating layer 106 is provided over the conductive layer 112p, and the conductive layer 212b is provided over the insulating layer 106. The conductive layer 212b functions as one of a source electrode and a drain electrode of the transistor 52B and also functions as one electrode of the capacitor 53. Note that the structure of the capacitor 53 is not particularly limited.

[0476] An insulating layer 195 is provided to cover the transistor 52A, the transistor 52B, and the capacitor 53. An insulating layer 233 is provided to cover the insulating layer 195. An insulating layer 235 is provided to cover the insulating layer 233. A light-emitting device 61 can be provided on the insulating layer 235. FIG. 19C shows a pixel electrode 111 that functions as one electrode of the light-emitting device 61. The insulating layer 195 and the insulating layer 233 have a first opening that reaches the conductive layer 212b, and a conductive layer 234 is provided to cover the first opening. The conductive layer 234 is connected to the conductive layer 212b through the first opening. The insulating layer 235 has a second opening that reaches the conductive layer 234, and a pixel electrode 111 is provided to cover the second opening. The pixel electrode 111 is connected to the conductive layer 234 through the second opening. The insulating layer 195 can be described above, so a detailed description thereof will be omitted. The insulating layer 233 and the insulating layer 235 have a function of reducing unevenness caused by the transistor 52A, the transistor 52B, and the transistor 52C and making the surface on which the light-emitting device 61 is formed more flat. Note that in this specification and the like, the insulating layer 233 and the insulating layer 235 may each be referred to as a planarizing layer.

[0477] The insulating layers 233 and 235 are preferably each made of an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 can have a laminated structure of an organic insulating film and an inorganic insulating film. The insulating layer 235 preferably has a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. This allows the inorganic insulating film to function as an etching protection layer when forming the light-emitting device 61. Specifically, this can prevent a portion of the insulating layer 235 from being etched during the formation of the pixel electrode 111, thereby preventing the formation of a recess in the insulating layer 235. Alternatively, a recess may be formed in the insulating layer 235 during the formation of the pixel electrode 111. Similarly, the insulating layer 233 can have a laminated structure of an organic insulating film and an inorganic insulating film.

[0478] 20 shows a configuration example different from the pixel 230 described above. The pixel 230 has a pixel circuit 51B and a light-emitting device 61.

[0479] The pixel circuit 51B includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a capacitance element C11, and a capacitance element C12. The pixel circuit 51B is a 6Tr2C type pixel circuit including six transistors (Tr) and two capacitance elements (C).

[0480] 20 does not explicitly show where the backgates of the transistors other than the transistor M12 (the transistor M11, the transistor M13, the transistor M14, the transistor M15, and the transistor M16) are connected. As described in Embodiment 1, the backgates of the transistors of one embodiment of the present invention can be connected to a wiring to which a ground potential or any potential is applied, or can be connected to another terminal (gate, source, or drain) of the transistor.

[0481] The anode of the light-emitting device 61 is connected to one of the source or drain of the transistor M15. The cathode of the light-emitting device 61 is connected to the wiring VCOM. The other of the source or drain of the transistor M15 is connected to one of the source or drain of the transistor M12, one of the source or drain of the transistor M13, one of the source or drain of the transistor M16, one electrode of the capacitor C11, and one electrode of the capacitor C12. The gate of the transistor M12 is connected to one of the source or drain of the transistor M11, the other of the source or drain of the transistor M13, and the other electrode of the capacitor C11. The back gate of the transistor M12 is connected to one of the source or drain of the transistor M14 and the other electrode of the capacitor C12.

[0482] The other of the source and the drain of the transistor M11 is connected to the wiring SL. The other of the source and the drain of the transistor M12 is connected to the wiring ANO. The other of the source and the drain of the transistor M14 is connected to the wiring V0. The other of the source and the drain of the transistor M16 is connected to the wiring V1. For example, a constant potential is supplied to the wiring V1. The gates of the transistors M11 and M16 are connected to the wiring GL1. The gates of the transistors M13 and M14 are connected to the wiring GL2. The gate of the transistor M15 is connected to the wiring GL3.

[0483] The transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of the transistor M12 and the wiring SL. The transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61. The transistor M14 supplies the potential of the wiring V0 to the back gate of the transistor M12. The threshold voltage of the transistor M12 can be controlled by supplying a constant potential to the back gate of the transistor M12. The capacitor C11 maintains the gate potential of the transistor M12. The capacitor C12 maintains the back gate potential of the transistor M12. The pixel circuit 51B has a so-called internal threshold voltage correction function that corrects the threshold voltage of the transistor M12 using the back gate. Specifically, the capacitor C12 maintains a back gate potential such that the threshold voltage of the transistor M12 is 0 V. This allows the threshold voltage of the transistor M12 to be corrected so that it is fixed at or near 0 V, regardless of variations in the threshold voltage of the transistor or deterioration over time.

[0484] The above-described semiconductor device can be suitably used in the pixel circuit 51B. For example, the transistors M11, M13, M14, M15, and M16 can be one or more of the transistors 100 and 100A to 100E shown in FIG. 1B and the like, and the transistor M12 can be one of the transistors 200 and 200A to 200D.

[0485] The transistor M12, which functions as a driving transistor, preferably has high saturation. By using the transistor 200 or one of the transistors 200A to 200D, which have a long channel length, as the transistor M12, a highly reliable display device can be obtained. By using the transistor 100 or one or more of the transistors 100A to 100E as the transistors M11, M13, M14, M15, and M16, the area occupied by the pixel circuit 51B can be reduced, and a high-resolution display device can be obtained.

[0486] Note that the transistor M12 can also be one of the transistors 100 and 100A to 100E. By using a transistor with a short channel length as the transistor M12, a display device with high luminance can be provided. Furthermore, the area occupied by the pixel circuit 51B can be reduced, resulting in a high-resolution display device.

[0487] By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be provided. By applying the semiconductor device of one embodiment of the present invention, the occupied area can be reduced even when the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be provided. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be provided.

[0488] Since the semiconductor device of one embodiment of the present invention can occupy a small area, the aperture ratio of a pixel in a bottom-emission display device can be increased. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0489] In this specification and the like, the aperture ratio refers to the ratio of the area of ​​the region through which light is emitted to the area of ​​the pixel.

[0490] <Configuration example 1 of display device> Figure 21A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit portion 164, a portion of the display portion 162, a portion of the connection portion 140, and a portion of the area including the end portion are cut away.

[0491] 21A includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 207G, a transistor 207B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, and the like between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the pixel 230R that emits red light, the light-emitting element 130G is a display element included in the pixel 230G that emits green light, and the light-emitting element 130B is a display element included in the pixel 230B that emits blue light.

[0492] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0493] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0494] The transistor 205D, the transistor 205R, the transistor 205G, the transistor 207G, and the transistor 207B are all formed over a substrate 151. These transistors can be manufactured using some common steps.

[0495] One or more of the transistors 100, 100A to 100E, 200, and 200A to 200D can be used for one or more of the transistors 205D, 205R, 205G, 207G, and 207B. Figure 21A shows a configuration example in which the transistor 100 is used for the transistors 205D, 205R, and 205G, and the transistor 200 is used for the transistors 207G and 207B.

[0496] A high-resolution display device can be obtained by using one or more of the transistors 100 and 100A to 100E as the transistors provided in the display portion 162. Furthermore, one or more of the highly saturable transistors 200 and 200A to 200D can be preferably used as driving transistors for the light-emitting elements 130R, 130G, and 130B. This can provide a highly reliable display device.

[0497] By using one or more of the transistors 100 and 100A to 100E described above in the circuit portion 164, a display device that operates at high speed can be obtained. Compared to the transistors provided in the display portion 162, the transistors provided in the circuit portion 164 may require a large on-state current. It is preferable to use a transistor with a short channel length in the circuit portion 164. For example, one or more of the transistors 100 and 100A to 100E described above can be suitably used in the circuit portion 164. By using one or more of the transistors 100 and 100A to 100E in the circuit portion 164, the occupied area can be reduced, and a display device with a narrow frame can be obtained. Note that one or more of the transistors 200 and 200A to 200D can also be used in the circuit portion 164.

[0498] Note that the transistor included in the display device of this embodiment is not limited to the transistor included in the semiconductor device of one embodiment of the present invention. For example, a transistor included in the semiconductor device of one embodiment of the present invention and a transistor having another structure can be combined. The display device of this embodiment can have a structure including, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment can be either a top-gate transistor or a bottom-gate transistor. Alternatively, a structure in which gates are provided above and below a semiconductor layer in which a channel is formed can be used.

[0499] The transistors 205D, 205R, 205G, 207G, and 207B can preferably be OS transistors.

[0500] The display device of this embodiment may also have a Si transistor.

[0501] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0502] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0503] In terms of the saturation of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the EL element vary. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0504] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 can have the same structure, or can have different structures. The transistors included in the circuit portion 164 can all have the same structure, or can have two or more types of transistor structures. Similarly, the transistors included in the display portion 162 can all have the same structure, or can have two or more types of transistor structures.

[0505] All the transistors included in the display portion 162 can be OS transistors. Alternatively, all the transistors included in the display portion 162 can be Si transistors. Alternatively, some of the transistors included in the display portion 162 can be OS transistors and the rest can be Si transistors.

[0506] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0507] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and the drain of the driving transistor is connected to a pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0508] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0509] An insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, the transistor 207G, and the transistor 207B, and an insulating layer 235 is provided over the insulating layer 195.

[0510] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0511] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 21A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0512] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 21A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0513] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 21A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0514] 21A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may each have a different thickness. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element can be increased.

[0515] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B (not shown).

[0516] Each end of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B is covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can insulate the pixel electrode from the common electrode. Furthermore, the insulating layer 237 can insulate adjacent light-emitting elements from each other.

[0517] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. The insulating layer 237 may also be provided up to the edge of the display device 50A.

[0518] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0519] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0520] A conductive film that transmits visible light can also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device.

[0521] Materials for forming the pair of electrodes of a light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), as well as silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above as examples, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these elements, and graphene.

[0522] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0523] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0524] The EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape. In FIG. 21A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 21A , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both portions where adjacent EL layers overlap and portions where adjacent EL layers do not overlap but are spaced apart.

[0525] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0526] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0527] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transporting properties (hole-transporting material) and a substance with high electron-transporting properties (electron-transporting material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transporting properties and high hole-transporting properties) or a TADF material may be used.

[0528] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing efficient emission. This configuration allows the light-emitting element to simultaneously achieve high efficiency, low-voltage operation, and a long life.

[0529] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0530] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. Each of the layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink-jet method, or a coating method.

[0531] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure may also be called a stack structure.

[0532] In Figure 21A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0533] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 21A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0534] The protective layer 131 is preferably provided on at least the display portion 162, and is preferably provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162, but also the connection portion 140 and the circuit portion 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, the connection portion 197 has a portion where the protective layer 131 is not provided, in order to connect the FPC 172 and the conductive layer 166.

[0535] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0536] The protective layer 131 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed of at least one of an insulating film, a semiconductor film, and a conductive film.

[0537] The protective layer 131 has an inorganic film, which prevents the common electrode 115 from being oxidized, prevents impurities (water, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0538] The protective layer 131 can be made of an inorganic insulating film. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.

[0539] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0540] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0541] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0542] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0543] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. The conductive layer 165 can be formed, for example, by processing the same conductive film as the conductive layer 112b. The conductive layer 166 can be formed, for example, by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode and the conductive layer 112b. Specifically, FIG. 21A illustrates an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242 .

[0544] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0545] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, the circuit section 164, and the like.

[0546] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0547] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.

[0548] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0549] The substrate 151 and the substrate 152 can each be made of glass, quart...

Claims

a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, a third insulating layer, and a fourth insulating layer; the second transistor has a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, the fourth insulating layer, and a fifth insulating layer; the first insulating layer is provided on the first conductive layer; the second conductive layer is provided on the first insulating layer and has a region overlapping with the first conductive layer; the second insulating layer is provided on the first insulating layer and the second conductive layer; the third conductive layer is provided on the second insulating layer and has a region overlapping with the second conductive layer; a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer; the third insulating layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer within the first opening; the first semiconductor layer is in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and an upper surface of the first conductive layer in the first opening; the fifth conductive layer is provided on the second insulating layer in a region different from the third conductive layer; the fifth insulating layer is provided in contact with an upper surface and a side surface of the fifth conductive layer, the second semiconductor layer is provided on the fifth insulating layer and has a region overlapping with the fifth conductive layer; the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer, and has a second opening and a third opening in a region overlapping with the second semiconductor layer; the fourth conductive layer is provided on the fourth insulating layer and has a region overlapping with the first semiconductor layer; the sixth conductive layer is provided in the second opening and in contact with an upper surface of the second semiconductor layer; the seventh conductive layer is provided in the third opening and in contact with an upper surface of the second semiconductor layer; the eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, and has a region overlapping with the second semiconductor layer; Semiconductor device. 　 In claim 1, the first semiconductor layer and the second semiconductor layer include a metal oxide; the third insulating layer comprises one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide; The fifth insulating layer includes one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 In claim 1 or 2, the third conductive layer and the fifth conductive layer have a first material, and the first material is one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium; Semiconductor device. 　 In claim 1 or 2, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer comprise one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride; The seventh insulating layer and the tenth insulating layer include one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, a third insulating layer, and a fourth insulating layer; the second transistor has a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, the fourth insulating layer, and a fifth insulating layer; the first insulating layer is provided on the first conductive layer and on the fifth conductive layer; the second conductive layer is provided on the first insulating layer and has a region overlapping with the first conductive layer; the second insulating layer is provided on the first insulating layer and the second conductive layer; the third conductive layer is provided on the second insulating layer and has a region overlapping with the second conductive layer; a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer; the third insulating layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer within the first opening; the first semiconductor layer is in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and an upper surface of the first conductive layer in the first opening; the fifth insulating layer is provided on the second insulating layer and has a region overlapping with the fifth conductive layer; the second semiconductor layer is provided on the fifth insulating layer and has a region overlapping with the fifth conductive layer; the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer, and has a second opening and a third opening in a region overlapping with the second semiconductor layer; the fourth conductive layer is provided on the fourth insulating layer and has a region overlapping with the first semiconductor layer; the sixth conductive layer is provided in the second opening and in contact with an upper surface of the second semiconductor layer; the seventh conductive layer is provided in the third opening and in contact with an upper surface of the second semiconductor layer; the eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, and has a region overlapping with the second semiconductor layer; Semiconductor device. 　 In claim 5, the first semiconductor layer and the second semiconductor layer include a metal oxide; the third insulating layer comprises one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide; The fifth insulating layer includes one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 In claim 5 or 6, the first conductive layer and the fifth conductive layer have a first material, and the first material is one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium; Semiconductor device. 　 In claim 5 or 6, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer comprise one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride; The seventh insulating layer and the tenth insulating layer include one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 a first transistor, a second transistor, a first insulating layer, and a second insulating layer; the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first semiconductor layer, a third insulating layer, and a fourth insulating layer; the second transistor has a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a second semiconductor layer, the fourth insulating layer, and a fifth insulating layer; the first insulating layer is provided on the first conductive layer; the second conductive layer is provided on the first insulating layer and has a region overlapping with the first conductive layer; the fifth conductive layer is provided on the first insulating layer in a region different from the second conductive layer; the second insulating layer is provided on the first insulating layer, the second conductive layer, and the fifth conductive layer; the third conductive layer is provided on the second insulating layer and has a region overlapping with the second conductive layer; a first opening reaching the first conductive layer is provided in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer; the third insulating layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer within the first opening; the first semiconductor layer is in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and an upper surface of the first conductive layer in the first opening; the fifth insulating layer is provided on the second insulating layer and has a region overlapping with the fifth conductive layer; the second semiconductor layer is provided on the fifth insulating layer and has a region overlapping with the fifth conductive layer; the fourth insulating layer is provided on the first semiconductor layer and the second semiconductor layer, and has a second opening and a third opening in a region overlapping with the second semiconductor layer; the fourth conductive layer is provided on the fourth insulating layer and has a region overlapping with the first semiconductor layer; the sixth conductive layer is provided in the second opening and in contact with an upper surface of the second semiconductor layer; the seventh conductive layer is provided in the third opening and in contact with an upper surface of the second semiconductor layer; the eighth conductive layer is provided on the fourth insulating layer sandwiched between the second opening and the third opening, and has a region overlapping with the second semiconductor layer; Semiconductor device. 　 In claim 9, the first semiconductor layer and the second semiconductor layer include a metal oxide; the third insulating layer comprises one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide; The fifth insulating layer includes one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 In claim 9 or 10, the second conductive layer and the fifth conductive layer comprise a first material, the first material being one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, niobium, and a metal oxide; Semiconductor device. 　 In claim 9 or 10, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer comprise one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride; The seventh insulating layer and the tenth insulating layer include one or both of silicon oxide and silicon oxynitride. Semiconductor device. 　 forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a first conductive film on the first insulating film; processing the first conductive film to form a second conductive layer on the first insulating film so as to have a region overlapping with the first conductive layer; forming a second insulating film on the second conductive layer and the first insulating film; forming a third conductive layer on the second insulating film in a region not overlapping with the first conductive layer and the second conductive layer; forming a first insulating layer on the third conductive layer and the second insulating film so as to have a region overlapping the third conductive layer; forming a second conductive film on the first insulating layer and the second insulating film; removing a portion of the first insulating film, the second conductive layer, the second insulating film, and the second conductive film to form a second insulating layer having a first opening reaching the first conductive layer, a fourth conductive layer, a third insulating layer, and a fifth conductive layer; forming a fourth insulating layer in contact with a side surface of the second insulating layer in the first opening, a side surface of the fourth conductive layer in the first opening, a side surface of the third insulating layer in the first opening, and a side surface of the fifth conductive layer in the first opening; processing the fifth conductive layer to form a sixth conductive layer having an area overlapping the first conductive layer and the fourth conductive layer; forming a first semiconductor layer in contact with an upper surface of the first conductive layer in the first opening, a side surface of the fourth insulating layer in the first opening, and an upper surface of the sixth conductive layer, and forming a second semiconductor layer on the first insulating layer so as to have a region overlapping with the third conductive layer; forming a third insulating film on the first semiconductor layer and the second semiconductor layer; processing the third insulating film to form a fifth insulating layer having a second opening and a third opening reaching the second semiconductor layer; forming a seventh conductive layer overlapping the first semiconductor layer, an eighth conductive layer overlapping the second semiconductor layer and the third conductive layer, a ninth conductive layer overlapping the second opening, and a tenth conductive layer overlapping the third opening on the fifth insulating layer; A method for manufacturing a semiconductor device.

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