Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device with a small occupancy area. This semiconductor device has first and second transistors and an insulating layer. The first transistor has first and second conductive layers and a first semiconductor layer. The second transistor has third and fourth conductive layers and a second semiconductor layer. The insulating layer has a first opening reaching the first conductive layer and a second opening reaching the third conductive layer. The second conductive layer has a third opening overlapping the first opening, and the fourth conductive layer has a fourth opening overlapping the second opening. The first semiconductor layer has a first region in contact with an upper surface of the first conductive layer and a second region in contact with a side surface of the insulating layer, and the second semiconductor layer has a third region in contact with an upper surface of the third conductive layer and a fourth region in contact with a side surface of the insulating layer. The first region has a first element and the first element is boron or phosphorus. The first region has a portion having a higher concentration of the first element than the second region and the third region.

Description

Semiconductor device and method for manufacturing the same

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with high saturation. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first semiconductor layer. The second transistor includes a third conductive layer, a fourth conductive layer, and a second semiconductor layer. The first insulating layer is located over the first conductive layer and the third conductive layer. The first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the third conductive layer. The second conductive layer and the fourth conductive layer are each located over the first insulating layer. The second conductive layer has a third opening in a region overlapping with the first opening. The fourth conductive layer has a fourth opening in a region overlapping with the second opening. The first semiconductor layer has a first region in contact with the top surface of the first conductive layer and a second region in contact with the side surface of the first insulating layer in the first opening, and has a region in contact with the side surface of the second conductive layer in the third opening. The second semiconductor layer has a third region in contact with the top surface of the third conductive layer and a fourth region in contact with the side surface of the first insulating layer in the second opening, and has a region in contact with the side surface of the fourth conductive layer in the fourth opening. The first region contains a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The first region has a portion where the concentration of the first element is higher than that of the third region.

[0012] In the above-described semiconductor device, the first region preferably has a portion where the concentration of the first element is higher than that of the fourth region.

[0013] In the above-described semiconductor device, the first semiconductor layer preferably has a fifth region in contact with an upper surface of the second conductive layer. The second semiconductor layer preferably has a sixth region in contact with an upper surface of the fourth conductive layer. The fifth region preferably contains the first element. The fifth region preferably has a portion having a higher concentration of the first element than the second region. The fifth region preferably has a portion having a higher concentration of the first element than the sixth region.

[0014] In the above-described semiconductor device, the fifth region preferably has a portion where the concentration of the first element is higher than that of the fourth region.

[0015] In the semiconductor device described above, the concentration of the first element in the second region is 1×10 of the concentration of the first element in the first region. −３ It is preferable that the ratio is 1:1 or less.

[0016] The semiconductor device preferably includes a second insulating layer. The second insulating layer is preferably located on the first semiconductor layer and the second semiconductor layer. A portion of the second insulating layer in contact with the first region preferably contains the first element.

[0017] In the semiconductor device described above, it is preferable that the angle formed between the side surface of the first insulating layer and the top surface of the first conductive layer in the first opening be equal to or greater than 65 degrees and equal to or less than 90 degrees.

[0018] In the semiconductor device described above, the first region preferably contains hydrogen, and the concentration of hydrogen in the first region is preferably higher than the concentration of hydrogen in the second region.

[0019] In the semiconductor device described above, the first region preferably contains a second element. The second element is preferably argon, krypton, or xenon. The first region preferably has a portion where the concentration of the second element is higher than that of the second region. The first region preferably has a portion where the concentration of the second element is higher than that of the third region.

[0020] In the above-described semiconductor device, the first semiconductor layer and the second semiconductor layer preferably each contain a metal oxide.

[0021] In the semiconductor device described above, the first insulating layer preferably includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. The third insulating layer and the fifth insulating layer preferably include silicon and nitrogen, respectively. The fourth insulating layer preferably includes silicon and oxygen.

[0022] In the semiconductor device described above, the first insulating layer preferably includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen. The fifth insulating layer preferably includes one or both of aluminum and hafnium, and oxygen.

[0023] One embodiment of the present invention includes forming a first conductive layer and a second conductive layer over a substrate, forming an insulating film over the first conductive layer and the second conductive layer, forming a third conductive layer having a region overlapping with the first conductive layer and a fourth conductive layer having a region overlapping with the second conductive layer over the insulating film, and processing the insulating film, the third conductive layer, and the fourth conductive layer to form a first insulating layer having a first opening reaching the first conductive layer and a second opening reaching the second conductive layer, and forming a fifth conductive layer having a third opening overlapping with the first opening and a fourth conductive layer overlapping with the second opening. a sixth conductive layer having an opening; a first semiconductor layer over the first conductive layer, the first insulating layer, and the fifth conductive layer; a second semiconductor layer over the second conductive layer, the first insulating layer, and the sixth conductive layer; a second insulating layer over the first semiconductor layer and the second semiconductor layer; a mask layer over the second insulating layer in a region overlapping with the second semiconductor layer; a first element is supplied to the first semiconductor layer through the second insulating layer using the mask layer as a mask; and the mask layer is removed; the first element is boron or phosphorus.

[0024] In the above-described method for manufacturing a semiconductor device, the first element is preferably supplied by ion implantation.

[0025] In the above-described method for manufacturing a semiconductor device, the first element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate.

[0026] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with high saturation can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIG. 4A is a top view showing an example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A to 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A to 12C are cross-sectional views showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIG. 15B is a cross-sectional view showing an example of a semiconductor device. FIGS. 16A to 16G are circuit diagrams showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIGS. 17B and 17C are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a top view showing an example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a top view showing an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a semiconductor device. FIGS. 20A and 20B are equivalent circuit diagrams of a semiconductor device. FIG. 20C is a top view showing an example of a semiconductor device. FIG. 21 is a cross-sectional view showing an example of a semiconductor device. FIG. 22 is a perspective view showing an example of a semiconductor device. FIGS. 23A to 23D are perspective views showing an example of a semiconductor device. FIGS. 24A and 24B are equivalent circuit diagrams of a semiconductor device. FIG. 24C is a top view showing an example of a semiconductor device. FIG. 25 is a cross-sectional view showing an example of a semiconductor device. FIG. 26 is a perspective view showing an example of a semiconductor device. 27A to 27D are perspective views showing an example of a semiconductor device, and Fig. 28A to Fig. 28E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.29A to 29D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30A to 30C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 31A to 31C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 32A and 32B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 33 is a perspective view illustrating an example of a display device. FIGS. 34A and 34B are cross-sectional views illustrating an example of a display device. FIG. 35 is a cross-sectional view illustrating an example of a display device. FIGS. 36A to 36C are cross-sectional views illustrating an example of a display device. FIGS. 37A and 37B are cross-sectional views illustrating an example of a display device. FIG. 38 is a cross-sectional view illustrating an example of a display device. FIGS. 39A to 39D are diagrams illustrating examples of electronic devices. FIGS. 40A to 40F are diagrams illustrating examples of electronic devices. FIGS. 41A to 41G are diagrams illustrating examples of electronic devices.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims. Even if a term does not have an ordinal number attached to it in this specification, the ordinal number may be attached in the claims. Even if a term has an ordinal number attached to it in this specification, the ordinal number may be omitted in the claims.

[0033] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0034] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0035] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed depending on the situation, such as the source terminal and drain terminal, or the source electrode and drain electrode.

[0036] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0037] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the gate-source voltage (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the gate-source voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0039] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0040] In this specification, the phrase "top surface shapes are approximately the same" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned.

[0041] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0042] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0043] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0044] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0045] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0046] In this specification, the sacrificial layer is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0047] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0048] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0049] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer.

[0050] The first transistor has a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer, and a first gate electrode. The second transistor has a third conductive layer, a fourth conductive layer, a second semiconductor layer, a second insulating layer, and a second gate electrode. The first conductive layer functions as one of a source electrode and a drain electrode of the first transistor, and the second conductive layer functions as the other. A region of the first semiconductor layer in contact with the first conductive layer functions as one of a source region and a drain region of the first transistor, and a region in contact with the second conductive layer functions as the other. The third conductive layer functions as one of a source electrode and a drain electrode of the second transistor, and the fourth conductive layer functions as the other. A region of the second semiconductor layer in contact with the third conductive layer functions as one of a source region and a drain region of the second transistor, and a region in contact with the fourth conductive layer functions as the other. A part of the second insulating layer functions as a gate insulating layer of the first transistor, and another part functions as a gate insulating layer of the second transistor.

[0051] The first insulating layer is located on the first conductive layer and the third conductive layer. The first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the third conductive layer. The second conductive layer and the fourth conductive layer are each located on the first insulating layer. The second conductive layer has a third opening in a region overlapping with the first opening. The fourth conductive layer has a fourth opening in a region overlapping with the second opening.

[0052] The first semiconductor layer has a first region in contact with the top surface of the first conductive layer and a second region in contact with the side surface of the first insulating layer in the first opening, and has a region in contact with the side surface of the second conductive layer in the third opening. The second semiconductor layer has a third region in contact with the top surface of the third conductive layer and a fourth region in contact with the side surface of the first insulating layer in the second opening, and has a region in contact with the side surface of the fourth conductive layer in the fourth opening.

[0053] The first semiconductor layer preferably has a fifth region in contact with the top surface of the second conductive layer, and the second semiconductor layer preferably has a sixth region in contact with the top surface of the fourth conductive layer.

[0054] A second insulating layer is located on the first semiconductor layer and the second semiconductor layer. A first gate electrode and a second gate electrode are located on the second insulating layer. The first gate electrode has a region overlapping with the first semiconductor layer via the second insulating layer. The second gate electrode has a region overlapping with the second semiconductor layer via the second insulating layer.

[0055] The first region and the fifth region each contain an impurity element. The impurity element is preferably a first element. The first element is preferably one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and a noble gas (helium, neon, argon, krypton, xenon, etc.).

[0056] The first region and the fifth region each have a portion where the concentration of the first element is higher than any of the second region, the third region, the fourth region, and the sixth region.

[0057] By including the impurity element in the first region and the fifth region, the electrical resistance of the source region and the drain region of the first transistor can be reduced. Therefore, the first transistor can have a larger on-state current than the second transistor. On the other hand, the second transistor can have a higher saturation property than the first transistor. For example, by applying the first transistor to a transistor that requires a large on-state current and the second transistor to a transistor that requires a high saturation property, a high-performance semiconductor device can be obtained.

[0058] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0059] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0060] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0061] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 1A. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some of the components are also omitted in the top views of the semiconductor device in the following drawings.

[0062] The semiconductor device 10 includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIGS. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film. The transistor 100 and the transistor 200 can be formed on the same substrate by sharing some of the steps.

[0063] Perspective views of the transistor 100 are shown in FIGS. 2A to 2D. FIG. 2B shows a cross section taken along dashed line C1-C2 in FIG. 2A. FIG. 2C shows a perspective view of the insulating layer shown in FIG. 2A, with the outline indicated by a dashed line. Similarly, FIG. 2D shows a perspective view of the insulating layer shown in FIG. 2B, with the outline indicated by a dashed line. FIG. 3A shows an enlarged view of the transistor 100 shown in FIG. 1B, and FIG. 3B shows an enlarged view of the transistor 200.

[0064] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0065] The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other. A region of the semiconductor layer 208 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. A region of the semiconductor layer 208 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0066] A conductive layer 112a and a conductive layer 212a are provided over a substrate 102, an insulating layer 110 is provided over the conductive layer 112a and the conductive layer 212a, and a conductive layer 112b and a conductive layer 212b are provided over the insulating layer 110. The insulating layer 110 has a region in contact with the conductive layer 112a and the conductive layer 112b and sandwiched therebetween, and a region in contact with the conductive layer 212a and the conductive layer 212b and sandwiched therebetween. The conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween. The conductive layer 212a has a region overlapping with the conductive layer 212b with the insulating layer 110 interposed therebetween.

[0067] The insulating layer 110 has an opening 141 that reaches the conductive layer 112a and an opening 241 that reaches the conductive layer 212a. It can be said that the conductive layer 112a is exposed in the opening 141, and the conductive layer 212a is exposed in the opening 241. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. The conductive layer 212b has an opening 243 in a region overlapping with the conductive layer 212a. The opening 243 is provided in a region overlapping with the opening 241. Note that in FIG. 1B and other figures, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, it can be said that the insulating layer 110 and the conductive layer 112b have a first opening that reaches the conductive layer 112a. Similarly, the opening 241 and the opening 243 can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 212b can be said to have a second opening that reaches the conductive layer 212a.

[0068] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 is provided along the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0069] The semiconductor layer 208 is provided to cover the openings 241 and 243. The semiconductor layer 208 is provided along the openings 241 and 243. The semiconductor layer 208 has a region in contact with the top surface of the conductive layer 212a and a region in contact with the side surface of the insulating layer 110 in the opening 241, and a region in contact with the side surface of the conductive layer 212b in the opening 243. Furthermore, the semiconductor layer 208 preferably has a region in contact with the top surface of the conductive layer 212b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface of the insulating layer 110, and the top surface of the conductive layer 212a.

[0070] By configuring the semiconductor layer 108 to be in contact with not only the side surface but also the top surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b is increased, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. Similarly, by configuring the semiconductor layer 208 to be in contact with not only the side surface but also the top surface of the conductive layer 212b, the contact area between the semiconductor layer 208 and the conductive layer 212b is increased, and the contact resistance between the semiconductor layer 208 and the conductive layer 212b can be reduced. This can increase the on-state current of the transistor 100 and the transistor 200. Note that FIG. 1B and other drawings illustrate a structure in which an end of the semiconductor layer 108 is in contact with the top surface of the conductive layer 112b and an end of the semiconductor layer 208 is in contact with the top surface of the conductive layer 212b; however, one embodiment of the present invention is not limited to this. A structure in which the semiconductor layer 108 covers an end of the conductive layer 112b on a side not facing the opening 143 and the semiconductor layer 208 covers an end of the conductive layer 212b on a side not facing the opening 243 can be used. The end of the semiconductor layer 108 and the end of the semiconductor layer 208 can be in contact with the top surface of the insulating layer 110. Alternatively, a structure in which the semiconductor layer 108 is not in contact with the top surface of the conductive layer 112b and is in contact only with the side surface of the conductive layer 112b on the opening 143 side can be used. A structure in which the semiconductor layer 208 is not in contact with the top surface of the conductive layer 212b and is in contact only with the side surface of the conductive layer 212b on the opening 243 side can be used.

[0071] The insulating layer 106 is provided to cover the openings 141 and 143 and the openings 241 and 243. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110.

[0072] The conductive layer 104 and the conductive layer 204 are each provided over the insulating layer 106 and have a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 204 has a region overlapping with the semiconductor layer 208 with the insulating layer 106 interposed therebetween. The conductive layer 104 and the conductive layer 204 have shapes that follow the shape of the top surface of the insulating layer 106.

[0073] In the transistor 100 and the transistor 200, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the electrodes are formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. In other words, the drain current flows in the vertical direction or approximately vertically in the transistor 100 and the transistor 200. Therefore, the transistor according to one embodiment of the present invention can be called a VFET.

[0074] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. The channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, the transistors 100 and 200 having channel lengths shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, the characteristic variations among the plurality of transistors 100 and among the plurality of transistors 200 are also reduced. This stabilizes the operation of the semiconductor device 10, thereby improving its reliability. Furthermore, the reduced characteristic variations among the transistors increase the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be lowered. This reduces the power consumption of the semiconductor device.

[0075] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0076] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. Similarly, the conductive layers 212a, 212b, and 204 can each function as wirings, and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100, the transistor 200, and wirings, the area occupied by these can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0077] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0078] The semiconductor layer 108 has a region 108Da in one part and a region 108Db in the other part. The region 108Da and the region 108Db each contain an impurity element. The region 108Da and the region 108Db each have a higher concentration of the impurity element and a lower electrical resistance (hereinafter also referred to as a low-resistance region) than other regions (e.g., channel formation regions) of the semiconductor layer 108. In the semiconductor layer 108, the channel formation region is located between the region 108Da and the region 108Db.

[0079] 1B, 1C, and 3A show an example in which a region 108Da is formed in a region of the semiconductor layer 108 that is in contact with the top surface of the conductive layer 112a and is located between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 104, and a region 108Db is formed in a region of the semiconductor layer 108 that is in contact with the top surface of the conductive layer 112b. The region in which the region 108Da is formed is not limited thereto, and for example, the region 108Da may be formed in the entire region that is in contact with the top surface of the conductive layer 112a. The region 108Db may also be provided in a region of the semiconductor layer 108 that is in contact with the side surface of the conductive layer 112b. The region 108Db may also be provided in a part of a region of the semiconductor layer 108 that is in contact with the side surface of the insulating layer 110. For example, the impurity element may diffuse due to heat applied when the impurity element is supplied to the semiconductor layer 108 or in a process after the impurity element is supplied. 3A and other cross-sectional views show two regions of the semiconductor layer 108 that contact the upper surface of the conductive layer 112b, but in top view, the regions 108Db are connected into one. By forming the regions 108Db into one connected region, the contact area between the regions 108Db and the conductive layer 112b is increased, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. The semiconductor layer 108 may also be configured to have multiple regions 108Db that are separated from one another.

[0080] The semiconductor layer 208 has a region 208Da in contact with the upper surface of the conductive layer 212a and a region 208Db in contact with the upper surface of the conductive layer 212b. The impurity element concentrations in the regions 208Da and 208Db are lower than the impurity element concentrations in the region 108Da and the region 108Db, respectively. Note that while the cross-sectional views such as FIG. 3B show two regions of the semiconductor layer 208 in contact with the upper surface of the conductive layer 212b, in top view, the regions 208Db are connected as one. By providing the region 208Db as one connected region, the contact area between the region 208Db and the conductive layer 212b is increased, thereby reducing the contact resistance between the semiconductor layer 208 and the conductive layer 212b. Note that the semiconductor layer 208 may also be configured to have multiple regions 208Db that are separated from each other.

[0081] When the impurity element is supplied to the semiconductor layer 108, it is preferable that the impurity element is not supplied to the semiconductor layer 208. For example, it is preferable that a layer functioning as a mask (hereinafter also referred to as a mask layer) is provided over the semiconductor layer 208, and the impurity element is supplied to the semiconductor layer 108 using the mask layer as a mask. The mask layer is preferably provided in at least a region overlapping with the semiconductor layer 208. It is also preferable that the mask layer is not provided in a region overlapping with the semiconductor layer 108. This allows the impurity element to be selectively supplied to the semiconductor layer 108. A resist mask or a hard mask can be used as the mask layer. Furthermore, it is preferable that the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106. By supplying the impurity element to the semiconductor layer 108 through the insulating layer 106, the impurity element can be preferentially supplied to the regions 108Da and 108Db in the semiconductor layer 108. Furthermore, supplying the impurity element through the insulating layer 106 can reduce damage to the semiconductor layer 108 during supply. Specifically, it is preferable to form the insulating layer 106 over the semiconductor layer 108 and the semiconductor layer 208, form a mask layer in a region on the insulating layer 106 that overlaps with the semiconductor layer 208, and supply an impurity element to the semiconductor layer 108 using the mask layer as a mask.

[0082] By including the regions 108Da and 108Db containing impurity elements in the semiconductor layer 108, the electrical resistance of the source region and the drain region of the semiconductor layer 108 can be reduced. Furthermore, the contact resistance between the semiconductor layer 108 and the conductive layer 112a and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. Therefore, the transistor 100 can have a larger on-state current than the transistor 200. Furthermore, by increasing the on-state current, the operating voltage of the transistor 100 can be reduced. Meanwhile, the transistor 200 can have a higher saturation characteristic than the transistor 100. For example, by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation characteristic, a high-performance semiconductor device can be obtained.

[0083] The transistor 100 has a similar structure to the transistor 200, except that the semiconductor layer 108 includes regions 108Da and 108Db containing impurity elements. The semiconductor layer 208 of the transistor 200 corresponds to the semiconductor layer 108 of the transistor 100, the conductive layer 212a corresponds to the conductive layer 112a, the conductive layer 212b corresponds to the conductive layer 112b, the conductive layer 204 corresponds to the conductive layer 104, the opening 241 corresponds to the opening 141, and the opening 243 corresponds to the opening 143.

[0084] The transistor 100 and the transistor 200 can be formed over the same substrate by sharing some of the steps. For example, the conductive layer 112a and the conductive layer 212a can be formed using the same material and in the same step. The conductive layer 112b and the conductive layer 212b can be formed using the same material and in the same step. The semiconductor layer 108 and the semiconductor layer 208 can be formed using the same material and in the same step. The conductive layer 104 and the conductive layer 204 can be formed using the same material and in the same step. Furthermore, the opening 141 and the opening 241 can be formed in the same step. The opening 143 and the opening 243 can be formed in the same step.

[0085] When the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, a part of the insulating layer 106 may also contain the impurity element. For example, a region of the insulating layer 106 that is in contact with the semiconductor layer 108 may contain the impurity element. When the impurity element is supplied using a mask layer, a region of the insulating layer 106 where the mask layer is not provided may contain the impurity element. It is preferable that the regions 108Da and 108Db each have a portion with a higher concentration of the impurity element than the insulating layer 106, because this can further reduce the electrical resistance of the regions 108Da and 108Db.

[0086] The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0087] The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0088] The semiconductor layer 108 and the semiconductor layer 208 can each be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor.

[0089] The semiconductor layer 108 and the semiconductor layer 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The band gap of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0090] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0091] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0092] The insulating layer 110 has a region in contact with the semiconductor layer 108 and a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 and at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110 and the interface characteristics between the semiconductor layer 208 and the insulating layer 110. Specifically, it is preferable that the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208 each contain oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region.

[0093] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that at least a part of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 and at least a part of the region that is in contact with the semiconductor layer 208 release oxygen by heating. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ H) can be reduced.

[0094] The insulating layer 110 preferably has a stacked structure. In Fig. 1B and other drawings, the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0095] The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. As a result, at least a region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region of the transistor 100, and a region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel formation region of the transistor 200. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b.

[0096] 3A and 3B, the semiconductor layer 108 has a region 108M in contact with the side surface of the insulating layer 110b, and the semiconductor layer 208 has a region 208M in contact with the side surface of the insulating layer 110b. The region 108M functions as a channel formation region of the transistor 100, and the region 208M functions as a channel formation region of the transistor 200. The impurity element concentrations in the region 108M and the region 208M are preferably lower than the impurity element concentrations in the region 108Da and lower than the impurity element concentrations in the region 108Db. Note that while the cross-sectional views such as FIG. 3A show two regions of the semiconductor layer 108 in contact with the side surface of the insulating layer 110b, the regions 108M are connected together in top view. Similarly, the regions 208M are connected together. Note that a structure in which the semiconductor layer 108 has a plurality of regions 108M separated from one another and the semiconductor layer 208 has a plurality of regions 208M separated from one another may also be used.

[0097] It is more preferable to use a material that releases oxygen when heated for the insulating layer 110b. When the insulating layer 110b releases oxygen due to heat applied during the manufacturing process of the semiconductor device 10, oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208, particularly to their channel formation regions, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0098] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. Then, the film can be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0099] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, when the insulating layer 110b is formed by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The insulating layer 110b can be formed by a sputtering method in particular. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0100] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a and the conductive layer 212a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b and the conductive layer 212b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0101] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a and the conductive layer 212a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b and the conductive layer 212b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208, reducing oxygen vacancies (V Ｏ ) and V ＯH can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layers 112a, 112b, 212a, and 212b are prevented from being oxidized by oxygen contained in the insulating layer 110b, and an increase in their electrical resistance can be suppressed. Therefore, the transistor 100 and the transistor 200 can have a large on-state current.

[0102] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby preventing the substance from passing through the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0103] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0104] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0105] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208 to be increased, and oxygen deficiency (V Ｏ ) can be effectively reduced.

[0106] As described above, the regions 108Da and 108Db each contain an impurity element, preferably the first element.

[0107] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0108] The first element is not limited to the above elements, and one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements can be used.

[0109] By supplying the first element to the source region and the drain region of the transistor 100 (which may also be referred to as adding or injecting the first element), oxygen vacancies (V Ｏ ) occurs. Then, the oxygen deficiency (V Ｏ ) with hydrogen in it. ＯCarriers are generated by H. This can reduce the electrical resistance of the source region and the drain region. Therefore, the transistor 100 can have a larger on-state current than the transistor 200. On the other hand, the transistor 200 can have a higher saturation property than the transistor 100. For example, by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation property, a high-performance semiconductor device can be obtained.

[0110] When an element that easily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state of being bonded to oxygen. Ｏ ) occurs. When an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state, and is therefore unlikely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device 10, making it possible to maintain low electrical resistance. For this reason, it is preferable to use as the first element an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process. Specifically, preferred first elements include typical nonmetal elements other than hydrogen, typical metal elements, and transition elements (transition metals), and particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0111] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0112] Ion implantation can be suitably used to supply the impurity element. The ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurity element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0113] When boron is used as the first element, the source gas may be, for example, BF ３ When phosphorus is used as the first element, the source gas may be, for example, PH ３ Furthermore, by mass-separating ions generated from these gases and supplying them, ions of specific masses can be supplied to the region 108Da and the region 108Db, which is more preferable.

[0114] In addition to the first element, hydrogen can also be supplied to the regions 108Da and 108Db. The supply of hydrogen can eliminate oxygen deficiency (V Ｏ ) occurs, and oxygen deficiency (V Ｏ ) by entering V Ｏ This is a suitable impurity element because it generates H. By supplying the first element and hydrogen, the electrical resistance of each of the regions 108Da and 108Db can be easily reduced and the electrical resistance can be maintained at a low level.

[0115] When both the first element and hydrogen are supplied, a gas containing the first element and hydrogen (for example, PH ３ Gas and B ２ H ６Alternatively, a mixed gas of a gas containing the first element and a gas containing hydrogen can be used as the source gas. By using a source gas containing the first element and hydrogen, ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity. For example, a source gas containing B ２ H ６ By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using gas, phosphorus and hydrogen can be supplied as impurity elements.

[0116] Each of the regions 108Da and 108Db preferably has a portion with a higher concentration of impurity elements than the region 108M. Also, each of the regions 108Da and 108Db preferably has a portion with a higher concentration of impurity elements than the region 208M, the region 208Da, and the region 208Db.

[0117] The regions 108Da and 108Db each have an impurity element concentration of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5×10, more preferably １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３It is preferable that the impurity element concentration includes a portion where the impurity element concentration is less than or equal to the region 108Da. If the impurity element concentration is low, the electrical resistance of the regions 108Da and 108Db may become high. On the other hand, if the impurity element concentration is high, that is, if a large amount of the impurity element is supplied, the semiconductor layer 108 may be damaged during supply, which may increase the electrical resistance of the regions 108Da and 108Db. Therefore, by setting the impurity element concentration within the above-mentioned range, the electrical resistance of the regions 108Da and 108Db can be reduced, and the transistor 100 can have a large on-state current.

[0118] When the region 108Da contains two or more impurity elements, it is preferable that the concentration of at least one of the impurity elements is in the above range. It is more preferable that the concentration of each impurity element is in the above range. The same applies to the region 108Db.

[0119] When the impurity elements are supplied to the regions 108Da and 108Db, the impurity elements may also be supplied to the channel formation region of the semiconductor layer 108. Alternatively, due to heat or the like applied during the manufacturing process, some of the impurity elements contained in the regions 108Da and 108Db may diffuse into the channel formation region.

[0120] The impurity element concentrations in the regions 108M and 208M, which function as channel formation regions, are preferably low. The impurity element concentrations in the regions 108M and 208M are preferably lower than the impurity element concentrations in the regions 108Da and 108Db, respectively. This prevents the carrier concentration in the channel formation region from increasing. A high carrier concentration in the channel formation region may shift the threshold voltage of the transistor, increasing the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V. For example, in the case of an n-channel transistor, a negative shift in the threshold voltage may increase the cutoff current. By preventing the carrier concentration in the channel formation region from increasing, the threshold voltage shift is prevented, resulting in the transistors 100 and 200 having low cutoff currents. Therefore, a semiconductor device with low power consumption can be obtained.

[0121] The concentration of the impurity element in the region 108M and the concentration of the impurity element in the region 208M are each 1×10 −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ Similarly, the concentration of the impurity element in the region 108M and the concentration of the impurity element in the region 208M are preferably 1×10 times or less of the concentration of the impurity element in the region 108Db. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ This allows the transistor 100 and the transistor 200 to have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0122] The concentration of impurity elements in each region of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA). When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in regions with low impurity element concentrations, quantification may be difficult or the concentration may be below the detection limit.

[0123] For the analysis of the concentration of the impurity element in the insulating layer 106, the description of the analysis of the concentration of the impurity element in the semiconductor layer 108 can be referred to.

[0124] In manufacturing the semiconductor device of one embodiment of the present invention, the source region and the drain region of the semiconductor layer 108 are preferably more easily supplied with an impurity element than the channel formation region. The impurity element is preferably supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. In this case, the amount of the impurity element supplied to a region of the semiconductor layer 108 that is inclined with respect to the top surface of the substrate 102 is smaller than that supplied to a region that is parallel or substantially parallel to the top surface of the substrate 102. That is, the amount of the impurity element supplied to the source region and the drain region of the semiconductor layer 108 is larger than that supplied to the channel formation region. Therefore, the electrical resistance of the source region and the drain region can be preferentially reduced.

[0125] The insulating layer 106 is preferably formed by a method with high coverage because it is provided to cover the openings 141, 143, 241, and 243. The insulating layer 106 is preferably formed by a sputtering method, a PECVD method, or an atomic layer deposition (ALD) method. As the ALD method, a thermal ALD method or a PEALD (Plasma Enhanced ALD) method can be used. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it exhibits high coverage and allows low-temperature film formation.

[0126] 3A shows the thickness Ta of the insulating layer 106 at a portion thereof in contact with the region 108Da, the thickness Tb of the portion thereof in contact with the region 108Db, and the thickness Tc of the portion thereof in contact with the region 108M. The thicknesses Ta, Tb, and Tc are each the thicknesses in a direction perpendicular or substantially perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112a and the top surface of the insulating layer 106. The thickness Tb is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112b and the top surface of the insulating layer 106. The thickness Tc is the shortest distance between the side surface of the semiconductor layer 108 provided along the side surface of the insulating layer 110 on the insulating layer 106 side and the side surface of the insulating layer 106 on the conductive layer 104 side.

[0127] 3A illustrates a structure in which the thicknesses Ta, Tb, and Tc are the same, but one embodiment of the present invention is not limited to this. The thicknesses Ta, Tb, and Tc may be partly or entirely different from each other. The thickness Tc of the region of the insulating layer 106 provided along the side surface of the insulating layer 110 may be thinner than the thicknesses Ta and Tb of the region of the insulating layer 106 provided along the top surface of the conductive layer 112a or 112b. For example, when the insulating layer 106 is formed by a PECVD method or a sputtering method, the thickness Tc may be thinner than both the thicknesses Ta and Tb. Furthermore, when the insulating layer 106 is formed by an ALD method, the thickness Tc can be closer to the thicknesses Ta and Tb. Alternatively, the thickness Tc can be the same as or approximately the same as the thicknesses Ta and Tb.

[0128] As described above, part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and the other part functions as a gate insulating layer for the transistor 200. The thickness Tc of the portion of the insulating layer 106 in contact with the region 108M is preferably 1 nm to 200 nm, more preferably 1 nm to 150 nm, and even more preferably 1 nm to 100 nm. For example, when the channel length is 100 nm to 500 nm, the thickness Tc is preferably 30 nm to 100 nm. For example, when the channel length is 10 nm to 100 nm, the thickness Tc is preferably 1 nm to 50 nm. For example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm. For example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm. Similarly, the thickness of the region of the insulating layer 106 in contact with the region 208M is preferably within the above-described range of thickness Tc. 3B, the thickness of the portion of insulating layer 106 that contacts region 208M is shown as thickness Tc, but the relationship between these thicknesses is not particularly limited. The thickness of the portion that contacts region 208M and thickness Tc may be different.

[0129] Supply of the impurity element to the semiconductor layer 108 will be described. Here, an example will be described in which the impurity element is supplied from a direction perpendicular to the top surface of the substrate 102. Note that the cross-sectional view shown in Figure 3A illustrates a configuration in which the surface of the insulating layer 106 (specifically, the top surface and side surface of the insulating layer 106) is parallel to the top surface and side surface of the semiconductor layer 108, which are surfaces on which the insulating layer 106 is formed.

[0130] As described above, the impurity element is preferably supplied to the semiconductor layer 108 through the insulating layer 106. When the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the impurity element penetrates from the surface of the insulating layer 106, passes through the insulating layer 106, and then reaches the semiconductor layer 108 through the interface between the insulating layer 106 and the semiconductor layer 108. In this case, the thickness of the insulating layer 106 in the direction in which the impurity element is supplied can also be said to be the depth from the surface of the insulating layer 106 to the semiconductor layer 108. Specifically, the thickness Ta can be said to be the depth from the surface of the insulating layer 106 to the region 108Da of the impurity element, and the thickness Tb can be said to be the depth from the surface of the insulating layer 106 to the region 108Db of the impurity element.

[0131] FIG. 3A shows the thickness Td of the insulating layer 106 along the side surface of the insulating layer 110 in a direction perpendicular to the top surface of the substrate 102. For example, the thickness Td can be the thickness of the insulating layer 106 on a line extending from the midpoint between the top and bottom edges of the insulating layer 110b in a direction perpendicular to the top surface of the substrate 102. The thickness Td can also be considered the depth from the surface of the insulating layer 106 to the region 108M where the impurity element reaches. Compared to the thickness Td, the thicknesses Ta and Tb are thinner. As a result, the regions of the semiconductor layer 108 along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b (e.g., regions 108Da and 108Db) receive a larger amount of impurity element than the regions along the side surface of the insulating layer 110 (e.g., region 108M). In this way, the supply of the impurity element to the channel formation region of the semiconductor layer 108 is suppressed, and the electrical resistance of the source and drain regions can be preferentially reduced.

[0132] The thicker the insulating layer 106, the larger the difference between the thickness Ta and the thickness Td and the difference between the thickness Tb and the thickness Td can be. This can suppress the supply of impurity elements to the channel formation region of the semiconductor layer 108, and can preferentially reduce the electrical resistance of the source and drain regions. On the other hand, in order to miniaturize transistors or fabricate transistors with extremely short channel lengths, a smaller thickness Tc is preferable from the viewpoints of improving on-current and suppressing the short channel effect.

[0133] The insulating layer 106 preferably includes an insulating layer containing oxygen. When an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state bonded to oxygen in the insulating layer 106 as in the semiconductor layer 108. When oxygen and the impurity element are bonded and stabilized, oxygen is less likely to be released from the region containing the impurity element even when heat is applied, thereby suppressing oxygen diffusion to other layers. This suppresses oxygen supply from the insulating layer 106 to the regions 108Da and 108Db while efficiently supplying oxygen to the channel formation region. Therefore, oxygen vacancies in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da and 108Db from increasing. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0134] For example, when boron is used as an impurity element, the boron contained in the regions 108Da, 108Db, and the insulating layer 106 may exist in a state of being bonded to oxygen. ２ O ３ In XPS analysis, the spectral peak due to the existence of elemental boron is not observed or the peak intensity is extremely small, almost to the background level.

[0135] Note that a layer to which an impurity element is supplied may be referred to as an implanted layer. For example, when an impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, each of the insulating layer 106 and the semiconductor layer 108 may be referred to as an implanted layer.

[0136] The acceleration energy used to supply the impurity element is preferably set according to the type of impurity element (specifically, the type of ion), the composition, film density, and thickness of the implanted layer. For example, it is preferable to set the acceleration energy so that the concentration of the impurity element is highest at the interface between region 108Da and insulating layer 106, the interface between region 108Db and insulating layer 106, or in the vicinity thereof. Furthermore, if the acceleration energy is too high, the concentration of the impurity element in region 108M will also be high. Therefore, it is preferable to set the acceleration energy so that the concentration of the impurity element in region 108M does not become high.

[0137] The concentration of the impurity element in the depth direction can be simulated using software, for example. Examples of simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. The type of impurity element to be supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy can be used as simulation parameters. When the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the depth to the region 108Da is "Ta", the depth to the region 108Db is "Tb", and the depth to the region 108M is "Td". It is preferable to select an acceleration energy that results in a high concentration of the impurity element in the regions 108Da and 108Db and a low concentration of the impurity element in the region 108M. Furthermore, it is preferable to select an acceleration energy that allows the concentrations of the impurity elements in the regions 108Da, 108Db, and 108M to fall within the aforementioned ranges.

[0138] The regions 108Da and 108Db can each have a configuration including a first element and a second element as an impurity element. The second element is different from the first element. The second element can be one or more of the elements that can be used as the first element. The second element preferably has a larger mass number than the first element. The first element preferably easily bonds with oxygen. For example, boron or phosphorus can be used as the first element, and argon, krypton, or xenon can be used as the second element.

[0139] After the second element is supplied to the semiconductor layer 108, the first element can be supplied to the semiconductor layer 108. When the mass number of the supplied element is large, the number of metal-oxygen bonds broken in the metal oxide contained in the semiconductor layer 108 increases. Furthermore, due to the breaking of the metal-oxygen bonds, oxygen vacancies (V Ｏ ) occurs. By supplying the first element after supplying the second element having a larger mass number to break more bonds between the metal and oxygen, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0140] When the amount of the second element supplied to the channel forming region increases, oxygen vacancies (V Ｏ ) occurs, and V Ｏ There is a risk that H will increase, resulting in an increase in carrier concentration. Therefore, it is preferable that the concentration of the second element in the channel formation region is lower than the concentration of the second element in the region 108Da and lower than the concentration of the second element in the region 108Db. More specifically, it is preferable that the concentration of the second element in the region 108M is lower than the concentration of the second element in the region 108Da and lower than the concentration of the second element in the region 108Db.

[0141] When the second element is supplied to the semiconductor layer 108, it is preferable that the second element is not supplied to the semiconductor layer 208. For example, it is preferable to provide a mask layer in the region overlapping with the semiconductor layer 208 and supply the second element using the mask layer as a mask. This allows the second element to be selectively supplied to the semiconductor layer 108. Furthermore, it is preferable that the second element be supplied to the semiconductor layer 108 via the insulating layer 106. By supplying the second element to the semiconductor layer 108 via the insulating layer 106, the second element can be preferentially supplied to the regions 108Da and 108Db. Furthermore, by supplying the second element via the insulating layer 106, damage to the semiconductor layer 108 during supply can be reduced. Specifically, it is preferable to form the insulating layer 106 on the semiconductor layer 108 and the semiconductor layer 208, form a mask layer on the insulating layer 106 in the region overlapping with the semiconductor layer 208, and supply the first element and the second element to the semiconductor layer 108 using the mask layer as a mask.

[0142] It is more preferable to supply the second element to the semiconductor layer 108 through the insulating layer 106 and then supply the first element to the semiconductor layer 108 through the insulating layer 106. This allows the electrical resistance of the regions 108Da and 108Db to be efficiently reduced. More specifically, the insulating layer 106 is formed on the semiconductor layer 108 and the semiconductor layer 208, and a mask layer is formed on the insulating layer 106 in a region overlapping the semiconductor layer 208. It is then preferable to supply the second element to the semiconductor layer 108 using the mask layer as a mask, and then supply the first element to the semiconductor layer 108. The mask layer used to supply the second element can also be used to supply the first element. This increases productivity. The mask layer can be removed after the first element is supplied. The mask layer used to supply the second element and the mask layer used to supply the first element may be different.

[0143] When the first element and the second element are supplied to the semiconductor layer 108 through the insulating layer 106, a part of the insulating layer 106 may also contain the first element and the second element. For example, a region of the insulating layer 106 that is in contact with the semiconductor layer 108 may contain the first element and the second element. When the first element and the second element are supplied using a mask layer, a region of the insulating layer 106 where the mask layer is not provided may contain the first element and the second element.

[0144] The second element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the substrate 102. The second element can be supplied by the same method as that used to supply the first element. For example, ion implantation can be suitably used to supply the second element. Since the second element has a larger mass number than the first element, it is more preferable that the acceleration energy used to supply the second element be higher than the acceleration energy used to supply the first element. This increases the amount of the second element supplied to the regions 108Da and 108Db, thereby efficiently reducing the electrical resistance of the regions 108Da and 108Db.

[0145] Alternatively, the first element and the second element can be supplied in the same process. For example, a source gas containing the first element and the second element can be used to supply the first element and the second element to the semiconductor layer 108. Alternatively, a mixed gas of a gas containing the first element and a gas containing the second element can be used as the source gas. For example, when the first element is boron and the second element is argon, BF ３ The source gas is not limited to a mixed gas, and a gas containing the first element and the second element can also be used.

[0146] 1B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 cover the openings 241 and 243, but one embodiment of the present invention is not limited to this. A structure can be used in which a step is formed between the insulating layer 110 and the conductive layer 112b and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, a structure can be used in which a step is formed between the insulating layer 110 and the conductive layer 212b and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0147] [Semiconductor Layer 108, Semiconductor Layer 208] Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0148] The semiconductor layer 108 and the semiconductor layer 208 may be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al— Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0149] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0150] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0151] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0152] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0153] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0154] The electrical characteristics and reliability of the transistor 100 and the transistor 200 vary depending on the composition of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0155] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0156] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0157] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0158] By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or the field-effect mobility of the transistor 100 and the transistor 200 can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0159] Here, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, the unevenness of the surfaces of the semiconductor layers 108 and 208 may increase. This may increase the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layers 108 and 208, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layers 108 and 208 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0160] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0161] A metal oxide that does not contain element M can be applied to the semiconductor layer 108 and the semiconductor layer 208. When the metal oxide is an In—Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, the atomic ratio of In is more preferably equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0162] The compositions of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis can be performed by combining a plurality of these techniques. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0163] The sputtering method or the ALD method can be suitably used for forming the metal oxide. As the ALD method, the thermal ALD method or the PEALD method can be used. When the metal oxide is formed by the sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target. The PECVD method can also be used for forming the metal oxide.

[0164] It is preferable to use a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0165] The semiconductor layer 108 and the semiconductor layer 208 are preferably formed using a CAAC-OS or an nc-OS.

[0166] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are aligned in the normal direction to the surface where the semiconductor layer 108 and the semiconductor layer 208 are preferably formed. For example, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b, and layered crystals parallel to or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the side surface of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed, in the opening 141. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel to or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current. The same applies to the semiconductor layer 208.

[0167] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0168] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total flow rate of film formation gas (hereinafter also referred to as oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0169] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0170] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0171] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration in the channel formation region is 1×10 １８ cm −３Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0172] A region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and a region of the semiconductor layer 208 in contact with the conductive layer 112b functions as the other. A region of the semiconductor layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and a region of the semiconductor layer 208 in contact with the conductive layer 212b functions as the other. The source and drain regions have lower electrical resistance than the channel formation region. The source and drain regions can also be referred to as regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.

[0173] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0174] The semiconductor layer 108 and the semiconductor layer 208 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0175] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0176] The semiconductor layer 108 and the semiconductor layer 208 can have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 are the same or approximately the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0177] When the semiconductor layer 108 and the semiconductor layer 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, and therefore the crystallinity of the second metal oxide layer may be increased. Furthermore, by performing heat treatment after the second metal oxide layer is formed, the crystallinity of the first metal oxide layer can be increased. This heat treatment can also be called a crystallization treatment.

[0178] A first metal oxide layer is formed, and then a second metal oxide layer having higher crystallinity than the first layer is formed. For example, ALD can be suitably used to form the first metal oxide layer, and sputtering can be suitably used to form the second metal oxide layer. By performing heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. In this case, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to serve as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

[0179] A three-layer structure having a third metal oxide layer on the second metal oxide layer can be formed. For example, the first metal oxide layer and the third metal oxide layer can be formed by an ALD method, and the second metal oxide layer can be formed by a sputtering method. Heat treatment after the formation of the third metal oxide layer can increase the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer. In this case, crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer and the third metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. When the second metal oxide layer has a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

[0180] By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. This allows for a highly reliable transistor to be realized. Note that the thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the semiconductor layer is formed. A metal oxide layer with increased crystallinity in this manner can be called an axial growth CAAC (AG CAAC). Note that, in addition to crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the semiconductor layer is formed.

[0181] The temperature of the heat treatment is preferably 100°C or higher and 800°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 550°C or lower. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C or higher and 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by thermal conduction or thermal radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0182] [Insulating Layer 110] As described above, the insulating layer 110 preferably has a stacked-layer structure. The insulating layer 110b has a function of supplying oxygen to a channel formation region. The insulating layers 110a and 110c function as barrier films.

[0183] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. As shown in FIG. 4B , the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0184] If the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, which may reduce the amount of oxygen supplied to the channel formation region. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, which may increase the amount of impurities diffusing into the channel formation region. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce the thickness T110a. In addition, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112a. The thickness T110a is not limited to the above range.

[0185] The thickness T110a can be made thicker than the thickness T110c of the insulating layer 110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, the distance from the source region or the drain region to the gate electrode can be made more uniform by making the thickness T110a thicker. The same applies to the semiconductor layer 208. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.

[0186] The thickness T110c is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 3 nm to 50 nm, even more preferably 3 nm to 30 nm, even more preferably 3 nm to 20 nm, even more preferably 3 nm to 10 nm, even more preferably 5 nm to 10 nm. As shown in FIG. 4B , the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0187] The thickness T110c is preferably a value that at least functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness T110a. If the thickness T110c is thick, the amount of impurities released from the insulating layer 110c increases, which may result in a larger amount of impurities diffusing into the channel formation region. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b via the insulating layer 110c, which may result in a reduced amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce H. Furthermore, it is possible to prevent the conductive layer 112b from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112b. Note that the thickness T110c is not limited to the above range.

[0188] At least one of the regions of the semiconductor layer 108 in contact with the insulating layer 110a and the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region can function as a buffer region for alleviating the drain electric field. Note that the low-resistance region can also function as a source region or a drain region. The same applies to the semiconductor layer 208.

[0189] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided. The same applies to the semiconductor layer 208.

[0190] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0191] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0192] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0193] [Opening 141, Opening 143, Opening 241, Opening 243] The top surface shapes of openings 141, 143, 241, and 243 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141, 143, 241, and 243 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0194] In this specification and the like, the top surface shape of opening 141 refers to the shape of the top surface end portion of insulating layer 110 on the opening 141 side. The top surface shape of opening 143 refers to the shape of the bottom surface end portion of conductive layer 112b on the opening 143 side. The top surface shape of opening 241 refers to the shape of the top surface end portion of insulating layer 110 on the opening 241 side. In addition, the top surface shape of opening 243 refers to the shape of the bottom surface end portion of conductive layer 212b on the opening 243 side.

[0195] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. The top shapes of the openings 141 and 143 may not be identical to each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric. The same applies to the openings 241 and 243. For the opening 241, see the description of the opening 141, and for the opening 243, see the description of the opening 143.

[0196] The channel lengths and channel widths of the transistors 100 and 200 will be described with reference to FIGS. 4A to 4C.

[0197] In FIG. 4B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ100 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0198] 4C , the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200 of the transistor 200 corresponds to the length of the side surface of the insulating layer 110b on the opening 241 side in a cross-sectional view. In other words, the channel length L200 is determined by the thickness T110b and the angle θ200 formed between the side surface of the insulating layer 110b on the opening 241 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a).

[0199] When the angle θ200 is the same as or approximately the same as the angle θ100, the channel length L200 is the same as or approximately the same as the channel length L100. For example, by forming the opening 141 and the opening 241 in the same process, the angles θ100 and θ200 can be made the same as or approximately the same. Note that the angles θ100 and θ200 can be configured to be different from each other. For example, by forming the opening 141 and the opening 241 in different processes and making the angles θ100 and θ200 different from each other, the channel lengths L100 and L200 can be made different from each other. For example, by reducing the angle θ200, the channel length L200 becomes longer, thereby further improving the saturation of the transistor 200.

[0200] The channel length L100 and the channel length L200 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0201] By shortening the channel lengths L100 and L200, the on-state current of the transistor 100 and the transistor 200 can be increased. By using the transistor 100 and the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0202] By adjusting the thickness T110b, the angle θ100, and the angle θ200, the channel length L100 and the channel length L200 can be controlled.

[0203] The thickness T110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b may be appropriately set to obtain the desired channel length L100 and channel length L200. As shown in FIG. 4B , the thickness T110b may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0204] The side surface of the insulating layer 110 on the opening 141 side and the side surface on the opening 241 side are preferably tapered. The angles θ100 and θ200 are preferably each less than 90 degrees. By reducing the angles θ100 and θ200, the coverage of layers formed on the insulating layer 110 (e.g., the semiconductor layer 108 and the semiconductor layer 208) can be improved. Furthermore, the smaller the angle θ100, the longer the channel length L100 can be, and the larger the angle θ100, the shorter the channel length L100 can be. The same applies to the angle θ200 and the channel length L200.

[0205] The angles θ100 and θ200 can each be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angles θ100 and θ200 can also each be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angles θ100 and θ200 can be set appropriately so as to obtain the desired channel lengths L100 and L200.

[0206] When the angle θ100 is less than 90 degrees, the larger the angle θ100, the larger the difference between the thickness Ta and the thickness Td, and the difference between the thickness Tb and the thickness Td. Therefore, the supply of impurity elements to the region 108M is suppressed, and the impurity elements are preferentially supplied to the regions 108Da and 108Db. This allows the electrical resistance of the source region and the drain region of the semiconductor layer 108 to be efficiently reduced.

[0207] 4B and 4C , the angles θ100 and θ200 are each shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. As shown in FIGS. 5A and 5B , for example, the angles θ100 and θ200 can be set to 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened.

[0208] In a configuration in which the angle θ100 is 90 degrees, when an impurity element is supplied through the insulating layer 106, the impurity element must pass through the insulating layer 106, the region of the semiconductor layer 108 that contacts the side surface of the conductive layer 112b, and the region that contacts the side surface of the insulating layer 110c before reaching the region 108M. Therefore, the depth in the region 108M is deeper than the depth in the regions 108Da and 108Db. Therefore, the concentration of the impurity element in the region 108M is lower than the concentration in the regions 108Da and 108Db. Note that the higher the film density of the material used for the semiconductor layer 108, the higher the stopping power in ion implantation, and the lower the amount of impurity element reaching the channel formation region. For example, if the film density of the semiconductor layer 108 is higher than that of the insulating layer 106, the amount of impurity element supplied to the semiconductor layer 108 will be lower even at the same depth. Furthermore, because the stopping power in ion implantation varies depending on the type of element, the amount of impurity element supplied also varies depending on the composition of the implanted layer.

[0209] 1B and the like show a configuration in which the side surface of the insulating layer 110 on the opening 141 side and the side surface of the opening 241 side are linear in cross section, but one embodiment of the present invention is not limited to this. In cross section, the side surface of the insulating layer 110 on the opening 141 side and the side surface of the opening 241 side may be curved, or the side surface may have both linear and curved regions.

[0210] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view. The same applies to the conductive layer 212b, the opening 241, and the opening 243.

[0211] 4A to 4C , the width D141 of the opening 141 and the width D241 of the opening 241 are indicated by double-headed arrows with dashed double-dashed lines. FIG. 4A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the perimeter of the circle. That is, the channel width W100 is π×D141. Similarly, when the top surface shape of the opening 241 is circular, the channel width W200 of the transistor 200 is π×D241. In this way, when the top surface shapes of the openings 141 and 241 are circular, the transistors 100 and 200 can be realized with smaller channel widths than those with other shapes.

[0212] As shown in FIG. 4A and other figures, when the top surface shape and size of the opening 241 are the same as or approximately the same as those of the opening 141, the channel width W200 is the same as or approximately the same as the channel width W100. The channel widths W100 and W200 can be made different from each other by making the perimeters of the openings 141 and 241 different from each other. One or both of the top surface shape and size of the opening 241 can be made different from one or both of the top surface shape and size of the opening 141. For example, the top surface shapes of the openings 141 and 241 can be circular, and the diameters of these circles (i.e., widths D141 and D241) can be made different from each other, thereby making the channel widths W100 and W200 different from each other. For example, increasing the channel width W100 can increase the on-current of the transistor 100. The channel widths W100 and W200 can be made different from each other depending on the on-current required for the transistor.

[0213] The widths D141 and D241 may vary in the depth direction. For example, the widths D141 and D241 may be the average values ​​of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, and the diameters at the midpoints between these. Alternatively, the widths D141 and D241 may be any of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, or the diameters at the midpoints between these.

[0214] When the openings 141 and 241 are formed using photolithography, the widths D141 and D241 are equal to or greater than the minimum exposure dimension of the exposure device. The widths D141 and D241 may be, for example, equal to or greater than 20 nm, equal to or greater than 50 nm, equal to or greater than 100 nm, equal to or greater than 200 nm, equal to or greater than 300 nm, equal to or greater than 400 nm, or equal to or greater than 500 nm, and may be less than 5 μm, equal to or less than 4.5 μm, equal to or less than 4 μm, equal to or less than 3.5 μm, equal to or less than 3 μm, equal to or less than 2.5 μm, equal to or less than 2 μm, equal to or less than 1.5 μm, or equal to or less than 1 μm.

[0215] Note that although the structure in which the region 108M and the region 208M each function as a channel formation region has been described as an example here, one embodiment of the present invention is not limited to this. A region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. A region in contact with the insulating layer 110c may also function as a channel formation region. The same applies to the semiconductor layer 208.

[0216] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 104, Conductive Layer 212a, Conductive Layer 212b, and Conductive Layer 204] The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the aforementioned metals. The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred due to its excellent mass productivity.

[0217] A conductive metal oxide (also referred to as an oxide conductor) can be used for each of the conductive layers 112a, 112b, 104, 212a, 212b, and 204. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0218] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0219] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0220] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may also be applied to each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0221] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can be formed using the same material, or at least one of them can be formed using a different material.

[0222] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108, and the conductive layer 212a and the conductive layer 212b each have a region in contact with the semiconductor layer 208. When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, or the conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer and the semiconductor layer, preventing electrical conduction therebetween. Therefore, for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0223] For the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108. Similarly, when the conductive layer 212a or the conductive layer 212b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 208.

[0224] The conductive layer 112 a, the conductive layer 112 b, the conductive layer 212 a, and the conductive layer 212 b can each be formed using any of the above-described oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0225] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 and the conductive layer 204 can each be made of the nitride conductors described above.

[0226] 6A to 7B are cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, refer to FIG. 1A. Each of FIGS. 6A to 7B is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0227] 1B and the like in that the conductive layer 112a has a stacked structure, and the transistor 200A differs from the transistor 200 in that the conductive layer 212a has a stacked structure.

[0228] 6A and 6B show a configuration in which the conductive layer 112a has a two-layer structure of a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1, and the conductive layer 212a has a two-layer structure of a conductive layer 212a_1 and a conductive layer 112a_2 over the conductive layer 212a_1.

[0229] For the conductive layer 112a_2 having a region in contact with the semiconductor layer 108, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112a_2, the description of the conductive layer 112a can be referred to.

[0230] The conductive layer 112a_1 does not have a region in contact with the semiconductor layer 108, and therefore the material used is not particularly limited. For example, the conductive layer 112a_1 is preferably made of a material having lower electrical resistivity than the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and copper or tungsten can be preferably used for the conductive layer 112a_1.

[0231] 6A, the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_1. For example, the conductive layer 112a can be formed by forming a first film to be the conductive layer 112a_1 and a second film to be the conductive layer 112a_2, and then processing the first film and the second film. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0232] The end of the conductive layer 112a_2 may not be aligned with the end of the conductive layer 112a_1. As shown in FIG. 6B , the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1. The conductive layer 112a_2 has a region in contact with the top surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion protruding beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 may be formed, a film to become the conductive layer 112a_2 may be formed on the conductive layer 112a_1, and the film may be processed to form the conductive layer 112a_2. By making the conductive layer 112a_2 protrude beyond the end of the conductive layer 112a_1, the step of the formation surface of a layer (e.g., the insulating layer 110) formed on the conductive layer 112a is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0233] 6A and 6B, the layers constituting the conductive layer 112a are shown to have the same or approximately the same thickness, but this is not limited to this embodiment of the present invention. Some or all of the layers constituting the conductive layer 112a may have different thicknesses. For example, it is more preferable to make the layer using a material with low electrical resistivity thicker than the other layers, which can reduce the electrical resistance of the conductive layer 112a. Specifically, a material with lower electrical resistivity than the conductive layer 112a_2 can be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 can be made thicker than the thickness of the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a.

[0234] The conductive layer 212a_1 can be formed using the same material and in the same process as the conductive layer 112a_1, and the conductive layer 212a_2 can be formed using the same material and in the same process as the conductive layer 112a_2. For the conductive layer 212a_1 and the conductive layer 212a_2, the description of the conductive layer 112a_1 and the conductive layer 112a_2 can be referred to.

[0235] 7A and 7B show a structure in which the conductive layer 112a has a three-layer structure including a conductive layer 112a_3, a conductive layer 112a_1 over the conductive layer 112a_3, and a conductive layer 112a_2 over the conductive layer 112a_1.

[0236] 7A , the end portion of the conductive layer 112a_1 can be in contact with the top surface of the conductive layer 112a_3. The conductive layer 112a_2 has regions in contact with the top surface and side surface of the conductive layer 112a_1 and the top surface of the conductive layer 112a_3. That is, it can be said that the conductive layers 112a_2 and 112a_3 each have portions that protrude beyond the end portion of the conductive layer 112a_1. It can also be said that the top surface, side surface, and bottom surface of the conductive layer 112a_1 are surrounded by the conductive layers 112a_2 and 112a_3. The conductive layer 112a_3 is preferably made of a material that has high adhesion to the surface on which the conductive layer 112a_3 is to be formed (here, the surface of the substrate 102).

[0237] As described above, the conductive layer 112a_1 is preferably formed using a material with low electrical resistivity. However, depending on the material, adhesion between the conductive layer 112a_1 and a surface on which the conductive layer 112a_1 is to be formed (e.g., the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112a_3 that has higher adhesion to the surface on which the conductive layer 112a_1 is to be formed than the conductive layer 112a_1, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112a_3 is preferably a thickness that effectively increases the adhesion of the conductive layer 112a to the surface on which the conductive layer 112a is to be formed, and can be thinner than the thicknesses of the conductive layer 112a_1 and the conductive layer 112a_2. Reducing the thickness of the conductive layer 112a_3 can reduce manufacturing costs.

[0238] For example, it is preferable to use In—Sn—Si oxide (ITSO) for the conductive layer 112a_3, copper for the conductive layer 112a_1, and In—Sn—Si oxide (ITSO) for the conductive layer 112a_2. When a glass substrate is used as the substrate 102, adhesion between the glass substrate and an ITSO film is higher than adhesion between a glass substrate and a copper film. Furthermore, using the same material for the conductive layers 112a_2 and 112a_3 facilitates processing when the conductive layers 112a_2 and 112a_3 are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0239] As shown in FIG. 7A , the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_3. For example, a first film to be the conductive layer 112a_3 is formed, a conductive layer 112a_1 is formed on the first film, and a second film to be the conductive layer 112a_2 is formed on the first film and the conductive layer 112a_1. Then, by processing the first film and the second film, the conductive layer 112a can be formed, including the conductive layer 112a_3, the conductive layer 112a_1, and the conductive layer 112a_2. Processing the first film and the second film in the same process can reduce manufacturing costs. Alternatively, as shown in FIG. 7B , the edge of the conductive layer 112a_1 can be aligned or substantially aligned with the edge of the conductive layer 112a_3.

[0240] The conductive layer 212a_3 can be formed using the same material and in the same process as the conductive layer 112a_3. For the conductive layer 212a_3, the description of the conductive layer 112a_3 can be referred to.

[0241] Although the conductive layer 112a and the conductive layer 212a each have a stacked structure of two or three layers in this example, one embodiment of the present invention is not limited to this. The conductive layer 112a and the conductive layer 212a may also have a stacked structure of four or more layers.

[0242] Note that the structures of the conductive layers 112a and 212a shown in FIGS. 6A to 7B can also be applied to other structure examples.

[0243] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0244] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0245] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0246] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0247] 8 is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 8 is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0248] The semiconductor device 10B includes a transistor 100B, a transistor 200B, and an insulating layer 110. The transistors 100B and 200B are different from the transistors 100 and 200 shown in FIG. 1B and the like mainly in that the insulating layer 106 has a stacked-layer structure. FIG. 8 shows a configuration in which the insulating layer 106 has a two-layer structure including an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0249] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer (the insulating layer 106a here) on the semiconductor layer 108 and the semiconductor layer 208 side preferably contains oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0250] It is preferable to use a material that is difficult for substances (e.g., atoms, molecules, and ions) to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100B and the transistor 200B from diffusing into the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ ) can be suppressed. In addition, it is possible to suppress an increase in the electrical resistance of the conductive layer 104 and the conductive layer 204 due to oxidation of the conductive layer 104 and the conductive layer 204 by oxygen contained in the semiconductor layer 108 and the semiconductor layer 208. As a result, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of an oxide and an oxynitride can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0251] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b.

[0252] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0253] The configuration of the insulating layer 106 shown in FIG. 8 can also be applied to other configuration examples.

[0254] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0255] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0256] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0257] 9A shows a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. For a top view of a semiconductor device 10B, see FIG. 1A. FIG. 9A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0258] The semiconductor device 10C includes a transistor 100C, a transistor 200C, and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0259] FIG. 9B shows an enlarged view of the transistor 100C shown in FIG. 9A , and FIG. 9C shows an enlarged view of the transistor 200C. The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of the same materials as those listed for the insulating layer 110a and the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of, for example, silicon nitride or silicon nitride oxide. The insulating layer 110d and the insulating layer 110e can be made of the same material, or different materials.

[0260] The insulating layer 110d is provided between the insulating layer 110a and the conductive layer 112a and the conductive layer 212a. The insulating layer 110d is provided so as to cover the conductive layer 112a and the conductive layer 212a. The insulating layer 110d has regions in contact with the top surface and side surface of the conductive layer 112a, the top surface and side surface of the conductive layer 212a, the top surface of the substrate 102, the side surface of the semiconductor layer 108, and the side surface of the semiconductor layer 208.

[0261] The insulating layer 110e is provided between the insulating layer 110c and the conductive layer 112b and the conductive layer 212b. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the bottom surface of the conductive layer 212b, the bottom surface of the insulating layer 106, the side surface of the semiconductor layer 108, and the side surface of the semiconductor layer 208.

[0262] It is more preferable that the insulating layer 110d and the insulating layer 110e are made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208. As a result, a region of the semiconductor layer 108 in contact with the insulating layer 110d, a region of the semiconductor layer 108 in contact with the insulating layer 110e, a region of the semiconductor layer 208 in contact with the insulating layer 110d, and a region of the semiconductor layer 208 in contact with the insulating layer 110e can each be a low-resistance region. The semiconductor layer 108 can have low-resistance regions between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region, and between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. Similarly, the semiconductor layer 208 may have low-resistance regions between a region in contact with the conductive layer 212a (one of the source region and the drain region) and the channel formation region, and between a region in contact with the conductive layer 212b (the other of the source region and the drain region) and the channel formation region. The low-resistance regions can function as buffer regions for reducing the drain electric field. Note that these low-resistance regions may function as source regions or drain regions.

[0263] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and thus reduces transistor degradation. For example, in the transistor 100C, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and thus reduces transistor degradation. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which suppresses the generation of hot carriers and thus reduces transistor degradation. The same applies to the transistor 200C.

[0264] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region of the semiconductor layer 108 to the gate electrode and the distance from the drain region to the gate electrode can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform. The same applies to the semiconductor layer 208.

[0265] The insulating layer 110a preferably releases a small amount of impurities and is less likely to penetrate the insulating layer 110a. This can prevent impurities from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 110a and the insulating layer 110b. Similarly, the insulating layer 110c preferably releases a small amount of impurities and is less likely to penetrate the insulating layer 110c. This can prevent impurities from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 110c and the insulating layer 110b. This can provide a transistor with good electrical characteristics and high reliability.

[0266] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is more preferable that the impurities released from the insulating layer 110d and the insulating layer 110e contain hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the regions of the semiconductor layer 108 and the semiconductor layer 208 that are in contact with the insulating layer 110d and the insulating layer 110e, thereby reducing the electrical resistance.

[0267] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0268] The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 110d and the insulating layer 110a. Specifically, the deposition conditions for the insulating layer 110d and the insulating layer 110a can be varied by varying one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density for the insulating layer 110d lower than the deposition power density for the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0269] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are formed by PECVD for the insulating layer 110d and the insulating layer 110a, respectively, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under conditions with a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased. For example, the insulating layer 110d can be formed using ammonia gas, and the insulating layer 110a can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form insulating layer 110a can be said to be zero, and the ammonia flow ratio of the deposition gas used to form insulating layer 110d can be said to be higher than the ammonia flow ratio of the deposition gas used to form insulating layer 110a.

[0270] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0271] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0272] Although the insulating layer 110 has a five-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a two-layer, three-layer, four-layer, or six or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0273] The configuration of the insulating layer 110 shown in Configuration Example 1-2 can also be applied to other configuration examples.

[0274] 10A shows a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, see FIG. 1A. FIG. 10A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0275] The semiconductor device 10D includes a transistor 100D, a transistor 200D, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the semiconductor device 10D includes the insulating layer 109 between the conductive layer 112a and the conductive layer 212a and the substrate 102.

[0276] An enlarged view of the transistor 100D shown in FIG. 10A is shown in FIG. 10B, and an enlarged view of the transistor 200D is shown in FIG. An insulating layer 109 is provided over a substrate 102, conductive layers 112a and 212a are provided over the insulating layer 109, and an insulating layer 110 is provided over the conductive layer 112a and the conductive layer 212a. The insulating layer 109 has regions in contact with the bottom surface of the conductive layer 112a, the bottom surface of the conductive layer 212a, and the bottom surface of the insulating layer 110. The conductive layer 112a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The conductive layer 212a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The insulating layer 110 has regions in contact with the top and side surfaces of the conductive layer 112a, the top and side surfaces of the conductive layer 212a, the top surface of the insulating layer 109, the side surfaces of the semiconductor layer 108, the bottom surface of the conductive layer 112b, the bottom surface of the conductive layer 212b, and the bottom surface of the insulating layer 106.

[0277] The insulating layer 109 is preferably made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208. The insulating layer 109 can be made of the same material as can be used for the insulating layer 110d and the insulating layer 110e. For example, the insulating layer 109 can be made of silicon nitride or silicon nitride oxide.

[0278] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a in contact with the insulating layer 109 and a region of the conductive layer 212a in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a diffuse into a region of the semiconductor layer 108 in contact with the conductive layer 112a, and the impurities diffused into the conductive layer 212a diffuse into a region of the semiconductor layer 208 in contact with the conductive layer 212a. This makes it possible to reduce the electrical resistance of the region of the semiconductor layer 108 in contact with the conductive layer 112a and the region of the semiconductor layer 208 in contact with the conductive layer 212a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be provided.

[0279] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the impurities released from the insulating layer 109 preferably contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, thereby reducing the electrical resistance of one of the source and drain regions. The same applies to the semiconductor layer 208.

[0280] The insulating layer 109 is preferably made of a material that emits impurities that reduce the electrical resistance of the conductive layer 112a and the conductive layer 212a. This can reduce the electrical resistance of the conductive layer 112a and the conductive layer 212a. For example, when a metal oxide is used for the conductive layer 112a and the conductive layer 212a, the impurity preferably contains hydrogen. This increases the carrier concentration of the conductive layer 112a and the conductive layer 212a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a and the conductive layer 212a can each function as wirings, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a and the conductive layer 212a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208.

[0281] The materials that can be used for the conductive layer 112a and the conductive layer 212a are as described above. Note that the conductive layer 112a and the conductive layer 212a preferably easily transmit impurities. The conductive layer 112a and the conductive layer 212a preferably do not easily adsorb impurities.

[0282] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109, the top surface and side surfaces of the conductive layer 112a, and the top surface and side surfaces of the conductive layer 212a. This can suppress impurities contained in the insulating layer 109, the conductive layer 112a, and the conductive layer 212a from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 110b.

[0283] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0284] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided. The same applies to the semiconductor layer 208.

[0285] 10A and other drawings show the insulating layer 110 having a four-layer structure of insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a three-layer structure of insulating layers 110a, 110b, and 110c. Alternatively, the insulating layer 110 can have a structure including insulating layers 110a, 110b, 110c, 110d, and 110e.

[0286] As shown in FIG. 11A , the insulating layer 109a under the conductive layer 112a and the insulating layer 109b under the conductive layer 212a can be provided separately. The insulating layer 110 has a region in contact with the side surface of the insulating layer 109a and a region in contact with the side surface of the insulating layer 109b. The insulating layer 109a may have an end portion aligned or substantially aligned with an end portion of the conductive layer 112a, and the insulating layer 109b may have an end portion aligned or substantially aligned with an end portion of the conductive layer 212a. For example, an insulating film to be the insulating layer 109a and the insulating layer 109b and a conductive film to be the conductive layer 112a and the conductive layer 212a may be formed and processed to form the insulating layer 109a and the insulating layer 109b, as well as the conductive layer 112a and the conductive layer 212a. Processing the insulating film and the conductive film in the same process can reduce manufacturing costs.

[0287] Alternatively, the end of the insulating layer 109a may not be aligned with the end of the conductive layer 112a, and the end of the insulating layer 109b may not be aligned with the end of the conductive layer 212a. As shown in FIG. 11B , the insulating layer 109a may have a portion protruding beyond the end of the conductive layer 112a, and the insulating layer 109b may have a portion protruding beyond the end of the conductive layer 212a. The end of the conductive layer 112a contacts the top surface of the insulating layer 109a, and the end of the conductive layer 212a contacts the top surface of the insulating layer 109b. This structure reduces the step on the formation surface of the conductive layer 112a and the insulating layer 109a, and a layer (e.g., the insulating layer 110) formed on the conductive layer 212a and the insulating layer 109b, thereby improving the coverage of the layer. This prevents defects such as discontinuities or voids in the layer.

[0288] The configuration of the insulating layer 109 shown in Configuration Example 1-3 can also be applied to other configuration examples.

[0289] 12A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, see FIG. 1A. FIG. 12A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0290] The semiconductor device 10E includes a transistor 100E, a transistor 200E, and an insulating layer 110. The transistor 100E differs mainly from the transistor 100 shown in FIG. 1B and the like in that the semiconductor layer 108 has a stacked structure, and the transistor 200E differs mainly from the transistor 200 in that the semiconductor layer 208 has a stacked structure.

[0291] Fig. 12B shows an enlarged view of the transistor 100E shown in Fig. 12A, and Fig. 12C shows an enlarged view of the transistor 200E. Fig. 12A to Fig. 12C show a configuration in which the semiconductor layer 108 has a three-layer structure of a semiconductor layer 108a, a semiconductor layer 108b on the semiconductor layer 108a, and a semiconductor layer 108c on the semiconductor layer 108b, and a configuration in which the semiconductor layer 208 has a three-layer structure of a semiconductor layer 208a, a semiconductor layer 208b on the semiconductor layer 208a, and a semiconductor layer 208c on the semiconductor layer 208b.

[0292] The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c can be formed using the materials listed for the semiconductor layer 108 and the semiconductor layer 208. The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c each preferably contains a metal oxide exhibiting semiconductor properties.

[0293] The semiconductor layers 108a and 208a can be formed using the same material and in the same process. The semiconductor layers 108b and 208b can be formed using the same material and in the same process. The semiconductor layers 108c and 208c can be formed using the same material and in the same process.

[0294] The band gap of each of the first metal oxide included in the semiconductor layer 108a and the semiconductor layer 208a, the second metal oxide included in the semiconductor layer 108b and the semiconductor layer 208b, and the third metal oxide included in the semiconductor layer 108c and the semiconductor layer 208c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0295] The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide. The semiconductor layer 108b is sandwiched between the semiconductor layers 108a and 108c, which have larger band gaps than the semiconductor layer 108b, to form a buried channel. As a result, the semiconductor layer 108b serves as the main current path in the semiconductor layer 108. Similarly, the semiconductor layer 208b is sandwiched between the semiconductor layers 208a and 208c to form a buried channel. As a result, the semiconductor layer 208b serves as the main current path in the semiconductor layer 208.

[0296] In the following, the semiconductor layer 108 including the semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c will be described as an example, and a description of the semiconductor layer 208 may be omitted. Note that with regard to the semiconductor layer 208, descriptions of the semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c can be read as the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c.

[0297] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0298] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0299] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0300] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141, and components of the conductive layers 112a and 112b that are attached to the side surfaces of the insulating layer 110 when the opening 141 is formed. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0301] Damage may occur to the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity. By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap states.

[0302] By sandwiching the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, between the semiconductor layer 108a and the semiconductor layer 108c, it is possible to reduce trap levels at the interface of the semiconductor layer 108b and in the vicinity of the interface. This makes it possible to provide a transistor with high on-state current and high reliability. Therefore, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0303] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0304] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0305] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide may be the same as or partially or entirely different from one another. When one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as or partially or entirely different from the elements M contained in the other metal oxides.

[0306] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0307] The second metal oxide may be free of element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio; the second metal oxide may have an atomic ratio of In:Zn=4:1 or a similar ratio; and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:1 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:4 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition.

[0308] 13A shows an enlarged view of the side surfaces of the semiconductor layer 108 and the insulating layer 110 and their vicinity, and FIG. 13B shows an enlarged view of the side surfaces of the semiconductor layer 208 and the insulating layer 110 and their vicinity. In FIG. 13A, the thickness T108a of the semiconductor layer 108a, the thickness T108b of the semiconductor layer 108b, and the thickness T108c of the semiconductor layer 108c are each indicated by solid arrows, and in FIG. 13B, the thickness T208a of the semiconductor layer 208a, the thickness T208b of the semiconductor layer 208b, and the thickness T208c of the semiconductor layer 208c are each indicated by solid arrows. Here, the thickness of the semiconductor layer 108 is defined as the shortest distance between the insulating layer 110b and the insulating layer 106 in a region in contact with the semiconductor layer 108 in a cross-sectional view, and the thickness of the semiconductor layer 208 is defined as the shortest distance between the insulating layer 110b and the insulating layer 106 in a region in contact with the semiconductor layer 208. The thickness of each of the semiconductor layers 108 and 208 can be, for example, the thickness of each of the semiconductor layers 108 and 208 at the midpoint between the height of the upper surface and the height of the lower surface of the insulating layer 110.

[0309] As described above, the semiconductor layers 208a, 208b, and 208c can be formed in the same process as the semiconductor layers 108a, 108b, and 108c. Furthermore, when the angles θ100 and θ200 (see FIGS. 4B and 4C ) of the insulating layer 110, which is the surface on which the semiconductor layers 108 and 208 are formed, are the same or approximately the same, the thicknesses T108a and T208a are the same or approximately the same, the thicknesses T108b and T208b are the same or approximately the same, and the thicknesses T108c and T208c are the same or approximately the same. Note that the thicknesses T108a and T208a may be different from each other. The same applies to the thicknesses T108b and T208b, and the thicknesses T108c and T208c.

[0310] The following description will be given taking as an example the thickness of each layer of the semiconductor layer 108. Note that with regard to the semiconductor layer 208, the descriptions relating to thickness T108a, thickness T108b, and thickness T108c can be read as thickness T208a, thickness T208b, and thickness T208c.

[0311] By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path, a transistor with a large on-state current can be obtained. However, if the thickness T108b is too thick, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. The thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0312] The thickness T108c is preferably thicker than the thickness T108a. By increasing the thickness T108c, the semiconductor layer 108b can be separated from trap levels that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof. Furthermore, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the semiconductor layer 108b increases, which may result in a small on-state current. The thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0313] Oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b via the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces the oxygen vacancy (V Ｏ ) and V ＯH can be reduced. If the thickness T108a is too thin, the distance between the interface between the insulating layer 110 and the semiconductor layer 108 and the trap level near the interface and the semiconductor layer 108b, which is the main current path, becomes short, which may result in a small on-current. Furthermore, reliability may be deteriorated. The thickness T108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.

[0314] It is more preferable that the semiconductor layers 108a, 108b, and 108c each have crystallinity. When the semiconductor layer 108a has crystallinity, the crystallinity of the semiconductor layer 108b formed thereon can be increased. Similarly, when the semiconductor layer 108b has crystallinity, the crystallinity of the semiconductor layer 108c formed thereon can be increased.

[0315] The band gap of the first metal oxide and the band gap of the third metal oxide may be different.

[0316] The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c located on the conductive layer 104 side functioning as the gate electrode, generation and induction of carriers in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (the insulating layer 106 here) can be suppressed, thereby making the transistor highly reliable. For example, generation and induction of carriers in the semiconductor layer 108c and at the interface thereof due to light incident on the transistor can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor due to light.

[0317] The semiconductor layer 108a has regions in contact with the conductive layers 112a and 112b, which function as a source electrode and a drain electrode. By making the band gap of the first metal oxide in the semiconductor layer 108a smaller than the band gap of the third metal oxide, the contact resistance between the semiconductor layer 108a and the conductive layer 112a and the contact resistance between the semiconductor layer 108a and the conductive layer 112b can be reduced. Therefore, a transistor with a large on-state current can be obtained.

[0318] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0319] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0320] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0321] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0322] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0323] 12A and the like illustrate an example in which the semiconductor layer 108 and the semiconductor layer 208 each have a three-layer structure, but one embodiment of the present invention is not limited to this. For example, the semiconductor layer 108 may have a structure in which the semiconductor layer 108a and the semiconductor layer 108c are not included or both, and the semiconductor layer 208 may have a structure in which the semiconductor layer 208a and the semiconductor layer 208c are not included or both. Specifically, as shown in FIG. 14A , the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108b and the semiconductor layer 108c, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208b and the semiconductor layer 208c. Alternatively, as shown in FIG. 14B , the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108a and the semiconductor layer 108b, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208a and the semiconductor layer 208b. Alternatively, each of the semiconductor layer 108 and the semiconductor layer 208 can have a stacked structure of four or more layers.

[0324] The structures of the semiconductor layer 108 and the semiconductor layer 208 shown in Structural Example 1-4 can also be applied to other structural examples.

[0325] 15A is a top view of a semiconductor device 10F according to one embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG.

[0326] 1B and the like in that the transistor 100F includes a conductive layer 103 and an insulating layer 107, and the transistor 200F includes a conductive layer 203 and an insulating layer 107. The transistor 200F differs from the transistor 200 mainly in that the transistor 100F includes a conductive layer 203 and an insulating layer 107.

[0327] The transistor 100F includes a conductive layer 103 and an insulating layer 107 between the conductive layer 112a and the insulating layer 110. The insulating layer 107 is located over the conductive layer 112a. The insulating layer 107 is provided to cover the top and side surfaces of the conductive layer 112a. The conductive layer 103 is located over the insulating layer 107. The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. An opening 148 reaching the insulating layer 107 is provided in the conductive layer 103 in a region overlapping with the conductive layer 112a.

[0328] The insulating layer 110 is provided over the insulating layer 107 and the conductive layer 103. The insulating layer 110 is provided to cover the top surface and side surfaces of the conductive layer 103 and the top surface of the insulating layer 107. An opening 141 reaching the conductive layer 112a is provided in the insulating layer 110 and the insulating layer 107.

[0329] The insulating layer 110a is located over the insulating layer 107 and the conductive layer 103. The insulating layer 110a is provided so as to cover the top surface and side surfaces of the conductive layer 103. The insulating layer 110a is also provided so as to cover part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 in the opening 148.

[0330] The top surface shape of opening 148 is not particularly limited. The top surface shape of opening 148 can be any shape that can be applied to openings 141 and 143. As shown in Fig. 15A, the top surface shapes of openings 141, 143, and 148 are preferably circular. By making the top surface shapes of the openings circular, processing accuracy can be improved when forming the openings, and openings of fine sizes can be formed.

[0331] In this specification and the like, the top surface shape of the opening 148 refers to the shape of the top surface end or the bottom surface end of the conductive layer 103 on the opening 148 side.

[0332] When the top shapes of the openings 141 and 148 are circular, the openings 141 and 148 are preferably concentric. This allows the shortest distance between the semiconductor layer 108 and the conductive layer 103 in a cross-sectional view to be equal on the left and right sides of the opening 141. In addition, the openings 141 and 148 may not be concentric.

[0333] In the transistor 100F, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 via the insulating layer 106 and overlaps with the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b). In other words, the semiconductor layer 108 has a region that is sandwiched between the conductive layer 104 via the insulating layer 106 and the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b).

[0334] In the transistor 100F, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode). Part of the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 103 can be formed using the same material as can be used for the conductive layers 112a, 112b, and 104.

[0335] By providing the back gate electrode in the transistor 100F, the potential of the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved.

[0336] Since the transistor 100F has a back gate electrode, the potential on the back channel side of the semiconductor layer 108 can be fixed, and a shift in the threshold voltage can be suppressed. Here, a shift in the threshold voltage of a transistor may increase the cutoff current. By suppressing the shift in the threshold voltage, a transistor with a small cutoff current can be obtained. This allows a semiconductor device with low power consumption.

[0337] The insulating layer 107 can be formed using a material that can be used for the insulating layer 110. The insulating layer 107 in contact with the conductive layer 112a and the conductive layer 103 is preferably formed using an insulating layer containing nitrogen. The insulating layer 107 can be formed using a material that can be used for the insulating layer 110a and the insulating layer 110c. For example, silicon nitride can be preferably used for the insulating layer 107. Note that although the insulating layer 107 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. The insulating layer 107 can also have a stacked structure of two or more layers.

[0338] The conductive layer 103 can be electrically connected to the conductive layer 112a. For example, an opening can be formed in a region of the insulating layer 107 that overlaps with the conductive layer 112a, and the conductive layer 103 can be provided to cover the opening, thereby making the conductive layer 103 and the conductive layer 112a in contact with each other. The conductive layer 112a, which functions as a source or drain electrode, is electrically connected to the conductive layer 103, which functions as a back gate electrode, so that the source or drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112a functions as a source electrode, a shift in the threshold voltage of the transistor 100F can be suppressed. Furthermore, the reliability of the transistor 100F can be improved. Note that the conductive layer 103 can also be formed in contact with the top surface of the conductive layer 112a without providing the insulating layer 107.

[0339] The conductive layer 103 can be electrically connected to the conductive layer 112b. For example, an opening is provided in a region of the insulating layer 110 that overlaps with the conductive layer 103, and the conductive layer 112b is provided to cover the opening, so that the conductive layer 103 and the conductive layer 112b can be in contact with each other.

[0340] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings can be provided in regions of the insulating layer 106 and the insulating layer 110 that overlap with the conductive layer 103, and the conductive layer 104 can be provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 103 and the conductive layer 104 are in contact with each other. When the conductive layer 104 that functions as a gate electrode is electrically connected to the conductive layer 103 that functions as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100F can be increased.

[0341] The thickness of the conductive layer 103 can be made thicker than the thickness of the insulating layer 110. This allows the potential on the back channel side of the semiconductor layer 108 to be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.

[0342] The transistor 100F has a region in which the conductive layer 103, the insulating layer 110, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 overlap in this order in one direction without any other layers therebetween. The direction may be perpendicular to the channel length direction. By widening the region, the potential on the back channel side of the semiconductor layer 108 can be more reliably controlled.

[0343] The thickness of the conductive layer 103 can be made larger than the sum of the thickness of the portion of the semiconductor layer 108 that is in contact with the conductive layer 112a inside the opening 141 and the thickness of the insulating layer 106 that is in contact with this portion.

[0344] The transistor 200F includes a conductive layer 203 and an insulating layer 107 between the conductive layer 212a and the insulating layer 110. The conductive layer 203 is located over the insulating layer 107. The conductive layer 212a and the conductive layer 203 are electrically insulated from each other by the insulating layer 107. An opening 248 reaching the insulating layer 107 is provided in the conductive layer 203 in a region overlapping with the conductive layer 212a.

[0345] In the transistor 200F, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode). Another part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 203 functions as a back gate electrode (also referred to as a second gate electrode). Another part of the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer).

[0346] The conductive layer 203 can be formed in the same process as the conductive layer 103. For example, a conductive film is formed over the insulating layer 107 and then processed to form the conductive layer 103 and the conductive layer 203. The description of the conductive layer 103 can be referred to for the conductive layer 203, and therefore detailed description thereof will be omitted.

[0347] Although the transistor 100F and the transistor 200F each have a backgate electrode, one embodiment of the present invention is not limited to this. One or both of these transistors may not have a backgate electrode.

[0348] Note that the structures of the conductive layer 103, the conductive layer 203, and the insulating layer 107 shown in Structural Example 1-5 can also be applied to other structural examples.

[0349] 16A to 16G show circuit diagrams of a semiconductor device of one embodiment of the present invention. FIGS. 17 to 19 show top views and cross-sectional views of the semiconductor device of one embodiment of the present invention. In the following, transistors 100 and 200 will be described as examples of transistors included in the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is not limited thereto, and can have a structure including one or more of the above-described transistors 100 to 100F and transistors 200 to 200F.

[0350] A semiconductor device of one embodiment of the present invention includes at least two transistors, and one of the gate, source, or drain of one transistor is electrically connected to the gate, source, or drain of another transistor.

[0351] 16A to 16G, the transistors 100 and 200 are n-channel transistors; however, one embodiment of the present invention is not limited to this. One or both of the transistors 100 and 200 may be p-channel transistors.

[0352] 16A can be referred to for a circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. FIG. 17A shows a top view of the semiconductor device 20. FIG. 17B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 17A , and FIG. 17C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0353] The semiconductor device 20 includes a transistor 100 and a transistor 200. The other of the source and the drain of the transistor 100 is electrically connected to the other of the source and the drain of the transistor 200.

[0354] 1A and the like. The conductive layer 112b has an opening 143 overlapping with the opening 141 and an opening 243 overlapping with the opening 241. A semiconductor layer 208 is provided to cover the openings 241 and 243.

[0355] In the transistor 100, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. In the transistor 200, the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. The conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 100 and also functions as the other of the source electrode and the drain electrode of the transistor 200. By sharing the conductive layer 112b between the transistors 100 and 200, the area occupied by the semiconductor device can be reduced.

[0356] 17B and the like show a structure in which the semiconductor layer 108 included in the transistor 100 and the semiconductor layer 208 included in the transistor 200 are separated; however, one embodiment of the present invention is not limited to this. The transistor 100 and the transistor 200 may share a semiconductor layer.

[0357] The configuration of the conductive layer 112b shown in Structural example 2-1 can also be applied to other structural examples.

[0358] [Configuration Example 2-2] FIG. 16B shows a circuit diagram of a semiconductor device 20A according to one embodiment of the present invention. FIG. 18A shows a top view of the semiconductor device 20A. FIG. 18B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 18A, and FIG. 18C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0359] The semiconductor device 20A includes a transistor 100 and a transistor 200. One of the source and the drain of the transistor 100 is electrically connected to one of the source and the drain of the transistor 200.

[0360] 1A etc. The transistor 200 includes a conductive layer 112a instead of the conductive layer 212a shown in FIG. 1A etc. The insulating layer 110 includes an opening 141 that reaches the conductive layer 112a and an opening 241 that reaches the conductive layer 212a.

[0361] In the transistor 100, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. In the transistor 200, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a source electrode and a drain electrode of the transistor 200. By sharing the conductive layer 112a between the transistors 100 and 200, the area occupied by the semiconductor device can be reduced.

[0362] 18B and the like show a structure in which the semiconductor layer 108 included in the transistor 100 and the semiconductor layer 208 included in the transistor 200 are separated; however, one embodiment of the present invention is not limited to this. The transistor 100 and the transistor 200 may share a semiconductor layer.

[0363] The configuration of the conductive layer 112a shown in Structural example 2-2 can also be applied to other structural examples.

[0364] [Configuration Example 2-3] FIG. 16C shows a circuit diagram of a semiconductor device 20B according to one embodiment of the present invention. FIG. 19A shows a top view of the semiconductor device 20B. FIG. 19B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 19A, and FIG. 19C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0365] The semiconductor device 20B includes a transistor 100 and a transistor 200. The other of the source and the drain of the transistor 100 is electrically connected to the gate of the transistor 200.

[0366] The insulating layer 106 has an opening 149 that reaches the conductive layer 112b. The conductive layer 204 is provided to cover the opening 149 and has a region that is in contact with the conductive layer 112b at the opening 149. The structure in which the conductive layer 112b and the conductive layer 204 are in contact with each other can reduce the occupied area compared to a structure in which the conductive layer 112b and the conductive layer 204 are electrically connected through a conductive layer different from the conductive layers 112b and 204. Note that a structure in which the conductive layer 112b and the conductive layer 204 are electrically connected through a conductive layer different from the conductive layers 112b and 204 can also be used. For example, a first opening that reaches the conductive layer 112b is provided in the insulating layer 106 and the insulating layer 195, a second opening that reaches the conductive layer 204 is provided in the insulating layer 195, and a conductive layer is provided to cover the first opening and the second opening. The conductive layer can have a region in contact with the conductive layer 112b in the first opening and a region in contact with the conductive layer 204 in the second opening.

[0367] Although the structure in which the other of the source and drain of the transistor 100 is electrically connected to the gate of the transistor 200 has been described here, one embodiment of the present invention is not limited thereto. As in a semiconductor device 20C illustrated in FIG. 16D , one of the source and drain of the transistor 100 may be electrically connected to the gate of the transistor 200. For example, openings reaching the conductive layer 112a are formed in the insulating layer 106 and the insulating layer 110, and a conductive layer 204 is provided to cover the openings. The conductive layer 204 may have a region in contact with the conductive layer 112a in the openings. Alternatively, as in a semiconductor device 20D illustrated in FIG. 16E , the gate of the transistor 100 may be electrically connected to the other of the source and drain of the transistor 200. As in a semiconductor device 20E illustrated in FIG. 16F , the gate of the transistor 100 may be electrically connected to the source or drain of the transistor 200.

[0368] The configuration of the conductive layer 204 and the opening 149 shown in Structural example 2-3 can also be applied to other structural examples.

[0369] A semiconductor device of one embodiment of the present invention includes at least one transistor and at least one capacitor, and a source or drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor. Figure 16G illustrates an example in which the source or drain of the transistor 100 is electrically connected to one of the electrodes of the capacitor 190. Note that although the transistor 100 is used as an example here, one embodiment of the present invention is not limited thereto. The semiconductor device can have a structure in which the capacitor 190 is electrically connected to one or more of the transistors 100 to 100F and the transistors 200 to 200F.

[0370] 20A illustrates an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer of 2 or greater). The transistors 100_1 to 100_p are connected in parallel and share a gate. The semiconductor device 30 can be regarded as a single transistor.

[0371] Gate electrodes of the transistors 100_1 to 100_p are electrically connected to each other, source electrodes of the transistors 100_1 to 100_p are electrically connected to each other, and drain electrodes of the transistors 100_1 to 100_p are electrically connected to each other.

[0372] 20A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be p-channel transistors.

[0373] A specific description will be given taking the case where p is 4 as an example. FIG. 20B shows an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. FIG. 20C shows a top view of the semiconductor device 30. FIG. 21 shows a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 20C. FIG. 22 shows a perspective view of the semiconductor device 30.

[0374] The semiconductor device 30 includes transistors 100_1 to 100_4. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example here, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100F can be applied to the transistors 100_1 to 100_4. Alternatively, any of the transistors 200 to 200F can be applied to the transistors 100_1 to 100_4.

[0375] 20C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0376] The transistors 100_1 to 100_4 each include a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. Part of the insulating layer 106 functions as a gate insulating layer of the transistors 100_1 to 100_4. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistors 100_1 to 100_4, and the conductive layer 112b functions as the other.

[0377] FIG. 23A is a perspective view showing an extracted conductive layer 112a.

[0378] 23B is a perspective view illustrating the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are indicated by dashed lines. The openings 141_1 to 141_4 and the openings 143_1 to 143_4 can be described with reference to the description of the openings 141 and 143, and therefore detailed description thereof will be omitted.

[0379] When the semiconductor device 30 is regarded as a single transistor, the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4. For example, if the top shapes of the openings 141_1 to 141_4 are circular, and the widths of the openings 141_1 to 141_4 are each defined as D141, the semiconductor device 30 can be regarded as a transistor having a channel width of "D141×π×4" (see FIGS. 4A and 4B). The semiconductor device 30 including p transistors can be regarded as a transistor having a channel width of "D141×π×p". Note that the semiconductor device 30 can be regarded as a transistor having a channel length of L100 (see FIG. 4B). Connecting multiple transistors in parallel increases the channel width, thereby increasing the on-state current. Furthermore, the channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel can be determined so as to achieve a desired on-state current.

[0380] 23C is a perspective view illustrating the conductive layer 112a and the semiconductor layer 108. The semiconductor layer 108 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. Note that although FIG. 23C and other drawings illustrate a structure in which the transistors 100_1 to 100_4 share the semiconductor layer 108, one embodiment of the present invention is not limited to this. The semiconductor layer 108 may be separate for each of the transistors 100_1 to 100_4.

[0381] 21 , the semiconductor layer 108 has a region 108Da_1 in the opening 141_1, a region 108Da_2 in the opening 141_2, a region 108Da_3 in the opening 141_3, and a region 108Da_4 in the opening 141_4. For the regions 108Da_1 to 108Da_4, the description of the region 108Da can be referred to. The semiconductor layer 108 also has a region 108Db in a region in contact with the top surface of the conductive layer 112b.

[0382] 23D is a perspective view illustrating the conductive layer 112a and the conductive layer 104. The conductive layer 104 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4.

[0383] The configuration of the semiconductor device 30 shown in Configuration Example 2-4 can also be applied to other configuration examples.

[0384] 24A illustrates an equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. The semiconductor device 40 includes transistors 100_1 to 100_q (q is an integer of 2 or greater). The transistors 100_1 to 100_q are connected in series and share a gate. The semiconductor device 40 can be regarded as a single transistor.

[0385] 24A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_q can also be p-channel transistors.

[0386] A specific description will be given taking the case where q is 4 as an example. FIG. 24B shows an equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. FIG. 24C shows a top view of the semiconductor device 40. FIG. 25 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 24C. FIG. 26 shows a perspective view of the semiconductor device 40.

[0387] The semiconductor device 40 includes transistors 100_1 to 100_4. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example here, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100F can be applied to the transistors 100_1 to 100_4. Alternatively, any of the transistors 200 to 200F can be applied to the transistors 100_1 to 100_4.

[0388] 24C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0389] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b functions as the other electrode.

[0390] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. The conductive layer 112a serves as one of a source electrode and a drain electrode of the transistor 100_2, and the conductive layer 112c serves as the other electrode. The conductive layer 112a is shared by the transistor 100_1 and the transistor 100_2.

[0391] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c serves as one of a source electrode and a drain electrode of the transistor 100_3, and the conductive layer 112d serves as the other electrode. The conductive layer 112c is shared by the transistors 100_2 and 100_3.

[0392] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d functions as one of a source electrode and a drain electrode of the transistor 100_4, and the conductive layer 112e functions as the other. The conductive layer 112d is shared by the transistors 100_3 and 100_4.

[0393] 27A is a perspective view showing the conductive layer 112a and the conductive layer 112d. The conductive layer 112a and the conductive layer 112d can be formed in the same process.

[0394] 27B is a perspective view illustrating the conductive layers 112a, 112b, 112c, 112d, and 112e, the openings 141 to 1414, and the openings 1431 to 1434. The conductive layers 112a to 112e can be formed in the same process. The conductive layer 112b has an opening 1431, the conductive layer 112c has openings 1432 and 1433, and the conductive layer 112e has an opening 1434.

[0395] 27C is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4. The semiconductor layers 108_1 to 108_4 can be formed in the same process.

[0396] 25, the semiconductor layer 108_1 has a region 108Da_1 in the opening 141_1. The semiconductor layer 108_2 has a region 108Da_2 in the opening 141_2. The semiconductor layer 108_3 has a region 108Da_3 in the opening 141_3. The semiconductor layer 108_4 has a region 108Da_4 in the opening 141_4. For the regions 108Da_1 to 108Da_4, the description of the region 108Da can be referred to. The semiconductor layer 108_1 has a region 108Db_1 in a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108_2 has a region 108Db_2 in a region in contact with the top surface of the conductive layer 112c. The semiconductor layer 108_3 has a region 108Db_3 in a region in contact with the top surface of the conductive layer 112c. The semiconductor layer 108_4 includes a region 108Db_4 in contact with the top surface of the conductive layer 112e. For the regions 108Db_1 to 108Db_4, the description of the region 108Db can be referred to.

[0397] 27D is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the conductive layer 104. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4.

[0398] One of the source electrode and the drain electrode of the transistor 100_1 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_2. The other of the source electrode and the drain electrode of the transistor 100_2 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_3. The other of the source electrode and the drain electrode of the transistor 100_3 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_4.

[0399] When the semiconductor device 40 is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 40 can be regarded as a transistor having a channel length of "L100×4" (see FIG. 4B). The semiconductor device 40, which is composed of q transistors, can be regarded as a transistor having a channel length of "L100×q". Note that the semiconductor device 40 can be regarded as a transistor having a channel width W100 (see FIGS. 4A and 4B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined so as to achieve the desired saturation.

[0400] The configuration of the semiconductor device 40 shown in Configuration Example 2-5 can also be applied to other configuration examples.

[0401] The semiconductor device 40 can be applied to each transistor included in the semiconductor device 30. That is, a configuration can be achieved in which a group of parallel-connected transistors are further connected in series (hereinafter also referred to as series-parallel connection).

[0402] In the above-described semiconductor device, one or more of the transistors included in the semiconductor device may have a back gate. For example, one or more of the transistors 100F and 200F shown in FIGS. 15A and 15B can be used as one or more of the transistors included in the semiconductor device.

[0403] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0404] 28A to 32B , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0405] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0406] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0407] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0408] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0409] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0410] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0411] 28A to 31C show cross-sectional views taken along dashed line A1-A2 in FIG.

[0412] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0413] Next, a conductive film is formed over the insulating layer 109 and processed to form the conductive layers 112a and 212a (FIG. 28A). The conductive film can be formed by a sputtering method.

[0414] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a and the conductive layer 212a (FIG. 28B).

[0415] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf continuously using the same device.

[0416] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above-described range during the formation of the insulating films 110af and 110bf, the amount of impurities (e.g., water and hydrogen) released from the insulating films can be reduced, and the diffusion of impurities into the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0417] Since the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

[0418] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0419] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic.

[0420] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0421] Next, a film 139 is preferably formed on the insulating film 110bf ( FIG. 28D ). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 28C shows, using arrows, a schematic diagram of oxygen being supplied to the insulating film 110bf.

[0422] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0423] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor that can be used for the semiconductor layer 108.

[0424] When forming the film 139, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0425] In this way, by forming the film 139 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be confined in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0426] Heat treatment can be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0427] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0428] After the film 139 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. As a method for supplying oxygen, for example, ion implantation or plasma treatment can be used. Regarding the plasma treatment, the above description can be referred to, and therefore detailed description thereof will be omitted.

[0429] Next, the film 139 is removed ( FIG. 28E ). Although there is no particular limitation on the method for removing the film 139, a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when the film 139 is removed. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0430] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0431] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110bf ( FIG. 29A ). The insulating film 110cf can be preferably formed by sputtering. The description of the formation of the insulating films 110af and 110bf can be referenced for the formation of the insulating films 110cf and 110ef, and therefore detailed description thereof will be omitted.

[0432] Next, a conductive film 112bf to be the conductive layer 112b and the conductive layer 212b is formed over the insulating film 110ef (FIG. 29B). The conductive film 112bf can be preferably formed by a sputtering method.

[0433] Next, the conductive film 112bf is processed to form the conductive layer 112B and the conductive layer 212B ( FIG. 29C ). Later, the conductive layer 112B becomes the conductive layer 112b, and the conductive layer 212B becomes the conductive layer 212b. For example, a wet etching method can be suitably used to form the conductive layer 112B and the conductive layer 212B.

[0434] Subsequently, parts of the conductive layer 112B and the conductive layer 212B are removed to form the conductive layer 112b having the opening 143 and the conductive layer 212b having the opening 243. The conductive layer 112b and the conductive layer 212b can be preferably formed by wet etching.

[0435] Subsequently, parts of the insulating films 110af, 110bf, 110cf, and 110ef are removed to form the insulating layer 110 having the openings 141 and 241 ( FIG. 29D ). The openings 141 are provided in regions overlapping with the openings 143, and the openings 241 are provided in regions overlapping with the openings 243. The formation of the openings 141 exposes the conductive layer 112a, and the formation of the openings 241 exposes the conductive layer 212a. The insulating layer 110 can be formed preferably by dry etching.

[0436] The openings 141 and 241 can be formed using, for example, the resist mask used to form the openings 143 and 243. Specifically, a resist mask is formed over the conductive layer 112B and the conductive layer 212B, and the openings 143 and 243 are formed by removing parts of the conductive layer 112B and the conductive layer 212B using the resist mask. The openings 141 and 241 can then be formed by removing parts of the insulating films 110af, 110bf, and 110cf using the resist mask. Using the same resist mask can improve productivity. The openings 141 and 241 can also be formed using a resist mask different from the resist mask used to form the openings 143 and 243.

[0437] Next, a metal oxide film 108f to be the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the openings 141, 143, 241, and 243 ( FIG. 30A ). The metal oxide film 108f is provided in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the conductive layer 212b, the top and side surfaces of the insulating layer 110, the top surface of the conductive layer 112a, and the top surface of the conductive layer 212a.

[0438] The metal oxide film 108f is preferably formed by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by ALD. Because ALD has high coverage, it can be suitably used to form the metal oxide film 108f that covers the openings 141, 143, 241, and 243. By using ALD, a metal oxide film can be formed with high coverage on the side surfaces of the insulating layer 110. Furthermore, because the film formation rate is easily controlled, a thin film can be formed with a high yield. Therefore, ALD is suitably used when the metal oxide film 108f is thin. Thermal ALD or PEALD can be used as the ALD. PECVD can also be used to form the metal oxide film 108f.

[0439] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0440] When the metal oxide film 108f is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0441] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later step, and oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 are eliminated. Ｏ H can be reduced.

[0442] The metal oxide film 108f can be formed by mixing oxygen gas with an inert gas (e.g., helium gas, argon gas, xenon gas, or the like). Note that the higher the oxygen flow rate ratio or oxygen partial pressure when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0443] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f.

[0444] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0445] The substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0446] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0447] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0448] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0449] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0450] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0451] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0452] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0453] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0454] Oxidizing agents include, for example, ozone, oxygen, and water.

[0455] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film 108f whose composition changes continuously.

[0456] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0457] In addition, when the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0458] When the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same deposition method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0459] Subsequently, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 30B).

[0460] The semiconductor layer 108 and the semiconductor layer 208 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in a region not overlapping with the semiconductor layer 108 and a part of the conductive layer 212b in a region not overlapping with the semiconductor layer 208 may be etched and thinned. Similarly, a part of the insulating layer 110 in a region not overlapping with any of the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, and the conductive layer 212b may be etched and thinned. For example, the insulating layer 110c of the insulating layer 110 may be removed by etching, exposing the surface of the insulating layer 110b. Note that, in etching the metal oxide film 108f, using a material with a high etching selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0461] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove hydrogen and water contained in or adsorbed to the surfaces of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 (for example, reduce defects or improve crystallinity).

[0462] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108 and the semiconductor layer 208. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0463] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0464] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 (FIG. 30C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0465] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 suppresses oxygen diffusion, thereby suppressing oxygen desorption from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ In addition, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is prevented from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106, thereby preventing the conductive layer 104 and the conductive layer 204 from being oxidized. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0466] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, causing oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0467] Before forming the insulating layer 106, plasma treatment can be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interfaces between the semiconductor layer 108 and the insulating layer 106 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0468] Subsequently, a mask layer 181 is formed on the insulating layer 106 ( FIG. 31A ). Here, a manufacturing method using a resist mask as the mask layer 181 will be described as an example. The mask layer 181 is provided at least in a region overlapping with the semiconductor layer 208. It is also preferable that the mask layer 181 is not provided in a region overlapping with the semiconductor layer 108.

[0469] Next, impurity elements 189 are supplied to the semiconductor layer 108 using the mask layer 181 as a mask ( FIG. 31B ). The mask layer 181 is preferably thick enough to prevent the impurity elements 189 from reaching the semiconductor layer 208. The impurity elements 189 are supplied to the semiconductor layer 108 via the insulating layer 106. By supplying the impurity elements 189, regions 108Da and 108Db are formed. Meanwhile, the semiconductor layer 208 is masked by the mask layer 181, so the impurity elements 189 are not supplied. The thickness of the mask layer 181 can be set depending on the type of impurity element 189 supplied, the acceleration energy used for supply, the composition of the mask layer 181, and the film density. If the mask layer 181 is too thin, the impurity elements 189 may also be supplied to the semiconductor layer 208. If the mask layer 181 is too thick, productivity decreases. When a resist mask is used as the mask layer 181, the thickness of the mask layer 181 is preferably, for example, 1 μm to 5 μm, more preferably 1 μm to 3 μm, and even more preferably 1 μm to 2 μm. By setting the thickness of the mask layer 181 within the above range, it is possible to suppress the impurity element 189 from being supplied to the semiconductor layer 208 and to increase productivity.

[0470] Although a resist mask has been described as an example of a mask layer used for supplying the impurity element 189, one embodiment of the present invention is not limited to this. A hard mask can be used instead of a resist mask. When using a hard mask, the hard mask can be formed by forming a film to serve as the hard mask over the insulating layer 106, forming a resist mask on the film, and processing the film. The material and conductivity of the hard mask are not particularly limited. The thickness of the hard mask can be set depending on the type of the impurity element 189 to be supplied, the acceleration energy used for supplying the impurity element 189, the composition of the hard mask, and the film density.

[0471] The impurity element 189 is preferably supplied from a direction perpendicular or substantially perpendicular to the upper surface of the substrate 102. In this case, as described above, the amount of the impurity element supplied to a region of the semiconductor layer 108 that is inclined with respect to the upper surface of the substrate 102 is smaller than that to a region that is parallel or substantially parallel to the upper surface of the substrate 102. That is, the amount of the impurity element supplied to the source and drain regions of the semiconductor layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source and drain regions can be preferentially reduced. By supplying the impurity element 189 to the semiconductor layer 108, oxygen vacancies (V Ｏ Alternatively, when the impurity element 189 is supplied to the semiconductor layer 108, oxygen vacancies (V Ｏ ) may be combined.

[0472] Furthermore, the impurity element 189 is preferably supplied to the semiconductor layer 108 through the insulating layer 106. The thickness of the insulating layer 106 in the direction in which the impurity element 189 is supplied varies depending on the location. Therefore, the semiconductor layer 108 has regions where the amount of the impurity element 189 is large and regions where the amount of the impurity element 189 is small. Specifically, the amount of the impurity element supplied is larger in a region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b than in a region provided along the side surface of the insulating layer 110. In this way, the impurity element is prevented from being supplied to the channel formation region of the semiconductor layer 108, and the electrical resistance of the source and drain regions can be preferentially reduced. At this time, the impurity element 189 is also supplied to a region of the insulating layer 106 that does not overlap with the mask layer 181. The impurity element 189 is also supplied to a region of the insulating layer 110 that does not overlap with any of the mask layer 181, the semiconductor layer 108, and the conductive layer 112b. In the region of the insulating layer 110, the concentration of the impurity element 189 increases toward the insulating layer 106. For example, the concentration of the impurity element 189 in the insulating layer 110e is high.

[0473] The elements that can be used for the impurity element 189 are as described above. As described above, the impurity element 189 can be preferably supplied by ion implantation.

[0474] The purity of the supplied impurity element can be increased by using an ion implantation method in which a source gas is ionized and the ions are mass-separated and supplied. The impurity element 189 is preferably the first element described above, and more preferably boron or phosphorus. The impurity element 189 is preferably an element that becomes stable when bonded with oxygen, thereby realizing the regions 108Da and 108Db that are stable and have low electrical resistance.

[0475] When hydrogen is also supplied as the impurity element 189, it can be supplied without mass separation, thereby improving productivity. It is preferable to use both the first element and hydrogen as the impurity element 189, and it is even more preferable to use both boron or phosphorus and hydrogen. By using both an element that becomes stable when bonded with oxygen and hydrogen as the impurity element 189, the electrical resistance of the regions 108Da and 108Db can be easily reduced and the low electrical resistance can be stably maintained.

[0476] The ion implantation equipment used to supply the impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors, so that the equipment in the existing LTPS manufacturing line can be used, which is preferable because no new capital investment is required, thereby reducing the initial capital investment costs for manufacturing semiconductor devices.

[0477] In the supplying treatment of the impurity element 189, the treatment conditions are preferably controlled so that the concentration of the impurity element in a portion of the semiconductor layer 108 that overlaps with the conductive layer 112 a or the conductive layer 112 b is higher than the concentration of the impurity element in other regions. This allows the impurity element 189 at an optimum concentration to be supplied to the source and drain regions of the semiconductor layer 108.

[0478] As a source gas of the impurity element 189, a gas containing the above-mentioned impurity element can be used.２ H ６ Gas, BF ３ In addition, when phosphorus is supplied, a typical example is a PH ３ Furthermore, a mixed gas obtained by diluting these source gases with hydrogen or a noble gas can be used.

[0479] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The raw material used to supply the impurity element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0480] For example, it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 189. In this case, the impurity element 189 can be supplied without mass separation, and the electrical resistance of the semiconductor layer 108 can be easily reduced, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.

[0481] The supply of the impurity element 189 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 189, the composition, film density, thickness, and the like of each of the insulating layer 106 and the semiconductor layer 108.

[0482] The method for supplying the impurity element 189 is not limited, and for example, plasma treatment or treatment using thermal diffusion due to heating can be used. In the case of plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0483] In one embodiment of the present invention, the impurity element 189 is supplied to the semiconductor layer 108 through the insulating layer 106. This can prevent the crystallinity of the semiconductor layer 108 from decreasing when the impurity element 189 is supplied. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be prevented.

[0484] If the insulating layer 106 is formed after the impurity element 189 is supplied, the inside of a deposition chamber for the insulating layer 106 may be contaminated. For this reason, it is preferable to supply the impurity element 189 after the insulating layer 106 is formed.

[0485] On the other hand, the impurity element 189 can be directly supplied to the semiconductor layer 108, and then the insulating layer 106 can be formed over the semiconductor layer 108. This can prevent the insulating layer 106 from being damaged by the supply of the impurity element 189.

[0486] The supplying step of the impurity element 189 is preferably performed while heating the substrate 102. This allows damage to the semiconductor layer 108 that occurs when the impurity element 189 is supplied to be repaired. That is, the supplying of the impurity element 189 to the semiconductor layer 108 and the repairing of damage caused by the supplying can be performed in parallel. Furthermore, damage to the insulating layer 106 that occurs when the impurity element 189 is supplied can also be repaired. Note that one embodiment of the present invention is not limited thereto, and the supplying step of the impurity element 189 can be performed without heating the substrate 102.

[0487] The substrate temperature in the supplying step of the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0488] Next, the mask layer 181 is removed. The mask layer 181 can be removed by either or both of a wet etching method and a dry etching method. The wet etching method is preferable because it can prevent damage to the insulating layer 106. Alternatively, ashing can be used as the dry etching method.

[0489] After the impurity element 189 is supplied, heat treatment can be performed. By performing the heat treatment, damage to the semiconductor layer 108 and the insulating layer 106 that occurs in the step of supplying the impurity element 189 can be repaired. Note that if a high temperature is applied to the mask layer 181, it may be difficult to remove the mask layer 181 later. Therefore, when heat treatment is performed, it is preferable to perform the heat treatment after removing the mask layer 181.

[0490] If the temperature of the heat treatment is too high, the electrical resistance of the region 108Da, the electrical resistance of the region 108Db, the contact resistance between the region 108Da and the conductive layer 112a, and the contact resistance between the region 108Db and the conductive layer 112b may increase. Therefore, the temperature of the heat treatment after supplying the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, further preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 400°C or lower, further preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, and further preferably 300°C or higher and 350°C or lower.

[0491] By using an element that becomes stable by bonding with oxygen as the impurity element 189, it is possible to prevent the impurity element 189 from being desorbed in the heat application process. Therefore, after the impurity element 189 is supplied, the electrical resistance of the regions 108Da and 108Db can be kept low even after the heat application process.

[0492] Subsequently, a conductive film is formed over the insulating layer 106 and processed to form the conductive layers 104 and 204 (FIG. 31C). The conductive film can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0493] Next, an insulating layer 195 is formed over the transistor 100D and the transistor 200D (FIG. 10A). The insulating layer 195 can be preferably formed by a PECVD method.

[0494] Through the above steps, the semiconductor device 10D of one embodiment of the present invention can be manufactured.

[0495] <Fabrication Method Example 2> Here, a fabrication method for a structure in which the regions 108Da and 108Db contain a second element in addition to a first element will be described. Note that descriptions of parts that overlap with the above-described <Fabrication Method Example 1> will be omitted, and differences will be described.

[0496] 32A and 32B show cross-sectional views taken along the dashed dotted line A1-A2 shown in FIG. 1A.

[0497] First, similarly to <Fabrication Method Example 1>, steps are performed up to the formation of the mask layer 181. Since the description of Fig. 28A and Fig. 31A can be referred to for the steps up to the formation of the mask layer 181, detailed description thereof will be omitted.

[0498] Next, using the mask layer 181 as a mask, an impurity element 187 is supplied to the semiconductor layer 108 ( FIG. 32A ). The impurity element 187 is supplied to the semiconductor layer 108 via the insulating layer 106. The impurity element 187 is preferably the second element described above, and argon is preferably used. By supplying the impurity element 187, regions 108Ea and 108Eb containing the second element are formed. Later, the region 108Ea becomes the region 108Da, and the region 108Eb becomes the region 108Db.

[0499] The impurity element 187 can be supplied by the same method as that used for supplying the impurity element 189. An ion implantation method can be suitably used for supplying the impurity element 187. The supply of the impurity element 187 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 187, the composition, film density, thickness, and the like of the insulating layer 106 and the semiconductor layer 108.

[0500] The impurity element 187 is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. For the supply of the impurity element 187, the above description of the supply of the impurity element 189 can be referred to.

[0501] By supplying the impurity element 187, the bond between the metal and oxygen of the metal oxide is broken in the region 108Ea which becomes the region 108Da and the region 108Eb which becomes the region 108Db. In addition, the breaking of the bond between the metal and oxygen causes oxygen deficiency (V Ｏ ) occurs. Then, by supplying the first element to the regions 108Ea and 108Eb, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0502] Next, using the mask layer 181 as a mask, an impurity element 189 is supplied to the semiconductor layer 108 ( FIG. 32B ). The impurity element 189 is supplied to the semiconductor layer 108 via the insulating layer 106. By supplying the impurity element 189, a region 108Da and a region 108Db are formed. The region 108Da and the region 108Db each have a first element and a second element.

[0503] The supply conditions of the impurity element 189 can be made different from the supply conditions of the impurity element 187. It is preferable to set conditions such as acceleration energy and dose amount depending on the type of the first element and the type of the second element. Note that the supply conditions of the impurity element 187 and the impurity element 189 can also be made the same.

[0504] Although an example in which the first element and the second element are supplied in different steps has been described here, one embodiment of the present invention is not limited thereto and may be configured to supply the first element and the second element in the same step.

[0505] Subsequently, the mask layer 181 is removed.

[0506] By using the mask layer 181 in common for supplying the impurity element 187 and the impurity element 189, productivity can be improved. Alternatively, different mask layers can be used for supplying the impurity element 187 and the impurity element 189. For example, a first resist mask is formed over the insulating layer 106, the impurity element 187 is supplied using the first resist mask, and then the first resist mask is removed. Then, a second resist mask is formed over the insulating layer 106, the impurity element 189 is supplied using the second resist mask, and then the second resist mask is removed. When a common resist mask is used for supplying the impurity element 187 and the impurity element 189, the resist mask may be deteriorated and difficult to remove, resulting in residues of the resist mask. In this case, it is preferable to use different resist masks for supplying the impurity element 187 and the impurity element 189, because this can prevent residues of the resist mask.

[0507] For the steps after removing the mask layer 181, the description in <Fabrication Method Example 1> can be referred to.

[0508] Through the above steps, the semiconductor device 10D of one embodiment of the present invention can be manufactured.

[0509] This embodiment mode can be combined with other embodiment modes as appropriate.

[0510] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0511] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0512] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0513] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0514] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0515] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0516] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0517] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0518] <Display Device 50A> FIG. 33 shows a perspective view of the display device 50A.

[0519] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 33, the substrate 152 is indicated by a dashed line.

[0520] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 33 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 33 can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0521] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 33 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the...

Claims

a first transistor, a second transistor, and a first insulating layer; the first transistor has a first conductive layer, a second conductive layer, and a first semiconductor layer; the second transistor has a third conductive layer, a fourth conductive layer, and a second semiconductor layer; the first insulating layer is located on the first conductive layer and on the third conductive layer; the first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the third conductive layer; the second conductive layer and the fourth conductive layer are each located on the first insulating layer; the second conductive layer has a third opening in a region overlapping with the first opening; the fourth conductive layer has a fourth opening in a region overlapping with the second opening; the first semiconductor layer has, in the first opening, a first region in contact with an upper surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer, and has, in the third opening, a region in contact with a side surface of the second conductive layer; the second semiconductor layer has, in the second opening, a third region in contact with an upper surface of the third conductive layer and a fourth region in contact with a side surface of the first insulating layer, and has, in the fourth opening, a region in contact with a side surface of the fourth conductive layer; the first region has a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; The first region has a portion having a higher concentration of the first element than the third region. 　 In claim 1, The first region has a portion having a higher concentration of the first element than the fourth region. 　 In claim 1, the first semiconductor layer has a fifth region in contact with an upper surface of the second conductive layer; the second semiconductor layer has a sixth region in contact with an upper surface of the fourth conductive layer; the fifth region has the first element, the fifth region has a portion having a higher concentration of the first element than the second region, The fifth region has a portion having a higher concentration of the first element than the sixth region. 　 In claim 3, The fifth region has a portion having a higher concentration of the first element than the fourth region. 　 In any one of claims 1 to 4, The concentration of the first element in the second region is 1×10 −３ 4. A semiconductor device, comprising: 　 In any one of claims 1 to 4, A second insulating layer is provided. the second insulating layer is located on the first semiconductor layer and on the second semiconductor layer; a portion of the second insulating layer in contact with the first region, the portion containing the first element. 　 In any one of claims 1 to 4, a side surface of the first insulating layer in the first opening and a top surface of the first conductive layer form an angle of 65 degrees or more and 90 degrees or less. 　 In any one of claims 1 to 4, the first region comprises hydrogen; A semiconductor device, wherein a concentration of hydrogen in the first region is higher than a concentration of hydrogen in the second region. 　 In any one of claims 1 to 4, the first region has a second element; the second element is argon, krypton or xenon; the first region has a portion having a higher concentration of the second element than the second region; The first region has a portion having a higher concentration of the second element than the third region. 　 In any one of claims 1 to 4, The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer each include a metal oxide. 　 In any one of claims 1 to 4, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer; the third insulating layer and the fifth insulating layer each include silicon and nitrogen; The fourth insulating layer comprises silicon and oxygen. 　 In any one of claims 1 to 4, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer; the third insulating layer comprises silicon and nitrogen; the fourth insulating layer comprises silicon and oxygen; The fifth insulating layer comprises one or both of aluminum and hafnium, and oxygen. 　 forming a first conductive layer and a second conductive layer on a substrate; forming an insulating film on the first conductive layer and the second conductive layer; forming a third conductive layer having a region overlapping with the first conductive layer and a fourth conductive layer having a region overlapping with the second conductive layer on the insulating film; forming a first insulating layer having a first opening reaching the first conductive layer and a second opening reaching the second conductive layer by processing the insulating film, the third conductive layer, and the fourth conductive layer, and forming a fifth conductive layer having a third opening overlapping with the first opening, and a sixth conductive layer having a fourth opening overlapping with the second opening; forming a first semiconductor layer on the first conductive layer, the first insulating layer, and the fifth conductive layer, and forming a second semiconductor layer on the second conductive layer, the first insulating layer, and the sixth conductive layer; forming a second insulating layer on the first semiconductor layer and the second semiconductor layer; forming a mask layer on the second insulating layer in a region overlapping the second semiconductor layer; supplying a first element to the first semiconductor layer through the second insulating layer using the mask layer as a mask; removing the mask layer; The method for manufacturing a semiconductor device, wherein the first element is boron or phosphorus. 　 In claim 13, The method for manufacturing a semiconductor device, wherein the first element is supplied by an ion implantation method. 　 In claim 13 or 14, The method for manufacturing a semiconductor device, wherein the first element is supplied from a direction perpendicular or approximately perpendicular to an upper surface of the substrate.

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