Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a transistor having favorable electrical properties, having a large on-state current, and having a small parasitic capacitance. Provided is a miniaturized transistor, a semiconductor device which can be highly integrated, and a storage device. The semiconductor device has a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, a transistor including a gate electrode, a first insulating layer on the first conductive layer, and a second insulating layer on the first insulating layer. The second conductive layer is located between the second insulating layer and the first insulating layer, the first insulating layer and the second conductive layer have a first opening reaching the first conductive layer, and the second insulating layer has a second opening overlapping the first opening. The semiconductor layer has a region which contacts the upper surface of the second conductive layer and is located between the second conductive layer and the second insulating layer, and also has a region which contacts lateral surfaces of the first opening and the second opening. The gate electrode is provided inside the first opening, and the height of the upper surface of the semiconductor layer is lower than the height of the upper surface of the gate electrode.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of large-scale integrated circuits (LSIs) has progressed, and active development has been underway for CPUs, memories, and other components used in semiconductor devices. A CPU is an assembly of semiconductor elements that have been processed from a semiconductor wafer and have semiconductor integrated circuits (at least transistors and memories) formed into chips, and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by using a vertical-structure transistor in which the channel of the transistor using an oxide semiconductor film is arranged vertically. Non-Patent Document 2 also discloses a vertical-structure transistor.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53X. Duan et. al, “Novel Vertical Channel-All-Around (CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F2 by Monolithic Stacking”, IEDM Tech. Dig. , 2021, pp. 222-225

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor that can be miniaturized. Another object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device that can be highly integrated. Another object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device. Another object of one embodiment of the present invention is to provide a transistor, semiconductor device, memory device, or display device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operating speed. Another object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention provides a transistor including a first insulating layer and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode. The first insulating layer is located over the first conductive layer, the second insulating layer is located over the first insulating layer, and the second conductive layer is located between the second insulating layer and the first insulating layer. A first opening reaching the first conductive layer is provided in the first insulating layer and the second conductive layer. A second opening overlapping with the first opening is provided in the second insulating layer. The semiconductor layer includes a The semiconductor device has a region in contact with a side surface of the second conductive layer in the first opening, a region in contact with a side surface of the first insulating layer in the first opening, a region in contact with an upper surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer in the second opening, the gate electrode has a region located inside the first opening and a region located inside the second opening, the height of the upper surface of the semiconductor layer is lower than the height of the upper surface of the gate electrode, and the gate insulating layer is sandwiched between the semiconductor layer and the gate electrode within the first opening.

[0014] Alternatively, one embodiment of the present invention includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode. The first insulating layer is over the first conductive layer, the second insulating layer is over the first insulating layer, and the second conductive layer is between the second insulating layer and the first insulating layer. A first opening reaching the first conductive layer is provided in the first insulating layer and the second conductive layer. A second opening overlapping with the first opening is provided in the second insulating layer. The semiconductor layer has a region in contact with a top surface of the second conductive layer. a region in contact with a side surface of the second conductive layer in the first opening, a region in contact with a side surface of the first insulating layer in the first opening, a region in contact with an upper surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer in the second opening; in the semiconductor layer, the region in contact with the upper surface of the second conductive layer is located between the second conductive layer and the second insulating layer; the gate electrode has a region located inside the first opening and a region located inside the second opening; and the gate insulating layer is sandwiched between the semiconductor layer and the gate electrode within the first opening.

[0015] Alternatively, one embodiment of the present invention includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode. The first insulating layer is located over the first conductive layer, the second insulating layer is located over the first insulating layer, and the second conductive layer is located between the second insulating layer and the first insulating layer. A first opening reaching the first conductive layer is provided in the first insulating layer and the second conductive layer. A second opening overlapping with the first opening is provided in the second insulating layer. The semiconductor layer has a region in contact with a top surface of the second conductive layer and a region adjacent to the second conductive layer in the first opening. the semiconductor layer has a region in contact with a side surface of the first insulating layer at the first opening, a region in contact with a top surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer at the second opening; in the semiconductor layer, the region in contact with the top surface of the second conductive layer is located between the second conductive layer and the second insulating layer; the gate electrode has a region located inside the first opening and a region located inside the second opening; the height of the top surface of the semiconductor layer is lower than the height of the top surface of the gate electrode; and the gate insulating layer is sandwiched between the semiconductor layer and the gate electrode within the first opening.

[0016] In the above structure, it is preferable that the height of the upper surface of the gate electrode is approximately the same as the height of the upper surface of the second insulating layer.

[0017] In the above structure, the height of the upper surface of the semiconductor layer is preferably lower than the height of the upper surface of the second opening.

[0018] Alternatively, one embodiment of the present invention includes forming a first insulating layer on a first conductive layer, forming a second conductive layer on the first insulating layer, forming a sacrificial layer on the second conductive layer, forming a second insulating layer to cover a top surface of the sacrificial layer, a side surface of the sacrificial layer, and a side surface of the second conductive layer, providing an opening that reaches the first conductive layer in the second insulating layer, the sacrificial layer, the second conductive layer, and the first insulating layer, and removing the sacrificial layer to provide a first gap, and forming a first semiconductor layer so as to have a region in contact with the top surface of the first conductive layer, a region in contact with a side surface of the first insulating layer in the opening, a region in contact with a side surface of the second conductive layer in the opening, a region in contact with a side surface of the second insulating layer in the opening, a region in contact with the top surface of the second conductive layer in the first gap, and a region in contact with the top surface of the second insulating layer. a third insulating layer and a third conductive layer are sequentially formed on the first semiconductor layer; a planarization treatment is performed to remove part of the third conductive layer, part of the third insulating layer, and part of the first semiconductor layer to expose an upper surface of the second insulating layer; a gate electrode is formed by removing part of the third conductive layer; a gate insulating layer is formed by removing part of the third insulating layer; a second semiconductor layer is formed by removing part of the first semiconductor layer; a third semiconductor layer is formed by removing part of a region of the second semiconductor layer that is located within an opening of the second insulating layer; and a fourth insulating layer is formed over the second insulating layer, the third semiconductor layer, the gate insulating layer, and the gate electrode.

[0019] In the above structure, the first semiconductor layer is preferably formed by atomic layer deposition.

[0020] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a transistor with high on-state current can be provided. According to another embodiment of the present invention, a transistor with low parasitic capacitance can be provided. According to another embodiment of the present invention, a miniaturized transistor can be provided. According to another embodiment of the present invention, a semiconductor device, a memory device, or a display device that can be highly integrated can be provided. According to another embodiment of the present invention, a highly reliable transistor, a semiconductor device, a memory device, or a display device can be provided. According to another embodiment of the present invention, a transistor, a semiconductor device, a memory device, or a display device that consumes low power can be provided. According to another embodiment of the present invention, a memory device that operates at high speed can be provided. According to another embodiment of the present invention, a manufacturing method of the transistor, the semiconductor device, the memory device, or the display device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are plan views showing examples of components of a semiconductor device. FIGS. 2C and 2D are cross-sectional views showing an example of a semiconductor device. FIGS. 3A to 3E are cross-sectional views showing an example of a semiconductor device. FIGS. 4A to 4C are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIGS. 6A to 6D are cross-sectional views showing an example of a semiconductor device. FIG. 7A is a plan view showing an example of a memory device. FIGS. 7B and 7C are cross-sectional views showing an example of a memory device. FIG. 8A is a plan view showing an example of a memory device. FIGS. 8B and 8C are cross-sectional views showing an example of a memory device. FIGS. 9A to 9D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 10A to 10D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 11A to 11D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 12A to 12D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view showing an example of a memory device. FIGS. 13B and 13C are cross-sectional views showing an example of a memory device. FIG. 14A is a plan view showing an example of a memory device. FIGS. 14B and 14C are cross-sectional views showing an example of a memory device. FIG. 15A is a plan view showing an example of a memory device. FIG. 15B is a cross-sectional view showing an example of a memory device. FIGS. 16A and 16B are cross-sectional views illustrating an example of a memory device. FIG. 17A is a plan view showing an example of a memory device. FIGS. 17B and 17C are cross-sectional views showing an example of a memory device. FIG. 18 is a cross-sectional view showing an example of a memory device. FIG. 19 is a cross-sectional view showing an example of a memory device. FIG. 20 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 21A to 21H are diagrams illustrating an example of a circuit configuration of a memory cell. FIG. 22 is a diagram illustrating an example of a circuit configuration of a memory cell. FIGS. 23A and 23B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 24 is a block diagram illustrating a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. 27A and 27B are diagrams showing various storage devices by hierarchical level.FIG. 28A is a block diagram showing an example of the configuration of a display device. FIG. 28B is a plan view showing an example of the configuration of a pixel. FIG. 28C is a circuit diagram showing an example of the configuration of a pixel. FIG. 29A is a block diagram showing an example of the configuration of a drive circuit. FIGS. 29B and 29C are circuit diagrams showing examples of the configuration of a drive circuit. FIG. 30 is a block diagram showing an example of the configuration of a display device. FIGS. 31A and 31B are diagrams showing an example of electronic components. FIGS. 32A to 32C are diagrams showing an example of a mainframe computer. FIG. 32D is a diagram showing an example of space equipment. FIG. 32E is a diagram showing an example of a storage system applicable to a data center. FIGS. 33A to 33F are diagrams showing an example of electronic equipment. FIGS. 34A to 34G are diagrams showing an example of electronic equipment. FIGS. 35A to 35F are diagrams showing an example of electronic equipment. FIGS. 36A and 36B are cross-sectional views showing an example of a semiconductor device.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0027] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0028] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0029] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0030] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0032] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0033] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0034] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0036] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0037] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0038] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0039] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0040] In this specification, the phrase "top surface shapes that are approximately the same" refers to at least a portion of the contours of the stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes that are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned. In this specification, the phrase "edges that are aligned" refers to at least a portion of the contours of the stacked layers overlapping in a plan view.

[0041] In general, it may be difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification and elsewhere, "match" may include both an exact match and an approximate match.

[0042] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0044] In this specification and the like, when it is stated that A is located on B, it means that at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0045] In this specification and the like, when it is stated that A covers B, it means that at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has a region that covers B.

[0046] In this specification and the like, when it is stated that A overlaps with B, it means that at least a part of A overlaps with B. Therefore, for example, it can be rephrased as saying that A has an overlapping region with B.

[0047] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0048] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0049] In a transistor of one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. Here, the height direction is, for example, a direction perpendicular to a substrate surface or a surface on which the transistor is formed.

[0050] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0051] <Structural Example of Semiconductor Device> The structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 1C. FIG. 1A is a plan view of a semiconductor device including a transistor 200. FIG. 1B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. 1A. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.

[0052] 1A to 1C includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, and an insulating layer 280, an insulating layer 281, an insulating layer 282, an insulating layer 284, a conductive layer 241, and a conductive layer 242 over the insulating layer 210. Note that the insulating layer 280 and the insulating layer 281 may be considered as components of the transistor 200.

[0053] The transistor 200 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An insulating layer 280 is located on the conductive layer 220, a conductive layer 240 is located on the insulating layer 280, and an insulating layer 281 is located on the conductive layer 240 and the insulating layer 280. An insulating layer 282 is located on the insulating layer 281. An insulating layer 284 is located on the insulating layer 282. The conductive layer 240 is located between the insulating layers 280 and 281. The conductive layer 220 and the conductive layer 240 are located at different heights with the insulating layer 280 sandwiched between them.

[0054] 1B and 1C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220. The bottom of the opening 290 is the upper surface of the conductive layer 220, for example.

[0055] 1A, regions where the top surface shapes of the semiconductor layer 230 and the conductive layer 240 are the same are denoted by reference numerals 230 and 240, but the top surface shape of the conductive layer 240 differs from that of the semiconductor layer 230 in that it has an opening 290. Fig. 2A shows the top surface shape of the conductive layer 240, and Fig. 2B shows the top surface shape of the semiconductor layer 230.

[0056] At least some of the components of the transistor 200 are disposed inside the opening 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion of each is located inside the opening 290.

[0057] The semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 220 that overlaps the opening 290, a region in contact with the side surface of the insulating layer 280 in the opening 290, and a region in contact with the side surface of the conductive layer 240 in the opening 290.

[0058] 1A-1C, insulating layer 250 and conductive layer 260 are disposed inside opening 290 in conductive layer 240. In FIG.

[0059] In the transistor 200, the semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating layer. The semiconductor layer 230 of the transistor of one embodiment of the present invention preferably contains a metal oxide (also referred to as an oxide semiconductor). When the semiconductor layer 230 contains a metal oxide, the off-state current of the transistor 200 can be extremely small.

[0060] The conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The semiconductor layer 230 is in contact with the top surface of the conductive layer 220. The semiconductor layer 230 is also in contact with the conductive layer 240. Since one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, a current flows vertically in the semiconductor layer 230. In other words, a channel is formed along the sidewall of the opening 290.

[0061] The semiconductor layer 230 may also have an n-type region (low-resistance region) having a higher carrier concentration than the channel formation region. The n-type region may function as a source region or a drain region. The regions of the semiconductor layer 230 in contact with the conductive layer 220 and the conductive layer 240 preferably function as low-resistance regions. When these regions of the semiconductor layer 230 function as low-resistance regions, for example, the contact resistance between the conductive layer 220 and the conductive layer 240 and the semiconductor layer 230 can be reduced. Furthermore, the low-resistance region may alleviate the electric field between the gate and the drain, thereby improving the reliability of the transistor.

[0062] The conductive layer 240 can function as a wiring included in the semiconductor device. By reducing the parasitic capacitance generated between the conductive layer 240 and another conductive layer functioning as a wiring, the operating speed of the semiconductor device can be increased.

[0063] An opening 290b is provided in the insulating layer 281. In the transistor of one embodiment of the present invention, parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced by providing the insulating layer 281 over the conductive layer 240 and disposing the conductive layer 260 in the opening 290b provided in the insulating layer 281. The opening 290b has a region overlapping with the opening 290 in a plan view.

[0064] The insulating layer 250 and the conductive layer 260 each have a region located within the opening 290 and a region located within the opening 290b.

[0065] In the transistor 200, the conductive layer 260 is provided inside an opening formed by collectively opening the insulating layer 280, the conductive layer 240, and the insulating layer 281 using the same mask. The conductive layer 260 is provided so as to cover the side surfaces of the opening, with the semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. Among the openings collectively opened, the openings in the insulating layer 280 and the conductive layer 240 are opening 290, and the opening in the insulating layer 281 is opening 290b.

[0066] The conductive layer 260 has a shape that reflects the shape of the opening. When the opening has a columnar shape, the conductive layer 260 also has a columnar shape. In the columnar conductive layer 260, the lower part of the pillar is located in the opening 290, and the upper part is located in the opening 290b. The conductive layer 260 is not provided on the upper surface of the insulating layer 281. The height of the upper surface of the conductive layer 260 is preferably formed to be approximately the same as the height of the upper surface of the insulating layer 281, thereby enabling a configuration in which the conductive layer 260 is not provided on the upper surface of the insulating layer 281 but is embedded in the insulating layer 281.

[0067] As described above, the conductive layer 260 is provided inside the opening formed by simultaneously opening the insulating layer 280, the conductive layer 240, and the insulating layer 281 using the same mask, and is not provided on the upper surface of the insulating layer 281. Therefore, the overlapping area between the conductive layer 240 and the conductive layer 260 can be made extremely small. Therefore, the conductive layer 260 and the conductive layer 240 do not have an overlapping region in a planar view. Because the overlapping area in a planar view is small (in the examples shown in FIGS. 1A to 1C , there is no overlap, i.e., the area is as small as possible), the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be made small.

[0068] An insulating layer 281 is provided on the conductive layer 240. Therefore, the conductive layer 240 and a conductive layer provided above the conductive layer 240 are separated by a distance at least equal to the thickness of the insulating layer 281 on the conductive layer 240. An example of a conductive layer provided above the conductive layer 240 is a wiring electrically connected to the conductive layer 260. This distance reduces the parasitic capacitance generated between the conductive layer 240 and the conductive layer above it. It also reduces the leakage current between the conductive layer 240 and the conductive layer above it. The insulating layer 281 preferably has a thickness sufficient to sufficiently reduce the parasitic capacitance generated between the conductive layer 240 and other conductive layers, and the equivalent oxide thickness (EOT) of the insulating layer 281 is preferably at least greater than the equivalent oxide thickness of the insulating layer 250. In this specification, the term "equivalent oxide thickness" refers to a value obtained by converting a physical film thickness into an electrical film thickness equivalent to silicon oxide or silicon oxynitride. The equivalent oxide thickness of insulating layer 281 is preferably, for example, more than three times, and more preferably more than five times, the equivalent oxide thickness of insulating layer 250. The thickness of insulating layer 281 can be determined by reference to the thickness of insulating layer 280, for example.

[0069] Furthermore, an insulating layer 280 is disposed between the conductive layer 220 and the conductive layer 240. Therefore, the conductive layer 220 and the conductive layer 240 are separated by a distance at least equal to the thickness of the insulating layer 280 on the conductive layer 220. This distance reduces the parasitic capacitance that occurs between the conductive layer 220 and the conductive layer 240. Furthermore, the insulating layer 280 and the insulating layer 281 also reduce the parasitic capacitance that occurs between the conductive layer 220 and the conductive layer above the insulating layer 281.

[0070] 1A to 1C, the conductive layer 260 has a columnar shape. The semiconductor layer 230 covers the side surfaces of the conductive layer 260 with the insulating layer 250 sandwiched therebetween.

[0071] Here, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided in this order inside the opening that is opened collectively, and the semiconductor layer 230 has a region in the opening 290b that covers the side surface of the conductive layer 260 with the insulating layer 250 sandwiched therebetween. Note that in this region, the semiconductor layer 230 is preferably in contact with the side surface of the insulating layer 281. The region of the semiconductor layer 230 located in the opening 290b does not contribute to a channel formation region and overlaps with the conductive layer 260 with the insulating layer 250, which is thinner than the insulating layer 281, sandwiched therebetween. Therefore, significant parasitic capacitance may be generated between the semiconductor layer 230 and the conductive layer 260. Therefore, in the semiconductor device of one embodiment of the present invention, it is preferable to reduce the area where the semiconductor layer 230 and the conductive layer 260 overlap within the opening 290b.

[0072] Therefore, in a region where the semiconductor layer 230 and the conductive layer 260 unnecessarily overlap, the area of ​​the unnecessarily overlapping region can be reduced by removing at least a portion of either the semiconductor layer 230 or the conductive layer 260. In the circuitry of the semiconductor device, the conductive layer 260 is used as wiring, an electrode, or the like. Therefore, the conductive layer 260 is preferably configured to be easily electrically connected to upper wiring layers using plugs or the like. Therefore, the conductive layer 260 preferably fills the opening 290b up to its upper portion. Meanwhile, in the semiconductor device, the semiconductor layer 230 is connected to wiring, plugs, or the like via the conductive layer 240, so the semiconductor layer 230 itself does not necessarily need to fill up to its upper portion of the opening 290b. Therefore, the overlapping area between the semiconductor layer 230 and the conductive layer 260 is reduced by removing a portion of the semiconductor layer 230.

[0073] 1B and 1C , the semiconductor layer 230 is not provided at or near the upper end of the opening 290b of the insulating layer 281, and the height of the upper surface of the semiconductor layer 230 provided in the opening 290b is lower than the height of the upper surface of the insulating layer 281. In addition, an insulating layer 282 is provided on the semiconductor layer 230 in the opening 290b. A region of the insulating layer 282 located on the semiconductor layer 230 in the opening 290b is shown as a region 289.

[0074] Furthermore, the height of the upper surface of the conductive layer 260 is approximately the same as the height of the upper surface of the insulating layer 281. Therefore, the height of the upper surface of the semiconductor layer 230 is lower than the height of the upper surface of the conductive layer 260 in the opening 290b.

[0075] The semiconductor layer 230 has a region located within the opening 290, a region located within the opening 290b, and the like. The semiconductor layer 230 has a channel formation region between a region in contact with the source electrode and a region in contact with the drain region. The channel formation region provided in the semiconductor layer 230 is located within the opening 290. As shown in FIGS. 1B and 1C , a region 289 of the insulating layer 282 is located on the semiconductor layer 230 within the opening 290b. The region 289 can be formed by removing a region above the channel formation region, specifically, at least a portion of the semiconductor layer 230 in the opening 290b, by etching, and filling the removed region with the insulating layer 282. Note that removing a portion of the semiconductor layer 230 creates a void. A configuration in which the insulating layer 282 is not filled in the void is also possible. By filling the void with the insulating layer 282, when a conductive layer (e.g., the conductive layer 249 shown in FIG. 14 ) is provided in a region of the transistor 200 that overlaps with the void in a structure such as that shown in FIG. 14 described later, the conductive layer can be prevented from entering the void and causing a short circuit with the semiconductor layer 230. Providing the region 289 allows the conductive layer 260 to be configured not to overlap with the semiconductor layer 230 at the upper end of the opening 290b and in the vicinity thereof. Therefore, the overlapping area between the conductive layer 260, which functions as the gate of the transistor, and the semiconductor layer 230 can be reduced, and parasitic capacitance generated between the gate and the semiconductor layer can be reduced. Therefore, the operating speed of the semiconductor device can be improved.

[0076] On the other hand, from the viewpoint of ease of fabrication of the semiconductor device, it is preferable that the semiconductor layer 230 remain in the opening 290b. That is, it is preferable that the height of the upper surface of the semiconductor layer 230 in the opening 290b is higher than the height of the upper surface of the semiconductor layer 230 on the conductive layer 240. By forming the semiconductor layer 230 in the opening 290b higher than the upper surface of the semiconductor layer 230 on the conductive layer 240, it is possible to suppress discontinuity of the semiconductor layer 230 even if over-etching occurs in the etching step for forming the semiconductor layer 230. Therefore, it is possible to increase the yield during fabrication and improve the reliability of the semiconductor device.

[0077] If the difference in height between the semiconductor layer 230 in the region covering the upper surface of the conductive layer 240 and the upper surface of the conductive layer 260 is H1, and the difference in height between the upper surface of the semiconductor layer 230 in the region covering the upper surface of the conductive layer 240 and the upper surface of the semiconductor layer 230 within the opening 290b is H2, then H2 is preferably, for example, 1 / 2 or less of H1, and more preferably 1 / 3 or less of H1.

[0078] Furthermore, when the semiconductor layer 230 is in contact only with the side surfaces of the conductive layer 240, the contact area depends on the film thickness of the conductive layer 240. Therefore, it is preferable that the semiconductor layer 230 be in contact with the top surface of the conductive layer 240 in addition to the side surfaces of the conductive layer 240. When the semiconductor layer 230 is in contact only with the side surfaces of the conductive layer 240, the contact area depends on the film thickness of the conductive layer 240, whereas the contact area between the top surface of the conductive layer 240 and the semiconductor layer 230 can be relatively easily increased by changing the top surface shape of the conductive layer 240. The semiconductor layer 230 has a region 279 as a region in contact with the top surface of the conductive layer 240. The region 279 is a region located between the conductive layer 240 and the insulating layer 281. The insulating layer 281 is located on the region 279.

[0079] In the semiconductor device shown in FIGS. 1A to 1C , the conductive layer 260 has a columnar shape. The semiconductor layer 230 covers the side surfaces of the conductive layer 260 with the insulating layer 250 sandwiched therebetween. Furthermore, a region 279 of the semiconductor layer 230 surrounds the conductive layer 260 with the insulating layer 250 sandwiched therebetween. The region 279 can be formed by forming a gap sandwiched between the insulating layers 280 and 281 and embedding a semiconductor layer in the gap. The semiconductor layer 230 having the region 279 can increase the contact area between the semiconductor layer 230 and the conductive layer 240. Therefore, the contact resistance can be reduced.

[0080] The semiconductor layer 230 is preferably in the form of a continuous film from the region 279 to a region in contact with the side surface of the conductive layer 240 on the opening 290 side. In the semiconductor layer 230, the region in contact with the top surface of the conductive layer 240 and the region in contact with the side surface of the conductive layer 240 on the opening 290 side have the same composition, for example. Furthermore, in the semiconductor layer 230, in the region in contact with the top surface of the conductive layer 240 and the region in contact with the side surface of the conductive layer 240 on the opening 290 side, no clear boundary is observed in a cross-sectional view using a transmission electron microscope (TEM), for example.

[0081] The side surfaces of the layers constituting the opening 290 preferably form a continuous surface. Alternatively, if the side surfaces of the layers form steps, it is preferable that the unevenness of the steps is small. By adopting such a configuration, the film thickness distribution of the semiconductor layer 230 provided inside the opening 290 can be made uniform. Furthermore, it is possible to prevent the semiconductor layer 230 from being divided by steps that may occur due to the side surfaces of the layers.

[0082] The width of the opening 290 in a cross-sectional view may vary in the depth direction, and may be, for example, the width of the opening 290 at the top end of each layer in which the opening 290 is provided, the width of the opening 290 at the bottom end, the width at half the depth of the layer, etc.

[0083] The insulating layer 250 is provided in contact with the upper surface of the semiconductor layer 230 in the opening 290. The semiconductor layer 230 covers the side surfaces of the insulating layer 280 and the conductive layer 240 in the opening 290, and the insulating layer 250 covers the semiconductor layer 230 in the opening 290.

[0084] The insulating layer 250 functions as a gate insulating layer of the transistor 200. By thinning the gate insulating layer, it is possible to reduce the gate potential applied during operation of the transistor 200. Furthermore, it is possible to operate the transistor 200 at high speed.

[0085] The sidewalls of the opening 290 may be, for example, vertical, or alternatively, the sidewalls of the opening 290 may be tapered.

[0086] Furthermore, by setting the angle between the top surface of the insulating layer 210 and the side surface of the opening 290 to be greater than 60 degrees and less than or equal to 90 degrees, preferably greater than 70 degrees and less than or equal to 90 degrees, more preferably greater than 75 degrees and less than or equal to 90 degrees, and even more preferably greater than or equal to 80 degrees and less than or equal to 90 degrees, the sidewall of the opening 290 can be made steep, thereby enabling higher integration of the semiconductor device. Furthermore, by setting the angle between the top surface of the insulating layer 210 and the sidewall of the opening 290 to be 60 degrees or less, coverage of the sidewall of the opening 290 by the semiconductor layer, insulating layer, conductive layer, and the like of the transistor 200 can be improved.

[0087] Alternatively, for example, the sidewall of the opening 290 may have a reverse tapered shape. In other words, the angle formed between the sidewall of the opening 290 and the top surface of the insulating layer 210 may be greater than 90 degrees.

[0088] 1A shows an example in which the end of the conductive layer 240 on the opposite side of the opening 290 coincides or substantially coincides with the end of the semiconductor layer 230. In a configuration in which the end of the conductive layer 240 coincides or substantially coincides with the end of the semiconductor layer 230, the same mask can be used when processing the conductive layer 240 and the semiconductor layer 230, which enables simplification of the process.

[0089] The end of the conductive layer 240 opposite the opening 290 and the end of the semiconductor layer 230 do not have to coincide with each other, and one may be located outside the other. Fig. 2C shows a modified example of Fig. 1C in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240.

[0090] In the structure shown in FIG. 2C, the semiconductor layer 230 covers the end portion of the conductive layer 240, so that the contact resistance between the conductive layer 240 and the semiconductor layer 230 can be reduced.

[0091] 2D shows a modified example of FIG. 1C in which an end of the conductive layer 240 is located outside the end of the semiconductor layer 230. With this structure, when a conductive layer such as the conductive layer 242 shown in FIG. 1B or the like is provided on the conductive layer 240, the conductive layer is provided on a region not covered by the semiconductor layer 230, eliminating the need to form an opening in the semiconductor layer 230, thereby simplifying the manufacturing process. Here, in FIG. 2D , the end of the conductive layer 240 is located outside the end of the semiconductor layer 230. For example, the end of the conductive layer 240 on the side opposite the opening 290 in FIG. 2D can be located outside the side opposite the opening 290 in the semiconductor layer 230 by 0.5 times or more the width of the opening 290.

[0092] Each layer constituting the semiconductor device may have a stacked structure. Figures 1B and 1C show an example in which the conductive layer 220 has a stacked structure of a conductive layer 220a and a conductive layer 220b on the conductive layer 220a. Also, an example in which the conductive layer 240 has a stacked structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a is shown. Also, an example in which the insulating layer 280 has a stacked structure of an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b is shown.

[0093] The conductive layer 220a and the conductive layer 240a can each be formed using a material with high conductivity. The conductive layer 220b and the conductive layer 240b can each be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as a conductive layer in contact with the semiconductor layer 230 or the like, when a metal oxide or the like is used as the semiconductor layer, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer.

[0094] The insulating layer 280b can be a layer that supplies oxygen. The insulating layers 280a and 280c can each be a layer that has a barrier property against oxygen. The insulating layer 280a can also be an insulating layer that has a function of capturing or fixing hydrogen.

[0095] A conductive layer 241 functioning as a plug is provided on the conductive layer 260. The conductive layer 241 is provided so as to fill openings provided in the insulating layer 284 and the insulating layer 282. The conductive layer 260 and a conductive layer provided on the insulating layer 284 are electrically connected to each other through the conductive layer 241.

[0096] A conductive layer 242 functioning as a plug is provided on the conductive layer 240. The conductive layer 242 is provided so as to fill openings provided in the insulating layer 284, the insulating layer 281, and the semiconductor layer 230. The conductive layer 240 and the conductive layer provided on the insulating layer 284 are electrically connected to each other through the conductive layer 242. In addition, in FIGS. 1B and 1C , the conductive layer 242 is provided so as to fill an opening provided in the conductive layer 240b and a recess provided in the conductive layer 240a. This allows the conductive layer 242 to be in contact with the conductive layer 240 not only on its bottom surface but also on its side surface, which may reduce the contact resistance between the conductive layer 240 and the conductive layer 242.

[0097] Furthermore, when the conductive layer 240 has a stacked structure of the conductive layer 240a and the conductive layer 240b, if the conductive layer 240b is made of a conductive material containing oxygen, the contact resistance between the conductive layer 242 and the conductive layer 240a can be lower than the contact resistance between the conductive layer 242 and the conductive layer 240b. For example, a metal material can be used for both the conductive layer 242 and the conductive layer 240a. Alternatively, a metal can be used for one of the conductive layer 242 and the conductive layer 240a, and a metal nitride can be used for the other. Alternatively, a metal nitride can be used for both the conductive layer 242 and the conductive layer 240a. In the configurations shown in FIGS. 1B and 1C , the side and bottom surfaces of the conductive layer 242 can be in contact with the conductive layer 240a, which can further reduce the contact resistance.

[0098] 36A , the thickness of the semiconductor layer 230 covering the sidewall of the opening 290 may be different from the thickness of the semiconductor layer 230 covering the top surface of the conductive layer 240. In the example shown in FIG. 36A , the thickness of the semiconductor layer 230 covering the sidewall of the opening 290 is thicker than the thickness of the semiconductor layer 230 covering the top surface of the conductive layer 240.

[0099] Furthermore, when the width of opening 290 is small, the volume occupied by semiconductor layer 230 and insulating layer 250 within opening 290 becomes relatively larger compared to a wide opening 290. Accordingly, the volume occupied by conductive layer 260 within opening 290 becomes relatively smaller, and the width of conductive layer 260 becomes smaller as in the example shown in FIG.

[0100] <Semiconductor Device Variation 2> The cross-sectional view shown in FIG. 3A differs from FIG. 1B mainly in that a recess overlapping the opening 290 in the insulating layer 280 is provided in the conductive layer 220. FIG. 3B shows an enlarged view of the area surrounded by the dashed line in FIG. 3A. When a recess overlapping the opening 290 in the insulating layer 280 is provided in the conductive layer 220, the opening 290 in the insulating layer 280 and the recess in the conductive layer 220 may form a continuous opening. In such a case, for example, the bottom of the continuous opening becomes the upper surface of the conductive layer 220. Alternatively, the sidewall of the opening 290 can be expressed as being formed by the side surface of the conductive layer 240, the side surface of the insulating layer 280, and the side surface of the recess in the conductive layer 220, and the bottom of the opening 290 can be expressed as being formed by the bottom edge of the recess in the conductive layer 220.

[0101] At least a portion of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is formed so as to fill the recess in the conductive layer 220. With this configuration, it is possible to easily apply the gate electric field of the conductive layer 260 up to the vicinity of the conductive layer 220 in the semiconductor layer 230. The recess in the conductive layer 220 is formed, for example, by over-etching when the opening 290 is formed.

[0102] FIG. 3C shows an example in which the depth of the recesses provided in the conductive layer 220 is shallower than that in FIG. 3B.

[0103] 3B , the conductive layer 220 and the conductive layer 260 have a region where they overlap with each other. This makes it easier for a gate electric field to be applied to a channel formation region of the semiconductor layer 230, for example, and improves the electrical characteristics of the transistor. Furthermore, since a gate electric field is also easier to be applied to a region of the semiconductor layer 230 that is in contact with the conductive layer 220, for example, the on-current of the transistor can be increased.

[0104] 3D shows an example in which an opening is provided in conductive layer 220 that overlaps with opening 290 in insulating layer 280. In Fig. 3D, it can also be expressed that the sidewall of opening 290 is formed by the side surface of conductive layer 240, the side surface of insulating layer 280, and the side surface of the opening in conductive layer 220, and the bottom of opening 290 is formed by the upper surface of insulating layer 210.

[0105] Note that Figure 3B shows an example in which the recess in conductive layer 220 is formed across conductive layer 220b and conductive layer 220a, with conductive layer 220a serving as the bottom surface of the recess; however, as shown in Figure 3E, the recess may be formed in conductive layer 220b, with conductive layer 220b serving as the bottom surface of the recess.

[0106] 3E, both the side surface and the bottom surface of the semiconductor layer 230 can be in contact with the conductive layer 220b, which may reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220b.

[0107] <Variation 3 of Semiconductor Device> The semiconductor layer 230 can have a stacked structure of two or more layers.

[0108] 4A differs from FIG. 1B mainly in that the semiconductor layer 230 has a two-layer stacked structure of a semiconductor layer 230a and a semiconductor layer 230b on the semiconductor layer 230a. Also, FIGS. 4B and 4C show enlarged views of regions 271 and 272 shown in FIG. 4A, respectively. Note that one or more of the semiconductor layers 230a and 230b may have an additional stacked structure.

[0109] In the semiconductor layer 230, a region sandwiched between the conductive layer 240 and the insulating layer 281 is defined as a region 279. The semiconductor layer 230 in the region 279 is the semiconductor layer 230 provided in a region 278, which will be described later in the manufacturing method. The region 278 is formed by removing the sacrificial layer 236 after the opening 290 is formed. The region 278 is, for example, a void.

[0110] 4B , in the region 279, the semiconductor layer 230a is provided along the side surfaces of the insulating layer 281, the top surface of the conductive layer 240, and the bottom surface of the insulating layer 281. In the region 279, the semiconductor layer 230b is provided so as to fill a recess (also referred to as a hollow) in the semiconductor layer 230a. In the example shown in FIG. 4B , in the region 279, the semiconductor layer 230a has a region sandwiched between the side surfaces of the insulating layer 281 and the semiconductor layer 230b, a region sandwiched between the top surface of the conductive layer 240 and the semiconductor layer 230b, and a region sandwiched between the bottom surface of the insulating layer 281 and the semiconductor layer 230b.

[0111] 5A shows an example in which the thickness of the semiconductor layer 230a is thicker than that of the semiconductor layer 230a shown in FIG. 5A. In FIG. 5A, since the thickness of the semiconductor layer 230a is thicker, the semiconductor layer 230a is formed in the region 279, and the semiconductor layer 230b is mainly formed in the opening 290. For example, the region 279 may be filled with the semiconductor layer 230a.

[0112] 5B differs from FIG. 4B mainly in that a void 277 is formed in region 279. In FIG. 5B, for example, after semiconductor layer 230a is formed in region 279, semiconductor layer 230b is less likely to be formed in region 279 because the diameter of the recess of semiconductor layer 230a is small, and semiconductor layer 230b is mainly formed in opening 290.

[0113] Here, the semiconductor layer 230a is preferably formed by a method with high coverage, for example. For example, the semiconductor layer 230a can be formed using an ALD method. The semiconductor layer 230b can be formed by a method with lower coverage than the semiconductor layer 230b. For example, the semiconductor layer 230a is formed by an ALD method, and the semiconductor layer 230b is formed by a sputtering method. Here, if a method with low coverage is used for the semiconductor layer 230b, the semiconductor layer 230b may not be easily formed in the region 279, as described in FIG. 5B .

[0114] Note that the semiconductor layer 230b can be formed by a method with high coverage. For example, the semiconductor layer 230b can be formed by an ALD method.

[0115] The semiconductor layer 230b may also have a laminated structure of two or more layers, for example, a first layer formed by sputtering and a second layer formed by ALD.

[0116] Here, when the semiconductor layer 230a and the semiconductor layer 230b are both metal oxides, the semiconductor layer formed by the ALD method may be amorphous. Furthermore, the semiconductor layer formed by the sputtering method may have crystallinity. For example, when the semiconductor layer 230a is formed by the ALD method and the semiconductor layer 230b is formed by the sputtering method, the semiconductor layer 230a may be amorphous and the semiconductor layer 230b may have crystallinity.

[0117] In addition, when the semiconductor layer 230a or the semiconductor layer 230b has a stacked structure, semiconductor layers formed by different methods may be stacked.

[0118] For example, the semiconductor layer 230b can have a laminated structure of a layer formed by sputtering and a layer formed thereon by ALD.

[0119] Here, the semiconductor layer 230 formed in the region 279 may be, for example, amorphous.

[0120] 6A is different from FIG. 1B mainly in that the insulating layer 282 has a two-layer laminated structure of an insulating layer 282a and an insulating layer 282b on the insulating layer 282a. Also, FIG. 6B shows an enlarged view of the area surrounded by the dashed line in FIG. 6A. Note that a further laminated structure may be provided above the positions of the insulating layers 282a and 282b.

[0121] 6B, the width of region 289 is smaller than the thickness of insulating layer 282a, and insulating layer 282a is formed so as to fill region 289. Insulating layer 282b is provided in contact with the upper surface of insulating layer 282a.

[0122] 6C shows a modification of Fig. 6B. In Fig. 6C, the insulating layer 282a is provided in a region 289 so as to be in contact with the top surface of the semiconductor layer 230, the side surface of the insulating layer 281, and the side surface of the insulating layer 250. Furthermore, since the thickness of the insulating layer 282a is small relative to the width of the region 289 and the insulating layer 282a does not fill the entire region 289, the insulating layer 282b is also provided in the region 289.

[0123] If the coverage of the insulating layer 282b is low, the insulating layer 282b may not easily enter the region 289, and voids may be formed in the region 289, as shown in FIG. 6D.

[0124] 7A to 7C show an example in which the angle between the side surface of the opening 290 and the top surface of the conductive layer 220 and the angle between the side surface of the opening 290b and the top surface of the conductive layer 220 are each less than 90 degrees. In such a case, the width of the opening 290b is wider than the width of the opening 290. FIG. 7A is a plan view of a semiconductor device including a transistor 200. FIG. 7B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 7A. FIG. 7C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in FIG. 7A. Note that because the opening 290b and the opening 290 are formed using the same mask, when the top surfaces of the opening 290 and the opening 290b are both circular, the opening 290b is, for example, concentric with the opening 290. Note that when the angle between the side surface of the opening 290b and the top surface of the conductive layer 220 is less than 90 degrees, the conductive layer 260 and the conductive layer 240 may overlap in a plan view.

[0125] 8A to 8C are different from FIG. 1B mainly in that an insulating layer 235 and a conductive layer 255 are included. FIG. 8A is a plan view of a semiconductor device including a transistor 200. FIG. 8B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 8A. FIG. 8C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in FIG. 8A.

[0126] The conductive layer 255 is provided so as to be embedded in the insulating layer 280b. 8B and 8C show an example in which the insulating layer 280b has a stacked structure of an insulating layer 280b1 located below the conductive layer 255 and an insulating layer 280b2 located above the conductive layer 255.

[0127] The conductive layer 255 has a region overlapping with the semiconductor layer 230 with the insulating layer 235 sandwiched therebetween. The insulating layer 235 is provided so as to cover the side surfaces of the opening 290 of the insulating layer 280. The insulating layer 235 has a region sandwiched between the semiconductor layer 230 and the conductive layer 255 and a region sandwiched between the semiconductor layer 230 and the insulating layer 280. The insulating layer 235 may also have a region covering the side surfaces of the opening 290 of the conductive layer 240. However, it is preferable that the upper end of the insulating layer 235 is lower than the height of the upper surface of the conductive layer 240.

[0128] The conductive layer 255 can function as a second gate electrode, and the insulating layer 235 can function as a second gate insulating layer.

[0129] <OS Transistor> The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 230 including a channel formation region. That is, the transistor 200 is preferably an OS transistor.

[0130] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V ＯH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0131] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance compared to a channel formation region, and the source and drain regions of the OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0132] In the OS transistor, a region of the semiconductor layer 230 in contact with the insulating layer 280 and its vicinity function as a channel formation region of the transistor 200. One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0133] In an OS transistor, when the semiconductor layer 230 and the conductive layer 220 are in contact with each other, a metal compound or oxygen vacancies are formed, and the region of the semiconductor layer 230 in contact with the conductive layer 220 has low resistance. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220. Similarly, when the semiconductor layer 230 and the conductive layer 240 are in contact with each other, the region of the semiconductor layer 230 in contact with the conductive layer 240 has low resistance. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 240.

[0134] It is also preferable that the resistance of the region of the semiconductor layer 230 that is in contact with the conductive layer 240 is reduced. When the semiconductor layer 230 is in contact with the conductive layer 240, a metal compound or oxygen vacancy is formed, and the resistance of the region of the semiconductor layer that is in contact with the conductive layer 240 can be reduced.

[0135] As shown in Figures 1A to 1C, when the semiconductor layer 230 is provided to cover the entire side surface of the insulating layer 280 in the opening 290 and the conductive layer 260 is provided to cover the entire surface via the insulating layer 250, the channel formation region of the transistor 200 can be formed in the entire region of the semiconductor layer 230 in contact with the insulating layer 280 within the opening 290.

[0136] 1A to 1C , for example, the channel length of the transistor 200 is the distance between the source region and the drain region. That is, in the configuration shown in FIGS. 1A to 1C , for example, the channel length of the transistor 200 can be determined by the thickness of the insulating layer 280 on the conductive layer 220. The channel length is the distance, in a cross-sectional view, between the edge of the region where the semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 240 contact each other. That is, the channel length corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side, in a cross-sectional view.

[0137] Alternatively, when the resistance of a region of the semiconductor layer 230 near the conductive layer 220 is reduced, the region can function as a source region or a drain region, rather than as a channel formation region.

[0138] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in the transistor included in the semiconductor device of one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure equal to or less than the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). Specifically, for example, the channel length of the transistor of one embodiment of the present invention can be made smaller than the minimum dimensions of the width of a conductive layer or the like in a plan view of the semiconductor device, the distance between two conductive layers or the like, the width of an opening in an insulating layer or the like, and the like. This increases the on-state current of the transistor 200, thereby improving frequency characteristics.

[0139] The channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by, for example, the thickness of the insulating layer 280 over the conductive layer 220. Therefore, even when the channel length is set to 60 nm or more, the area occupied by the transistor, specifically, for example, the area of ​​the transistor as viewed from above, is roughly determined by the width of the opening 290. As will be described later, the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. For example, even when the channel length is set to 150 nm, the width of the opening 290 can be set to be narrower than 150 nm. That is, the width of the opening can be narrower than the channel length of the transistor, which reduces the area occupied by the transistor and enables high integration of the semiconductor device.

[0140] Note that by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0141] Therefore, the channel length of a transistor included in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0142] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0143] 1A to 1C , the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in plan view). Increasing the width of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0144] When the opening 290 is formed using photolithography, the width D of the opening 290 is equal to or greater than the minimum dimension limited by the exposure limit of photolithography. The width D of the opening 290 is set depending on the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width of the opening 290 corresponds to the diameter of the opening 290, and the channel width is the circumferential length.

[0145] The channel length of the transistor 200 is preferably at least shorter than the channel width of the transistor 200. The channel length of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0146] Furthermore, by forming the opening 290 so as to have a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 230 approximately uniform, allowing a gate electric field to be applied to the semiconductor layer 230 approximately uniformly.

[0147] It should be noted that the shape of the opening 290 is not limited to a circle in plan view, and may be, for example, a substantially circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners.

[0148] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0149] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 282, insulating layer 284, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0150] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0151] Specifically, it is preferable to use a barrier insulating layer against impurities such as water and hydrogen, and oxygen.

[0152] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse, a property that makes it difficult for a corresponding substance to permeate, a property that makes it low permeable to a corresponding substance, a function to suppress the diffusion of a corresponding substance, or a function to suppress the permeation of a corresponding substance. Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0153] Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Other examples include oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0154] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0155] Furthermore, for example, as transistors become more miniaturized, thinner gate insulating layers can cause problems such as leakage current. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. Furthermore, using a material with a high dielectric constant as the dielectric layer of a capacitive element allows for an element with a larger capacitance value. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0156] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0157] Examples of materials with a low dielectric constant include resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0158] Furthermore, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be applied to both layers in which a material with a high dielectric constant is preferably used, such as a gate insulating layer, and layers in which a material with a low dielectric constant is preferably used, such as an interlayer film. These materials have a relatively low dielectric constant compared to high-k materials such as hafnium oxide, and therefore may be referred to as "materials with a low dielectric constant" in this specification and the like.

[0159] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. Ferroelectric materials include hafnium ... (here, element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0160] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0161] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0162] Although metal oxides and metal nitrides have been described above as examples of materials that can have ferroelectricity, the materials are not limited to these. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, may also be used.

[0163] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0164] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0165] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer. Also, in this specification, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

[0166] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0167] The insulating layer 250 functions as a gate insulating layer of the transistor 200. For the insulating layer 250, a material with a high dielectric constant is preferably used.

[0168] The insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration, particularly in the channel formation region of the semiconductor layer of the transistor. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0169] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing magnesium. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with amorphous structures have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0170] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0171] When the insulating layer 250 has a stacked-layer structure, it is preferable to use a layer having a function of capturing and fixing hydrogen as one of the layers (hereinafter referred to as a first insulating layer of the insulating layer 250).

[0172] The insulating layer 250 may be made of, for example, hafnium silicate as the first insulating layer. The first insulating layer of the insulating layer 250 preferably has an amorphous structure. The amorphous structure can suppress the formation of grain boundaries. Suppressing the formation of grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, reducing areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. Furthermore, the film thickness distribution of the film provided on the insulating layer can be made uniform.

[0173] Furthermore, by suppressing the formation of grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries, and thus the insulating layer can function as an insulating film with low leakage current.

[0174] Furthermore, since hafnium oxide is a material with a high dielectric constant, hafnium silicate can also be a material with a high dielectric constant depending on the silicon content. Therefore, when used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0175] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the first insulating layer of the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0176] Furthermore, the insulating layer 250 preferably includes a hydrogen barrier insulating layer as a second insulating layer in addition to the first insulating layer. By using a hydrogen barrier insulating layer as the second insulating layer of the insulating layer 250, impurities contained in the conductive layer 260 can be prevented from diffusing into layers below the insulating layer 250 in the transistor 200. Silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Examples of materials for the hydrogen barrier insulating layer include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Here, the second insulating layer is preferably an upper layer of the first insulating layer.

[0177] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0178] The insulating layer 250 preferably includes a layer capable of supplying oxygen. An oxide can be used as the layer capable of supplying oxygen. When the insulating layer 250 includes silicon oxide or silicon oxynitride, oxygen can be suitably supplied from the insulating layer 250 to the semiconductor layer 230. Furthermore, since a material such as silicon oxide or silicon oxynitride has a structure that is stable against heat, it can be suitably used as the insulating layer 250.

[0179] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0180] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 260, and the like. When the insulating layer 250 has a stacked structure, it is preferable that the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 each be a barrier insulating layer against oxygen.

[0181] The layer of the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280. The layer has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0182] For example, by using a barrier insulating layer against hydrogen and oxygen as the second insulating layer, it is possible to suppress oxidation of the conductive layer 260. In addition, it is possible to suppress the oxygen contained in the semiconductor layer 230 from diffusing into the conductive layer 260 and the formation of oxygen vacancies in the semiconductor layer 230.

[0183] Examples of the barrier insulating layer against oxygen include oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0184] Hafnium and silicon oxides (hafnium silicates) function as a barrier insulating layer against oxygen, and as mentioned above, they are also excellent insulating layers that can easily achieve an amorphous structure and have the ability to capture or fix hydrogen.

[0185] Furthermore, silicon nitride is an excellent insulating layer that not only functions as a barrier insulating layer against oxygen but also has high barrier properties against hydrogen, as described above.

[0186] The insulating layer 250 preferably has a two-layer structure in which, from the semiconductor layer 230 side, a first insulating layer having a function of capturing or fixing hydrogen and a second insulating layer having barrier properties against hydrogen and oxygen are stacked in this order.

[0187] For example, the first insulating layer can be made of an oxide containing one or both of aluminum and hafnium, and the second insulating layer can be made of silicon nitride.

[0188] Furthermore, the insulating layer 250 preferably has a three-layer structure in which, from the semiconductor layer 230 side, a third insulating layer made of a material with a relatively low dielectric constant, a first insulating layer having the function of capturing or fixing hydrogen, and a second insulating layer having barrier properties against hydrogen and oxygen are stacked in this order. The material with a relatively low dielectric constant of the third insulating layer refers, for example, to a material with a lower dielectric constant than any one or more of the other layers in the stacked structure. Here, an oxide can be used as the third insulating layer. Here, for example, silicon oxide or silicon oxynitride is used. Furthermore, providing a second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230 can be suppressed.

[0189] As an example, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0190] The insulating layer 250 preferably has a four-layer structure in which, from the semiconductor layer 230 side, a fourth insulating layer having a barrier property against oxygen, a third insulating layer made of a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. The first to third insulating layers can have a structure similar to that of the layers used in the three-layer structure described above. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, making it suitable for the fourth insulating layer in contact with the semiconductor layer 230.

[0191] As an example, aluminum oxide can be used as the fourth insulating layer, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0192] In the insulating layer 250, the thickness of the region overlapping with the channel formation region of the semiconductor layer 230 is preferably 0.1 nm to 30 nm, more preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 8.0 nm, and still more preferably 0.5 nm to 7.0 nm.

[0193] In order to miniaturize transistors, it is preferable that the thickness of each layer constituting the insulating layer 250 is thin. For example, the thickness of each layer constituting the insulating layer 250 is 0.1 nm to 10 nm, or 0.1 nm to 5 nm, or 0.5 nm to 5 nm, or 1 nm to less than 5 nm, or 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0194] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized.

[0195] The insulating layer 280 preferably has the aforementioned barrier insulating layer against hydrogen. The insulating layer 280 is provided so as to surround the semiconductor layer 230. The insulating layer 280 provided on the outside of the semiconductor layer 230 has barrier properties against hydrogen, thereby suppressing diffusion of hydrogen into the semiconductor layer 230. For example, the insulating layer 280 preferably has a silicon nitride film.

[0196] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be prevented from being extracted from the semiconductor layer 230, and excessive oxygen vacancies can be prevented from being formed in the semiconductor layer 230.

[0197] Furthermore, using silicon nitride for the insulating layer 280 can prevent excess oxygen from being supplied to the semiconductor layer 230. Therefore, excess oxygen can be prevented from being contained in the channel formation region of the semiconductor layer 230, which can improve the reliability of the transistor 200.

[0198] The insulating layer 280 preferably includes the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0199] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 in this manner, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 230. Therefore, when a metal oxide is used for the semiconductor layer 230, oxygen vacancies and VoH can be reduced.

[0200] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200.

[0201] The insulating layer 280 can also have a stacked structure of two or more layers. For example, the insulating layer 280 can have a structure in which a second layer that supplies oxygen is sandwiched between a first layer and a third layer that have a barrier property against oxygen. By configuring the insulating layer 280 in this manner, oxygen can be supplied to the channel formation region of the semiconductor layer 230, and the conductive layer 220 and the conductive layer 240 can be prevented from being oxidized by oxygen from the second layer, thereby preventing an increase in resistance.

[0202] The second layer of the insulating layer 280 preferably has a region with a higher oxygen content than at least one of the first layer and the third layer of the insulating layer 280 .

[0203] It is more preferable to use a film that releases oxygen by heating as the second layer of the insulating layer 280. By releasing oxygen by heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 230.

[0204] To improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0205] As an example, the amount of oxygen molecules released from the second insulating layer is 1.0×10 １４ molecules / cm ２ That's it, 1.0 x 10 １５ molecules / cm ２ The amount of released oxygen molecules can be measured by thermal desorption spectroscopy.

[0206] In particular, when the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and V Ｏ The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the semiconductor layer 230 and then optimizing the amount of oxygen supplied to the semiconductor layer 230, a transistor with a short channel length that has good electrical characteristics and high reliability can be realized, particularly when a metal oxide is used as the semiconductor layer 230.

[0207] Furthermore, the amount of oxygen supplied to the region of the semiconductor layer 230 that is in contact with the first layer of the insulating layer 280 and the region that is in contact with the third layer of the insulating layer 280 is smaller than that to the region that is in contact with the second layer of the insulating layer 280. Therefore, particularly when a metal oxide is used as the semiconductor layer 230, the region of the semiconductor layer 230 that is in contact with the first layer of the insulating layer 280 and the region that is in contact with the third layer of the insulating layer 280 may have low resistance.

[0208] Furthermore, it is preferable to use a material with a low relative dielectric constant for the second layer of the insulating layer 280. This can reduce the parasitic capacitance that occurs between wirings. For example, silicon oxide or silicon oxynitride can be used.

[0209] Alternatively, an insulating layer having a function of trapping or fixing hydrogen may be used as the first layer of the insulating layer 280. With such a structure, diffusion of hydrogen from below the first layer of the insulating layer 280 to the semiconductor layer or the like of the transistor 200 can be suppressed, and hydrogen contained in the semiconductor layer or the like of the transistor 200 can be trapped or fixed. For example, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon can be used. Alternatively, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used. Similarly, an insulating layer having a function of trapping or fixing hydrogen may be used as the third layer of the insulating layer 280.

[0210] The insulating layer 281 can be made of a material that can be used for the insulating layer 280 .

[0211] The insulating layer 281 may have a stacked structure. In the case where the insulating layer 281 is in contact with the semiconductor layer 230, a material that can be used as the third layer of the insulating layer 280, for example, a layer with a relatively low oxygen content, can be applied to the layer of the insulating layer 281 that is in contact with the semiconductor layer 230. In such a case, the amount of oxygen supplied to the semiconductor layer 230 is reduced, and the resistance of the semiconductor layer 230 may be reduced.

[0212] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0213] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200.

[0214] Furthermore, by using a barrier insulating layer against hydrogen as the insulating layer 210, diffusion of hydrogen into a semiconductor layer or the like included in the transistor 200 can be suppressed.

[0215] At least one of the insulating layers 282 and 284 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 282 or the insulating layer 284 into a semiconductor layer or the like included in the transistor 200.

[0216] In addition, one or more of the insulating layers 282 and 284 may include an insulating layer having a function of capturing or fixing hydrogen.

[0217] Furthermore, the insulating layers 282 and 284 may contain, for example, a material with a low relative dielectric constant. By using a material with a low relative dielectric constant as an interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0218] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layers 282 and 284. This can prevent impurities such as water and hydrogen from entering the semiconductor layers of the transistor 200.

[0219] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 241, conductive layer 242, etc.) included in the semiconductor device preferably contain a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium, and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0220] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0221] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0222] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0223] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0224] The conductive layer 260 can be made of the above-mentioned metal elements, alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. For example, it is preferable to use a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. As described above, examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 260.

[0225] The conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Nitrogen-containing indium gallium zinc oxide may also be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0226] The conductive layer 260 may have a thickness of, for example, 3 nm or more and 500 nm or less. The thickness of the conductive layer 260 may be, for example, equal to or greater than the thickness of the insulating layer 250. By making the conductive layer 260 thicker, the resistance of the conductive layer 260 can be reduced.

[0227] The conductive layer 260 may have a stacked structure. For example, a conductive material containing nitrogen, a conductive material containing oxygen, or the like can be used as the first layer of the conductive layer 260. Alternatively, for example, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed can be used. Furthermore, for example, the second layer on the first layer of the conductive layer 260 can be made of the aforementioned metal elements, alloys containing the aforementioned metal elements, or alloys combining the aforementioned metal elements. For example, tungsten can be used.

[0228] The conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with a semiconductor layer included in the transistor 200. In particular, when a metal oxide is used as the semiconductor layer, each of the conductive layer 220 and the conductive layer 240 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0229] By using a conductive material containing oxygen for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0230] When the conductive layer has a two-layer structure of a first conductive layer and a second conductive layer formed in this order on the insulating layer 210, it is preferable to use a highly conductive material for the first conductive layer and a conductive material containing oxygen for the second conductive layer. A third conductive layer may be provided between the insulating layer 210 and the first conductive layer. For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the third conductive layer. Specifically, it is preferable to use titanium nitride for the third conductive layer, tungsten for the first conductive layer, and ITO or ITSO for the second conductive layer. By using such a material for the second conductive layer in contact with the semiconductor layer 230 or the like, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer. Furthermore, when an oxide insulating layer is used for the insulating layer 210, the insulating layer 210 can prevent the conductive layer 220 from being excessively oxidized. Furthermore, when tungsten, which has high conductivity, is used for the second conductive layer, the conductivity of the conductive layer 220 can be increased.

[0231] When the conductive layer 240 has a stacked structure, for example, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion can be used as a layer that is mainly in contact with the semiconductor layer.

[0232] When the conductive layer 240 has a two-layer laminated structure, for example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the upper layer, and it is preferable to use a material with high conductivity for the lower layer.

[0233] It is preferable to use ITO or ITSO as the first conductive layer of the conductive layer 240. It is also preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the second conductive layer and the third conductive layer of the conductive layer 240.

[0234] [Semiconductor Layer 230] As described above, the semiconductor layer 230 has a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type.

[0235] The semiconductor layer 230 may also have an n-type region (low-resistance region) having a higher carrier concentration than the channel formation region. The n-type region may function as a source region or a drain region.

[0236] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0237] Metal oxides that can be used as the semiconductor layer 230 will be described below.

[0238] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because of the low off-state current of an OS transistor, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has a high withstand voltage between the source and drain, it can be suitably applied to circuits that handle high voltages. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0239] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of element M include gallium, tin, aluminum, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0240] Examples of metal oxides include indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO). Examples of usable oxides include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), or the like can be used. Alternatively, the above oxides having an amorphous structure can be used. For example, indium oxide having an amorphous structure, indium tin oxide having an amorphous structure, or the like can be used.

[0241] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0242] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0243] The metal oxide may also contain one or more nonmetallic elements. The presence of a nonmetallic element in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0244] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0245] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, a metal oxide with a wide band gap can be obtained. Furthermore, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, resulting in a transistor with a low off-state current. Furthermore, a shift in the threshold voltage of the transistor can be suppressed. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0246] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer of the transistor. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0247] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:1:2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions close to these. Note that the term "nearby composition" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of the transistor can be increased.

[0248] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0249] When the element M contains a plurality of metal elements, the total proportion of the number of atoms of the metal elements can be used as the proportion of the number of atoms of the element M.

[0250] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements.

[0251] Furthermore, when the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements in the In-Zn oxide may be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, or a composition in the vicinity thereof. The In-Zn oxide may also contain a trace amount of element M. For example, the atomic ratio may be In:M:Zn = 2:0.1:1, In:M:Zn = 4:0.1:1, or a composition in the vicinity thereof. Here, gallium, tin, or the like can be suitably used as the element M.

[0252] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. Furthermore, it may be difficult to quantify element M, or element M may not be detected.

[0253] For forming the metal oxide, atomic layer deposition (ALD) or sputtering can be suitably used. When forming the metal oxide by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the content of zinc in the metal oxide after film formation may decrease to about 50% compared to the target. For forming the metal oxide film, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or the like may also be used.

[0254] The semiconductor layer 230 may have a stacked structure of two or more oxide layers. By using a material with high conductivity for the oxide layer (hereinafter referred to as a first oxide layer) close to the source and drain electrodes (the conductive layer 220 and the conductive layer 240), the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor with a large on-state current can be obtained.

[0255] Here, if a material with high conductivity is used for the oxide layer (hereinafter referred to as the second oxide layer) provided on the conductive layer 260 side that functions as the gate electrode, the threshold voltage of the transistor 200 may shift, and the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage is 0 V may become large. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with relatively low conductivity for the second oxide layer. As a result, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.

[0256] A first oxide layer can be applied to semiconductor layer 230a, and a second oxide layer can be applied to semiconductor layer 230b.

[0257] The carrier concentration of the first oxide layer is preferably relatively high. Increasing the carrier concentration increases the conductivity, which can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240. In addition, decreasing the carrier concentration of the second oxide layer decreases the conductivity, which can provide a normally-off transistor.

[0258] The conductivity and carrier concentration of the two oxide layers of the semiconductor layer 230 are not limited to the above-described configuration.

[0259] The band gap of the first metal oxide used in the first oxide layer is preferably different from the band gap of the second metal oxide used in the second oxide layer. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0260] The band gap of the first metal oxide is preferably smaller than the band gap of the second metal oxide. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240, thereby providing a transistor with a large on-state current. Furthermore, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, making it a normally-off transistor. Furthermore, the large band gap of the second metal oxide can suppress generation and induction of carriers in the second oxide layer and at the interface between the second oxide layer and the insulating layer 250. This can improve the reliability of the transistor.

[0261] For example, it is preferable that the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide. More specifically, it is preferable that the first metal oxide has a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, and the second metal oxide has a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition thereabout. In this case, it is particularly preferable to use one or more of gallium, aluminum, and tin as the element M.

[0262] The semiconductor layer 230 is not limited to the above-described configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0263] Furthermore, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. The first metal oxide may contain a trace amount of element M or may not contain element M at all. For example, it is preferable that the first metal oxide be an In-Zn oxide and the second metal oxide be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide and the second metal oxide may be an In-Ga-Zn oxide.

[0264] For example, the first metal oxide may be a metal oxide having an In:Zn=1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Zn=2:1 atomic ratio or a composition thereabout, a metal oxide having an In:M:Zn=2:0.1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Zn=4:1 atomic ratio or a composition thereabout, a metal oxide having an In:M:Zn=4:0.1:1 atomic ratio or a composition thereabout, or an indium oxide. Gallium, tin, or the like can be suitably used as the element M of the first metal oxide. The second metal oxide is preferably a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar ratio, a metal oxide having an atomic ratio of In:M:Zn=1:3:2 or a similar ratio, or a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar ratio. Gallium can be preferably used as the element M of the second metal oxide. This increases the on-state current of the transistor 200 and provides a highly reliable transistor structure with minimal variation.

[0265] For example, it is preferable to use a metal oxide having an In:M:Zn = 1:3:2 (atomic ratio) or a metal oxide having an In:M:Zn = 1:3:4 (atomic ratio) or a metal oxide having an In:M:Zn = 1:1:1 (atomic ratio) or a metal oxide having an In:M:Zn = 1:1:1 (atomic ratio) or a metal oxide having an In:M:Zn = 1:1:1 (atomic ratio) or a metal oxide having an In:M:Zn = 1:1:1 (atomic ratio) or a metal oxide having an In:M:Zn = 1:1:1 (atomic ratio) as the first metal oxide. Using a metal oxide with a high In / Zn ratio can enhance the crystallinity of the first oxide layer. Furthermore, forming a second oxide layer on a highly crystalline first oxide layer also facilitates enhancing the crystallinity of the second oxide layer. This enhances the crystallinity of the entire semiconductor layer 230, which is preferable. In this case, it is particularly preferable to use gallium, aluminum, or tin as the element M. For example, two layers of IGZO having different compositions may be stacked. Alternatively, for example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0266] The semiconductor layer 230 is not limited to the above-described configuration, and the content of the element M in the first metal oxide may be higher than the content of the element M in the second metal oxide.

[0267] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0268] The semiconductor layer 230 preferably includes a crystalline metal oxide layer. Examples of crystalline metal oxide structures include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide layer for the semiconductor layer 230, the density of defect states in the semiconductor layer 230 can be reduced, resulting in a highly reliable semiconductor device. The CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in a layered manner in the crystalline portion. Therefore, an OS film having a CAAC structure can also be said to have a layered crystalline portion. Here, the direction of the c-axis of the CAAC structure may be, for example, perpendicular or approximately perpendicular to the surface on which the CAAC structure is formed.

[0269] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystal portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure, and therefore can realize a highly reliable semiconductor device.

[0270] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 230, the more the density of defect states in the semiconductor layer 230 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0271] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during the formation (hereinafter also referred to as oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0272] The crystallinity of the semiconductor layer 230 can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0273] The semiconductor layer 230 can have a stacked structure of two or more oxide layers with different crystallinity. In this case, the two or more oxide layers may have different compositions or may have the same or approximately the same composition. For example, the semiconductor layer 230 can have a stacked structure of a first oxide layer and a second oxide layer provided on the first oxide layer, and the second oxide layer can have a region with higher crystallinity than the first oxide layer. Alternatively, the second oxide layer can have a region with lower crystallinity than the first oxide layer. Note that when the second oxide layer has a region with lower crystallinity than the first oxide layer, the crystallinity of the second oxide layer can be increased by performing heat treatment (also referred to as crystallization treatment) after forming the second oxide layer.

[0274] The semiconductor layer 230 may have a stacked structure of three or more layers. For example, the semiconductor layer 230 may have a third oxide layer in addition to the first oxide layer and second oxide layer described above. It is preferable that the first oxide layer is provided on the third oxide layer, and the second oxide layer is provided on the first oxide layer.

[0275] The third oxide layer located below the first oxide layer can have the same structure as that applicable to the second oxide layer. Hereinafter, they will be collectively described as a pair of oxide layers (second oxide layer and third oxide layer) sandwiching the first oxide layer.

[0276] The semiconductor layer 230a may be a third oxide layer, and the semiconductor layer 230b may be a stacked structure of the first oxide layer and the second oxide layer. Alternatively, the semiconductor layer 230a may be a stacked structure of the third oxide layer and the first oxide layer, and the semiconductor layer 230b may be a second oxide layer.

[0277] For example, the first oxide layer may be formed of a metal oxide having an atomic ratio of In:Zn=1:1 or a similar ratio, an In:Zn=2:1 or a similar ratio, an In:Sn:Zn=2:0.1:1 or a similar ratio, an In:Zn=4:1 or a similar ratio, an In:Sn:Zn=4:0.1:1 or a similar ratio, or an indium oxide. The pair of oxide layers sandwiching the first oxide layer may be formed of a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio, an In:Ga:Zn=1:3:2 or a similar ratio, or an In:Ga:Zn=1:3:4 or a similar ratio, respectively.

[0278] Preferably, each of the pair of oxide layers sandwiching the first oxide layer has a band gap larger than that of the first oxide layer. As a result, the first oxide layer is sandwiched between the pair of oxide layers with a larger band gap, and the first oxide layer functions primarily as a current path (channel). By sandwiching the first oxide layer between the pair of oxide layers, trap levels at and near the interface of the first oxide layer can be reduced. This allows for a buried channel transistor in which the channel is spaced away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the influence of interface states that may form on the back channel side can be reduced, suppressing photodegradation (e.g., photodegradation due to negative bias current) of the transistor and improving the reliability of the transistor.

[0279] When the semiconductor layer 230 has a two-layer stacked structure, the ALD method can be preferably used to form the first oxide layer and the sputtering method can be preferably used to form the second oxide layer on the first oxide layer. Forming the second oxide layer by sputtering can enhance the crystallinity compared to the first oxide layer. Furthermore, performing heat treatment after the formation of the second oxide layer can further enhance the crystallinity of the first oxide layer and the second oxide layer. In this case, crystals contained in the second oxide layer may grow continuously toward the first oxide layer, making it difficult to clearly identify the boundary between the first oxide layer and the second oxide layer. It is particularly preferable that the second metal oxide layer have a CAAC structure.

[0280] Furthermore, when the semiconductor layer 230 has a three-layer stack structure, the ALD method can be suitably used to form the third oxide layer, the sputtering method can be used to form the first oxide layer on the third oxide layer, and the ALD method can be used to form the second oxide layer on the first oxide layer. Forming the first oxide layer by sputtering can improve the crystallinity compared to the third oxide layer. Heat treatment performed after the formation of the second oxide layer can improve the crystallinity of the third oxide layer, the first oxide layer, and the third oxide layer. In this case, crystals contained in the first oxide layer grow continuously toward the third oxide layer and the second oxide layer, and the boundary between the third oxide layer and the first oxide layer and the boundary between the first oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the first oxide layer have a CAAC structure.

[0281] The two or more oxide layers in the semiconductor layer 230 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, the layers can be formed using the same sputtering target, for example, which reduces manufacturing costs. When the two or more oxide layers in the semiconductor layer 230 have the same or substantially the same composition, the boundaries (interfaces) between these oxide layers may not be clearly visible.

[0282] By stacking an oxide layer with low crystallinity and an oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. This allows for a highly reliable transistor to be realized. The thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the semiconductor layer is formed. A metal oxide layer with increased crystallinity in this manner can be called an axial growth CAAC (AG CAAC). In addition to the crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the semiconductor layer is formed.

[0283] The temperature of the heat treatment is preferably 100°C or higher and 800°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 550°C or lower. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C or higher and 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by thermal conduction or thermal radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0284] The thickness of the semiconductor layer 230 is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, further preferably 20 nm to 50 nm. In a transistor used in a finer semiconductor device, the film thickness of the semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and 20 nm to 15 nm, 12 nm to 10 nm.

[0285] Hydrogen contained in the oxide semiconductor reacts with oxygen that bonds to metal atoms to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (i.e., a negative threshold voltage). Furthermore, hydrogen atoms in an oxide semiconductor are easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0286] In the channel formation region of the semiconductor layer, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies. Ｏ Stable electrical characteristics can be obtained by using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies is sometimes referred to as oxygen-adding treatment.

[0287] The carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0288] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0289] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0290] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0291] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10１８ atoms / cm ３ Less than.

[0292] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0293] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0294] Note that the semiconductor device of this embodiment may also be applied to a transistor using a material other than metal oxide in the channel formation region. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide, silicon germanium, indium phosphide, silicon carbide, boron nitride, and boron arsenide. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the above-mentioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0295] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0296] The semiconductor layer of a transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0297] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0298] [Substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0299] <Example of Manufacturing Method of Semiconductor Device> Thin films (insulating films, semiconductor films, conductive films, and the like) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a PLD method, an ALD method, or the like.

[0300] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF-superimposed DC sputtering, which superimposes RF and DC, is also available. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used when forming films using conductive targets. DC sputtering can also form insulating films by reactive sputtering, in addition to forming conductive films. Pulsed DC sputtering is primarily used when depositing films of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows for control of ion energy and target potential during film formation. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Furthermore, high-quality films can be obtained.

[0301] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is achieved by self-bias or the like. In addition, long-throw sputtering can form anisotropic films by increasing the distance between the sputtering target and the substrate.

[0302] CVD methods can be classified into PECVD, thermal CVD (TCVD) using heat, photo CVD (Photo CVD) using light, etc. They can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0303] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0304] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0305] Furthermore, the ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The PEALD (Plasma Enhanced ALD) method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0306] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0307] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0308] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0309] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0310] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0311] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0312] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0313] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0314] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0315] 9A to 12D , an example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. In each figure, drawings labeled A and C correspond to the dashed-dotted line A1-A2 in FIG. 1A , and drawings labeled B and D correspond to the dashed-dotted line A3-A4 in FIG. 1A .

[0316] First, an insulating layer 210 is formed on a substrate.

[0317] Next, a conductive layer 220 is formed over the insulating layer 210. Here, an example is shown in which the conductive layer 220 has a stacked structure of a conductive layer 220a and a conductive layer 220b over the conductive layer 220a.

[0318] Next, an insulating layer 280 is formed over the insulating layer 210 and the conductive layer 220. After the insulating layer 280 is formed, the top surface thereof may be planarized by planarization treatment. Here, an example is shown in which the insulating layer 280 has a stacked structure of an insulating layer 280a, an insulating layer 280b over the insulating layer 280a, and an insulating layer 280c over the insulating layer 280b.

[0319] Next, a conductive layer that will become the conductive layer 240 and a layer that will become the sacrificial layer 236 are formed in this order over the insulating layer 280. Next, a mask is used to remove part of the layer that will become the sacrificial layer 236, thereby forming the sacrificial layer 236. After that, a mask is used to remove part of the conductive layer that will become the conductive layer 240, thereby forming the conductive layer 240 ( FIGS. 9A and 9B ). The sacrificial layer 236 is provided in a region where the semiconductor layer 230 will be formed later. Therefore, the thickness of the sacrificial layer 236 may be set to, for example, a thickness that is preferable for the semiconductor layer 230. For example, the thickness of the sacrificial layer 236 is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 5 nm to 100 nm, still more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, still more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, and even more preferably 20 nm to 50 nm.

[0320] The sacrificial layer 236 is preferably made of a material that can be etched with a wet etching solution. Wet etching allows etching with a high selectivity, and when etching the sacrificial layer 236, the etching selectivity with respect to the conductive layer 220, the conductive layer 240, etc. is high. Here, a high etching selectivity means that the etching rate of the conductive layer 220, the conductive layer 240, etc. is lower than the etching rate of the sacrificial layer 236, and etching of the conductive layer 220, the conductive layer 240 can be suitably suppressed.

[0321] The sacrificial layer 236 may be any of the insulating layers listed above. Alternatively, the sacrificial layer 236 may be any of the metal oxides listed above. Alternatively, the sacrificial layer 236 may be a metal film or an alloy film. Alternatively, the sacrificial layer 236 may be made of a combination of two or more materials selected from these materials.

[0322] For example, aluminum oxide can be used as the sacrificial layer 236. Alternatively, In—Ga—Zn oxide can be used as the sacrificial layer 236.

[0323] Here, the conductive layer 240 and the sacrificial layer 236 can be formed using the same mask. By using the same mask, a structure can be achieved in which the end of the conductive layer 240 on the opposite side of the opening 290 and the end of the semiconductor layer 230 coincide or approximately coincide. By using the same mask, the manufacturing process can be simplified. Alternatively, different mask layers may be used to form the conductive layer 240 and the sacrificial layer 236. By using different mask layers, a structure can be achieved in which the end of the conductive layer 240 on the opposite side of the opening 290 and the end of the semiconductor layer 230 do not coincide. For example, a structure can be achieved in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240. Alternatively, for example, a structure can be achieved in which the end of the conductive layer 240 is located outside the end of the semiconductor layer 230.

[0324] Next, an insulating layer 281 is formed on the sacrificial layer 236 and the insulating layer 280 (FIGS. 9A and 9B).

[0325] Next, an opening 299 is formed using a mask (FIGS. 9C and 9D). The opening 299 is composed of an opening 290b formed in a region overlapping with the conductive layer 220 by removing a part of the insulating layer 281, an opening formed in a region overlapping with the conductive layer 220 by removing a part of the sacrificial layer 236, and an opening 290 formed in a region overlapping with the conductive layer 220 by removing a part of the conductive layer 240 and a part of the insulating layer 280.

[0326] Next, the sacrificial layer 236 is removed by etching to form regions 278, which may be voids, for example (FIGS. 10A and 10B).

[0327] The sacrificial layer can be etched using, for example, wet etching. In addition, as a chemical solution for wet etching the sacrificial layer 236, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a chemical solution using a mixture of these liquids can be used.

[0328] Next, a semiconductor layer 230f is formed to fill region 278. The semiconductor layer 230f is also formed to cover the sidewalls of opening 290b, the sidewalls of opening 290, the top surface of conductive layer 220, and the top surface of insulating layer 281 (FIGS. 10C and 10D). Here, the height of region 278 is extremely thin, approximately the thickness of sacrificial layer 236, compared to the depth of the opening in the Y direction. Therefore, region 278 where semiconductor layer 230f is formed can be said to be a region with a high aspect ratio. When forming semiconductor layer 230f to fill such a high aspect ratio region, it is preferable to use the ALD method as a method for forming semiconductor layer 230f. Region 279 of semiconductor layer 230f is a region formed to fill region 278.

[0329] Next, an insulating layer 250f is formed on the semiconductor layer 230f and the insulating layer 281. Next, a conductive layer 260f is formed on the insulating layer 250f (FIGS. 11A and 11B).

[0330] Next, a part of the conductive layer 260f, a part of the insulating layer 250f, and a part of the semiconductor layer 230f on the insulating layer 281 are sequentially removed by planarization treatment to form the conductive layer 260, the insulating layer 250, and the semiconductor layer 230g (FIGS. 11C and 11D). The planarization treatment removes the conductive layer 260f, the insulating layer 250f, and the semiconductor layer 230f on the insulating layer 281, exposing the top surface of the insulating layer 281. The planarization treatment also removes the conductive layer 260f, the insulating layer 250f, and the semiconductor layer 230f located outside the opening 290 in a planar view. CMP (Chemical Mechanical Polishing) treatment can be used for the planarization.

[0331] Next, a portion of the semiconductor layer 230g provided in the opening 290b, including a portion located at the upper end of the opening 290b, is removed by etching to form the semiconductor layer 230 ( FIGS. 12A and 12B ). The removed region is shown as region 288 in FIGS. 12A and 12B . Region 288 is, for example, a void. If region 288 were provided in a region of the semiconductor layer 230 that is lower than the top surface of the conductive layer 240, the region of the semiconductor layer 230 formed in contact with the top surface of the conductive layer 240 and the region provided in the opening 290 would not be continuous and would be discontinuous. Therefore, region 288 is provided in a region of the semiconductor layer 230 that is higher than the region formed in contact with the top surface of the conductive layer 240.

[0332] Next, an insulating layer 282 is formed over the insulating layer 281. The insulating layer 282 is preferably provided so as to fill the region 288. A region 289 of the insulating layer 282 is formed so as to fill the region 288.

[0333] Next, an insulating layer 284 is formed on the insulating layer 282 (FIGS. 12C and 12D).

[0334] Through the above steps, the semiconductor device shown in FIGS. 1B and 1C can be manufactured.

[0335] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0336] 13 to 26. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0337] 13A to 13C , the structure of a memory device including a transistor and a capacitor will be described. Fig. 13A is a plan view of a memory device including a transistor 200 and a capacitor 100. Fig. 13B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in Fig. 13A . Fig. 13C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in Fig. 13A .

[0338] 13A to 13C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180, an insulating layer 280, an insulating layer 281 over the conductive layer 110, and an insulating layer 282 and an insulating layer 284 over the memory cell 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 281, the insulating layer 282, and the insulating layer 284 function as interlayer films. The conductive layer 110 functions as a wiring.

[0339] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0340] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0341] As shown in FIGS. 13B and 13C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIGS. 13B and 13C , the conductive layer 120 is preferably provided so as to fill the opening 190. The films provided inside the opening 190 are preferably formed using a method with high coverage, such as an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed by an ALD method, a metal CVD method, or the like.

[0342] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote higher integration of memory devices.

[0343] 13B and 13C show an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a configuration, a memory device can be highly integrated.

[0344] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench capacitor or a trench capacitor.

[0345] An insulating layer 280 and an insulating layer 281 are disposed on the capacitor element 100 .

[0346] The structure of the transistor 200 described in Embodiment 1 can be applied to the transistor 200. Note that in the example shown in Figures 13B and 13C, the conductive layer 120 is used instead of the conductive layer 220 of the transistor 200 described in Embodiment 1. Note that the conductive layer 220 can be formed over the conductive layer 120 without omitting the conductive layer 220.

[0347] The transistor 200 can be described in Embodiment 1; therefore, detailed description thereof will be omitted.

[0348] As shown in FIGS. 13A to 13C , the transistor 200 is provided so as to overlap with the capacitor 100. An opening 290 where part of the structure of the transistor 200 is provided overlaps with an opening 190 where part of the structure of the capacitor 100 is provided. In particular, the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0349] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0350] 14A to 7C are modifications of FIGS. 13A to 13C. FIG. 14A is a plan view of a memory device including a transistor 200 and a capacitor 100. FIG. 14B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 14A. FIG. 14C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in FIG. 14A.

[0351] 14B and 14C , the insulating layer 282 has a stacked structure of an insulating layer 282a and an insulating layer 282b over the insulating layer 282a. As shown in Fig. 14B and 14C , an opening is formed in the insulating layer 282, and a conductive layer 249 is provided so as to fill the opening. The opening formed in the insulating layer 282 is provided so as to overlap with the conductive layer 260 in a plan view. The conductive layer 249 is preferably provided so as to be in contact with the upper surface of the conductive layer 260.

[0352] When forming the opening in the insulating layer 282, for example, by using conditions in which the etching rate of the insulating layer 282b is higher than the etching rate of the insulating layer 282a, the insulating layer 282a can be made to function as an etching stopper. Here, the etching stopper has a low etching rate under the etching conditions and has the function of protecting the underlying film from etching.

[0353] After forming the opening in the insulating layer 282b, the insulating layer 282a can be opened using the mask used to open the insulating layer 282b. Alternatively, the insulating layer 282b itself may be used as a mask to open the insulating layer 282a. Furthermore, as shown in FIGS. 14B and 14C , over-etching may occur when openings are formed in the insulating layer 282a, resulting in the formation of recesses in the underlying insulating layer 281. Note that, because the thickness of the insulating layer 282a is thinner than that of the insulating layer 282b, the amount of over-etching can be kept small.

[0354] 14A shows an example in which the conductive layer 249 includes the conductive layer 260, but the conductive layer 249 does not have to include the conductive layer 260. For example, the wiring width of the conductive layer 249 in the X direction may be narrower than the width of the conductive layer 260.

[0355] Fig. 15A is a plan view showing an example in which 12 memory cells 150 shown in Fig. 13A are arranged in three rows in the Y direction and four columns in the X direction. Fig. 15B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 15A. The conductive layer 110 is shared by multiple memory cells 150 arranged in the X direction.

[0356] [Insulating Layer 130] It is preferable to use a material with a high relative dielectric constant (high-k) as the insulating layer 130. By using a material with a high relative dielectric constant as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0357] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a stack structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0358] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material with a high relative dielectric constant and the material that can have ferroelectricity, see the description of the first embodiment.

[0359] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when the thickness is as thin as a few nanometers, and are therefore preferable as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0360] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0361] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0362] 16A shows an example in which the conductive layer 115 of the capacitor 100 has a columnar shape. The conductive layer 115 has a region formed so as to be embedded in the insulating layer 180 and a region disposed within an opening 190 in the insulating layer 180. The insulating layer 130 has a region disposed so as to surround the outside of the columnar region of the conductive layer 115, a region provided along the sidewall of the opening 190, and a region covering the top surface of the insulating layer 180. The conductive layer 120 is provided on the insulating layer 180. The conductive layer 120 can also have a region formed so as to fill the opening 190. The capacitor 100 shown in FIG. 16A is sometimes called a pillar-type capacitor.

[0363] In the case of a trench-type capacitance element, for example, a conductor is formed to cover the inner wall of an opening formed in an insulator or the like, and a dielectric is formed to cover the inside of the conductor. In this case, if the diameter of the opening formed in the insulator or the like is small, coverage may be reduced at the bottom of the opening or in the region extending from the bottom to the sidewall. By using a configuration in which the conductive layer 115 is columnar or cone-shaped and the outside of the conductive layer 120 is covered with a dielectric, it becomes possible to accommodate miniaturization.

[0364] 16B shows an example in which the capacitor 100 does not have the conductive layer 115, but has a conductive layer 110 and a planar conductive layer 120 sandwiched between them by an insulating layer 130. The capacitor 100 shown in FIG. 16B can be easily formed. Furthermore, since there is no unevenness, leakage current of the capacitor may be less likely to flow.

[0365] 17A to 17C , the structure of a memory device including a transistor and a capacitor will be described. FIG. 17A is a plan view of a memory device including a transistor 200, a transistor 200(2), and a capacitor 100. FIG. 17B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 17A . FIG. 17C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in FIG. 17A .

[0366] 17A to 17C includes an insulating layer 140 over a substrate (not shown) and a memory cell 151 over the insulating layer 140. The memory cell 151 includes a transistor 200 over a conductive layer 110, a capacitor 100b over the transistor 200, and a transistor 200 over the capacitor 100b. The two transistors 200 included in the memory cell 151 are stacked vertically with the capacitor 100b sandwiched between them. The transistor 200 located on the lower side is referred to as transistor 200(2). In addition, in FIGS. 17B and 17C, the conductive layer 220 and the conductive layer 240 included in the transistor 200(2) are referred to as conductive layer 220(2) and conductive layer 240(2), respectively.

[0367] The capacitor 100 b includes a conductive layer 120 , a conductive layer 115 , and an insulating layer 130 .

[0368] An insulating layer 180 is provided over the transistor 200(2). An insulating layer 130 is provided over the insulating layer 280.

[0369] The conductive layer 120 has a region that is provided so as to be embedded in the insulating layer 180. The insulating layer 130 has a region that is sandwiched between the conductive layer 115 and the conductive layer 120. In the capacitor 100b, the conductive layer 120 has a columnar shape, and the insulating layer 130 is provided so as to surround the conductive layer 120. The conductive layer 115 is provided so as to surround the conductive layer 120 with the insulating layer 130 sandwiched therebetween.

[0370] The conductive layer 260 of the transistor 200(2) and the conductive layer 220 of the transistor 200 are electrically connected to each other through the conductive layer 120. The conductive layer 120 is preferably provided in contact with the top surface of the conductive layer 260 of the transistor 200(2). The conductive layer 220 of the transistor 200 is preferably provided in contact with the top surface of the conductive layer 120.

[0371] <Configuration Example 3 of Memory Device> FIG. 18 shows an example in which a plurality of memory cells are stacked in n layers (n is an integer of 3 or more) in the Z direction.

[0372] 18 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost layer. The number of memory cells included in one memory layer 160 is not particularly limited, and one memory layer 160 may have two or more memory cells.

[0373] 18 , an insulating layer 282, an insulating layer 284 over the insulating layer 282, and an insulating layer 286 over the insulating layer 284 are provided over a transistor 200 included in the memory cell 150. The insulating layer 286 functions as an interlayer film. A conductive layer 241 is provided to fill the insulating layer 282 and the insulating layer 284, and a conductive layer 243 is provided over the conductive layer 241 and the insulating layer 284. The conductive layer 243 is electrically connected to a conductive layer 260 of the transistor 200 through the conductive layer 241.

[0374] On the insulating layer 286, an upper memory layer 160 is further provided.

[0375] 18, two memory cells are connected to common wiring (conductive layer 245, conductive layer 246, conductive layer 247, conductive layer 248, etc.). The conductive layer 245, conductive layer 246, conductive layer 247, and conductive layer 248 are electrically connected to, for example, a sense amplifier (not shown) provided below the n-layer memory layer 160.

[0376] 18, by stacking a plurality of memory cells, it is possible to integrate and arrange the cells without increasing the area occupied by the memory cell array, that is, it is possible to configure a 3D memory cell array.

[0377] 19 shows a cross-sectional structure example of a memory device. In the structure example shown in FIG. 19, a layer 170 including a transistor 200 and a memory layer 160 are stacked in this order over a layer 169 including a transistor 300.

[0378] Peripheral circuitry such as sense amplifiers may be provided in layer 169. Transistor 300 is, for example, a Si transistor.

[0379] 19 shows an example in which the transistor 300 included in the layer 169 is electrically connected to the memory cell 150 included in the memory layer 160. The connection example shown in FIG. 19 can be applied to the case in which the transistor 300 is one of the transistors included in a sense amplifier.

[0380] 19 , by providing a layer 169 so as to overlap the memory cell 150, the wiring connecting the memory cell 150 and the layer 169 can be shortened. For example, the bit line connecting to the sense amplifier can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell. Furthermore, by reducing the bit line capacitance, the memory device can be driven at high speed.

[0381] The transistor included in the layer 170 can be used as, for example, a transistor that forms a peripheral circuit.

[0382] Furthermore, the transistor included in the layer 170 can be used in combination with, for example, the transistor included in the layer 169. A CMOS circuit can be configured by combining the transistor 300 in the layer 169 as a p-channel transistor and the transistor included in the layer 170 as an n-channel transistor.

[0383] 19 can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0384] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0385] Here, in the transistor 300 shown in FIG. 19 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0386] Note that the transistor 300 illustrated in FIG. 19 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0387] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0388] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0389] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0390] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 19 , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0391] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0392] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material, such as aluminum or copper, is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0393] The conductive layer 240 of the transistor 200 in the memory layer 160 is electrically connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, the conductive layer 328, and a conductive layer provided to be embedded in the insulating layer of the layer 170.

[0394] The conductive layer 643 is embedded in the insulating layer 280. The conductive layer 240 of the transistor 200 included in the memory cell 150 is electrically connected to the conductive layer 643. In the structure shown in FIG. 19 , the conductive layer 240 is located below the semiconductor layer 230, and therefore, the conductive layer 240 can be easily provided so as to be in contact with the top surface of the conductive layer 643.

[0395] The conductive layer 642 is provided over the insulating layer 130 and is embedded in the insulating layer 641. The conductive layer 642 can be manufactured using the same material and process as the conductive layer 120. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 can be manufactured using the same material and process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The insulating layer 648 electrically insulates the transistor 300 from the layer 170. An insulating layer 647 is provided over the layer 170. The conductive layer 645 is embedded in the insulating layer 647. The insulating layer 647 electrically insulates the transistor 200 of the layer 170 from the conductive layer 110.

[0396] As described above, the memory device of this embodiment has a transistor with reduced parasitic capacitance, and therefore the operating speed can be increased. In addition, the memory device of this embodiment has a capacitor and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a memory device with high integration can be realized.

[0397] <Application to Circuit Diagrams> The memory device described in this embodiment can be applied to circuit diagrams described in later embodiments, for example, the circuit diagrams shown in FIGS.

[0398] The memory device described in this embodiment can be applied to, for example, the circuit diagram shown in Figure 21A. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, by using the transistor 200 as the transistor M1 and the capacitor 100 as the capacitor CA, the configuration of the memory cell 150 shown in Figures 13A to 13C and the like can be applied to Figure 21A.

[0399] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. The wiring BIL functions as a bit line, and the wiring WOL functions as a word line.

[0400] Here, in the transistor of one embodiment of the present invention, an insulating layer 281 is provided between the conductive layer 240 and the conductive layer 260 which function as a bit line, and an insulating layer 280 is provided between the conductive layer 220. Therefore, the wiring capacitance between the conductive layer 240 and the conductive layer 260 and the wiring capacitance between the conductive layer 240 and the conductive layer 220 can be reduced. That is, in the memory device of one embodiment of the present invention, the parasitic capacitance of the bit line can be made extremely small.

[0401] Furthermore, when a low potential signal is applied to the gate of the transistor, carriers are not induced in the semiconductor layer, and it can be said that parasitic capacitance generated between the conductive layer 260 functioning as a word line and the semiconductor layer 230 is extremely small. Furthermore, when a high potential signal is applied to the gate, carriers are induced in the semiconductor layer, and significant parasitic capacitance may be generated between the conductive layer 260 and the semiconductor layer 230. However, since the influence of parasitic capacitance on the word line is smaller than that on the bit line in the operation of the memory device, by extremely reducing the parasitic capacitance of the bit line, a sufficiently high operating speed can be achieved in the memory device of one embodiment of the present invention.

[0402] 21C and 21D . The memory cell 953 and the memory cell 954 each include a transistor M2, a transistor M3, and a capacitor CB. Here, by using the transistor 200 as the transistor M2, the transistor 200(2) as the transistor M3, and the capacitor CB as the capacitor CB, the configuration of the memory cell 151 shown in FIGS. 17A to 17C and the like can be applied to FIGS. 21C and 21D .

[0403] 21C , the wiring WBL corresponds to the conductive layer 240 of the transistor 200, the wiring WOL corresponds to the conductive layer 260 of the transistor 200, the wiring CAL corresponds to the conductive layer 115, and the wiring RBL and the wiring SL correspond to one of the conductive layers 240 and 220 of the transistor 200(2), respectively. The conductive layers 240 and 220 of the transistor 200(2) are referred to as the conductive layer 240(2) and the conductive layer 220(2), respectively, in FIGS. 17B and 17C . The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines.

[0404] In the memory device of one embodiment of the present invention, the conductive layer 240 of the transistor 200, which functions as a write bit line, has the insulating layer 281 between it and a wiring above it and the insulating layer 280 between it and a wiring below it, so that parasitic capacitance can be made extremely small. Similarly, the conductive layer 240(2) of the transistor 200(2), which functions as a read bit line, can also have extremely small parasitic capacitance.

[0405] Furthermore, the conductive layer 240 of the transistor 200 can be electrically connected to one of the conductive layer 240 and the conductive layer 220 of the transistor 200(2) and at least one of the conductive layers can be used as a wiring BIL, thereby enabling application to the circuit diagram shown in FIG. 21D.

[0406] The circuit diagrams shown in FIGS. 21A to 21H and FIG. 22 will be described in detail later.

[0407] This embodiment mode can be combined with other embodiment modes as appropriate.

[0408] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0409] Fig. 20 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 20 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 20 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0410] The memory cell 950 can be any of the memory devices described in Embodiment 2 (such as the memory cell 150 ).

[0411] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0412] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0413] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0414] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0415] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0416] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0417] Each circuit included in the peripheral circuit 911 can have a function of generating or outputting a fixed potential, a variable potential (for example, a pulse voltage, a pulse signal, a clock signal, or the like).

[0418] The peripheral circuits may use Si transistors or the like.

[0419] An example of the structure of a Si transistor will be described below. An element isolation layer, a semiconductor region, a low-resistance region functioning as a source region or a drain region, and the like can be provided on a single-crystal silicon substrate or an SOI substrate having single-crystal silicon. Furthermore, a gate insulating layer, a gate electrode, and the like can be provided in a region overlapping with the semiconductor layer.

[0420] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0421] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0422] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply voltage of the semiconductor device 900 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply voltage used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 20, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0423] Here, V ＤＤ For example, 0.8 V can be used as V ＨＭ For example, 1.8 V, 2.5 V, 3.3 V, etc. can be used.

[0424] When the difference between the high power supply voltage and the low power supply voltage applied to the word line is 3.3 V, for example, the high power supply voltage can be 3.3 V and the low power supply voltage can be 0 V (e.g., ground potential). Alternatively, the high power supply voltage can be 2.5 V and the low power supply voltage can be −0.8 V. Alternatively, the high power supply voltage can be 1.8 V and the low power supply voltage can be −1.5 V.

[0425] Also, in the column driver 924, V ＤＤ For example, when data is written to the memory cell 950, a higher potential (for example, 1.8 V, 2.5 V, or 3.3 V) can be used. For example, when data is written to the memory cell 950, the write speed can be improved by using a higher potential. ＤＤ For example, V ＨＭ can be used for the column driver 924. Alternatively, V ＤＤ and V ＨＭ A different high power supply potential may be used.

[0426] 21A to 21H, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0427] In the following description, when two components are said to be connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0428] 21A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0429] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0430] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0431] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0432] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0433] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 21B may be used. The memory cell 952 is an example in which the capacitor CA and the wiring CAL are not included. The first terminal of the transistor M1 is in a floating state.

[0434] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0435] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0436] 21C shows an example circuit configuration of a gain cell memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0437] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0438] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines. The wiring WOL may be called a write word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0439] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. At this time, a high-level potential is also applied to the wiring CAL. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential between the first and second terminals of the capacitor CB. Then, by applying a low-level potential to the wiring CAL, the gate potential of the transistor M3 decreases due to capacitive coupling of the capacitor CB, turning off the transistor M3.

[0440] Data is read by applying a high-level potential to the wiring CAL and a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0441] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 21D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0442] 21E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 21F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0443] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0444] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0445] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0446] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0447] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0448] 21G shows a gain cell type memory cell 957 having three transistors and one capacitor element. The memory cell 957 has transistors M4 to M6 and a capacitor element CC.

[0449] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0450] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0451] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0452] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0453] Note that at least the transistor M4 is preferably an OS transistor.

[0454] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0455] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0456] A memory cell 957b shown in FIG. 21H includes transistors M4 to M6 and does not include a capacitor CC.

[0457] A first terminal of the transistor M4 is connected to the gate of the transistor M5 and the node N, a second terminal of the transistor M4 is connected to the wiring WBL, and a gate of the transistor M4 is connected to the wiring WOL. A first terminal of the transistor M5 is connected to the wiring SL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6. A second terminal of the transistor M6 is connected to the wiring RBL, and a gate of the transistor M6 is connected to the wiring RWL.

[0458] To write data, a high-level potential is applied to the wiring WOL to turn on the transistor M4, thereby bringing the wiring WBL and the node N into electrical continuity, and charge is accumulated in the node N. After that, a low-level potential is applied to the wiring WOL to turn off the transistor M4, thereby maintaining the potential of the node N. Note that a constant potential (GND (ground potential) or low potential)) is always applied to the wiring SL.

[0459] To read data, the wiring RBL is precharged to a predetermined potential. The potential of the wiring SL is maintained constant. Furthermore, the potential of the wiring RWL is set to a high potential, and the transistor M6 is turned on, thereby bringing the wiring RWL and the second terminal of the transistor M5 into electrical continuity.

[0460] At this time, a high potential is applied to the second terminal of the transistor M5, and GND or a low potential is applied to the first terminal thereof. A potential having a magnitude corresponding to the data written to the node N is applied to the gate of the transistor M5. In other words, the type of data determines whether the transistor M5 is in an on state or an off state.

[0461] Here, when the data stored in the memory cell is "0", the difference between the gate potential and the source potential of transistor M5 is assumed to be lower than the threshold voltage of transistor M5. Also, when the data stored in the memory cell is "1", the difference between the gate potential and the source potential of transistor M5 is assumed to be higher than the threshold voltage of transistor M5. In this case, if the data stored in the memory cell is "0", transistor M5 is turned off (transistor M6 is turned on), and therefore no current flows from wiring RBL to wiring SL. On the other hand, if the data stored in the memory cell is "1", both transistors M5 and M6 are turned on, and therefore current flows from wiring RBL to wiring SL. The data stored in the memory cell can be read from the current flowing through wiring RBL or the potential of wiring RBL.

[0462] 22 shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 22 is a memory cell of an SRAM capable of backing up data.

[0463] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0464] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0465] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0466] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0467] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0468] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0469] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0470] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0471] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0472] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0473] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0474] Note that Si transistors may be used as the transistors MS1 to MS4.

[0475] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 23A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 23B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0476] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0477] 24 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 24 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.

[0478] The arithmetic device 960 shown in FIG. 24 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0479] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0480] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0481] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0482] The arithmetic device 960 shown in FIG. 24 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 24 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0483] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0484] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and reads and writes data from and to the registers 996 depending on the state of the arithmetic unit 960.

[0485] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0486] 24, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0487] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 25A and 25B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 25B.

[0488] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0489] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and the two substrates are electrically connected using a through-via or a conductive film bonding technique (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0490] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0491] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0492] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0493] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0494] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 989, or may be configured so that the drive circuit 910L1 is connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured so that they are connected thereto.

[0495] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0496] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0497] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 26A shows a perspective view of a semiconductor device 970B.

[0498] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0499] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0500] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 970C.

[0501] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0502] This embodiment mode can be combined with other embodiment modes as appropriate.

[0503] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0504] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 27A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and recording density are required. In FIG. 27A , from the top layer, there are memories embedded as registers in an arithmetic processing unit such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that while an example having up to an L3 cache is shown here, lower-level caches may also be included.

[0505] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0506] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0507] The main memory has a function of holding programs, data, etc. read from storage.

[0508] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.

[0509] A storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 27A , the storage device according to one embodiment of the present invention can be suitably used in both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be applied to a tier where a storage is located.

[0510] FIG. 27B also shows an example in which an SRAM is used as part of a cache and an OS memory of one embodiment of the present invention is used as the other part of the cache.

[0511] The lowest level cache can be called a last level cache (LLC). While an LLC does not require faster operation speed than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operation speed and can retain data for a long period of time, and therefore can be suitably used for an LLC. The OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0512] For example, as shown in Fig. 27B, a configuration can be adopted in which SRAM is used for the higher-level caches (L1 cache, L2 cache, etc.) and the OS memory according to one aspect of the present invention is used for the LLC. Also, as shown in Fig. 27B, not only the OS memory but also DRAM can be applied to the main memory.

[0513] This embodiment mode can be combined with other embodiment modes as appropriate.

[0514] Embodiment 5 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0515] <Structure Example of Display Device> One embodiment of the present invention can also be applied to a display device. FIG. 28A is a block diagram showing a structure example of a display device 70, which is a display device of one embodiment of the present invention. The display device 70 includes a display portion 80, a scan line driver circuit 71, a signal line driver circuit 73, a power supply circuit 75, and a reference potential generation circuit 77. The display portion 80 includes a plurality of pixels 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the display device 70.

[0516] The scanning line driving circuit 71 is electrically connected to the pixels 81 via the wiring 31 (the wiring 31a, the wiring 31b, and the wiring 31c). The wiring 31 extends, for example, in the row direction of the matrix.

[0517] The signal line driving circuit 73 is electrically connected to the pixels 81 via the wiring 33. The wiring 33 extends, for example, in the column direction of the matrix.

[0518] The power supply circuit 75 is electrically connected to the pixels 81 via the wiring 35. The wiring 35 extends, for example, in the row direction of the matrix.

[0519] The reference potential generating circuit 77 is electrically connected to the pixels 81 via the wiring 38. The wiring 38 extends, for example, in the column direction of the matrix.

[0520] The pixel 81 has a display element (also referred to as a display device), and can display an image on the display unit 80 by using the display element. As the display element, for example, a light-emitting element (also referred to as a light-emitting device) can be used, and specifically, an organic EL element can be used. Furthermore, as the display element, a liquid crystal element (also referred to as a liquid crystal device) can be used.

[0521] The scanning line driver circuit 71 has a function of selecting, for example, pixels 81 to which image data is to be written, row by row. Specifically, the scanning line driver circuit 71 can select the pixels 81 to which image data is to be written by outputting a signal to the wiring 31. Here, the scanning line driver circuit 71 can select all the pixels 81 by, for example, outputting the signal to the wiring 31 in the first row, then outputting the signal to the wiring 31 in the second row, and so on, sequentially up to the wiring 31 in the final row. Thus, the signal output by the scanning line driver circuit 71 to the wiring 31 is a scanning signal, and the wiring 31 provided in the display device 70 can be referred to as a scanning line.

[0522] The signal line driver circuit 73 has a function of generating image data. The image data is supplied to the pixels 81 via the wirings 33. For example, the image data can be written to all the pixels 81 included in the row selected by the scanning line driver circuit 71. Here, the image data can be expressed as a signal (image signal). Therefore, the wirings 33 provided in the display device 70 can be called signal lines.

[0523] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 35. The power supply circuit 75 has a function of generating, for example, a high power supply potential (hereinafter also simply referred to as a "high potential" or "VDD") and supplying it to the wiring 35. The power supply circuit 75 may also have a function of generating a low power supply potential (hereinafter also simply referred to as a "low potential" or "VSS"). As described above, the wiring 35 functions as a power supply line.

[0524] The reference potential generating circuit 77 has a function of generating a reference potential and supplying it to the wiring 38. Because the potential of the wiring 38 serves as the reference potential, the wiring 38 can be referred to as a reference potential line. Note that the electrical characteristics of each pixel may be read out to the reference potential generating circuit 77 outside the pixel via the wiring 38. In other words, the reference potential generating circuit 77 may have a function of sensing the electrical characteristics of each pixel. By reading the electrical characteristics of each pixel with the reference potential generating circuit 77, deterioration and variations in elements (transistors, light-emitting elements, etc.) within each pixel may be sensed. The read characteristics may then be fed back to a video signal to correct deterioration and variations in image quality.

[0525] 29A is a block diagram showing a configuration example of the signal line driver circuit 73. The signal line driver circuit 73 includes a shift register circuit 171, latch circuits 173<1> to 173<n / 2>, and demultiplexer circuits 175<1> to 175<n / 2>.

[0526] The latch circuits 173<1> to 173<n / 2> are electrically connected to a circuit 17 provided outside the signal line driver circuit 73. Note that the circuit 17 may be included in the signal line driver circuit 73. The latch circuit 173 is electrically connected to an input terminal of a demultiplexer circuit 175 via a wiring 34. The output terminal of the demultiplexer circuit 175 is electrically connected to a wiring 33. FIG. 29A illustrates an example in which the demultiplexer circuit 175 has two output terminals, each electrically connected to a different wiring 33. Specifically, the example illustrates an example in which the two output terminals of the demultiplexer circuit 175<1> are electrically connected to a wiring 33[1] and a wiring 33[2], respectively. The example also illustrates an example in which the two output terminals of the demultiplexer circuit 175<n / 2> are electrically connected to a wiring 33[n-1] and a wiring 33[n], respectively.

[0527] The circuit 17 has a function as an interface that receives image data from outside the display device 70. Note that the circuit 17 may also generate image data.

[0528] The image data output from the circuit 17 is supplied to the latch circuits 173<1> to 173<n / 2>. The shift register circuit 171 has a function of generating a signal for controlling the driving of the latch circuit 173. For example, when a start pulse is supplied to the shift register circuit 171, the shift register circuit 171 sequentially outputs signals for controlling the driving of the latch circuits 173<1> to 173<n / 2>.

[0529] The latch circuit 173 has a function of holding or outputting the image data output from the circuit 17. Whether the latch circuit 173 holds or outputs the image data is selected based on a signal supplied from the shift register circuit 171 to the latch circuit 173.

[0530] The demultiplexer circuit 175 has a function of outputting the image data output by the latch circuit 173 from one of its output terminals. The demultiplexer circuit 175 can determine the output terminal to which the image data is to be output in accordance with a selection signal input to a selection signal input terminal of the demultiplexer circuit 175. The selection signal can be generated by a selection signal generation circuit 19 provided outside the signal line driver circuit 73. The selection signal generation circuit 19 may be included in the signal line driver circuit 73.

[0531] By providing the demultiplexer circuit 175 in the signal line driver circuit 73, it is possible to reduce the scale of the signal line driver circuit 73. For example, it is possible to reduce the number of latch circuits 173 included in the signal line driver circuit 73. Furthermore, it is possible to reduce the number of transistors included in the shift register circuit 171.

[0532] For example, if the signal line driver circuit 73 does not include the demultiplexer circuit 175, the signal line driver circuit 73 will have n latch circuits 173. On the other hand, if the signal line driver circuit 73 includes the demultiplexer circuit 175, the number of latch circuits 173 can be reduced to less than n. This allows the signal line driver circuit 73 to be smaller in size.

[0533] As described above, assuming that the pixel density of the display unit 80 is the same, the density of transistors provided in the signal line driver circuit 73 can be lower than when the demultiplexer circuit 175 is not provided. Therefore, assuming that the density of transistors provided in the signal line driver circuit 73 is the same, the pixel density of the display unit 80 can be increased. This allows the pixels 81 to be miniaturized, making the display device 70 a high-definition display device. Furthermore, increasing the density of transistors provided in the signal line driver circuit 73 allows the signal line driver circuit 73 to be miniaturized. This allows the display device 70 to be a compact display device. Furthermore, the display device 70 can be a display device with a narrow frame. The demultiplexer circuit 175 does not necessarily need to be provided in the signal line driver circuit 73. Alternatively, the demultiplexer circuit 175 may be provided outside the signal line driver circuit 73.

[0534] 29A shows an example in which the demultiplexer circuit 175 has two output terminals, but the demultiplexer circuit 175 may have, for example, three or more output terminals. For example, if the demultiplexer circuit 175 has, for example, three output terminals, the signal line driver circuit 73 can be configured to have n / 3 demultiplexer circuits 175.

[0535] The more output terminals that one demultiplexer circuit 175 has, the smaller the scale of the signal line driving circuit 73 can be, and the fewer the number of wirings 33 electrically connected to the signal line driving circuit 73. This allows the display device 70 to have higher definition, be more compact, and have a narrower frame.

[0536] Fig. 29B is a circuit diagram showing an example of the configuration of the latch circuit 173. Note that Fig. 29B also shows the circuit 17 and the shift register circuit 171 in order to show the connection relationship.

[0537] In this specification, circuit diagrams may not show all of the components of a circuit. For example, a circuit may include a buffer amplifier in addition to the components shown in the circuit diagram.

[0538] The latch circuit 173 is electrically connected to terminals R, D, and Q. The terminal R is electrically connected to the output terminal of the shift register circuit 171. The terminal D is electrically connected to the output terminal of the circuit 17. The terminal Q is electrically connected to the wiring 34. From the perspective of the latch circuit 173, the terminals R and D are input terminals, and the terminal Q is an output terminal.

[0539] The latch circuit 173 includes a transistor 381 , a transistor 383 , a capacitor 385 , and an inverter circuit 390 .

[0540] The gate of the transistor 381 and the input terminal of the inverter circuit 390 are electrically connected to the terminal R. One of the source and the drain of the transistor 381 is electrically connected to the terminal D. The other of the source and the drain of the transistor 381 is electrically connected to one of the source and the drain of the transistor 383. The one of the source and the drain of the transistor 383 is electrically connected to one electrode of the capacitor 385. The other of the source and the drain of the transistor 383 is electrically connected to the terminal Q. The other electrode of the capacitor 385 can be supplied with a potential VSS.

[0541] 29B , the on and off states of the transistors 381 and 383 are switched by a signal input to the terminal R. For example, when a signal corresponding to a logical value of "1" is input to the terminal R, the transistor 381 is turned on and the transistor 383 is turned off. Also, for example, when a signal corresponding to a logical value of "0" is input to the terminal R, the transistor 381 is turned off and the transistor 383 is turned on.

[0542] When a signal corresponding to a logical value of "1" is input to the terminal R, the potential representing the image data input from the circuit 17 to the terminal D is held by the capacitor 385. As a result, the image data is held in the latch circuit 173.

[0543] Next, when a signal corresponding to a logical value "0" is input to the terminal R, the transistor 381 is turned off and the transistor 383 is turned on. Therefore, the potential held in the capacitor 385 is output from the terminal Q. As a result, image data is output from the latch circuit 173.

[0544] As described above, the driving of the latch circuit 173 can be controlled by the signal input to the terminal R. As described above, the terminal R is electrically connected to the output terminal of the shift register circuit 171. Therefore, the shift register circuit 171 can control the driving of the latch circuit 173.

[0545] The transistors 381 and 383 are preferably OS transistors. In particular, it is preferable that an OS transistor use a metal oxide containing at least one of indium, an element M (wherein the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region. By using such an OS transistor as the transistors 381 and 383, the off-state current of the transistors 381 and 383 can be significantly reduced. Therefore, leakage of the potential held in the capacitor 385 can be suppressed. This enables the image data held in the latch circuit 173 to be converted into analog data. Note that digital data may be held in the latch circuit 173. In this case, the signal line driver circuit 73 includes a digital-to-analog converter (D / A converter), and the digital data output from the latch circuit 173 is converted into analog data by the D / A converter, and the analog data is then supplied to the demultiplexer circuit 175.

[0546] A buffer circuit may be provided between the transistor 381 and the transistor 383 .

[0547] Here, it is preferable to use the transistor 200 or the like described in the above embodiment as the transistors 381 and 383 because the area occupied by the latch circuit 173 can be reduced.

[0548] 29C is a circuit diagram showing an example of the configuration of the inverter circuit 390. The inverter circuit 390 includes a transistor 92, a transistor 94, a transistor 95, a transistor 97, and a capacitor 99.

[0549] A potential VDD can be supplied to one of the source or drain of the transistor 92, the gate of the transistor 92, and one of the source or drain of the transistor 95 included in the latch circuit 173. The other of the source or drain of the transistor 92 is electrically connected to one of the source or drain of the transistor 94. The one of the source or drain of the transistor 94 is electrically connected to the gate of the transistor 95. The other of the source or drain of the transistor 95 is electrically connected to one electrode of a capacitor 99. The gate of the transistor 95 is electrically connected to the other electrode of the capacitor 99. The one electrode of the capacitor 99 is electrically connected to one of the source or drain of the transistor 97. The one of the source or drain of the transistor 97 is electrically connected to the gate of the transistor 383. A potential VSS can be supplied to the other of the source or drain of the transistor 94 and the other of the source or drain of the transistor 97. The gates of the transistors 94 and 97 are electrically connected to the terminal R.

[0550] All the transistors included in the latch circuit 173 can be transistors of the same polarity, for example, n-channel transistors. This allows all the transistors included in the latch circuit 173 to be the same type of transistors. For example, all the transistors included in the latch circuit 173 can be OS transistors. For example, the transistor 200 or the like described in the above embodiment can be used as all the transistors included in the latch circuit 173.

[0551] By using the same type of transistors for all the transistors included in the latch circuit 173, all the transistors included in the latch circuit 173 can be manufactured in the same process. Therefore, the number of manufacturing steps for the latch circuit 173 can be reduced compared to when the latch circuit 173 includes two or more types of transistors. Furthermore, by using the transistors described in the above embodiment as all the transistors included in the latch circuit 173, the latch circuit 173 can be miniaturized.

[0552] Note that the transistors described in the above embodiments do not necessarily have to be applied to the transistors included in the latch circuit 173. For example, some of the transistors may be planar transistors.

[0553] At least one of the transistors 92, 94, 95, and 97 included in the inverter circuit 390 does not need to be an OS transistor and may be, for example, a Si transistor. Furthermore, one or both of the transistors 381 and 383 also does not need to be an OS transistor and may be, for example, a Si transistor.

[0554] 30 is a block diagram showing a specific configuration example of the demultiplexer circuit 175 included in the signal line driving circuit 73. Fig. 30 also shows the selection signal generation circuit 19. Fig. 30 shows an example in which the demultiplexer circuit 175 has two transistors 93.

[0555] 30 shows an example in which the demultiplexer circuit 175<1> includes the transistor 93[1] and the transistor 93[2], and the demultiplexer circuit 175<n / 2> includes the transistor 93[n-1] and the transistor 93[n].

[0556] One of the source or drain of the transistor 93[1] and one of the source or drain of the transistor 93[2] function as an input terminal of the demultiplexer circuit 175<1> and are electrically connected to the wiring 34<1>. One of the source or drain of the transistor 93[n-1] and one of the source or drain of the transistor 93[n] function as an input terminal of the demultiplexer circuit 175<n / 2> and are electrically connected to the wiring 34<n / 2>.

[0557] The other of the source and the drain of the transistor 93[1] functions as a first output terminal of the demultiplexer circuit 175<1> and is electrically connected to the wiring 33[1]. The other of the source and the drain of the transistor 93[2] functions as a second output terminal of the demultiplexer circuit 175<1> and is electrically connected to the wiring 33[2]. The other of the source and the drain of the transistor 93[n-1] functions as a first output terminal of the demultiplexer circuit 175<n / 2> and is electrically connected to the wiring 33[n-1]. The other of the source and the drain of the transistor 93[n] functions as a second output terminal of the demultiplexer circuit 175<n / 2> and is electrically connected to the wiring 33[n].

[0558] The gate of the transistor 93[1] functions as a selection signal input terminal of the demultiplexer circuit 175<1> and is electrically connected to the selection signal generation circuit 19 through a wiring 32_1. The gate of the transistor 93[2] functions as a selection signal input terminal of the demultiplexer circuit 175<1> and is electrically connected to the selection signal generation circuit 19 through a wiring 32_2. The gate of the transistor 93[n-1] functions as a selection signal input terminal of the demultiplexer circuit 175<n / 2> and is electrically connected to the selection signal generation circuit 19 through a wiring 32_1. The gate of the transistor 93[n] functions as a selection signal input terminal of the demultiplexer circuit 175<n / 2> and is electrically connected to the selection signal generation circuit 19 through a wiring 32_2.

[0559] The selection signal generation circuit 19 can generate, for example, a first signal and a second signal as the selection signals. In this case, the selection signal generation circuit 19 can output the first signal to the wiring 32_1 and the second signal to the wiring 32_2. Here, for example, by setting the first signal to a signal that turns on the transistor 93 and the second signal to a signal that turns off the transistor 93, the demultiplexer circuit 175 can output image data from the first output terminal. Furthermore, for example, by setting the first signal to a signal that turns off the transistor 93 and the second signal to a signal that turns on the transistor 93, the demultiplexer circuit 175 can output image data from the second output terminal.

[0560] As described above, for example, when the first signal is a signal that turns on the transistor 94, the second signal can be a signal that turns off the transistor 93, and when the first signal is a signal that turns off the transistor 94, the second signal can be a signal that turns on the transistor 93. Therefore, the first signal and the second signal can be complementary to each other. For example, when the first signal and the second signal are 1-bit digital signals, when the first signal is at a high potential, the second signal can be at a low potential, and when the first signal is at a low potential, the second signal can be at a high potential.

[0561] The demultiplexer circuit 175 may have three or more transistors 93. In this case, the demultiplexer circuit 175 can have three or more output terminals.

[0562] FIG. 28B is a plan view illustrating a configuration example of a pixel 61 included in a display device. The pixel 61 can have multiple subpixels 63. The pixel 81 illustrated in FIG. 28A can be applied to each of the subpixels 63. FIG. 28B illustrates an example in which the pixel 61 includes subpixels 63R, 63G, and 63B as the subpixels 63. Here, when the pixel 61 includes a light-emitting element as a display element, for example, the planar shape of the subpixels illustrated in FIG. 28B corresponds to the planar shape of the light-emitting region of the light-emitting element. Note that FIG. 28B illustrates the subpixels 63R, 63G, and 63B as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the subpixels 63R, 63G, and 63B can be determined as appropriate. The aperture ratios of the sub-pixel 63R, the sub-pixel 63G, and the sub-pixel 63B may be different from one another, or two or more of them may be equal or approximately equal.

[0563] 28B, a stripe arrangement is applied as an arrangement method of the sub-pixels 63. Note that an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as an arrangement method of the sub-pixels 63.

[0564] The sub-pixels 63R, 63G, and 63B each emit light of a different color. Examples of the sub-pixels 63R, 63G, and 63B include sub-pixels of three colors: red (R), green (G), and blue (B), and sub-pixels of three colors: yellow (Y), cyan (C), and magenta (M). The pixel 61 may also be provided with four or more sub-pixels 63. For example, the pixel 61 may be provided with four sub-pixels of R, G, B, and white (W). As described above, the display device 70 can display a full-color image on the display unit 80 by including a plurality of sub-pixels 63 that emit light of different colors in the pixel 61. The pixel 61 may also be provided with sub-pixels of R, G, B, and infrared (IR) light, for example.

[0565] Note that a sensor may be provided in the display unit 80, and for example, a sensor may be provided in the pixel 61. For example, the display unit 80 may have a function as a fingerprint sensor. For example, the display unit 80 may have a function as an optical or ultrasonic fingerprint sensor.

[0566] Fig. 28C is a circuit diagram showing an example of the configuration of the pixel 81 shown in Fig. 28A. The pixel shown in Fig. 28C has a pixel circuit 90 and a light-emitting element 91.

[0567] The pixel circuit 90 includes a transistor 41, a transistor 42, a transistor 43, a transistor 53, a capacitor 51, and a capacitor 58. In other words, the pixel circuit 90 is a 4Tr2C type pixel circuit.

[0568] For example, one structure selected from the transistor 200, the transistor 200(2), the transistor 200(3), etc. described in the above embodiment can be applied to each of the transistors 41, 42, 43, and 53. For example, one structure selected from the capacitor 100, the capacitor 100b, etc. described in the above embodiment can be applied to each of the capacitors 51, 58, etc.

[0569] For example, the transistors M4, M5, and M6 shown in the above embodiments can be applied to the transistors 42, 41, and 43, respectively, and the wirings WOL, WBL, and SL can be applied to the wirings 31a, 33, and 35, respectively.

[0570] In the pixel circuit 90, one of the source and the drain of the transistor 42 is electrically connected to a wiring 33. The other of the source and the drain of the transistor 42 is electrically connected to one electrode of a capacitor 51 and the gate of the transistor 41. The gate of the transistor 42 is electrically connected to a wiring 31a. One of the source and the drain of the transistor 41 is electrically connected to one of the source and the drain of the transistor 43. The other of the source and the drain of the transistor 43 is electrically connected to a wiring 35. The gate of the transistor 43 is electrically connected to a wiring 31c. One electrode of the capacitor 58 is electrically connected to the other of the source and the drain of the transistor 41, one of the source and the drain of the transistor 53, the other electrode of the capacitor 51, and one electrode of the light-emitting element 91. The other electrode of the capacitor 58 is electrically connected to a wiring 35. The other of the source and the drain of the transistor 53 is electrically connected to a wiring 38. The gate of the transistor 53 is electrically connected to a wiring 31b. The other electrode of the light emitting element 91 is electrically connected to the wiring 37 .

[0571] The transistor 43 functions as a switch and controls conduction or non-conduction between the wiring 35 and one of the source and the drain of the transistor 41 based on the potential of the wiring 31c.

[0572] By turning on the transistor 43, a current having a magnitude corresponding to the gate potential of the transistor 41 flows, for example, from the wiring 35 to the wiring 37. This causes the light-emitting element 91 to emit light with a luminance corresponding to the gate potential of the transistor 41. On the other hand, by turning off the transistor 43, no current flows through the light-emitting element 91, and therefore the light-emitting element 91 does not emit light.

[0573] OS transistors are preferably used as the transistors 41, 42, and 43. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 41 and 42, the display device 70 can be driven at high speed.

[0574] Furthermore, as described above, an OS transistor has an extremely small off-state current. Therefore, by using an OS transistor as the transistor 42, charge stored in the capacitor 51 can be held for a long period of time. This allows image data written to the subpixel 63 to be held for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the subpixel 63). As a result, the power consumption of the display device 70 can be reduced.

[0575] Here, to increase the emission luminance of the light-emitting element 91, it is necessary to increase the amount of current flowing through the light-emitting element 91. To achieve this, it is necessary to increase the source-drain voltage of the transistor 41, which is a driving transistor. Because an OS transistor has a higher withstand voltage between the source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 41, it is possible to increase the amount of current flowing through the light-emitting element 91 and increase the emission luminance of the light-emitting element 91.

[0576] It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting element 91. Examples of the light-emitting material included in the light-emitting element 91 include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (for example, a quantum dot material). Alternatively, an LED such as a micro LED (light-emitting diode) can be used as the light-emitting element 91.

[0577] This embodiment mode can be combined with other embodiment modes as appropriate.

[0578] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0579] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0580] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0581] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0582] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0583] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism and depth. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0584] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0585] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0586] [Electronic Component] FIG. 31A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 31A has semiconductor device 710 inside mold 711. FIG. 31A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0587] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0588] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0589] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0590] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0591] 31B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0592] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0593] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0594] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0595] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0596] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0597] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0598] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0599] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 31B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0600] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0601] [Mainframe] Next, Fig. 32A shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 32A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0602] The computer 5620 can have the configuration shown in the perspective view in Fig. 32B, for example. In Fig. 32B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0603] PC card 5621 shown in Figure 32C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 32C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced.

[0604] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0605] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0606] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0607] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used...

Claims

a transistor, a first insulating layer, and a second insulating layer; the transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode; the first insulating layer overlies the first conductive layer; the second insulating layer is located on the first insulating layer; the second conductive layer is located between the second insulating layer and the first insulating layer; a first opening portion is provided in the first insulating layer and the second conductive layer, the first opening portion reaching the first conductive layer; the second insulating layer is provided with a second opening overlapping the first opening; the semiconductor layer has a region in contact with a side surface of the second conductive layer in the first opening, a region in contact with a side surface of the first insulating layer in the first opening, a region in contact with an upper surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer in the second opening, the gate electrode has a region located inside the first opening and a region located inside the second opening, the height of the upper surface of the semiconductor layer is lower than the height of the upper surface of the gate electrode; The gate insulating layer is sandwiched between the semiconductor layer and the gate electrode in the first opening. 　 a transistor, a first insulating layer, and a second insulating layer; the transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode; the first insulating layer overlies the first conductive layer; the second insulating layer is located on the first insulating layer; the second conductive layer is located between the second insulating layer and the first insulating layer; a first opening portion is provided in the first insulating layer and the second conductive layer, the first opening portion reaching the first conductive layer; the second insulating layer is provided with a second opening overlapping the first opening; the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer at the first opening, a region in contact with a side surface of the first insulating layer at the first opening, a region in contact with an upper surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer at the second opening, a region of the semiconductor layer that is in contact with an upper surface of the second conductive layer is located between the second conductive layer and the second insulating layer; the gate electrode has a region located inside the first opening and a region located inside the second opening, The gate insulating layer is sandwiched between the semiconductor layer and the gate electrode in the first opening. 　 a transistor, a first insulating layer, and a second insulating layer; the transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode; the first insulating layer overlies the first conductive layer; the second insulating layer is located on the first insulating layer; the second conductive layer is located between the second insulating layer and the first insulating layer; a first opening portion is provided in the first insulating layer and the second conductive layer, the first opening portion reaching the first conductive layer; the second insulating layer is provided with a second opening overlapping the first opening; the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer at the first opening, a region in contact with a side surface of the first insulating layer at the first opening, a region in contact with an upper surface of the first conductive layer overlapping the first opening, and a region in contact with a side surface of the second insulating layer at the second opening, a region of the semiconductor layer that is in contact with an upper surface of the second conductive layer is located between the second conductive layer and the second insulating layer; the gate electrode has a region located inside the first opening and a region located inside the second opening, the height of the upper surface of the semiconductor layer is lower than the height of the upper surface of the gate electrode; The gate insulating layer is sandwiched between the semiconductor layer and the gate electrode in the first opening. 　 In any one of claims 1 to 3, A semiconductor device, wherein the height of the upper surface of the gate electrode is approximately equal to the height of the upper surface of the second insulating layer. 　 In claim 1 or claim 3, A semiconductor device in which the height of the upper surface of the semiconductor layer is lower than the height of the upper surface of the second opening. forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a sacrificial layer on the second conductive layer; forming a second insulating layer covering an upper surface of the sacrificial layer, a side surface of the sacrificial layer, and a side surface of the second conductive layer; providing an opening in the second insulating layer, the sacrificial layer, the second conductive layer, and the first insulating layer, the opening reaching the first conductive layer; providing a first gap by removing the sacrificial layer; forming a first semiconductor layer to have a region in contact with an upper surface of the first conductive layer, a region in contact with a side surface of the first insulating layer at the opening, a region in contact with a side surface of the second conductive layer at the opening, a region in contact with a side surface of the second insulating layer at the opening, a region in contact with an upper surface of the second conductive layer in the first gap, and a region in contact with an upper surface of the second insulating layer; forming a third insulating layer and a third conductive layer in sequence on the first semiconductor layer; removing a portion of the third conductive layer, a portion of the third insulating layer, and a portion of the first semiconductor layer by a planarization process to expose an upper surface of the second insulating layer; forming a gate electrode by removing the portion of the third conductive layer; forming a gate insulating layer by removing the portion of the third insulating layer; forming a second semiconductor layer by removing the portion of the first semiconductor layer; forming a third semiconductor layer by removing a portion of the second semiconductor layer located within the opening of the second insulating layer; a fourth insulating layer is formed over the second insulating layer, the third semiconductor layer, the gate insulating layer, and the gate electrode. 　 In claim 6, The method for manufacturing a semiconductor device, wherein the first semiconductor layer is formed by using an atomic layer deposition method.

Images