Semiconductor device

Abstract

Provided is a semiconductor device having a narrow occupation area. The semiconductor device comprises a transistor, a first insulating layer, and a first conductive layer. The transistor has a metal oxide layer, a gate insulating layer, and a gate electrode. The first insulating layer has a first opening portion reaching the first conductive layer. The metal oxide layer has a first region in contact with an upper surface of the first conductive layer, a second region in contact with a side surface of the first insulating layer, and a third region in contact with an upper surface of the first insulating layer. The metal oxide layer has a region in contact with an end portion of the upper surface of the first insulating layer in the first opening portion. The gate electrode has a region that overlaps with the metal oxide layer via the gate insulating layer in the first opening portion. Each of the first region and the third region has a first element. The first element is boron or phosphorus. The first region has a portion higher in concentration of the first element than the second region and the third region has a portion higher in concentration of the first element than the second region.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely applied to electronic devices. In recent years, the applications of display devices have been diversified, and display devices are used in, for example, mobile information terminals, television devices (also called television receivers), digital signage, and public information displays (PIDs). Examples of display devices include display devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs), display devices having liquid crystal elements, and electronic paper that displays using an electrophoretic method.

[0005] In display devices, by reducing the area occupied by a transistor, the pixel size can be reduced and the resolution can be increased. In addition, by reducing the area occupied by a transistor, the aperture ratio can be increased. Therefore, there is a demand for miniaturized transistors.

[0006] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a transistor with a small size. Another object is to provide a transistor with a short channel length. Another object is to provide a transistor with high on-state current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, and a first conductive layer. The transistor includes a metal oxide layer, a gate insulating layer, and a gate electrode. The first insulating layer is located over the first conductive layer. The first insulating layer has a first opening that reaches the first conductive layer. The metal oxide layer has a first region that contacts a top surface of the first conductive layer in the first opening, a second region that contacts a side surface of the first insulating layer in the first opening, and a third region that contacts a top surface of the first insulating layer. The third region is continuous with the second region. The gate insulating layer is located over the metal oxide layer. The gate electrode has a region that overlaps with the metal oxide layer through the gate insulating layer in the first opening. The first region and the third region each contain a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The third region has a portion where the concentration of the first element is higher than that of the second region.

[0012] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, and a first conductive layer. The first transistor includes a first metal oxide layer, a gate insulating layer, and a first gate electrode. The first insulating layer is located over the first conductive layer. The first insulating layer has a first opening that reaches the first conductive layer. The first metal oxide layer includes a first region in contact with a top surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with a top surface of the first insulating layer. The gate insulating layer is located over the first metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer through the gate insulating layer in the first opening. The first region and the third region each include a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region, the third region has a portion where the concentration of the first element is higher than that of the second region, and the first metal oxide layer has a region in the third region that is in contact with any one of the gate, source, and drain of the second transistor.

[0013] One aspect of the present invention includes a first transistor, a second transistor, a first insulating layer, a first conductive layer, and a second conductive layer. The first transistor includes a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor includes the first metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located on the first conductive layer and the second conductive layer. The first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The first metal oxide layer has a first region in contact with the top surface of the first conductive layer at the first opening, a second region in contact with the side surface of the first insulating layer at the first opening, a third region in contact with the top surface of the first insulating layer, a fourth region in contact with the top surface of the second conductive layer at the second opening, and a fifth region in contact with the side surface of the first insulating layer at the second opening. The gate insulating layer is located on the first metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer via the gate insulating layer at the first opening. The second gate electrode has a region that overlaps with the first metal oxide layer via the gate insulating layer at the second opening. The first region and the third region each contain a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The third region has a portion where the concentration of the first element is higher than that of the second region.

[0014] In the semiconductor device described above, the fourth region preferably contains the first element, and the fourth region preferably has a portion having a higher concentration of the first element than the fifth region.

[0015] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, and a first conductive layer. The first transistor includes a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor includes a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer and a second opening. The first metal oxide layer has a first region in contact with a top surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with the top surface of the first insulating layer. The second metal oxide layer has a fourth region in contact with the top surface of the first conductive layer in the second opening, a fifth region in contact with the side surface of the first insulating layer in the second opening, and a sixth region in contact with the top surface of the first insulating layer. The gate insulating layer is located on the first metal oxide layer and the second metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer via the gate insulating layer in the first opening. The second gate electrode has a region that overlaps with the second metal oxide layer via the gate insulating layer in the second opening. The first region and the third region each contain a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The third region has a portion where the concentration of the first element is higher than that of the second region.

[0016] In the semiconductor device described above, the fourth region and the sixth region each preferably contain the first element. The fourth region preferably has a portion having a higher concentration of the first element than the fifth region. The sixth region preferably has a portion having a higher concentration of the first element than the fifth region.

[0017] One embodiment of the present invention is a semiconductor device including a capacitor, a first insulating layer, and a first conductive layer. The transistor includes a metal oxide layer, a gate insulating layer, and a gate electrode. The capacitor includes a metal oxide layer, a second conductive layer, and a gate insulating layer sandwiched between the metal oxide layer and the second conductive layer. The first insulating layer is located over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The metal oxide layer has a first region in contact with a top surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with a top surface of the first insulating layer. The gate insulating layer is located over the metal oxide layer. The gate electrode has a region overlapping with the metal oxide layer through the gate insulating layer in the first opening. The first region and the third region each contain a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The third region has a portion where the concentration of the first element is higher than that of the second region. The second conductive layer has a portion that overlaps with the third region with the gate insulating layer interposed therebetween.

[0018] One embodiment of the present invention is a semiconductor device including a capacitor, a first insulating layer, and a first conductive layer. The transistor includes a metal oxide layer, a gate insulating layer, and a gate electrode. The capacitor includes a metal oxide layer, a second conductive layer, and a first insulating layer sandwiched between the metal oxide layer and the second conductive layer. The first insulating layer is located over the first conductive layer and the second conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The metal oxide layer includes a first region in contact with a top surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with a top surface of the first insulating layer. The gate insulating layer is located over the metal oxide layer. The gate electrode has a region overlapping with the metal oxide layer through the gate insulating layer in the first opening. The first region and the third region each contain a first element. The first element is boron or phosphorus. The first region has a portion where the concentration of the first element is higher than that of the second region. The third region has a portion where the concentration of the first element is higher than that of the second region. The second conductive layer has a portion that overlaps with the third region via the first insulating layer.

[0019] In the semiconductor device described above, the concentration of the first element in the second region is 1×10 of the concentration of the first element in the first region. −３ It is preferable that the ratio is 1:1 or less.

[0020] In the semiconductor device described above, the concentration of the first element in the second region is 1×10 of the concentration of the first element in the third region. −３ It is preferable that the ratio is 1:1 or less.

[0021] In the above-described semiconductor device, the gate insulating layer preferably contains the first element.

[0022] In the semiconductor device described above, it is preferable that the angle formed between the side surface of the first insulating layer and the top surface of the first conductive layer in the first opening be equal to or greater than 65 degrees and equal to or less than 90 degrees.

[0023] In the semiconductor device described above, the first region preferably contains hydrogen, and the concentration of hydrogen in the first region is preferably higher than the concentration of hydrogen in the second region.

[0024] In the semiconductor device described above, the third region preferably contains hydrogen, and the concentration of hydrogen in the third region is preferably higher than the concentration of hydrogen in the second region.

[0025] In the semiconductor device described above, the first region preferably contains a second element, which is preferably argon, krypton, or xenon, and the first region preferably has a portion having a higher concentration of the second element than the second region.

[0026] In the semiconductor device described above, the third region preferably contains a second element. The second element is preferably argon, krypton, or xenon. The third region preferably has a portion having a higher concentration of the second element than the second region.

[0027] In the semiconductor device described above, the first insulating layer preferably includes a second insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer. The second insulating layer and the fourth insulating layer preferably each include silicon and nitrogen. The third insulating layer preferably includes silicon and oxygen.

[0028] In the semiconductor device described above, the first insulating layer preferably includes a second insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer. The second insulating layer preferably includes silicon and nitrogen. The third insulating layer preferably includes silicon and oxygen. The fourth insulating layer preferably includes one or both of aluminum and hafnium, and oxygen.

[0029] According to one embodiment of the present invention, a transistor with a small size can be provided. Alternatively, a transistor with a short channel length can be provided. Alternatively, a transistor with high on-state current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0031] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIG. 3A is a top view showing an example of a semiconductor device. FIGS. 3B and 3C are cross-sectional views showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIGS. 5A to 5D are cross-sectional views showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIG. 9A is a top view showing an example of a semiconductor device. FIG. 9B is a cross-sectional view showing an example of a semiconductor device. FIGS. 10A to 10F are circuit diagrams showing an example of a semiconductor device. FIGS. 11A to 11G are circuit diagrams showing an example of a semiconductor device. FIG. 12A is a top view showing an example of a semiconductor device. FIGS. 12B and 12C are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a top view showing an example of a semiconductor device. FIGS. 13B and 13C are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a top view showing an example of a semiconductor device. FIG. 14B is a cross-sectional view showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIGS. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a top view showing an example of a semiconductor device. FIG. 16B is a cross-sectional view showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIG. 17B is a cross-sectional view showing an example of a semiconductor device. FIGS. 18A to 18C are cross-sectional views showing an example of a semiconductor device. FIGS. 19A and 19B are equivalent circuit diagrams of a semiconductor device. FIG. 19C is a top view showing an example of a semiconductor device. FIG. 20 is a cross-sectional view showing an example of a semiconductor device. FIG. 21 is a perspective view showing an example of a semiconductor device. FIGS. 22A to 22D are perspective views showing an example of a semiconductor device. FIGS. 23A and 23B are equivalent circuit diagrams of a semiconductor device. FIG. 23C is a top view showing an example of a semiconductor device. FIG. 24 is a cross-sectional view showing an example of a semiconductor device. FIG. 25 is a perspective view showing an example of a semiconductor device. 26A to 26D are perspective views showing an example of a semiconductor device.27A to 27E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28A to 28D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29A to 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30A and 30B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31 is a perspective view illustrating an example of a display device. FIGS. 32A and 32B are cross-sectional views illustrating an example of a display device. FIG. 33 is a cross-sectional view illustrating an example of a display device. FIGS. 34A to 34C are cross-sectional views illustrating an example of a display device. FIGS. 35A and 35B are cross-sectional views illustrating an example of a display device. FIG. 36 is a cross-sectional view illustrating an example of a display device. FIG. 37 is a cross-sectional view illustrating an example of a display device. FIG. 38 is a cross-sectional view illustrating an example of a display device. FIGS. 39A to 39F are cross-sectional views illustrating an example of a method for manufacturing a display device. FIGS. 40A to 40D are views illustrating an example of an electronic device. FIGS. 41A to 41F are views illustrating an example of an electronic device. FIGS. 42A to 42G are views illustrating an example of an electronic device.

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0033] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0034] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims. Even if a term does not have an ordinal number attached to it in this specification, the ordinal number may be attached in the claims. Even if a term has an ordinal number attached to it in this specification, the ordinal number may be omitted in the claims.

[0036] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0037] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0038] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed depending on the situation, such as the source terminal and drain terminal, or the source electrode and drain electrode.

[0039] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0040] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the gate-source voltage (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the gate-source voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0041] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0042] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0043] In this specification, the phrase "top surface shapes are approximately the same" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned.

[0044] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0045] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0046] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0047] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0048] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0049] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0050] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0051] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0052] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 1A. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some of the components are also omitted in the top views of the semiconductor device in the following drawings.

[0053] 2A to 2D are perspective views of the semiconductor device 10. Fig. 2B shows a cross section taken along dashed line C1-C2 in Fig. 2A. Fig. 2C shows the insulating layer shown in Fig. 2A with its outline indicated by a dashed line. Similarly, Fig. 2D shows the insulating layer shown in Fig. 2B with its outline indicated by a dashed line.

[0054] The semiconductor device 10 includes a transistor 100, an insulating layer 110, and a conductive layer 112. The semiconductor device 10 is provided on an insulating surface. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film.

[0055] The transistor 100 includes a conductive layer 104, an insulating layer 106, and a layer 108. The layer 108 contains a semiconductor material. The layer 108 includes a channel formation region, a region 108Da functioning as one of a source electrode and a drain electrode, and a region 108Db functioning as the other of the source electrode and the drain electrode. A part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer) of the transistor 100, and the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode).

[0056] The regions 108Da and 108Db each contain an impurity element. The regions 108Da and 108Db each have a higher concentration of the impurity element and a lower electrical resistance than other regions (e.g., a channel formation region) of the layer 108. In the layer 108, the channel formation region is located between the regions 108Da and 108Db.

[0057] The conductive layer 112 has a region in contact with the region 108Da and is electrically connected to the transistor 100. The conductive layer 112 functions as a wiring.

[0058] A conductive layer 112 is provided on a substrate 102, and an insulating layer 110 is provided on the conductive layer 112. The insulating layer 110 has an opening 141 that reaches the conductive layer 112. In other words, the conductive layer 112 is exposed in the opening 141.

[0059] The layer 108 is provided to cover the opening 141. The layer 108 is provided along the opening 141. The layer 108 has a first region that contacts the conductive layer 112 at the opening 141, a second region that contacts the side surface of the insulating layer 110 at the opening 141, and a third region that contacts the top surface of the insulating layer 110. The layer 108 contacts the top edge of the insulating layer 110 at the opening 141. The third region is continuous with the second region, and the second region is continuous with the first region. No layer (particularly, a conductive layer) is provided between the top surface of the insulating layer 110 and the layer 108. That is, in a cross-sectional view, the entire third region contacts the top surface of the insulating layer 110. The region 108Da of the layer 108 has a region that contacts the conductive layer 112 at the opening 141 and is electrically connected to the conductive layer 112. The layer 108 has a shape that follows the shapes of the top surface and side surfaces of the insulating layer 110 and the top surface of the conductive layer 112. The layer 108 has a region that overlaps with the conductive layer 112 with the insulating layer 110 interposed therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112 and the layer 108.

[0060] The insulating layer 106 is provided to cover the opening 141. The insulating layer 106 is provided on the layer 108 and the insulating layer 110. The insulating layer 106 has a region in contact with the upper surface and side surfaces of the layer 108 and the upper surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the upper surface and side surfaces of the layer 108 and the upper surface of the insulating layer 110.

[0061] The conductive layer 104 is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the layer 108 in the opening 141 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0062] In the transistor 100, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows in the vertical direction or approximately vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0063] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure device used to fabricate the transistor can be fabricated with high precision. Furthermore, the characteristic variation among multiple transistors 100 is also reduced. Therefore, the operation of a semiconductor device including the transistor 100 can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0064] In the transistor of one embodiment of the present invention, a region functioning as a source electrode, a channel formation region, and a region functioning as a drain electrode can be provided so as to overlap with each other, and therefore the area occupied can be significantly reduced compared to a so-called planar transistor in which a source electrode, a semiconductor layer having a channel formation region, and a drain electrode are arranged in a planar shape.

[0065] The regions 108Da, 108Db, and the conductive layer 104 can also function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. Furthermore, the transistor 100 can be provided over the conductive layer 112, which functions as a wiring. That is, in a circuit including the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a compact semiconductor device can be achieved. Furthermore, because parts of the layer 108 (here, the regions 108Da and 108Db) function as a source electrode and a drain electrode, there is no need to provide source electrodes and drain electrodes separately from the layer 108, and therefore the area occupied can be further reduced. Furthermore, the manufacturing process of the semiconductor device can be simplified, leading to reduced manufacturing costs. The yield of the semiconductor device can be increased.

[0066] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0067] FIG. 3A shows an enlarged view of FIG. 1A , and FIGS. 3A and 3B show enlarged views of FIG. 1B . FIGS. 1B , 1C , 3B , and 3C illustrate an example in which a region 108Da is formed in the region of the opening 141 that overlaps with the lower surface of the conductive layer 104 of the layer 108, and a region 108Db is formed in the region of the layer 108 that contacts the upper surface of the insulating layer 110. More specifically, the region 108Da is formed in the region of the layer 108 that contacts the upper surface of the conductive layer 112, between the upper surface of the conductive layer 112 and the lower surface of the conductive layer 104. The region in which the region 108Da is formed is not limited thereto; for example, the region 108Da may be formed over the entire region that contacts the upper surface of the conductive layer 112. The region 108Db may also be provided in a portion of the region of the layer 108 that contacts the side surface of the insulating layer 110. For example, the impurity element may diffuse due to heat applied when the impurity element is supplied to the layer 108 or in a process after the impurity element is supplied. Note that, although two regions of the layer 108 that contact the upper surface of the insulating layer 110 are shown in the cross-sectional views such as Figure 3B, the regions 108Db are connected as one in top view. Note that the layer 108 may also be configured to have a plurality of regions 108Db that are separated from each other.

[0068] The impurity element is preferably supplied to the layer 108 through the insulating layer 106. By supplying the impurity element to the layer 108 through the insulating layer 106, the impurity element can be preferentially supplied to the regions 108Da and 108Db in the layer 108. Furthermore, by supplying the impurity element through the insulating layer 106, damage to the layer 108 during supply can be reduced.

[0069] The semiconductor material used for the layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0070] The crystallinity of the semiconductor material used for the layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0071] The layer 108 can be made of silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0072] The layer 108 preferably includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. When a metal oxide is used for the layer 108, the layer 108 can be considered a metal oxide layer. The band gap of the metal oxide used for the layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0073] The insulating layer 110 can be an organic insulating layer or an inorganic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0074] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0075] The insulating layer 110 has a region in contact with the layer 108. When a metal oxide is used for the layer 108, at least a part of the region of the insulating layer 110 in contact with the layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 in contact with the channel formation region of the layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region of the layer 108.

[0076] When a metal oxide is used for the layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the layer 108 releases oxygen by heating. As a result, oxygen is supplied from the insulating layer 110 to the layer 108, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and the oxygen vacancy (V Ｏ) into which hydrogen has entered (hereinafter referred to as V Ｏ H) can be reduced.

[0077] The insulating layer 110 preferably has a stacked structure. Figure 1B and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layers 110a, 110b, and 110c can each be made of the materials listed for the insulating layer 110. The layer 108 has a region 108M in contact with the insulating layer 110b.

[0078] The insulating layer 110b preferably contains oxygen. As a result, at least a region 108M of the layer 108 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably includes one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can preferably include one or both of silicon oxide and silicon oxynitride. Note that, although two regions of the layer 108 in contact with the insulating layer 110b are shown in cross-sectional views such as FIG. 3B, the regions 108M are connected as one in top view. Note that the layer 108 may also have a configuration including multiple regions 108M separated from each other.

[0079] It is more preferable to use a film that releases oxygen by heating for the insulating layer 110b. When heat is applied during the manufacturing process of the transistor 100, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the layer 108. By supplying oxygen from the insulating layer 110b to the layer 108, particularly to the region 108M that functions as a channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0080] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming an oxide film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the oxide film can be removed.

[0081] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The insulating layer 110b can be formed by a sputtering method in particular. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0082] Here, by using a material with high conductivity for the layer 108, a transistor with large on-state current can be obtained. However, when a material with high conductivity is used, oxygen vacancies (V Ｏ ) is easily formed in the channel formation region, and oxygen vacancies (V Ｏ ) increases, the threshold voltage of the transistor shifts, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may increase. For example, in an n-channel transistor, the cutoff current may increase when the threshold voltage shifts to the negative side. By providing the insulating layer 110b, oxygen is supplied to at least the region 108M of the layer 108 that is in contact with the insulating layer 110b, i.e., the channel formation region, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0083] The insulating layer 110a is provided between the substrate 102 and the conductive layer 112 and the insulating layer 110b. The insulating layer 110c is provided between the insulating layer 110b and the layer 108. The insulating layers 110a and 110c preferably release small amounts of impurities (e.g., hydrogen and water). Furthermore, the insulating layers 110a and 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layers 110a and 110c can also function as barrier films. Specifically, the insulating layers 110a and 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layers 110a and 110c from diffusing into the channel formation region of the layer 108. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0084] It is preferable that the insulating layer 110a and the insulating layer 110c are made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112 side through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the region 108Db side through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the layer 108, and reduces oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained. Furthermore, an increase in electrical resistance due to diffusion of oxygen contained in the insulating layer 110b into the region 108Db can be suppressed. Therefore, the transistor 100 can have a large on-state current. Furthermore, an increase in electrical resistance due to oxidation of the conductive layer 112 by oxygen contained in the insulating layer 110b can be suppressed. This allows a semiconductor device capable of high-speed operation.

[0085] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0086] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0087] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0088] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the layer 108 to be increased, and oxygen deficiency (V Ｏ ) can be effectively reduced.

[0089] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. As shown in FIG. 3C , the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0090] If the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112 side through the insulating layer 110a, which may reduce the amount of oxygen supplied to the channel formation region. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, which may increase the amount of impurities diffusing into the channel formation region. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the conductive layer 112 from being oxidized by oxygen contained in the insulating layer 110b, which would increase the electrical resistance of the conductive layer 112. The thickness T110a is not limited to the above range.

[0091] The thickness T110a can be made thicker than the thickness T110c of the insulating layer 110c. When the region of the layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or the drain region to the gate electrode more uniform. The same applies to the layer 208. This can make the electric field of the gate electrode applied to the channel formation region more uniform.

[0092] The thickness T110c is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 3 nm to 50 nm, even more preferably 3 nm to 30 nm, even more preferably 3 nm to 20 nm, even more preferably 3 nm to 10 nm, even more preferably 5 nm to 10 nm. As shown in FIG. 3C , the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0093] The thickness T110c is preferably a value that at least functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness T110a. If the thickness T110c is thick, the amount of impurities released from the insulating layer 110c increases, which may result in a larger amount of impurities diffusing into the channel formation region. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the region 108Db via the insulating layer 110c, which may result in a decrease in the amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above-mentioned range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ The thickness T110c is not limited to the above range.

[0094] As described above, the region 108Da and the region 108Db function as a source electrode and a drain electrode. The thickness T108a of the region 108Da and the thickness T108b of the region 108Db are preferably 5 nm to 300 nm, more preferably 10 nm to 200 nm, even more preferably 15 nm to 150 nm, even more preferably 15 nm to 100 nm, and even more preferably 20 nm to 100 nm. As shown in FIG. 3B , the thickness T108a can be the shortest distance between the top surface of the conductive layer 112 and the top surface of the layer 108 in a cross-sectional view. The thickness T108b can be the shortest distance between the top surface of the insulating layer 110 and the top surface of the layer 108.

[0095] If the thickness T108a and the thickness T108b are small, the electrical resistance of the regions 108Da and 108Db may become high. On the other hand, if the thickness T108a and the thickness T108b are large, the thickness of the region 108M also becomes large, and oxygen vacancies (V Ｏ By setting the thickness T108a and the thickness T108b within the above ranges, the electrical resistance of the source electrode and the drain electrode can be reduced, and a transistor with favorable electrical characteristics can be obtained.

[0096] The sheet resistance (also referred to as surface resistivity or sheet resistivity) of each of the regions 108Da and 108Db is preferably 1000 Ω / □ (also written as Ω / sq) or less, more preferably 500 Ω / □ or less, even more preferably 300 Ω / □ or less, even more preferably 200 Ω / □ or less, and even more preferably 100 Ω / □ or less. Note that, since it is preferable that the electrical resistance of the regions 108Da and 108Db is low, there is no lower limit to the sheet resistance.

[0097] The regions 108Da and 108Db each contain an impurity element, preferably a first element.

[0098] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0099] The first element is not limited to the above elements, and one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements can be used.

[0100] By supplying the first element to the regions 108Da and 108Db (which may also be referred to as adding or injecting the first element), oxygen vacancies (V Ｏ ) occurs. Then, the oxygen deficiency (V Ｏ ) with hydrogen in it. Ｏ Carriers are generated by H, and the electrical resistance is reduced. As a result, the regions 108Da and 108Db exhibit conductivity and can function as conductors. Therefore, in the layer 108, the regions 108Da and 108Db can function as a source electrode and a drain electrode. Note that a metal oxide that functions as a conductor can be called an oxide conductor (OC). In general, metal oxides have a wide band gap and therefore transmit visible light (in other words, they have transparency to visible light). Furthermore, an oxide conductor is a metal oxide that has a donor level near the conduction band. Therefore, an oxide conductor is less affected by absorption due to the donor level and has transparency to visible light comparable to that of a metal oxide.

[0101] When an element that easily bonds with oxygen is used as the first element, the first element takes away oxygen from the layer 108 and exists in a state of being bonded to oxygen. Also, oxygen vacancies (V Ｏ) occurs. When an element that becomes stable when bonded with oxygen is used as the first element, the first element in layer 108 exists stably in an oxidized state, and is therefore less likely to be desorbed by heat or the like applied during the manufacturing process of semiconductor device 10, making it possible to maintain low electrical resistance. For this reason, it is preferable to use as the first element an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process. Specifically, preferred first elements include typical nonmetal elements other than hydrogen, typical metal elements, and transition elements (transition metals), and particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0102] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0103] Ion implantation can be suitably used to supply the impurity element. The ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Note that by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurity element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased.

[0104] When boron is used as the first element, the source gas may be, for example, BF ３ When phosphorus is used as the first element, the source gas may be, for example, PH ３ Furthermore, by mass-separating ions generated from these gases and supplying them, ions of specific masses can be supplied to the region 108Da and the region 108Db, which is more preferable.

[0105] In addition to the first element, hydrogen can be used as the impurity element. By supplying hydrogen, oxygen vacancies (V Ｏ ) occurs, and V ＯThe first element and hydrogen are suitable as impurity elements because they generate H. By using the first element and hydrogen as impurity elements, the electrical resistance of each of the regions 108Da and 108Db can be easily reduced and the electrical resistance can be maintained at a low level.

[0106] When the first element and hydrogen are supplied, a gas containing the first element and hydrogen (for example, PH ３ Gas and B ２ H ６ Alternatively, a mixed gas of a gas containing the first element and a gas containing hydrogen can be used as the source gas. By using a source gas containing the first element and hydrogen, ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity. For example, a source gas containing B ２ H ６ By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using gas, phosphorus and hydrogen can be supplied as impurity elements.

[0107] Each of the regions 108Da and 108Db preferably has a portion with a higher concentration of impurity elements than the region 108M.

[0108] The regions 108Da and 108Db each have an impurity element concentration of 5×10 １８ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 1 × 10, preferably １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ or less, more preferably 5 × 10 １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ or less, more preferably 5 × 10 １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３It is preferable that the impurity element concentration includes a portion where the region 108Da and the region 108Db are equal to or less than 108Db. If the concentration of the impurity element is low, the electrical resistance of the region 108Da and the region 108Db may become high. On the other hand, if the concentration of the impurity element is high, that is, if a large amount of the impurity element is supplied, the layer 108 may be damaged during supply, which may increase the electrical resistance of the region 108Da and the region 108Db. Therefore, by setting the concentration of the impurity element within the above-mentioned range, the electrical resistance of the region 108Da and the region 108Db can be reduced, and the transistor 100 can have a large on-current.

[0109] When the region 108Da contains two or more impurity elements, it is preferable that the concentration of at least one of the impurity elements is in the above range. It is more preferable that the concentration of each impurity element is in the above range. The same applies to the region 108Db.

[0110] When the impurity elements are supplied to the regions 108Da and 108Db, the impurity elements may also be supplied to the channel formation region of the layer 108. Alternatively, due to heat or the like applied during the manufacturing process, some of the impurity elements contained in the regions 108Da and 108Db may diffuse into the channel formation region.

[0111] The concentration of the impurity element in the region 108M, which functions as a channel formation region, is preferably low. The concentration of the impurity element in the region 108M is preferably lower than the concentrations of the impurity elements in the regions 108Da and 108Db. This can prevent the carrier concentration in the channel formation region from increasing. Therefore, a shift in the threshold voltage can be prevented, and the transistor 100 can have a small cutoff current. Furthermore, the semiconductor device can have low power consumption.

[0112] The concentration of the impurity element in the region 108M is 1×10 −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４Similarly, the concentration of the impurity element in the region 108M is preferably 1×10 times or less of the concentration of the impurity element in the region 108Db. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ This allows the transistor 100 to have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0113] The concentration of impurity elements in each region of the layer 108 can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) or electron spectrometry for chemical analysis (ESCA). When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in regions with low impurity element concentrations, quantification may be difficult or the concentration may be below the detection limit.

[0114] When the impurity element is supplied to the layer 108 through the insulating layer 106, the insulating layer 106 may also contain the impurity element. It is preferable that the regions 108Da and 108Db each have a portion with a higher concentration of the impurity element than the insulating layer 106, because the electrical resistance of the regions 108Da and 108Db can be reduced. Furthermore, the impurity element may also be supplied to the insulating layer 110 through the insulating layer 106 and the layer 108, or through the insulating layer 106. In this case, the concentration of the impurity element is higher in a region of the insulating layer 110 that does not overlap with the layer 108 than in a region of the insulating layer 110 that overlaps with the layer 108. Furthermore, the concentration of the impurity element is higher in a position of the insulating layer 110 closer to the insulating layer 106. For example, the concentration of the impurity element in the insulating layer 110c is higher than that in the insulating layer 110a. For analysis of the concentrations of the impurity elements in the insulating layer 106 and the insulating layer 110, the description of the analysis of the concentration of the impurity element in the layer 108 can be referred to.

[0115] In manufacturing the semiconductor device of one embodiment of the present invention, the regions 108Da and 108Db are preferably more easily supplied with impurity elements than the channel formation region (here, the region 108M). The impurity element is preferably supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. In this case, the amount of the impurity element supplied to a region of the layer 108 that is inclined with respect to the top surface of the substrate 102 is smaller than that supplied to a region that is parallel or substantially parallel to the top surface of the substrate 102. In other words, the amount of the impurity element supplied to the regions 108Da and 108Db is larger than that supplied to the channel formation region. Therefore, the electrical resistance of the regions 108Da and 108Db can be preferentially reduced.

[0116] Since the insulating layer 106 is provided so as to cover the opening 141, it is preferable to use a method with high coverage for its formation. The insulating layer 106 is preferably formed by sputtering, PECVD, or atomic layer deposition (ALD). As the ALD method, thermal ALD or PEALD (Plasma Enhanced ALD) can be used. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it exhibits high coverage and allows low-temperature film formation.

[0117] 3C shows the thickness Ta of the insulating layer 106 at a portion thereof in contact with the region 108Da, the thickness Tb of the portion thereof in contact with the region 108Db, and the thickness Tc of the portion thereof in contact with the region 108M. The thicknesses Ta, Tb, and Tc are each the thicknesses in a direction perpendicular or substantially perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the top surface of the layer 108 provided along the top surface of the conductive layer 112 and the top surface of the insulating layer 106. The thickness Tb is the shortest distance between the top surface of the layer 108 provided along the top surface of the insulating layer 110 and the top surface of the insulating layer 106. The thickness Tc is the shortest distance between the side surface of the layer 108 provided along the side surface of the insulating layer 110 on the insulating layer 106 side and the side surface of the insulating layer 106 on the conductive layer 104 side.

[0118] 3A illustrates a structure in which the thicknesses Ta, Tb, and Tc are the same, but one embodiment of the present invention is not limited to this. The thicknesses Ta, Tb, and Tc may be partially or entirely different from each other. The thickness Tc of the region of the insulating layer 106 provided along the side surface of the insulating layer 110 may be thinner than the thicknesses Ta and Tb of the region of the insulating layer 106 provided along the top surface of the conductive layer 112 or the insulating layer 110. For example, when the insulating layer 106 is formed by a PECVD method or a sputtering method, the thickness Tc may be thinner than both the thicknesses Ta and Tb. Furthermore, when the insulating layer 106 is formed by an ALD method, the thickness Tc can be closer to the thicknesses Ta and Tb. Alternatively, the thickness Tc can be the same as or approximately the same as the thicknesses Ta and Tb.

[0119] As described above, the insulating layer 106 functions as a gate insulating layer in the transistor 100. The thickness Tc of the portion of the insulating layer 106 in contact with the region 108M is preferably 1 nm to 200 nm, more preferably 1 nm to 150 nm, and even more preferably 1 nm to 100 nm. For example, when the channel length is 100 nm to 500 nm, the thickness Tc is preferably 30 nm to 100 nm. Furthermore, for example, when the channel length is 10 nm to 100 nm, the thickness Tc is preferably 1 nm to 50 nm. Furthermore, for example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm.

[0120] The supply of the impurity element to the layer 108 will be described with reference to Fig. 3C. Here, an example will be described in which the impurity element is supplied from a direction perpendicular to the top surface of the substrate 102. Note that the cross-sectional view shown in Fig. 3C illustrates a configuration in which the surface of the insulating layer 106 (specifically, the top surface and side surface of the insulating layer 106) is parallel to the top surface and side surface of the layer 108, which is the surface on which the insulating layer 106 is formed.

[0121] As described above, the impurity element is preferably supplied to the layer 108 through the insulating layer 106. When the impurity element is supplied to the layer 108 through the insulating layer 106, the impurity element penetrates from the surface of the insulating layer 106, passes through the insulating layer 106, and then reaches the layer 108 through the interface between the insulating layer 106 and the layer 108. In this case, the thickness of the insulating layer 106 in the direction in which the impurity element is supplied can also be said to be the depth from the surface of the insulating layer 106 to the layer 108 of the impurity element. Specifically, the thickness Ta can be said to be the depth from the surface of the insulating layer 106 to the region 108Da of the impurity element, and the thickness Tb can be said to be the depth from the surface of the insulating layer 106 to the region 108Db of the impurity element.

[0122] FIG. 3C shows the thickness Td of the insulating layer 106 along the side surface of the insulating layer 110 in a direction perpendicular to the top surface of the substrate 102. For example, the thickness Td can be the thickness of the insulating layer 106 on a line extending from the midpoint between the top and bottom edges of the insulating layer 110b in a direction perpendicular to the top surface of the substrate 102. The thickness Td can also be considered the depth from the surface of the insulating layer 106 to the region 108M where the impurity element reaches. Compared to the thickness Td, the thicknesses Ta and Tb are thinner. As a result, the regions of the layer 108 along the top surface of the conductive layer 112 or the top surface of the insulating layer 110 (e.g., regions 108Da and 108Db) receive a larger amount of impurity element than the regions along the side surface of the insulating layer 110 (e.g., region 108M). In this way, the supply of impurity element to the channel formation region can be suppressed, and the electrical resistance of the source and drain electrodes can be preferentially reduced.

[0123] The thicker the insulating layer 106, the larger the difference between the thickness Ta and the thickness Td and the difference between the thickness Tb and the thickness Td can be. This can suppress the supply of impurity elements to the channel formation region and preferentially reduce the electrical resistance of the source electrode and the drain electrode. On the other hand, in order to miniaturize transistors or fabricate transistors with extremely short channel lengths, a smaller thickness Tc is preferable from the viewpoints of improving on-current and suppressing the short channel effect.

[0124] The insulating layer 106 preferably includes an insulating layer containing oxygen. When an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state bonded to oxygen in the insulating layer 106 as in the layer 108. When oxygen and the impurity element are bonded and stabilized, oxygen is less likely to be released from the region containing the impurity element even when heat is applied, thereby suppressing oxygen diffusion to other layers. This suppresses oxygen supply from the insulating layer 106 to the regions 108Da and 108Db while efficiently supplying oxygen to the channel formation region. Therefore, oxygen vacancies in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da and 108Db from increasing. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0125] For example, when boron is used as an impurity element, the boron contained in the regions 108Da, 108Db, and the insulating layer 106 may exist in a state of being bonded to oxygen. ２ O ３ In XPS analysis, the spectral peak due to the existence of elemental boron is not observed or the peak intensity is extremely small, almost to the background level.

[0126] Note that a layer to which an impurity element is supplied may be referred to as an implanted layer. For example, when an impurity element is supplied to the layer 108 through the insulating layer 106, each of the insulating layer 106 and the layer 108 may be referred to as an implanted layer.

[0127] The acceleration energy used to supply the impurity element is preferably set according to the type of impurity element (specifically, the type of ion), the composition, film density, and thickness of the implanted layer. For example, it is preferable to set the acceleration energy so that the concentration of the impurity element is highest at the interface between region 108Da and insulating layer 106, the interface between region 108Db and insulating layer 106, or in the vicinity thereof. Furthermore, if the acceleration energy is too high, the concentration of the impurity element in region 108M will also be high. Therefore, it is preferable to set the acceleration energy so that the concentration of the impurity element in region 108M does not become high.

[0128] The concentration of the impurity element in the depth direction can be simulated using software, for example. Examples of simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. The type of impurity element to be supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy can be used as simulation parameters. When the impurity element is supplied to the layer 108 through the insulating layer 106, the depth to the region 108Da is "Ta", the depth to the region 108Db is "Tb", and the depth to the region 108M is "Td". It is preferable to select an acceleration energy that results in a high concentration of the impurity element in the regions 108Da and 108Db and a low concentration of the impurity element in the region 108M. Furthermore, it is preferable to select an acceleration energy that allows the concentrations of the impurity elements in the regions 108Da, 108Db, and 108M to fall within the aforementioned ranges.

[0129] The regions 108Da and 108Db can each have a configuration including a first element and a second element as an impurity element. The second element is different from the first element. The second element can be one or more of the elements that can be used as the first element. The second element preferably has a larger mass number than the first element. The first element preferably easily bonds with oxygen. For example, boron or phosphorus can be used as the first element, and argon, krypton, or xenon can be used as the second element.

[0130] After the second element is supplied to the layer 108, the first element can be supplied to the layer 108. When the mass number of the supplied element is large, the number of metal-oxygen bonds broken in the metal oxide of the layer 108 increases. Furthermore, due to the breaking of the metal-oxygen bonds, oxygen vacancies (V Ｏ ) occurs. By supplying the first element after supplying the second element having a larger mass number to break more bonds between the metal and oxygen, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0131] When the amount of the second element supplied to the channel forming region increases, oxygen vacancies (V Ｏ ) occurs, and V Ｏ There is a risk that H will increase, resulting in an increase in carrier concentration. Therefore, it is preferable that the concentration of the second element in the channel formation region is lower than the concentration of the second element in the region 108Da and lower than the concentration of the second element in the region 108Db. More specifically, it is preferable that the concentration of the second element in the region 108M is lower than the concentration of the second element in the region 108Da and lower than the concentration of the second element in the region 108Db.

[0132] The second element is preferably supplied to the layer 108 via the insulating layer 106. By supplying the second element to the layer 108 via the insulating layer 106, the second element can be preferentially supplied to the regions 108Da and 108Db. Furthermore, by supplying the second element via the insulating layer 106, damage to the layer 108 during supply can be reduced. When the first element and the second element are supplied to the layer 108 via the insulating layer 106, the insulating layer 106 may contain the second element in addition to the first element. Furthermore, the insulating layer 110 may also contain the second element in addition to the first element.

[0133] It is more preferable to supply the second element to the layer 108 through the insulating layer 106, and then supply the first element to the layer 108 through the insulating layer 106. This makes it possible to efficiently reduce the electrical resistance of the regions 108Da and 108Db.

[0134] The second element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the substrate 102. The second element can be supplied by the same method as that used to supply the first element. For example, ion implantation can be suitably used to supply the second element. Since the second element has a larger mass number than the first element, it is more preferable that the acceleration energy used to supply the second element be higher than the acceleration energy used to supply the first element. This increases the amount of the second element supplied to the regions 108Da and 108Db, thereby efficiently reducing the electrical resistance of the regions 108Da and 108Db.

[0135] Alternatively, the first element and the second element can be supplied in the same step. For example, the first element and the second element can be supplied to the layer 108 using a source gas containing the first element and the second element. Alternatively, a mixed gas of a gas containing the first element and a gas containing the second element can be used as the source gas. For example, when the first element is boron and the second element is argon, BF ３ The source gas is not limited to a mixed gas, and a gas containing the first element and the second element can also be used.

[0136] 1B and the like show an example in which the insulating layer 110 has the opening 141, and the layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141; however, one embodiment of the present invention is not limited to this. A structure in which a step is formed in the insulating layer 110, and the layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step may also be used.

[0137] An insulating layer 195 is provided to cover the transistor 100. The insulating layer 195 functions as a protective layer for the transistor 100. The insulating layer 195 is provided over the insulating layer 106 and the conductive layer 104. Note that the insulating layer 195 is omitted in the perspective views shown in FIGS. 2A to 2D.

[0138] [Layer 108] Metal oxides that can be used for the layer 108 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0139] The layer 108 may be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0140] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0141] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0142] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0143] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0144] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0145] The electrical characteristics and reliability of the transistor 100 vary depending on the composition of the metal oxide used in the layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0146] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0147] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0148] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0149] By using a material with a high indium content for the layer 108, the on-state current or the field-effect mobility of the transistor 100 can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0150] Here, if a polycrystalline metal oxide is used for the layer 108, the crystal grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Furthermore, if a polycrystalline metal oxide is used for the layer 108, the surface of the layer 108 may become uneven. This may increase the step on the surface on which a layer (e.g., the insulating layer 106) formed on the layer 108 is formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily forms a polycrystalline structure is used for the layer 108, it is preferable to include an element that inhibits crystallization. This prevents the layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the layer 108 can be improved, preventing defects such as discontinuities or voids in the layer.

[0151] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure and is therefore suitable for use in the layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the layer 108, it is preferable that the ITSO have crystallinity. Note that the layer 108 may have an amorphous region or may be amorphous.

[0152] A metal oxide that does not contain element M can be applied to the layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0153] The composition of the layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low concentrations, the actual concentration may differ from the concentration obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0154] The sputtering method or the ALD method can be suitably used for forming the metal oxide. As the ALD method, the thermal ALD method or the PEALD method can be used. When the metal oxide is formed by the sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target. The PECVD method can also be used for forming the metal oxide.

[0155] The layer 108 is preferably formed using a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0156] The layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0157] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the layer 108 is formed. The layer 108 preferably has layered crystals parallel or approximately parallel to the surface where the layer 108 is formed. For example, the layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the insulating layer 110 in a region in contact with the top surface of the insulating layer 110 and layered crystals parallel or approximately parallel to the side surface of the insulating layer 110 in a region in contact with the side surface of the insulating layer 110. In particular, the layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface where the layer 108 is formed, in the opening 141. With this structure, the layered crystals of the layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0158] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0159] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total flow rate of film formation gas (hereinafter also referred to as oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0160] The crystallinity of the layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of these techniques.

[0161] When a metal oxide is used for the layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0162] When a metal oxide is used for the layer 108, the carrier concentration in the channel forming region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0163] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0164] The layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0165] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0166] The layer 108 can have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers in the layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers in the layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly visible.

[0167] When the layer 108 has a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, and therefore the crystallinity of the second metal oxide layer may be increased. Furthermore, by performing heat treatment after forming the second metal oxide layer, the crystallinity of the first metal oxide layer can be increased. This heat treatment can also be called a crystallization treatment.

[0168] A first metal oxide layer is formed, and then a second metal oxide layer having higher crystallinity than the first layer is formed. For example, ALD can be suitably used to form the first metal oxide layer, and sputtering can be suitably used to form the second metal oxide layer. By performing heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. In this case, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to serve as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

[0169] A three-layer structure having a third metal oxide layer on the second metal oxide layer can be formed. For example, the first metal oxide layer and the third metal oxide layer can be formed by an ALD method, and the second metal oxide layer can be formed by a sputtering method. Heat treatment after the formation of the third metal oxide layer can increase the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer. In this case, crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer and the third metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. When the second metal oxide layer has a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

[0170] By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the semiconductor layer. This allows for a highly reliable transistor to be realized. Note that the thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the semiconductor layer is formed. A metal oxide layer with increased crystallinity in this manner can be called an axial growth CAAC (AG CAAC). Note that, in addition to crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the semiconductor layer is formed.

[0171] The temperature of the heat treatment can be set to 100°C or higher and lower than the strain point of the substrate. Specifically, a temperature of 100°C or higher and 800°C or lower is preferable, more preferably a temperature of 250°C or higher and 650°C or lower, and even more preferably a temperature of 350°C or higher and 550°C or lower is preferable. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C to 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by thermal conduction or thermal radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0172] [Opening 141] The top surface shape of the opening 141 is not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or any other polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shape of the opening 141 is preferably circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other figures, "circular" is not limited to a perfect circle.

[0173] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface edge of the insulating layer 110 on the opening 141 side.

[0174] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 3A and 3B.

[0175] In Figures 3B and 3C, the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, for example, the channel length L100 can be set to a value smaller than the minimum exposure dimension of an exposure tool, thereby achieving a transistor with a very small size. Specifically, it is possible to achieve a transistor with an extremely short channel length that could not be achieved using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to achieve a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0176] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0177] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0178] The channel length L100 can be controlled by adjusting the thickness T110b and the angle θ110.

[0179] The thickness T110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b may be appropriately set to obtain a desired channel length L100. As shown in FIG. 3B , the thickness T110b may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0180] The side surface of the insulating layer 110 on the opening 141 side is preferably tapered. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of a layer (e.g., layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0181] The angle θ110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angle θ110 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angle θ110 can be set appropriately to obtain the desired channel length L100.

[0182] When the angle θ110 is less than 90 degrees, the larger the angle θ110, the larger the difference between the thickness Ta and the thickness Td, and the difference between the thickness Tb and the thickness Td. Therefore, the impurity element is prevented from being supplied to the region 108M, and the impurity element is preferentially supplied to the region 108Da and the region 108Db. This allows the electrical resistance of the source electrode and the drain electrode to be efficiently reduced.

[0183] 3B, the angle θ110 is shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. For example, as shown in FIG. 4, the angle θ110 can be set to 90 degrees or approximately 90 degrees. This allows the channel length L100 to be shortened.

[0184] In a configuration in which the angle θ110 is 90 degrees, when an impurity element is supplied through the insulating layer 106, the impurity element must pass through the insulating layer 106 and the region of the layer 108 that contacts the side surface of the insulating layer 110c before reaching the region 108M. Therefore, the depth in the region 108M is deeper than the depth in the regions 108Da and 108Db. Therefore, the concentration of the impurity element in the region 108M is lower than the concentration of the impurity element in the regions 108Da and 108Db. Note that the higher the film density of the material used for the layer 108, the higher the stopping power in ion implantation, and the lower the amount of impurity element reaching the channel formation region. For example, if the film density of the layer 108 is higher than that of the insulating layer 106, the amount of the impurity element supplied to the layer 108 will be lower even at the same depth. Furthermore, because the stopping power in ion implantation varies depending on the type of element, the amount of the impurity element supplied also varies depending on the composition of the implanted layer.

[0185] 1B and the like show a structure in which the side surface of the insulating layer 110 on the opening 141 side has a straight line in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the side surface of the insulating layer 110 on the opening 141 side may have a curved line, or the side surface may have both a straight line region and a curved line region.

[0186] 3A and 3B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 3A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0187] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110 (or the insulating layer 110b) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any of the diameters at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these points of the insulating layer 110 (or the insulating layer 110b) in a cross-sectional view.

[0188] When the opening 141 is formed using photolithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0189] Note that, when the channel length L100 is shortened, it is preferable that the insulating layers 110a and 110c are made of materials that release less hydrogen. When the insulating layers 110a and 110c are made of materials that release even a small amount of hydrogen, it is preferable that these layers have a small thickness. For example, when the channel length L100 is set to 100 nm or less, the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are each preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 40 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 15 nm or less, even more preferably 3 nm or more and 10 nm or less, and even more preferably 5 nm or more and 10 nm or less. This reduces the amount of hydrogen that diffuses into the region 108M, and provides a highly reliable transistor that exhibits good electrical characteristics even when the channel length L100 is short.

[0190] Although the structure in which the region 108M of the layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described as an example here, one embodiment of the present invention is not limited to this. A part of the region of the layer 108 in contact with the insulating layer 110a (specifically, a region of the layer 108 in contact with a side surface of the insulating layer 110a other than the region 108Da) may also function as a channel formation region. Similarly, a part of the region in contact with the insulating layer 110c (specifically, a region of the layer 108 in contact with a side surface of the insulating layer 110c other than the region 108Db) may also function as a channel formation region.

[0191] Impurities released from the insulating layer 110a may lower the electrical resistance of a region of the layer 108 that contacts the insulating layer 110a (specifically, a region of the layer 108 that contacts the side surface of the insulating layer 110a other than the region 108Da). Similarly, impurities released from the insulating layer 110c may lower the electrical resistance of a portion of the region of the layer 108 that contacts the insulating layer 110c (specifically, a region of the layer 108 that contacts the side surface of the insulating layer 110c other than the region 108Db). These regions can be referred to as low-resistance regions. The low-resistance region is a region with lower electrical resistance than the channel formation region. The low-resistance region can also be referred to as a region with a higher carrier concentration or a higher oxygen defect density than the channel formation region.

[0192] The layer 108 may have a low-resistance region between the region 108Da and the region 108Db, which function as a source electrode and a drain electrode, and the channel formation region. The low-resistance region may function as a buffer region for alleviating the drain electric field. By providing a low-resistance region between the drain electrode and the channel formation region, a high electric field is less likely to be generated near the drain, which can suppress the generation of hot carriers and transistor degradation. For example, in the transistor 100, if the region 108Da functions as a source electrode and the region 108Db functions as a drain electrode, the region of the layer 108 that contacts the side surface of the insulating layer 110c may be made a low-resistance region, which can suppress the generation of high electric fields near the drain, which can suppress the generation of hot carriers and transistor degradation. When region 108Da functions as a drain electrode and region 108Db functions as a source electrode, by making the region of layer 108 that is in contact with the upper surface of conductive layer 112 other than region 108Da a low-resistance region, it becomes difficult for a high electric field to occur near the drain, thereby suppressing the generation of hot carriers and preventing deterioration of the transistor.

[0193] [Conductive Layer 104, Conductive Layer 112] The conductive layer 104 and the conductive layer 112 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 104 and the conductive layer 112 can each be preferably made of a conductive material with low electrical resistivity, including one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0194] A conductive metal oxide (also referred to as an oxide conductor) can be used for each of the conductive layer 104 and the conductive layer 112. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0195] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0196] The conductive layer 104 and the conductive layer 112 can each have a stacked-layer structure of a conductive film containing the above-described oxide conductor and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0197] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used for each of the conductive layer 104 and the conductive layer 112. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0198] Note that the conductive layer 104 and the conductive layer 112 can be formed using the same material, or at least one of them can be formed using a different material.

[0199] The conductive layer 112 has a region in contact with the layer 108. When an oxide semiconductor is used for the layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer and the semiconductor layer, hindering electrical conduction therebetween. Therefore, for the conductive layer 112, it is preferable to use a material that is not easily oxidized, a material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0200] For example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, or oxide containing lanthanum and nickel is preferably used for the conductive layer 112. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112 has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the layer 108.

[0201] The above-mentioned oxide conductors can be used for the conductive layer 112. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0202] A nitride conductor may be used for the conductive layer 112. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 may be made of any of the nitride conductors described above.

[0203] 5A to 5D are cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, refer to FIG. 1A. 5A to 5D are cross-sectional views of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0204] The semiconductor device 10A includes a transistor 100, an insulating layer 110, and a conductive layer 112. The semiconductor device 10A differs mainly from the semiconductor device 10 shown in FIG. 1B and the like in that the conductive layer 112 has a stacked structure.

[0205] 5A and 5B show a configuration in which the conductive layer 112 has a two-layer structure of a conductive layer 112a and a conductive layer 112b on the conductive layer 112a.

[0206] For the conductive layer 112b having a region in contact with the layer 108, a material that is not easily oxidized, a material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112b, the description of the conductive layer 112 can be referred to.

[0207] The conductive layer 112a does not have a region in contact with the layer 108, and therefore the material used is not particularly limited. For example, the conductive layer 112a is preferably made of a material having lower electrical resistivity than the conductive layer 112b. This can reduce the electrical resistance of the conductive layer 112. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112b, and copper or tungsten can be preferably used for the conductive layer 112a.

[0208] 5A, the edge of the conductive layer 112b can be aligned or approximately aligned with the edge of the conductive layer 112a. For example, the conductive layer 112 can be formed by forming a first film that will become the conductive layer 112a and a second film that will become the conductive layer 112b, and then processing the first and second films. By processing the first and second films in the same process, manufacturing costs can be reduced.

[0209] The end of the conductive layer 112b may not be aligned with the end of the conductive layer 112a. As shown in FIG. 5B , the conductive layer 112b may be provided so as to cover the conductive layer 112a. The conductive layer 112b has regions in contact with the top and side surfaces of the conductive layer 112a. It can also be said that the conductive layer 112b has portions that protrude beyond the end of the conductive layer 112a. For example, the conductive layer 112a may be formed, a film that will become the conductive layer 112b may be formed on the conductive layer 112a, and the film may be processed to form the conductive layer 112b. By making the conductive layer 112b protrude beyond the end of the conductive layer 112a, the step on the surface where a layer (e.g., the insulating layer 110) formed on the conductive layer 112a is formed is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0210] 5A and 5B, the layers constituting the conductive layer 112 are shown to have the same or approximately the same thickness, but this is not limited to this embodiment of the present invention. The thicknesses of some or all of the layers constituting the conductive layer 112 may be different. For example, it is more preferable to make the thickness of a layer using a material with low electrical resistivity thicker than the other layers, which can reduce the electrical resistance of the conductive layer 112. Specifically, a material with lower electrical resistivity than the conductive layer 112b can be used for the conductive layer 112a, and the thickness of the conductive layer 112a can be made thicker than the thickness of the conductive layer 112b. This can reduce the electrical resistance of the conductive layer 112a.

[0211] 5C and 5D show a configuration in which the conductive layer 112 has a three-layer structure consisting of a conductive layer 112c, a conductive layer 112a on the conductive layer 112c, and a conductive layer 112b on the conductive layer 112a.

[0212] 5C , the end portion of the conductive layer 112a can be in contact with the top surface of the conductive layer 112c. The conductive layer 112b has regions in contact with the top and side surfaces of the conductive layer 112a and the top surface of the conductive layer 112c. That is, it can be said that the conductive layers 112b and 112c each have portions that protrude beyond the end portions of the conductive layer 112a. It can also be said that the top, side, and bottom surfaces of the conductive layer 112a are surrounded by the conductive layers 112b and 112c. The conductive layer 112c is preferably made of a material that has high adhesion to the surface on which the conductive layer 112c is to be formed (here, the surface of the substrate 102).

[0213] As described above, the conductive layer 112a is preferably made of a material with low electrical resistivity. However, depending on the material, the adhesiveness between the conductive layer 112a and the surface on which the conductive layer 112a is to be formed (e.g., the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112c that has higher adhesiveness to the surface on which the conductive layer 112a is to be formed than the conductive layer 112a, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112c is preferably a thickness that effectively enhances the adhesiveness of the conductive layer 112a to the surface on which the conductive layer 112a is to be formed, and can be thinner than the thicknesses of the conductive layer 112a and the conductive layer 112b. By reducing the thickness of the conductive layer 112c, the manufacturing cost can be reduced.

[0214] For example, it is preferable to use In—Sn—Si oxide (ITSO) for the conductive layer 112c, copper for the conductive layer 112a, and In—Sn—Si oxide (ITSO) for the conductive layer 112b. When a glass substrate is used as the substrate 102, the adhesion between the glass substrate and an ITSO film is higher than the adhesion between a glass substrate and a copper film. Furthermore, using the same material for the conductive layers 112b and 112c facilitates processing when the conductive layers 112b and 112c are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0215] As shown in Figure 5D, the edge of the conductive layer 112b can be aligned or approximately aligned with the edge of the conductive layer 112c. For example, a first film that will become the conductive layer 112c is formed, a conductive layer 112a is formed on the first film, and a second film that will become the conductive layer 112b is formed on the first film and the conductive layer 112a. Then, by processing the first film and the second film, the conductive layer 112 can be formed, including the conductive layer 112c, the conductive layer 112a, and the conductive layer 112b. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0216] Although an example in which the conductive layer 112 has a stacked structure of two or three layers is shown here, one embodiment of the present invention is not limited thereto. The conductive layer 112 can also have a stacked structure of four or more layers.

[0217] The configuration of the conductive layer 112 shown in FIGS. 5A to 5D can also be applied to other configuration examples.

[0218] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0219] The insulating layer 106 has a region in contact with the layer 108. When a metal oxide is used for the layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0220] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0221] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0222] 6 is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 6 is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0223] The semiconductor device 10B includes a transistor 100A, an insulating layer 110, and a conductive layer 112. The transistor 100A differs from the transistor 100 shown in FIG. 1B and other figures mainly in that the insulating layer 106 has a stacked structure. FIG. 6 shows a configuration in which the insulating layer 106 has a two-layer structure including an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0224] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer (the insulating layer 106a here) on the layer 108 side preferably contains oxide or oxynitride. The insulating layer 106a can be preferably formed using, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0225] It is preferable that one or more layers constituting the insulating layer 106 have a barrier property. The layer can also be said to function as a barrier film. By providing a layer functioning as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100A from diffusing into the layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ ) can be suppressed. Furthermore, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the layer 108, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0226] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b.

[0227] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0228] The configuration of the insulating layer 106 shown in FIG. 6 can also be applied to other configuration examples.

[0229] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer, is preferably made of a material that is less susceptible to impurity diffusion. By providing the insulating layer 195, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0230] The insulating layer 195 can be an inorganic insulating layer or an organic insulating layer, or both. The insulating layer 195 preferably has one or more inorganic insulating layers. For example, one or more of oxide, oxynitride, nitride oxide, and nitride can be suitably used as the inorganic insulating layer. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating layers can be stacked. The insulating layer 195 can have a stacked structure of an inorganic insulating layer and an organic insulating layer.

[0231] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shapes of the semiconductor substrate and the insulating substrate are not particularly limited and may be circular or rectangular.

[0232] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0233] The following describes a configuration example that has some configurations different from the above-described configuration example 1-1. Note that, below, descriptions of parts that overlap with the above-described configuration example 1-1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-described configuration example 1-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0234] 7A and 7B show cross-sectional views of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, see FIG. 1A. FIG. 7A is a cross-sectional view of a section taken along dashed line A1-A2 in FIG. 1A, and FIG. 7B is a cross-sectional view of a section taken along dashed line B1-B2 in FIG. 1A.

[0235] The semiconductor device 10C includes a transistor 100, an insulating layer 110, an insulating layer 109, and a conductive layer 112. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 109.

[0236] The insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c. The insulating layer 110d is provided between the insulating layer 110c and the layer 108. The insulating layer 110d preferably has a region in contact with the lower surface of the layer 108. The insulating layer 109 is provided between the insulating layer 110 and the conductive layer 112 and the substrate 102. The insulating layer 109 preferably has a region in contact with the lower surface of the conductive layer 112.

[0237] The insulating layer 110d and the insulating layer 109 can be formed using the materials listed for the insulating layer 110a and the insulating layer 110c, respectively. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 110d and the insulating layer 109. Note that the insulating layer 110d and the insulating layer 109 can be formed using the same material, or different materials can be used for them.

[0238] The insulating layer 110d and the insulating layer 109 are each preferably made of a material that releases impurities that reduce the electrical resistance of the layer 108. When a metal oxide is used for the layer 108, the impurities released by the insulating layer 110d and the insulating layer 109 preferably contain hydrogen. Examples of such impurities include water and hydrogen.

[0239] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112. This can reduce the electrical resistance of the conductive layer 112. For example, when a metal oxide is used for the conductive layer 112, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112, thereby reducing the electrical resistance. Therefore, a semiconductor device with low wiring resistance can be obtained. Note that the impurities that reduce the electrical resistance of the conductive layer 112 may be the same as or different from the impurities that reduce the electrical resistance of the layer 108. The materials that can be used for the conductive layer 112 are as described above. Note that the conductive layer 112 is more preferably permeable to impurities. It is more preferable that the conductive layer 112 is less likely to adsorb impurities.

[0240] By releasing impurities from the insulating layer 110d, the carrier concentration in the region of the layer 108 in contact with the insulating layer 110d increases, thereby lowering the electrical resistance. Specifically, the electrical resistance of the region 108Db in contact with the top surface of the insulating layer 110d can be further reduced. Furthermore, the electrical resistance of the region of the layer 108 in contact with the side surface of the insulating layer 110d can be reduced. This region can be referred to as a low-resistance region. The low-resistance region has a higher electrical resistance than the regions 108Da and 108Db, and a lower electrical resistance than the channel formation region.

[0241] Impurities emitted from the insulating layer 109 diffuse into the region of the conductive layer 112 that contacts the insulating layer 109. Furthermore, the impurities diffused into the conductive layer 112 diffuse into the region of the layer 108 that contacts the conductive layer 112. This increases the carrier concentration in the region of the layer 108 that contacts the conductive layer 112, thereby reducing the electrical resistance. Specifically, the electrical resistance of the region 108Da that contacts the top surface of the conductive layer 112 can be reduced. Furthermore, the electrical resistance of the region of the layer 108 that contacts the top surface of the conductive layer 112 other than the region 108Da can be reduced. This region can also be called a low-resistance region.

[0242] By reducing the electrical resistance of the regions 108Da and 108Db, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0243] The layer 108 may have a low-resistance region between the region 108Da and the region 108Db, which function as a source electrode and a drain electrode, and the channel formation region. The low-resistance region may function as a buffer region for reducing the drain electric field.

[0244] By providing a low-resistance region between the drain electrode and the channel formation region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and transistor degradation. For example, in the transistor 100, when the region 108Da functions as a source electrode and the region 108Db functions as a drain electrode, by forming a region of the layer 108 that contacts the side surface of the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and transistor degradation. When the region 108Da functions as a drain electrode and the region 108Db functions as a source electrode, by forming a region of the layer 108 that contacts the top surface of the conductive layer 112 other than the region 108Da as a low-resistance region, a high electric field is less likely to be generated near the drain, which suppresses the generation of hot carriers and transistor degradation.

[0245] The insulating layer 110a is provided between the insulating layer 109 and the conductive layer 112 and the insulating layer 110b. This can prevent impurities released from the insulating layer 109 from diffusing into the channel formation region through the insulating layer 110a and the insulating layer 110b. The insulating layer 110c is provided between the insulating layer 110d and the insulating layer 110b. This can prevent impurities released from the insulating layer 110d from diffusing into the channel formation region through the insulating layer 110c and the insulating layer 110b. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0246] The insulating layer 109 preferably has a region with a higher impurity concentration than the insulating layer 110a. The insulating layer 110d preferably has a region with a higher impurity concentration than the insulating layer 110c. More specifically, the insulating layer 109 preferably has a region with a higher hydrogen concentration than the insulating layer 110a. The insulating layer 110d preferably has a region with a higher hydrogen concentration than the insulating layer 110c. The impurity concentrations of the insulating layer 110 and the insulating layer 109 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0247] The amount of released hydrogen can be adjusted by differentiating the film formation conditions between the insulating layer 109 and the insulating layer 110a. Specifically, the insulating layer 109 and the insulating layer 110a can be made different from each other in one or more of the following: film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode. For example, by making the film formation power density of the insulating layer 109 lower than the film formation power density of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than the hydrogen content in the insulating layer 110a. This can increase the amount of hydrogen released from the insulating layer 109 due to heat applied to the insulating layer 109.

[0248] The hydrogen content in the deposition gas used to form the insulating layer 109 is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when a silicon nitride film or a silicon nitride oxide film is formed as each of the insulating layer 109 and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 109 under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 109 can be increased. Furthermore, the amount of hydrogen released from the insulating layer 109 due to heat applied to the insulating layer 109 can be increased. For example, the insulating layer 109 can be formed using ammonia gas, and the insulating layer 110a can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form insulating layer 110a can be said to be zero, and the ammonia flow ratio of the deposition gas used to form insulating layer 109 can be said to be higher than the ammonia flow ratio of the deposition gas used to form insulating layer 110a.

[0249] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. This can prevent hydrogen contained in the insulating layer 109 from diffusing into the channel formation region of the layer 108 through the insulating layers 110a and 110b. The film density can be evaluated by, for example, Rutherford backscattering spectrometry (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear as a denser (darker) image than the insulating layer 109. Even if the same material is used for the insulating layer 109 and the insulating layer 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0250] The insulating layer 110d preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110d. For the insulating layers 110c and 110d, the descriptions of the insulating layers 110a and 109 can be referred to.

[0251] Note that a structure without either the insulating layer 110d or the insulating layer 109 is also possible. Although the insulating layer 110 has a four-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a two-layer, three-layer, or five or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0252] The configurations of the insulating layer 110 and the insulating layer 109 shown in Configuration Example 1-2 can also be applied to other configuration examples.

[0253] 8A and 8B show cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, see FIG. 1A. FIG. 8A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A, and FIG. 8B is a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 1A.

[0254] The semiconductor device 10D includes a transistor 100, an insulating layer 110, an insulating layer 109, and a conductive layer 112. The semiconductor device 10D differs from the semiconductor device 10C shown in FIG. 7A etc. mainly in that the insulating layer 110 includes an insulating layer 110e.

[0255] The insulating layer 110e is provided between the insulating layer 110a and the insulating layer 109 and the conductive layer 112. The insulating layer 110 includes the insulating layer 110e, the insulating layer 110a on the insulating layer 110e, the insulating layer 110b on the insulating layer 110a, the insulating layer 110c on the insulating layer 110b, and the insulating layer 110d on the insulating layer 110c.

[0256] The insulating layer 110e can be formed using the materials listed for the insulating layer 109 and the insulating layer 110d. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 110e. Note that the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, the insulating layer 110e, and the insulating layer 109 can be formed using the same material. Alternatively, different materials can be used for some or all of these layers.

[0257] By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110e, the region of the layer 108 in contact with the insulating layer 110e can be a low-resistance region. The layer 108 can have a low-resistance region between the region 108Da and the channel formation region. The low-resistance region can function as a buffer region for alleviating the drain electric field. This can suppress the generation of hot carriers and the degradation of the transistor.

[0258] The insulating layer 110e preferably has a region with a higher impurity concentration than the insulating layer 110a. More specifically, the insulating layer 110e preferably has a region with a higher hydrogen concentration than the insulating layer 110a.

[0259] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 110e, which can prevent hydrogen contained in the insulating layer 110e from diffusing into the channel formation region of the layer 108 through the insulating layers 110a and 110b.

[0260] The configuration of the insulating layer 110 shown in Configuration Example 1-2 can also be applied to other configuration examples.

[0261] 9A shows a top view of a semiconductor device 10E according to one embodiment of the present invention, and FIG. 9B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in FIG.

[0262] The semiconductor device 10E includes a transistor 100B, an insulating layer 110, an insulating layer 109, and a conductive layer 112. The transistor 100B differs from the transistor 100 shown in FIG. 1B and the like mainly in that the transistor 100B includes a conductive layer 103 and an insulating layer 107.

[0263] The transistor 100B includes the conductive layer 103 and the insulating layer 107 between the conductive layer 112 and the insulating layer 110 .

[0264] The insulating layer 107 is located over the conductive layer 112. The insulating layer 107 is provided to cover the top surface and side surfaces of the conductive layer 112.

[0265] The conductive layer 103 is located on the insulating layer 107. The conductive layer 112 and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. An opening 148 reaching the insulating layer 107 is provided in the conductive layer 103.

[0266] The insulating layer 110 is provided over the insulating layer 107 and the conductive layer 103. The insulating layer 110 is provided so as to cover the top surface and side surfaces of the conductive layer 103 and the top surface of the insulating layer 107. An opening 141 reaching the conductive layer 112 is provided in the insulating layer 110 and the insulating layer 107.

[0267] The insulating layer 110a is located over the insulating layer 107 and the conductive layer 103. The insulating layer 110a is provided so as to cover the top surface and side surfaces of the conductive layer 103. The insulating layer 110a is also provided so as to cover part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 through the opening 148.

[0268] The top surface shape of opening 148 is not particularly limited. The top surface shape of opening 148 can be any shape that can be applied to opening 141. As shown in Fig. 9A, the top surface shapes of openings 141 and 148 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, and openings of fine sizes can be formed.

[0269] In this specification and the like, the top surface shape of the opening 148 refers to the shape of the top surface end or the bottom surface end of the conductive layer 103 on the opening 148 side.

[0270] When the top surface shapes of the openings 141 and 148 are circular, the openings 141 and 148 are preferably concentric, which allows the shortest distance between the layer 108 and the conductive layer 103 in a cross-sectional view to be equal on the left and right sides of the opening 141. Also, the openings 141 and 148 may not be concentric.

[0271] In the transistor 100B, the layer 108 has a region that overlaps with the conductive layer 104 via the insulating layer 106 and with the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layers 110a and 110b). In other words, the layer 108 has a region that is sandwiched between the conductive layer 104 via the insulating layer 106 and the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layers 110a and 110b).

[0272] The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode) of the transistor 100B. Part of the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer) of the transistor 100B. The conductive layer 103 can be formed using the same material as can be used for the conductive layer 112 and the conductive layer 104. Note that a structure in which the conductive layer 103 is not provided is also possible.

[0273] By providing the back gate electrode in the transistor 100B, the potential of the back gate electrode side (also referred to as the back channel side) of the layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved.

[0274] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0275] Since the transistor 100B has a back gate electrode, the potential on the back channel side of the layer 108 can be fixed, and a shift in the threshold voltage can be suppressed. By suppressing a shift in the threshold voltage, a transistor with a small cutoff current can be obtained. As a result, a semiconductor device with low power consumption can be provided.

[0276] The insulating layer 107 can be formed using a material that can be used for the insulating layer 110. The insulating layer 107 in contact with the conductive layer 103 and the conductive layer 112 preferably has a barrier property. The insulating layer 107 can preferably be formed using a material that can be used for the insulating layer 110a and the insulating layer 110c. The insulating layer 107 preferably contains nitrogen, for example. The insulating layer 107 can preferably be formed using silicon nitride, for example. Note that although the insulating layer 107 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. The insulating layer 107 can also have a stacked structure of two or more layers.

[0277] The conductive layer 103 can be electrically connected to the conductive layer 112. For example, an opening reaching the conductive layer 112 can be formed in the insulating layer 107, and the conductive layer 103 can be formed to cover the opening, thereby forming a region in contact with the conductive layer 112. The region 108Da functioning as a source or drain electrode and the conductive layer 103 functioning as a back gate electrode are electrically connected through the conductive layer 112, thereby making it possible to make the source or drain electrode and the back gate electrode have the same potential. For example, when the region 108Da functions as a source electrode, a shift in the threshold voltage of the transistor 100B can be suppressed. Furthermore, the reliability of the transistor 100B can be improved. Note that the insulating layer 107 may not be provided, and the conductive layer 103 may be formed in contact with the top surface of the conductive layer 112.

[0278] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings reaching the conductive layer 103 are provided in the insulating layer 106 and the insulating layer 110, and the conductive layer 104 is provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 103 has a region in contact with the conductive layer 104. When the conductive layer 104 functioning as a gate electrode and the conductive layer 103 functioning as a back gate electrode are electrically connected, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100B can be increased.

[0279] The thickness of the conductive layer 103 can be made larger than the thickness T110b of the insulating layer 110. This allows the potential on the back channel side of the layer 108 to be fixed over a wide range between the source electrode and the drain electrode in the layer 108.

[0280] The transistor 100B has a region in which the conductive layer 103, the insulating layer 110, the layer 108, the insulating layer 106, and the conductive layer 104 overlap in this order in one direction without any other layers therebetween. The direction may be perpendicular to the channel length direction. By widening the region, the potential on the back channel side of the layer 108 can be more reliably controlled.

[0281] The structures of the conductive layer 103 and the insulating layer 107 shown in Structural Example 1-4 can also be applied to other structural examples.

[0282] 10A to 10F and 11A to 11G are circuit diagrams of a semiconductor device of one embodiment of the present invention. 12A to 18C are top views and cross-sectional views of a semiconductor device of one embodiment of the present invention. In the following, the transistor 100 will be mainly used as an example of a transistor included in a semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is not limited to this, and can have a structure including one or more of the above-described transistors 100 to 100B.

[0283] A semiconductor device according to one embodiment of the present invention includes at least two transistors, and one of the transistors has a gate, a source, or a drain electrically connected to the other of the transistors. Alternatively, the semiconductor device according to one embodiment of the present invention includes a transistor and a capacitor, and one of the transistors has a gate, a source, or a drain electrically connected to one terminal of the capacitor.

[0284] The semiconductor device of one embodiment of the present invention can be applied to a display device. The display device includes a transistor and a display element, and a source or a drain of the transistor is electrically connected to a pixel electrode of the display element.

[0285] [Configuration Example 2-1] Fig. 10A shows a circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. Fig. 12A shows a top view of the semiconductor device 20 according to one embodiment of the present invention. Fig. 12B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 12A, and Fig. 12C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0286] The semiconductor device 20 includes a transistor 100, a transistor 200, an insulating layer 110, a conductive layer 112, and a conductive layer 212. The other of the source and drain of the transistor 100 is electrically connected to the other of the source and drain of the transistor 200.

[0287] 12A and 12B show a configuration in which the semiconductor device 20 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 20 may be provided on the insulating film.

[0288] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0289] A conductive layer 112 and a conductive layer 212 are provided over a substrate 102, and an insulating layer 110 is provided over the conductive layer 112 and the conductive layer 212. The insulating layer 110 has an opening 141 that reaches the conductive layer 112 and an opening 241 that reaches the conductive layer 212. The conductive layer 112 and the conductive layer 212 each function as a wiring. The conductive layer 212 can be formed in the same process as the conductive layer 112. For example, the conductive layer 112 and the conductive layer 212 can be formed by forming and processing a conductive film. The opening 241 can be formed in the same process as the opening 141.

[0290] The transistor 200 includes a conductive layer 204, an insulating layer 106, and a layer 108. The layer 108 is provided to cover the openings 141 and 241. The insulating layer 106 is provided over the layer 108. Part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and the other part functions as a gate insulating layer for the transistor 200. The conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 204 has a region that overlaps with the layer 108 with the insulating layer 106 interposed therebetween in the opening 241. The conductive layer 204 functions as a gate electrode of the transistor 200. FIGS. 12B and 12C show an example in which a region 208Da is formed in a region of the layer 108 that overlaps with a lower surface of the conductive layer 204 in the opening 241.

[0291] The transistor 200 can be formed in the same process as the transistor 100 and has a similar structure to the transistor 100. The region 208Da corresponds to the region 108Da, and the conductive layer 204 corresponds to the conductive layer 104.

[0292] The transistor 100 and the transistor 200 share the layer 108. The layer 108 has a region 108Da in a region overlapping with the bottom surface of the conductive layer 104 in the opening 141, a region 208Da in a region overlapping with the bottom surface of the conductive layer 204 in the opening 241, and a region 108Db in a region in contact with the top surface of the insulating layer 110. The region 108Da functions as one of the source and drain electrodes of the transistor 100. The region 208Da functions as one of the source and drain electrodes of the transistor 200. The region 108Db functions as the other of the source and drain electrodes of the transistor 100 and also functions as the other of the source and drain electrodes of the transistor 200. In the layer 108, the channel formation region of the transistor 200 is located between the region 208Da and the region 108Db. Sharing the layer 108 between the transistors 100 and 200 enables the area occupied by the semiconductor device to be reduced.

[0293] The regions 108Da, 108Db, and 208Da each contain an impurity element. The regions 108Da, 108Db, and 208Da can be formed in the same process. The regions 108Da, 108Db, and 208Da each have a higher concentration of an impurity element and a lower electrical resistance than other regions (e.g., a channel formation region) of the layer 108. For the region 208Da, the description of the region 108Da can be referred to.

[0294] The conductive layer 212 has a region that contacts the region 208Da in the opening 241 and is electrically connected to the transistor 200 .

[0295] The configuration of the layer 108 and the region 108Db shown in Configuration Example 2-1 can also be applied to other configuration examples.

[0296] The following describes a configuration example that has some configurations different from the above-described configuration example 2-1. Note that, below, descriptions of parts that overlap with the above-described configuration example 2-1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-described configuration example 2-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0297] [Configuration Example 2-2] Fig. 10B shows a circuit diagram of a semiconductor device 20A according to one embodiment of the present invention. Fig. 13A shows a top view of the semiconductor device 20A. Fig. 13B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 13A, and Fig. 13C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0298] The semiconductor device 20A includes a transistor 100, a transistor 200, an insulating layer 110, and a conductive layer 112. One of the source and the drain of the transistor 100 is electrically connected to one of the source and the drain of the transistor 200.

[0299] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0300] The insulating layer 110 has an opening 141 that reaches the conductive layer 112, and an opening 241. The opening 241 can be formed in the same process as the opening 141.

[0301] The transistor 200 includes a conductive layer 204, an insulating layer 106, and a layer 208. The layer 208 is provided to cover the opening 241. The insulating layer 106 is provided over the layer 108 and the layer 208. FIGS. 13B and 13C show an example in which a region 208Da is formed in a region of the layer 208 that overlaps with the bottom surface of the conductive layer 204 in the opening 241, and a region 208Db is formed in a region of the layer 208 that contacts the top surface of the insulating layer 110. In the transistor 200, the region 208Da functions as one of a source electrode and a drain electrode, and the region 208Db functions as the other. In the layer 208, the channel formation region of the transistor 200 is located between the region 208Da and the region 208Db.

[0302] The transistor 200 can be formed in the same process as the transistor 100 and has a similar configuration to the transistor 100. The layer 208 corresponds to the layer 108, the region 208Da corresponds to the region 108Da, the region 208Db corresponds to the region 108Db, and the conductive layer 204 corresponds to the conductive layer 104.

[0303] The regions 108Da, 108Db, 208Da, and 208Db each contain an impurity element. The regions 108Da, 108Db, 208Da, and 208Db can be formed in the same process. The regions 108Da, 108Db, 208Da, and 208Db each have a higher concentration of an impurity element and a lower electrical resistance than other regions (e.g., a channel formation region) of the layer 108. For the regions 208Da and 208Db, the description of the regions 108Da and 108Db can be referred to.

[0304] The transistor 100 and the transistor 200 are electrically connected via the conductive layer 112. Specifically, the conductive layer 112 has a region in contact with the region 108Da in the opening 141, and is electrically connected to the transistor 100. Furthermore, the conductive layer 112 has a region in contact with the region 208Da in the opening 241, and is electrically connected to the transistor 200.

[0305] The configurations of the layer 208, the region 208Da, and the conductive layer 112 shown in Configuration Example 2-2 can also be applied to other configuration examples.

[0306] [Configuration Example 2-3] FIG. 14A shows a top view of a semiconductor device 20B according to one embodiment of the present invention. FIG. 14B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 14A. FIG. 12C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 14A. FIG. 10A can be referred to for a circuit diagram of the semiconductor device 20B.

[0307] The semiconductor device 20B includes a transistor 100, a transistor 200, an insulating layer 110, a conductive layer 112, a conductive layer 212, and a conductive layer 193. The other of the source and drain of the transistor 100 is electrically connected to the other of the source and drain of the transistor 200 through the conductive layer 193. The conductive layer 193 functions as a wiring that electrically connects the transistor and the transistor 200.

[0308] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0309] The transistor 200 includes a conductive layer 204, an insulating layer 106, and a layer 208. The layer 208 includes a region 208Da and a region 208Db. For the transistor 200, the description of the transistor 200 illustrated in FIGS. 13A to 13C can be referred to.

[0310] The insulating layer 106 has an opening 145 that reaches the region 108Db and an opening 245 that reaches the region 208Db. The conductive layer 193 is provided to cover the opening 145 and the opening 245. The conductive layer 193 has a region in contact with the region 108Db in the opening 145 and a region in contact with the region 208Db in the opening 245. That is, the region 108Db is electrically connected to the region 208Db via the conductive layer 193. The conductive layer 193 can be formed, for example, in the same process as the conductive layers 104 and 204. For example, the openings 145 and 245 are formed in the insulating layer 106, and a conductive film is formed to cover the openings 145 and 245. By forming the conductive film, the conductive layers 104, 204, and 193 can be formed. Note that the conductive layer 193 can also be formed in a process different from that for the conductive layers 104 and 204. For example, after forming an insulating layer 195 over the insulating layer 106, the conductive layer 104, and the conductive layer 204, openings 145 and 245 can be formed in the insulating layer 106 and the insulating layer 195, and a conductive layer 193 can be formed to cover the openings 145 and 245.

[0311] Here, when an oxide conductor (OC) is used for the wiring, the electrical resistance of the wiring may be higher than when a metal or an alloy is used. When the distance between the transistor 100 and the transistor 200 is long and the wiring resistance required for electrically connecting the transistor 100 and the transistor 200 is relatively low, it is preferable to use a material with low electrical resistivity for the conductive layer 193 that functions as the wiring. A metal or an alloy can be suitably used for the conductive layer 193.

[0312] When the distance between transistor 100 and transistor 200 is short and the wiring resistance required for electrically connecting transistor 100 and transistor 200 is relatively high, a conductive layer 193 may not be provided, and transistors 100 and 200 may share region 108Db, as shown in FIG. 12B, etc., so that the other of the source and drain of transistor 100 is electrically connected to the other of the source and drain of transistor 200.

[0313] The method for electrically connecting the transistor 100 and the transistor 200 can be determined depending on the material used for the layer 108 and the wiring resistance required for the wiring electrically connecting the transistor 100 and the transistor 200 .

[0314] The configuration of the layer 108, the region 108Db, the layer 208, the region 208Db, the conductive layer 193, and the insulating layer 106 shown in Configuration Example 2-3 can also be applied to other configuration examples.

[0315] [Configuration Example 2-4] Fig. 10C shows a circuit diagram of a semiconductor device 20C according to one embodiment of the present invention. Fig. 15A shows a top view of the semiconductor device 20C. Fig. 15B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 15A, and Fig. 15C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0316] The semiconductor device 20C includes a transistor 100, a transistor 200, an insulating layer 110, a conductive layer 112, and a conductive layer 212. The other of the source and the drain of the transistor 100 is electrically connected to the gate of the transistor 200.

[0317] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0318] The transistor 200 includes a conductive layer 204, an insulating layer 106, and a layer 208. The layer 208 includes a region 208Da and a region 208Db. For the transistor 200, the description of the transistor 200 illustrated in FIGS. 13A to 13C can be referred to.

[0319] The insulating layer 106 has an opening 145 that reaches the region 108Db. The conductive layer 204 is provided so as to cover the opening 145. The conductive layer 204 has a region that contacts the region 108Db in the opening 145. That is, the conductive layer 204 is electrically connected to the region 108Db in the opening 145.

[0320] Although the structure in which the conductive layer 204 has a region in contact with the region 108Da is shown here, one embodiment of the present invention is not limited to this. A structure in which the conductive layer 204 and the region 108Da are electrically connected to each other through a conductive layer different from the conductive layer 204 may also be used. For example, after forming the insulating layer 106, the conductive layer 104, and the insulating layer 195 over the conductive layer 104, a first opening reaching the region 108Da and a second opening reaching the conductive layer 204 are formed in the insulating layer 106 and the insulating layer 195, and a conductive layer is formed to cover the first opening and the second opening. The conductive layer may have a region in contact with the region 108Da in the first opening and a region in contact with the conductive layer 204 in the second opening.

[0321] The configurations of the layer 108, the region 108Db, the conductive layer 204, and the insulating layer 106 shown in Configuration Example 2-4 can also be applied to other configuration examples.

[0322] Although the structure examples 2-1 to 2-4 show examples in which the transistors 100 and 200 have the same structure, one embodiment of the present invention is not limited thereto. Transistors with different structures may also be used for the transistors 100 and 200. FIGS. 10D to 10F illustrate structures in which the transistor 100B having a back gate is used for the transistor 200. As shown in FIG. 10E, the conductive layer 103 functioning as the back gate of the transistor 200 can be electrically connected to the conductive layer 204 functioning as the gate. As shown in FIG. 10F, the conductive layer 103 can be electrically connected to the source electrode or drain electrode (region 208Da or region 208Db).

[0323] 11A is a circuit diagram of a semiconductor device 20D according to one embodiment of the present invention. FIG. 16A is a top view of the semiconductor device 20D. FIG. 16B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 16A.

[0324] The semiconductor device 20D includes a transistor 100, a transistor 250, and an insulating layer 110. One of a source and a drain of the transistor 250 is electrically connected to one of a source and a drain of the transistor 100.

[0325] A conductive layer 259 is provided over the substrate 102. An insulating layer 252 is provided over the substrate 102 and the conductive layer 259, and a semiconductor layer 253 is provided over the insulating layer 252. An insulating layer 254 is provided over the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 is provided over the insulating layer 254. The semiconductor layer 253 and the conductive layer 255 have an overlapping region. The conductive layer 259 functions as a back gate electrode of the transistor 250, and part of the insulating layer 252 functions as a back gate insulating layer. Part of the insulating layer 254 functions as a gate insulating layer, and the conductive layer 255 functions as a gate electrode.

[0326] An insulating layer 256 is provided over the insulating layer 254 and the conductive layer 255. An opening 257a is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with part of the semiconductor layer 253. An opening 257b is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with another part of the semiconductor layer 253.

[0327] A conductive layer 258a is provided over the insulating layer 256 and the opening 257a, and a conductive layer 258b is provided over the insulating layer 256 and the opening 257b. The conductive layer 258a is electrically connected to the semiconductor layer 253 in the opening 257a. The conductive layer 258b is electrically connected to the semiconductor layer 253 in the opening 257b.

[0328] In the semiconductor layer 253, a region overlapping with the conductive layer 255 functions as a channel formation region. The semiconductor layer 253 has a pair of regions 253D sandwiching the channel formation region. One of the pair of regions 253D functions as one of the source region and the drain region and is electrically connected to the conductive layer 258a. The other of the pair of regions 253D functions as the other of the source region and the drain region and is electrically connected to the conductive layer 258b.

[0329] The insulating layer 110 is provided over the insulating layer 256, the conductive layer 258a, and the conductive layer 258b.

[0330] The insulating layer 110 has an opening 146 in a region overlapping with part of the conductive layer 258a. The layer 108 is provided to cover the opening 146. In the opening 146, the conductive layer 258a has a portion in contact with the region 108Da. That is, one of the source and drain of the transistor 250 is electrically connected to one of the source and drain of the transistor 100.

[0331] The insulating layer 106 is provided over the insulating layer 110 and the layer 108, and the conductive layer 104 is provided over the insulating layer 106. In addition, an insulating layer 195 is provided over the insulating layer 106 and the conductive layer 104.

[0332] The conductive layer 259 preferably overlaps with the channel formation region and extends beyond the edge of the channel formation region. That is, the conductive layer 259 is preferably larger than the channel formation region. The conductive layer 259 also preferably extends beyond the edge of the semiconductor layer 253. That is, the conductive layer 259 is preferably larger than the semiconductor layer 253.

[0333] The back gate electrode and the gate electrode are arranged to sandwich the channel formation region. The threshold voltage of the transistor can be changed by changing the potential of the back gate electrode. The potential of the back gate electrode can be ground potential or any other potential.

[0334] The back gate electrode can be formed using the same materials and methods as the gate electrode, source electrode, drain electrode, etc. Furthermore, since the gate electrode and the back gate electrode are conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on a layer in which a channel is formed (particularly, an electric field shielding function against static electricity). That is, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity. Furthermore, by providing a back gate electrode, it is possible to reduce the amount of change in the threshold voltage of the transistor before and after a BT (Bias Temperature) stress test. By providing a back gate electrode, it is possible to reduce variations in the characteristics of the transistor and improve the reliability of the semiconductor device.

[0335] As shown in Fig. 11B, the transistor 250 may have a structure in which the back gate and the gate are electrically connected. Alternatively, as shown in Fig. 11C, the transistor 250 may have a structure in which the back gate and the source or the drain are electrically connected. Alternatively, as shown in Fig. 11D, the transistor 250 may have no back gate.

[0336] Like the transistor 100, the transistor 250 can be an OS transistor.

[0337] Here, the same material can be used for the layer 108 and the semiconductor layer 253. The semiconductor layer 253 can be made of a material that can be used for the layer 108. Alternatively, the layer 108 and the semiconductor layer 253 can be made of different materials.

[0338] The transistor 250 can also be a transistor using silicon in a channel formation region (hereinafter also referred to as a Si transistor).

[0339] Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having an LTPS structure in a channel formation region (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and good frequency characteristics.

[0340] By forming the transistor 100 over the conductive layer 258a, the area occupied by the semiconductor device can be reduced.

[0341] Note that the transistor 100 can be formed in a region overlapping with the opening 257a. Specifically, an opening 146 can be provided in a region overlapping with the opening 257a, and the conductive layer 258a and the layer 108 can be in contact with each other at the opening 257a. Furthermore, the conductive layer 258a can be omitted, and the region 253D and the region 108Da can be in contact with each other at the opening 257a. By adopting such a structure, a semiconductor device with a smaller occupation area can be obtained.

[0342] 11E is a circuit diagram of a semiconductor device 20E according to one embodiment of the present invention. FIG. 17A is a top view of the semiconductor device 20E. FIG. 17B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 17A.

[0343] The semiconductor device 20E includes a transistor 100, a transistor 250, and an insulating layer 110. A gate of the transistor 250 is electrically connected to one of the source and drain of the transistor 100.

[0344] The semiconductor device 20E is different from the semiconductor device 20E mainly in that the opening 146 is provided to overlap with the conductive layer 255 functioning as the gate electrode of the transistor 250. Thus, in the semiconductor device 20E, the transistor 100 is provided to overlap with the gate electrode of the transistor 250.

[0345] 17A and 17B , the opening 146 overlaps with the channel formation region of the transistor 250; however, this is not limiting. The opening 146 may also be provided without overlapping with the channel formation region of the transistor 250 and overlapping with the conductive layer 255. The conductive layer 255 has a region in contact with the region 108Da. That is, the gate electrode of the transistor 250 has a region in contact with one of the source electrode and the drain electrode of the transistor 100.

[0346] By providing the transistor 100 and the transistor 250 so that they overlap, a semiconductor device with a smaller occupation area can be realized.

[0347] The semiconductor device 20E differs from the semiconductor device 20D in the configurations of the opening 257a, the opening 257b, the conductive layer 258a, and the conductive layer 258b.

[0348] The openings 257a and 257b are formed by selectively removing parts of the insulating layer 254 and the insulating layer 110 in regions overlapping with the region 253D of the semiconductor layer 253. The conductive layers 258a and 258b are provided over the insulating layer 110 and are electrically connected to the region 253D through the openings 257a and 257b.

[0349] In the semiconductor device 20E, the conductive layer 258a and the conductive layer 258b can also be formed in the same process as the conductive layer 104. Specifically, after the insulating layer 106 is formed over the layer 108, openings reaching the region 253D are formed. Films that will become the conductive layer 104, the conductive layer 258a, and the conductive layer 258b are formed so as to cover the openings, and the conductive layer 104, the conductive layer 258a, and the conductive layer 258b can be formed by processing the film. Forming the conductive layer 104, the conductive layer 258a, and the conductive layer 258b in the same process shortens the manufacturing process of the semiconductor device, and improves the productivity of the semiconductor device.

[0350] 11A to 11E, the transistor 100 is illustrated as an n-channel transistor and the transistor 250 is illustrated as a p-channel transistor, but one embodiment of the present invention is not limited to this. Both the transistor 100 and the transistor 250 can be n-channel or p-channel. Alternatively, the transistor 100 can be a p-channel transistor and the transistor 250 can be an n-channel transistor.

[0351] The transistor of one embodiment of the present invention is a type of vertical transistor, and since a source electrode, a layer having a channel formation region, and a drain electrode can be provided in a stacked manner, the occupied area can be significantly reduced compared to a planar transistor. Furthermore, the transistor of one embodiment of the present invention can also be combined with a planar transistor. For example, a complementary metal oxide semiconductor (CMOS) circuit can be configured by using a p-channel Si transistor as the planar transistor and an n-channel OS transistor as the vertical transistor. Furthermore, by using this structure and providing the planar transistor and the vertical transistor in a stacked manner, the occupied area of ​​the CMOS circuit can be reduced.

[0352] 11F and 18A show a circuit diagram and a cross-sectional view of a semiconductor device 20F according to one embodiment of the present invention.

[0353] The semiconductor device 20F includes a transistor 100, a capacitor 190, an insulating layer 110, and a conductive layer 112. The capacitor 190 includes a pair of electrodes and a dielectric sandwiched between the pair of electrodes. The source or drain of the transistor 100 is electrically connected to one of the pair of electrodes of the capacitor 190.

[0354] A region 108Db included in the layer 108 functions as the other of the source electrode and drain electrode of the transistor 100 and also functions as one of a pair of electrodes of the capacitor 190. A conductive layer 191 functioning as the other of the pair of electrodes of the capacitor 190 is provided over the insulating layer 106. The conductive layer 191 can be formed in the same process as the conductive layer 104 included in the transistor 100. A region of the insulating layer 106 sandwiched between the region 108Db and the conductive layer 191 functions as a dielectric of the capacitor 190.

[0355] 18B , a conductive layer 191 can be provided on the substrate 102. The conductive layer 191 can be formed in the same process as the conductive layer 112. The insulating layer 110 in the region sandwiched between the region 108Db and the conductive layer 191 functions as a dielectric of the capacitance element 190.

[0356] By sharing the region 108Db between the transistor 100 and the capacitor 190, it is not necessary to provide one of the pair of electrodes of the capacitor 190 separately from the layer 108 (specifically, the region 108Db), which simplifies the manufacturing process of the semiconductor device, reduces manufacturing costs, and increases the yield of the semiconductor device.

[0357] Structural Example 2-8 A circuit diagram of a semiconductor device 20G according to one embodiment of the present invention is shown in Fig. 11G. A cross-sectional view of the semiconductor device 20G is shown in Fig. 18C.

[0358] The semiconductor device 20G includes a transistor 100, a capacitor 190, and a conductive layer 112.

[0359] The conductive layer 112 functions as a wiring of the transistor 100 and as one of a pair of electrodes of the capacitor 190. The conductive layer 192, which functions as the other of the pair of electrodes of the capacitor 190, is provided over the insulating layer 110. The conductive layer 192 can be formed in the same process as the regions 108Da and 108Db of the transistor 100. Specifically, after forming an opening 141 in the insulating layer 110, a film that will become the layer 108 and the conductive layer 192 is formed and processed to form the layer 108 and the conductive layer 192. Then, the regions 108Da, 108Db, and the conductive layer 192 can be formed by supplying an impurity element to the layer 108 and the conductive layer 192. The conductive layer 192 is provided in a region in contact with the top surface of the insulating layer 110. The region of the insulating layer 110 sandwiched between the conductive layer 112 and the conductive layer 192 functions as a dielectric of the capacitor 190.

[0360] 19A illustrates an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer of 2 or greater). The transistors 100_1 to 100_p are connected in parallel. The transistors 100_1 to 100_p share a gate, and the semiconductor device 30 can be regarded as a single transistor.

[0361] Gate electrodes of the transistors 100_1 to 100_p are electrically connected to each other, source electrodes of the transistors 100_1 to 100_p are electrically connected to each other, and drain electrodes of the transistors 100_1 to 100_p are electrically connected to each other.

[0362] 19A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be p-channel transistors.

[0363] A specific description will be given taking the case where p is 4 as an example. FIG. 19B shows an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention. FIG. 19C shows a top view of the semiconductor device 30. FIG. 20 shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 19C. FIG. 21 shows a perspective view of the semiconductor device 30.

[0364] The semiconductor device 30 includes transistors 100_1 to 100_4, an insulating layer 110, and a conductive layer 112. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example in the description here, one embodiment of the present invention is not limited thereto. Either the transistor 100A or the transistor 100B can be applied to the transistors 100_1 to 100_4.

[0365] 19C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0366] A conductive layer 112 is provided over a substrate 102, and an insulating layer 110 is provided over the conductive layers 112_1 and 112_2. The insulating layer 110 has openings 141_1, 141_2, 141_3, and 141_4 that reach the conductive layer 112.

[0367] The transistors 100_1 to 100_4 each include a conductive layer 104, an insulating layer 106, and a layer 108. The layer 108 is provided to cover the openings 141_1 to 141_4. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. Part of the insulating layer 106 functions as a gate insulating layer of the transistors 100_1 to 100_4. The layer 108 includes regions 108Da_1 to 108Da_4 and a region 108Db. The regions 108Da_1 to 108Da_4 correspond to the aforementioned region 108Da. The region 108Da_1 functions as one of a source electrode and a drain electrode of the transistor 100_1, the region 108Da_2 functions as one of a source electrode and a drain electrode of the transistor 100_2, the region 108Da_3 functions as one of a source electrode and a drain electrode of the transistor 100_3, the region 108Da_4 functions as one of a source electrode and a drain electrode of the transistor 100_4, and the region 108Db_1 functions as the other of the source electrode and the drain electrode of the transistors 100_1 to 100_4. The conductive layer 112 has a region in contact with the region 108Da_1 in an opening 141_1, a region in contact with the region 108Da_2 in an opening 141_2, a region in contact with the region 108Da_3 in an opening 141_3, and a region in contact with the region 108Da_4 in an opening 141_4.

[0368] FIG. 22A is a perspective view showing an extracted conductive layer 112. FIG.

[0369] 22B is a perspective view illustrating the conductive layer 112 and the openings 141_1 to 141_4. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are indicated by dashed lines. The openings 141_1 to 141_4 are provided in regions overlapping with the conductive layer 112. The openings 141_1 to 141_4 can be described in detail with reference to the opening 141, and therefore will not be described in detail again.

[0370] When the semiconductor device 30 is regarded as one transistor, the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4. For example, if the top shapes of the openings 141_1 to 141_4 are circular, and the widths of the openings 141_1 to 141_4 are each defined as D141, the semiconductor device 30 can be regarded as a transistor having a channel width of "D141×π×4" (see FIGS. 3A and 3B). The semiconductor device 30 including p transistors can be regarded as a transistor having a channel width of "D141×π×p". The semiconductor device 30 can also be regarded as a transistor having a channel length of L100 (see FIG. 3B). Connecting multiple transistors in parallel increases the channel width, thereby increasing the on-state current. The channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel can be determined so as to achieve a desired on-state current.

[0371] 22C is a perspective view illustrating the conductive layer 112 and the layer 108. The layer 108 is provided to cover the openings 141_1 to 141_4.

[0372] 22D is a perspective view illustrating the conductive layer 112 and the conductive layer 104. The conductive layer 104 is provided to cover the openings 141_1 to 141_4.

[0373] The configuration of the semiconductor device 30 shown in Configuration Example 2-9 can also be applied to other configuration examples. For example, the semiconductor device 30 can be applied to one or more of the transistors included in the semiconductor devices shown in Figures 10A to 10F and 11A to 11G.

[0374] 23A illustrates an equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. The semiconductor device 40 includes transistors 100_1 to 100_q (q is an integer of 2 or greater). The transistors 100_1 to 100_q are connected in series. The transistors 100_1 to 100_q share a gate, and the semiconductor device 40 can be regarded as a single transistor.

[0375] 23A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_q can also be p-channel transistors.

[0376] A specific description will be given taking the case where q is 4 as an example. FIG. 23B shows an equivalent circuit diagram of a semiconductor device 40 which is one embodiment of the present invention. FIG. 23C shows a top view of the semiconductor device 40. FIG. 24 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 23C. FIG. 25 shows a perspective view of the semiconductor device 40.

[0377] The semiconductor device 40 includes transistors 100_1 to 100_4, an insulating layer 110, a conductive layer 112_1, and a conductive layer 112_2. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example here, one embodiment of the present invention is not limited thereto. Either the transistor 100A or the transistor 100B can be applied to the transistors 100_1 to 100_4.

[0378] 23C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0379] A conductive layer 112_1 and a conductive layer 112_2 are provided over a substrate 102, and an insulating layer 110 is provided over the conductive layer 112_1 and the conductive layer 112_2. The insulating layer 110 has openings 141_1 and 141_2 that reach the conductive layer 112_1, and openings 141_3 and 141_4 that reach the conductive layer 112_2.

[0380] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, and a layer 108_1. The layer 108_1 is provided to cover the opening 141_1. A region 108Da_1 included in the layer 108_1 functions as one of a source electrode and a drain electrode of the transistor 100_1, and a region 108Db_1 functions as the other electrode. In the opening 141_1, the conductive layer 112_1 has a region in contact with the region 108Da_1.

[0381] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, and a layer 108_2. The layer 108_2 is provided to cover the openings 141_2 and 141_3. A region 108Da_2 included in the layer 108_2 functions as one of a source electrode and a drain electrode of the transistor 100_2, and a region 108Db_2 functions as the other. In the opening 141_2, the conductive layer 112_1 has a region in contact with the region 108Da_2. That is, the other of the source electrode and the drain electrode of the transistor 100_2 is electrically connected to the other of the source electrode and the drain electrode of the transistor 100_1.

[0382] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, and a layer 108_2. A region 108Da_3 included in the layer 108_2 functions as one of a source electrode and a drain electrode of the transistor 100_3, and a region 108Db_2 functions as the other. In the opening 141_3, the conductive layer 112_2 has a region in contact with the region 108Da_3. The layer 108 is shared by the transistors 100_2 and 100_3. The region 108Db_2 functions as the other of the source electrode and the drain electrode of the transistor 100_3 and also functions as the other of the source electrode and the drain electrode of the transistor 100_2. That is, the other of the source electrode and the drain electrode of the transistor 100_3 is electrically connected to the other of the source electrode and the drain electrode of the transistor 100_2.

[0383] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, and a layer 108_3. The layer 108_3 is provided to cover the opening 141_4. A region 108Da_4 included in the layer 108_3 functions as one of a source electrode and a drain electrode of the transistor 100_4, and the region 108Db_3 functions as the other. In the opening 141_4, the conductive layer 112_2 has a region in contact with the region 108Da_4. That is, one of the source electrode and the drain electrode of the transistor 100_4 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_3.

[0384] 26A is a perspective view illustrating the conductive layer 112_1 and the conductive layer 112_2. The conductive layer 112_1 and the conductive layer 112_2 can be formed in the same process. For the conductive layer 112_1 and the conductive layer 112_2, the description of the conductive layer 112 can be referred to.

[0385] 26B is a perspective view illustrating the conductive layer 112_1, the conductive layer 112_2, and the openings 141_1 to 141_4. The openings 141_1 and 141_2 are provided in a region overlapping with the conductive layer 112_1, and the openings 141_3 and 141_4 are provided in a region overlapping with the conductive layer 112_2.

[0386] 26C is a perspective view illustrating the conductive layer 112_1, the conductive layer 112_2, and the layers 108_1 to 108_3. The layer 108_1 is provided to cover the opening 141_1, the layer 108_2 is provided to cover the openings 141_2 and 141_3, and the layer 108_3 is provided to cover the opening 141_4. The layers 108_1 to 108_3 can be formed in the same process. For the layers 108_1 to 108_3, the description of the layer 108 can be referred to.

[0387] 26D is a perspective view illustrating the conductive layer 112_1, the conductive layer 112_2, and the conductive layer 104. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4.

[0388] When the semiconductor device 40 is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 40 can be regarded as a transistor having a channel length of "L100×4" (see FIG. 3B). The semiconductor device 40, which is configured with q transistors, can be regarded as a transistor having a channel length of "L100×q". Note that the semiconductor device 40 can be regarded as a transistor having a channel width W100 (see FIGS. 3A and 3B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel length can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined so as to achieve a desired saturation.

[0389] The configuration of the semiconductor device 40 shown in Configuration Example 2-10 can also be applied to other configuration examples. For example, the semiconductor device 40 can be applied to one or more of the transistors included in the semiconductor devices shown in FIGS. 10A to 10F and 11A to 11G.

[0390] The semiconductor device 40 can be applied to each transistor included in the semiconductor device 30. That is, a configuration can be achieved in which a group of parallel-connected transistors are further connected in series (hereinafter also referred to as series-parallel connection).

[0391] Although the structures of a semiconductor device including a plurality of transistors and a semiconductor device including a transistor and a capacitor have been described here, one embodiment of the present invention is not limited thereto. The semiconductor device according to one embodiment of the present invention can be suitably used for a display device. In the display device according to one embodiment of the present invention, the region 108Da or the region 108Db of the transistor can be in contact with a pixel electrode of a display element. The structure of the display device will be described in detail in Embodiment 3.

[0392] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0393] 27A to 30B , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0394] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0395] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0396] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0397] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0398] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0399] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0400] 27A to 29C show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 in FIG.

[0401] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0402] Subsequently, a conductive film is formed over the insulating layer 109 and processed to form a conductive layer 112 (FIG. 27A). The conductive film can be formed by a sputtering method.

[0403] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112 (FIG. 27B).

[0404] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf continuously using the same device.

[0405] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf can be reduced, and the diffusion of the impurities into the layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0406] Since the insulating films 110af and 110bf are formed before the layer 108, there is no need to worry about oxygen being desorbed from the layer 108 due to heat applied during the formation of the insulating films 110af and 110bf.

[0407] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0408] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic.

[0409] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0410] Next, a film 139 is preferably formed on the insulating film 110bf ( FIG. 27D ). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 27C shows a schematic diagram of oxygen being supplied to the insulating film 110bf using arrows.

[0411] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0412] The film 139 is preferably made of an oxide containing one or more of the same elements as those of the layer 108. In particular, it is preferably made of an oxide applicable to the layer 108.

[0413] When forming the film 139, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0414] By forming the film 139 by sputtering in an oxygen-containing atmosphere in this manner, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0415] Heat treatment can be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0416] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0417] After the film 139 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. As a method for supplying oxygen, for example, ion implantation or plasma treatment can be used. Regarding the plasma treatment, the above description can be referred to, and therefore detailed description thereof will be omitted.

[0418] Next, the film 139 is removed ( FIG. 27E ). Although there is no particular limitation on the method for removing the film 139, a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when removing the film 139. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0419] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0420] Next, an insulating film 110cf, which will become the insulating layer 110c, and an insulating film 110df, which will become the insulating layer 110d, are formed on the insulating film 110bf ( FIG. 28A ). The insulating film 110cf can be preferably formed by sputtering. The description of the formation of the insulating films 110af and 110bf can be referenced for the formation of the insulating films 110cf and 110df, and therefore detailed description thereof will be omitted.

[0421] Subsequently, parts of the insulating films 110af, 110bf, 110cf, and 110df are removed to form the insulating layer 110 having openings 141 ( FIG. 28B ). The openings 141 are provided in regions overlapping with the conductive layer 112. The conductive layer 112 is exposed by the formation of the openings 141. The insulating layer 110 can be preferably formed by dry etching.

[0422] Next, a metal oxide film 108f that will become the layer 108 is formed so as to cover the opening 141 (FIG. 28C). The metal oxide film 108f is provided in contact with the upper surface and side surfaces of the insulating layer 110 and the upper surface of the conductive layer 112.

[0423] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. Because the ALD method has high coverage, it can be suitably used to form the metal oxide film 108f that covers the opening 141. By using the ALD method, a metal oxide film can be formed with high coverage also on the side surfaces of the insulating layer 110. Furthermore, the ALD method makes it easy to control the film formation rate, so a thin film can be formed with a high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Instead of the sputtering method and the ALD method, a CVD method can also be used to form the metal oxide film 108f.

[0424] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0425] When the metal oxide film 108f is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0426] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the layer 108 in a later process, and oxygen vacancies and V Ｏ H can be reduced.

[0427] The metal oxide film 108f can be formed by mixing oxygen gas with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0428] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f.

[0429] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0430] The substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0431] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0432] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0433] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0434] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0435] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0436] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0437] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0438] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0439] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0440] Oxidizing agents include, for example, ozone, oxygen, and water.

[0441] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film 108f whose composition changes continuously.

[0442] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ Oxygen can also be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide gas. When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0443] When the layer 108 has a stacked structure, it is preferable to deposit a metal oxide film first and then deposit a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0444] When the layer 108 has a stacked structure, all layers constituting the layer 108 can be formed by the same deposition method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used for different layers. For example, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0445] Subsequently, the metal oxide film 108f is processed into an island shape to form the layer 108 (FIG. 28D).

[0446] The layer 108 can be preferably formed by wet etching. At this time, a part of the insulating layer 110 in a region that does not overlap with the layer 108 may be etched, resulting in a thinning of the thickness. For example, the insulating layer 110d of the insulating layer 110 may be removed by etching, exposing the surface of the insulating layer 110c. Note that, in etching the metal oxide film 108f, using a material with a high selectivity for the insulating layer 110d can prevent the insulating layer 110 from becoming thin.

[0447] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the layer 108. The heat treatment can remove hydrogen and water contained in or adsorbed on the surface of the metal oxide film 108f or the layer 108. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the layer 108 (for example, reduce defects or improve crystallinity).

[0448] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the layer 108. In this case, it is preferable to perform the heat treatment before processing into the layer 108. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0449] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0450] Subsequently, the insulating layer 106 is formed to cover the layer 108 and the insulating layer 110 (FIG. 29A). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0451] When a metal oxide is used for the layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 suppresses oxygen diffusion, thereby suppressing oxygen desorption from the layer 108 and preventing oxygen vacancies (V ＯIn addition, oxygen contained in the layer 108 is prevented from diffusing into the conductive layer 104 through the insulating layer 106, and thus the conductive layer 104 is prevented from being oxidized. As a result, a highly reliable transistor can be obtained, which exhibits favorable electrical characteristics.

[0452] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the layer 108, causing oxygen vacancies and V in the layer 108. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen desorption from the layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0453] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the layer 108. Therefore, impurities at the interface between the layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the layer 108 is exposed to the air between the formation of the layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0454] Next, an impurity element 189 is supplied to the layer 108 (FIG. 29B). By supplying the impurity element 189, regions 108Da and 108Db are formed.

[0455] The impurity element 189 is preferably supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. In this case, as described above, the amount of the impurity element supplied to a region of the layer 108 that is inclined with respect to the top surface of the substrate 102 is smaller than that to a region that is parallel or substantially parallel to the top surface of the substrate 102. That is, the amount of the impurity element supplied to the source electrode and the drain electrode of the layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source electrode and the drain electrode can be preferentially reduced. By supplying the impurity element 189 to the layer 108, oxygen vacancies (V Ｏ Alternatively, when the impurity element 189 is supplied to the layer 108, oxygen vacancies (V Ｏ ) may be combined.

[0456] Furthermore, the impurity element 189 is preferably supplied to the layer 108 through the insulating layer 106. The thickness of the insulating layer 106 in the supply direction of the impurity element 189 varies depending on the location. Therefore, the layer 108 has regions where the amount of the impurity element 189 is large and regions where the amount of the impurity element 189 is small. Specifically, the amount of the impurity element supplied is larger in the region of the layer 108 provided along the top surface of the insulating layer 110 and the region of the layer 108 provided along the top surface of the conductive layer 112 than in the region of the layer 108 provided along the side surface of the insulating layer 110. In this way, the impurity element can be prevented from being supplied to the channel formation region of the layer 108, and the electrical resistance of the source electrode and the drain electrode can be preferentially reduced. At this time, the impurity element 189 is also supplied to the insulating layer 106. In addition, the impurity element 189 may also be supplied to the insulating layer 110 through the insulating layer 106 and the layer 108 or through the insulating layer 106.

[0457] The elements that can be used as the impurity element 189 are as described above.

[0458] As described above, the impurity element 189 can be preferably supplied by ion implantation.

[0459] The purity of the supplied impurity element can be increased by using an ion implantation method in which a source gas is ionized and the ions are mass-separated and supplied. When using the ion implantation method, it is preferable to use the first element described above as the impurity element 189, and it is more preferable to use boron or phosphorus. By using an element that becomes stable when bonded with oxygen as the impurity element 189, it is possible to realize the regions 108Da and 108Db that are stable and have low electrical resistance.

[0460] Supplying the impurity element 189 without mass separation can improve productivity. In this case, it is preferable to use both the first element and hydrogen as the impurity element 189, and it is even more preferable to use both boron or phosphorus and hydrogen. By using both an element that becomes stable when bonded with oxygen and hydrogen as the impurity element 189, the electrical resistance of the regions 108Da and 108Db can be easily reduced and the low electrical resistance can be stably maintained.

[0461] The ion implantation equipment used to supply the impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors, so that the equipment in the existing LTPS manufacturing line can be used, which is preferable because no new capital investment is required, thereby reducing the initial capital investment costs for manufacturing semiconductor devices.

[0462] In the supplying treatment of the impurity element 189, the treatment conditions are preferably controlled so that the concentration of the impurity element in a region of the layer 108 provided along the top surface of the conductive layer 112 and a region of the layer 108 provided along the top surface of the insulating layer 110 is higher than the concentration of the impurity element in other regions. In this way, the impurity element 189 at an optimum concentration can be supplied to the source electrode and the drain electrode of the layer 108.

[0463] As a source gas of the impurity element 189, a gas containing the above-mentioned impurity element can be used. ２ H ６ Gas, BF ３ In addition, when phosphorus is supplied, a typical example is a PH ３It is also possible to use a mixed gas in which these source gases are diluted with hydrogen or a noble gas.

[0464] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The raw material used to supply the impurity element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0465] For example, it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 189. In this case, the impurity element 189 can be supplied without mass separation, and the electrical resistance of the layer 108 can be easily reduced, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.

[0466] The supply of the impurity element 189 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 189, the composition, film density, thickness, and the like of each of the insulating layer 106 and the layer 108.

[0467] The method for supplying the impurity element 189 is not limited, and for example, plasma treatment or treatment using thermal diffusion due to heating can be used. In the case of plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0468] In one embodiment of the present invention, the impurity element 189 is supplied to the layer 108 through the insulating layer 106. This can prevent the crystallinity of the layer 108 from decreasing when the impurity element 189 is supplied. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be prevented.

[0469] If the insulating layer 106 is formed after the impurity element 189 is supplied, the inside of a deposition chamber for the insulating layer 106 may be contaminated. For this reason, it is preferable to supply the impurity element 189 after the insulating layer 106 is formed.

[0470] On the other hand, the impurity element 189 can be directly supplied to the layer 108, and then the insulating layer 106 can be formed over the layer 108. In this way, damage to the insulating layer 106 due to the supply of the impurity element 189 can be suppressed.

[0471] The supplying step of the impurity element 189 is preferably performed while heating the substrate 102. This allows damage to the layer 108 that occurs when the impurity element 189 is supplied to be repaired. That is, the supply of the impurity element 189 to the layer 108 and repairing of damage caused by the supply can be performed in parallel. Furthermore, damage to the insulating layer 106 that occurs when the impurity element 189 is supplied can also be repaired. Note that one embodiment of the present invention is not limited thereto, and the supplying step of the impurity element 189 can be performed without heating the substrate 102.

[0472] The substrate temperature in the supplying step of the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0473] Heat treatment can be performed after supplying the impurity element 189. By performing the heat treatment, damage to the layer 108 and the insulating layer 106 caused in the step of supplying the impurity element 189 can be repaired.

[0474] If the temperature of the heat treatment is too high, there is a risk of increasing the electrical resistance of the region 108Da, the electrical resistance of the region 108Db, and the contact resistance between the region 108Da and the conductive layer 112. Therefore, the temperature of the heat treatment after supplying the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, further preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 400°C or lower, further preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, further preferably 300°C or higher and 350°C or lower.

[0475] By using an element that becomes stable by bonding with oxygen as the impurity element 189, it is possible to prevent the impurity element 189 from being desorbed in the heat application process. Therefore, after the impurity element 189 is supplied, the electrical resistance of the regions 108Da and 108Db can be kept low even after the heat application process.

[0476] Subsequently, the conductive layer 104 is formed on the insulating layer 106 (FIG. 29C). The conductive film that becomes the conductive layer 104 can be suitably formed by, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0477] Next, an insulating layer 195 is formed over the transistor 100 (FIGS. 7A and 7B). The insulating layer 195 can be preferably formed by a PECVD method.

[0478] Through the above steps, the semiconductor device 10C of one embodiment of the present invention can be manufactured.

[0479] <Fabrication Method Example 2> Here, a fabrication method for a structure in which the regions 108Da and 108Db contain a second element in addition to a first element will be described. Note that descriptions of parts that overlap with the above-described <Fabrication Method Example 1> will be omitted, and differences will be described.

[0480] 30A and 30B show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in FIG. 1A side by side.

[0481] First, similarly to Manufacturing Method Example 1, steps up to the formation of the insulating layer 106 are performed. Since the description of FIGS. 27A and 29A can be referred to for the steps up to the formation of the insulating layer 106, detailed description thereof will be omitted.

[0482] Next, an impurity element 187 is supplied to the layer 108 ( FIG. 30A ). The impurity element 187 is preferably the second element described above, and argon is preferably used. By supplying the impurity element 187, regions 108Ea and 108Eb containing the second element are formed. Later, the region 108Ea becomes the region 108Da, and the region 108Eb becomes the region 108Db.

[0483] The impurity element 187 can be supplied by the same method as that used for supplying the impurity element 189. An ion implantation method can be suitably used for supplying the impurity element 187. The supply of the impurity element 187 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 187, the composition, film density, thickness, and the like of the insulating layer 106 and the layer 108.

[0484] The impurity element 187 is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. For the supply of the impurity element 187, the above description of the supply of the impurity element 189 can be referred to.

[0485] By supplying the impurity element 187, the bond between the metal and oxygen of the metal oxide is broken in the region 108Ea which becomes the region 108Da and the region 108Eb which becomes the region 108Db. In addition, the breaking of the bond between the metal and oxygen causes oxygen deficiency (V Ｏ ) occurs. Then, by supplying the first element to the regions 108Ea and 108Eb, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0486] Next, an impurity element 189 is supplied to the layer 108 (FIG. 30B). By supplying the impurity element 189, regions 108Da and 108Db are formed. The regions 108Da and 108Db each contain a first element and a second element.

[0487] The supply conditions of the impurity element 189 can be made different from the supply conditions of the impurity element 187. It is preferable to set conditions such as acceleration energy and dose amount depending on the type of the first element and the type of the second element. Note that the supply conditions of the impurity element 187 and the impurity element 189 can also be made the same.

[0488] Although an example in which the first element and the second element are supplied in different steps has been described here, one embodiment of the present invention is not limited thereto and may be configured to supply the first element and the second element in the same step.

[0489] Subsequently, the conductive layer 104 is formed on the insulating layer 106. For the steps subsequent to the formation of the conductive layer 104, the above description can be referred to.

[0490] Through the above steps, the semiconductor device 10C of one embodiment of the present invention can be manufactured.

[0491] This embodiment mode can be combined with other embodiment modes as appropriate.

[0492] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0493] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0494] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0495] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0496] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0497] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0498] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0499] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0500] [Display Device 50A] FIG. 31 shows a perspective view of the display device 50A.

[0501] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 31, the substrate 152 is indicated by a dashed line.

[0502] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 31 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 31 can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0503] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 31 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0504] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0505] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0506] 31 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0507] The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the circuit portion 164 of the display device 50A, for example.

[0508] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0509] An oxide semiconductor (OS) can be preferably used for a channel formation region of a transistor included in the display device. By using an OS transistor, a display device with low power consumption can be obtained. Furthermore, the semiconductor device according to one embodiment of the present invention can be used in both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0510] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 31 shows an enlarged view of one pixel 201.

[0511] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0512] The pixel 201 shown in FIG. 31 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0513] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0514] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0515] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0516] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0517] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0518] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0519] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0520] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0521] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0522] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0523] Figure 32A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0524] 32A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0525] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0526] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0527] The transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same material and in the same process.

[0528] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0529] Specifically, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each have a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, and a layer 108 containing metal oxide. The layer 108 has regions 108Da and 108Db that function as a source electrode and a drain electrode. The conductive layer 112 has a region in contact with the region 108Da and functions as a wiring. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 110 is located between the conductive layer 112 and the layer 108. The insulating layer 106 is located between the conductive layer 104 and the layer 108.

[0530] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0531] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a layer in which a channel is formed.

[0532] The display device of this embodiment may have a Si transistor.

[0533] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0534] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0535] In terms of the saturation of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0536] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0537] All the transistors included in the display portion 162 may be OS transistors, all the transistors included in the display portion 162 may be Si transistors, or some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors.

[0538] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0539] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to a pixel electrode of the light-emitting element. The driving transistor is preferably an LTPS transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0540] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0541] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218.

[0542] The insulating layer 218 preferably functions as a protective layer for the transistor. The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0543] The insulating layer 218 preferably includes one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of materials that can be used for the inorganic insulating film are as described above.

[0544] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc.

[0545] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0546] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 32A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0547] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 32A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0548] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 32A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0549] 32A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element can be improved.

[0550] The pixel electrode 111R is electrically connected to the region 108Da of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is electrically connected to the region 108Da of the transistor 205G, and the pixel electrode 111B is electrically connected to the region 108Da of the transistor 205B.

[0551] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0552] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0553] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140. The conductive layer 123 is preferably formed using the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0554] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0555] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0556] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof, as appropriate. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0557] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0558] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0559] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 32A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 32A , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both overlapping portions between adjacent EL layers and portions between adjacent EL layers that do not overlap but are spaced apart.

[0560] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0561] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0562] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0563] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0564] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0565] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0566] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0567] In Figure 32A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0568] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 32A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0569] The protective layer 131 is preferably provided on at least the display unit 162, and is preferably provided so as to cover the entire display unit 162. The protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, the connection unit 197 has a portion where the protective layer 131 is not provided, in order to electrically connect the FPC 172 and the conductive layer 166.

[0570] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0571] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0572] The protective layer 131 has an inorganic film, which can prevent oxidation of the common electrode 115, prevent impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0573] For example, an inorganic insulating film containing one or more of oxide, nitride, oxynitride, and nitride oxide can be used for the protective layer 131. Specific examples of materials that can be used for the inorganic insulating film are as described above. In particular, the protective layer 131 preferably contains a nitride or nitride oxide, and more preferably contains a nitride.

[0574] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0575] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0576] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0577] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0578] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242. FIG. 32A shows an example in which the conductive layer 165 has the same structure as the region 108Db. For example, a film that will become the layer 108 and the conductive layer 165 is formed, processed, and an impurity element is added. As a result, the regions 108Da and 108Db are formed in the layer 108, and the conductive layer 165 is also formed. The conductive layer 165 is provided in a region that contacts the upper surface of the insulating layer 110. In this example, the conductive layer 166 is obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.

[0579] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0580] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0581] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0582] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.

[0583] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0584] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0585] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrate 151 and substrate 152 can be made of glass having a thickness sufficient to provide flexibility.

[0586] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0587] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0588] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0589] [Display Device 50B] Figure 32B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that each subpixel of each color uses a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter). The configuration shown in Figure 32B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 32A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0590] A display device 50B shown in FIG. 32B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that t...

Claims

a transistor, a first insulating layer, and a first conductive layer; the transistor comprises a metal oxide layer, a gate insulating layer, and a gate electrode; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the metal oxide layer has a first region in contact with an upper surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with the upper surface of the first insulating layer; the third region is continuous with the second region, the gate insulating layer is located on the metal oxide layer; the gate electrode has a region overlapping the metal oxide layer through the gate insulating layer in the first opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; The third region has a portion having a higher concentration of the first element than the second region. 　 a first transistor, a second transistor, a first insulating layer, and a first conductive layer; the first transistor has a first metal oxide layer, a gate insulating layer, and a first gate electrode; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the first metal oxide layer has a first region in contact with an upper surface of the first conductive layer at the first opening, a second region in contact with a side surface of the first insulating layer at the first opening, and a third region in contact with an upper surface of the first insulating layer; the gate insulating layer is located on the first metal oxide layer; the first gate electrode has a region overlapping the first metal oxide layer through the gate insulating layer in the first opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; the third region has a portion having a higher concentration of the first element than the second region, the first metal oxide layer has a region in the third region that is in contact with any one of a gate, a source, and a drain of the second transistor. 　 a first transistor, a second transistor, a first insulating layer, a first conductive layer, and a second conductive layer; the first transistor has a first metal oxide layer, a gate insulating layer, and a first gate electrode; the second transistor has the first metal oxide layer, the gate insulating layer, and a second gate electrode; the first insulating layer overlies the first conductive layer and the second conductive layer; the first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the second conductive layer; the first metal oxide layer has a first region in contact with an upper surface of the first conductive layer at the first opening, a second region in contact with a side surface of the first insulating layer at the first opening, a third region in contact with an upper surface of the first insulating layer, a fourth region in contact with an upper surface of the second conductive layer at the second opening, and a fifth region in contact with a side surface of the first insulating layer at the second opening; the gate insulating layer is located on the first metal oxide layer; the first gate electrode has a region overlapping the first metal oxide layer through the gate insulating layer in the first opening, the second gate electrode has a region overlapping the first metal oxide layer through the gate insulating layer in the second opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; The third region has a portion having a higher concentration of the first element than the second region. 　 In claim 3, the fourth region has the first element; The fourth region has a portion having a higher concentration of the first element than the fifth region. 　 a first transistor, a second transistor, a first insulating layer, and a first conductive layer; the first transistor has a first metal oxide layer, a gate insulating layer, and a first gate electrode; the second transistor has a second metal oxide layer, the gate insulating layer, and a second gate electrode; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer and a second opening; the first metal oxide layer has a first region in contact with an upper surface of the first conductive layer at the first opening, a second region in contact with a side surface of the first insulating layer at the first opening, and a third region in contact with an upper surface of the first insulating layer; the second metal oxide layer has a fourth region in contact with an upper surface of the first conductive layer in the second opening, a fifth region in contact with a side surface of the first insulating layer in the second opening, and a sixth region in contact with an upper surface of the first insulating layer; the gate insulating layer is located on the first metal oxide layer and the second metal oxide layer; the first gate electrode has a region overlapping the first metal oxide layer through the gate insulating layer in the first opening, the second gate electrode has a region overlapping the second metal oxide layer through the gate insulating layer in the second opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; The third region has a portion having a higher concentration of the first element than the second region. 　 In claim 5, the fourth region and the sixth region each have the first element, the fourth region has a portion having a higher concentration of the first element than the fifth region, The sixth region has a portion having a higher concentration of the first element than the fifth region. 　 a transistor, a capacitor, a first insulating layer, and a first conductive layer; the transistor comprises a metal oxide layer, a gate insulating layer, and a gate electrode; the capacitance element includes the metal oxide layer, a second conductive layer, and the gate insulating layer sandwiched between the metal oxide layer and the second conductive layer; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the metal oxide layer has a first region in contact with an upper surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with the upper surface of the first insulating layer; the gate insulating layer is located on the metal oxide layer; the gate electrode has a region overlapping the metal oxide layer through the gate insulating layer in the first opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; the third region has a portion having a higher concentration of the first element than the second region, the second conductive layer has a portion overlapping with the third region via the gate insulating layer. 　 a transistor, a capacitor, a first insulating layer, and a first conductive layer; the transistor comprises a metal oxide layer, a gate insulating layer, and a gate electrode; the capacitive element includes the metal oxide layer, a second conductive layer, and the first insulating layer sandwiched between the metal oxide layer and the second conductive layer; the first insulating layer overlies the first conductive layer and the second conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the metal oxide layer has a first region in contact with an upper surface of the first conductive layer in the first opening, a second region in contact with a side surface of the first insulating layer in the first opening, and a third region in contact with the upper surface of the first insulating layer; the gate insulating layer is located on the metal oxide layer; the gate electrode has a region overlapping the metal oxide layer through the gate insulating layer in the first opening, the first region and the third region each have a first element; the first element is boron or phosphorus; the first region has a portion having a higher concentration of the first element than the second region; the third region has a portion having a higher concentration of the first element than the second region, the second conductive layer has a portion overlapping with the third region via the first insulating layer. 　 In any one of claims 1 to 8, The concentration of the first element in the second region is 1×10 −３ 4. A semiconductor device, comprising: 　 In any one of claims 1 to 8, The concentration of the first element in the second region is 1×10 4 of the concentration of the first element in the third region. −３ 4. A semiconductor device, comprising: 　 In any one of claims 1 to 8, The gate insulating layer comprises the first element. 　 In any one of claims 1 to 8, a side surface of the first insulating layer in the first opening and a top surface of the first conductive layer form an angle of 65 degrees or more and 90 degrees or less. 　 In any one of claims 1 to 8, the first region comprises hydrogen; A semiconductor device, wherein a concentration of hydrogen in the first region is higher than a concentration of hydrogen in the second region. 　 In any one of claims 1 to 8, the third region comprises hydrogen; A semiconductor device, wherein a concentration of hydrogen in the third region is higher than a concentration of hydrogen in the second region. 　 In any one of claims 1 to 8, the first region has a second element; the second element is argon, krypton or xenon; The first region has a portion having a higher concentration of the second element than the second region. 　 In any one of claims 1 to 8, the third region has a second element; the second element is argon, krypton or xenon; The third region has a portion having a higher concentration of the second element than the second region. 　 In any one of claims 1 to 8, the first insulating layer includes a second insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer; the second insulating layer and the fourth insulating layer each include silicon and nitrogen; The third insulating layer comprises silicon and oxygen. 　 In any one of claims 1 to 8, the first insulating layer includes a second insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer on the third insulating layer; the second insulating layer comprises silicon and nitrogen; the third insulating layer comprises silicon and oxygen; The fourth insulating layer comprises one or both of aluminum and hafnium, and oxygen.

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