Manufacturing device and method for producing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. Also provided is a manufacturing device that is used for producing said semiconductor device. A manufacturing device in which a forming chamber having a function of forming a film by thermal ALD and a film forming chamber having a function of forming a film by plasma ALD are connected through a transfer chamber is used, whereby film formation by thermal ALD and film formation by plasma ALD are continuously performed without exposure to the atmosphere. Thus, for example, a plurality of layers constituting a gate insulating layer to be provided on an oxide semiconductor layer are continuously formed without being exposed to the atmosphere.

Description

Manufacturing apparatus and method for manufacturing semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing apparatus and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Another object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, a display device, or a memory device. Another object of one embodiment of the present invention is to provide a semiconductor device, a display device, or a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operating speed.

[0012] An object of one embodiment of the present invention is to provide a novel manufacturing apparatus capable of successively forming a plurality of films without exposure to the air, or a manufacturing method of a transistor, a semiconductor device, a display device, or a memory device, which includes a step of successively forming a plurality of films without exposure to the air.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is a manufacturing apparatus including a first film formation chamber, a second film formation chamber, a third film formation chamber, a first treatment chamber, and a transfer chamber. The first film formation chamber has a function of performing film formation by a thermal ALD method using a first precursor and a first oxidant. The second film formation chamber has a function of performing film formation by a plasma ALD method using a second precursor and a second oxidant. The third film formation chamber has a function of performing film formation by a thermal ALD method using a third precursor and a third oxidant. The first treatment chamber has a function of performing heat treatment or microwave treatment. The first film formation chamber is connected to the second film formation chamber, the third film formation chamber, and the first treatment chamber via the transfer chamber.

[0015] The manufacturing apparatus preferably further includes a fourth film formation chamber. The fourth film formation chamber preferably has a function of forming a conductive layer by a CVD method. The fourth film formation chamber is preferably connected to the first film formation chamber, the second film formation chamber, and the first processing chamber via a transfer chamber.

[0016] One embodiment of the present invention is a manufacturing apparatus including a first film formation chamber, a second film formation chamber, a first treatment chamber, and a transfer chamber. The first film formation chamber has a function of performing film formation by a plasma ALD method using a first precursor and a first gas containing nitrogen. The second film formation chamber has a function of performing film formation by a thermal ALD method using a second precursor and an oxidizer. The first treatment chamber has a function of performing heat treatment or microwave treatment. The first film formation chamber is connected to the second film formation chamber and the first treatment chamber via the transfer chamber.

[0017] The manufacturing apparatus preferably further includes a third film formation chamber. The third film formation chamber preferably has a function of forming a film by a plasma ALD method using a third precursor and a second gas containing nitrogen. The third film formation chamber is preferably connected to the first film formation chamber, the second film formation chamber, and the first processing chamber via a transfer chamber.

[0018] The manufacturing apparatus preferably further includes a second treatment chamber. In this case, the first treatment chamber preferably has a function of performing heat treatment, and the second treatment chamber preferably has a function of performing microwave treatment. The second treatment chamber is preferably connected to the first film formation chamber, the second film formation chamber, and the first treatment chamber via a transfer chamber.

[0019] One embodiment of the present invention is a method for manufacturing a semiconductor device including an oxide semiconductor layer, a gate insulating layer, and a gate electrode, which are stacked in this order, using a manufacturing apparatus including a first film formation chamber, a second film formation chamber, a third film formation chamber, and a transfer chamber. The gate insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is formed over the oxide semiconductor layer by a thermal ALD method using a first precursor and a first oxidant in the first film formation chamber. a second insulating layer is formed on the first insulating layer by plasma ALD using a second precursor and a second oxidant in a second deposition chamber; a third insulating layer is formed on the second insulating layer by thermal ALD using a third precursor and a third oxidant in a third deposition chamber; the first deposition chamber is connected to the second deposition chamber and the third deposition chamber via a transfer chamber. The manufacturing apparatus preferably has a fourth deposition chamber. In this case, a conductive layer to be a gate electrode is preferably formed on the third insulating layer by CVD in the fourth deposition chamber.

[0020] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with high on-state current can be provided. According to one embodiment of the present invention, a transistor with low parasitic capacitance can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a highly reliable transistor, a semiconductor device, a display device, or a memory device can be provided. According to one embodiment of the present invention, a semiconductor device, a display device, or a memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided.

[0021] According to one embodiment of the present invention, a novel manufacturing apparatus capable of successively forming a plurality of films without exposure to the air can be provided, or a manufacturing method for a transistor, a semiconductor device, a display device, or a memory device, which includes a step of successively forming a plurality of films without exposure to the air, can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0023] FIG. 1 is a plan view showing an example of a manufacturing apparatus. FIGS. 2A and 2B are plan views showing an example of a manufacturing apparatus. FIG. 3 is a plan view showing an example of a manufacturing apparatus. FIGS. 4A and 4B are cross-sectional views showing an example of a manufacturing apparatus. FIGS. 5A to 5C are cross-sectional views showing an example of a manufacturing apparatus. FIG. 6 is a cross-sectional view showing an example of a manufacturing apparatus. FIGS. 7A to 7D are cross-sectional views illustrating a method for forming a metal oxide film according to an embodiment of the present invention. FIGS. 8A to 8D are cross-sectional views illustrating a method for forming a metal oxide film according to an embodiment of the present invention. FIGS. 9A1 and 9A2 are plan views showing an example of a semiconductor device. FIGS. 9B to 9E are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIGS. 13A to 13D are cross-sectional views showing an example of a semiconductor device. FIGS. 14A to 14D are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. 15B to 15E are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A to 17C2 are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a memory device. FIGS. 18B and 18C are cross-sectional views showing an example of a memory device. FIGS. 19A and 19B are cross-sectional views showing an example of a memory device. FIGS. 20A and 20B are cross-sectional views showing an example of a memory device. FIG. 21 is a cross-sectional view showing an example of a memory device. FIG. 22 is a cross-sectional view showing an example of a memory device. FIG. 23 is a cross-sectional view showing an example of a memory device. FIG. 24 is a cross-sectional view showing an example of a memory device. FIG. 25 is a cross-sectional view showing an example of a memory device. FIG. 26 is a cross-sectional view showing an example of a memory device. FIGS. 27A to 27D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 28A and 28B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 29A and 29B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 30A and 30B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. 31A and 31B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.32A and 32B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 33A is a plan view illustrating an example of a memory device. FIG. 33B is a cross-sectional view illustrating an example of a memory device. FIG. 34 is a cross-sectional view illustrating an example of a memory device. FIG. 35 is a cross-sectional view illustrating an example of a memory device. FIG. 36 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 37A to 37H are diagrams illustrating a circuit structural example of a memory cell. FIGS. 38A and 38B are perspective views illustrating a structural example of a semiconductor device. FIG. 39 is a block diagram illustrating a CPU. FIGS. 40A and 40B are perspective views of a semiconductor device. FIGS. 41A and 41B are perspective views of a semiconductor device. FIGS. 42A and 42B are diagrams illustrating various memory devices by layer. FIGS. 43A and 43B are perspective views of an example of a display device. FIG. 44 is a cross-sectional view of an example of a display device. FIG. 45 is a cross-sectional view of an example of a display device. FIGS. 46A to 46C are diagrams illustrating a structural example of a display device. FIGS. 47A and 47B are diagrams illustrating an example of an electronic component. Fig. 48A to Fig. 48C are diagrams showing an example of a mainframe computer. Fig. 48D is a diagram showing an example of space equipment. Fig. 48E is a diagram showing an example of a storage system applicable to a data center. Figs. 49A to 49F are diagrams showing an example of electronic equipment. Figs. 50A to 50G are diagrams showing an example of electronic equipment. Figs. 51A to 51F are diagrams showing an example of electronic equipment.

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0028] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0031] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0033] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0034] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0035] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0037] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0039] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0040] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0041] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0042] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0043] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0044] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0045] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0046] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0047] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0048] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0049] Embodiment 1 In this embodiment, a manufacturing apparatus according to one embodiment of the present invention will be described with reference to FIGS.

[0050] The manufacturing apparatus of one embodiment of the present invention can perform film formation by two or more film formation methods without exposing the substrate to the air. This allows, for example, in a manufacturing process of a transistor, a semiconductor device, a display device, or a memory device, to form a plurality of films by different film formation methods without exposing the substrate to the air. Therefore, impurities can be significantly reduced from being mixed in during the manufacturing process, and the reliability of the transistor, the semiconductor device, the display device, or the memory device can be improved. Specifically, in a manufacturing process of a transistor using an oxide semiconductor layer, impurities such as hydrogen and water can be prevented from being mixed into layers constituting the transistor.

[0051] First, an example of a film formation method that can be applied to a film formation chamber included in a manufacturing apparatus according to one embodiment of the present invention will be described.

[0052] For example, the manufacturing apparatus according to one embodiment of the present invention preferably has a function of performing at least one of film formation using a sputtering method, film formation using an atomic layer deposition (ALD) method, and film formation using a chemical vapor deposition (CVD) method.

[0053] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0054] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0055] The ALD method can deposit atoms layer by layer, which allows for the formation of ultrathin films, the formation of films on structures with high aspect ratios or surfaces with large steps, the formation of films with fewer defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures. Furthermore, the PEALD method may be preferable because it utilizes plasma, which allows for film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. The quantification of these elements can be performed using XPS or SIMS. By employing high substrate temperature conditions during film formation and / or performing an impurity removal process, the amount of carbon and chlorine contained in the film may be reduced compared to ALD without these methods.

[0056] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0057] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0058] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0059] A manufacturing apparatus according to one embodiment of the present invention includes a first film formation chamber, a second film formation chamber, a third film formation chamber, a first treatment chamber, and a transfer chamber.

[0060] The first film formation chamber has a function of forming a film by a thermal ALD method using a first precursor and a first oxidizing agent, the second film formation chamber has a function of forming a film by a PEALD method using a second precursor and a second oxidizing agent, the third film formation chamber has a function of forming a film by a thermal ALD method using a third precursor and a third oxidizing agent, the first treatment chamber has a function of performing a heat treatment or a microwave treatment, and the first film formation chamber is connected to the second film formation chamber, the third film formation chamber, and the first treatment chamber, respectively, via a transfer chamber.

[0061] This configuration allows the film formation process by thermal ALD and the film formation process by PEALD to be performed consecutively without exposing the substrate to the atmosphere. Furthermore, even if a heat treatment or microwave treatment is performed between the two film formation processes, it can be performed in the first treatment chamber, which is preferable because it does not require the substrate to be taken out of the manufacturing apparatus.

[0062] Specifically, for example, an aluminum oxide film can be formed by thermal ALD, a silicon oxide film can be formed by PEALD, and a hafnium oxide film can be formed by thermal ALD. This three-layer stack structure is suitable for, for example, a gate insulating layer of a transistor.

[0063] The fourth deposition chamber may be connected to the first deposition chamber, the second deposition chamber, and the first treatment chamber via a transfer chamber.

[0064] With this configuration, it is possible to perform a film formation process by thermal ALD, a film formation process by PEALD, and a film formation process by CVD successively without exposing the substrate to the atmosphere.

[0065] For example, it is preferable that a gate insulating layer be formed in the first to third deposition chambers, and then a conductive layer to be a gate electrode be formed in the fourth deposition chamber.

[0066] Alternatively, a manufacturing apparatus according to another embodiment of the present invention has three film formation chambers, two of which have the function of forming a film by an ALD method and the remaining film formation chamber has the function of forming a film by a sputtering method, and further has a treatment chamber for performing heat treatment, which is connected to each of the three film formation chambers via a transfer chamber.

[0067] With this configuration, a film formation step by an ALD method and a film formation step by a sputtering method can be performed consecutively without exposing the substrate to the air. Furthermore, even when a heat treatment is performed between the two film formation steps, the heat treatment can be performed in the treatment chamber, which is preferable because it is not necessary to take the substrate out of the manufacturing apparatus. The manufacturing apparatus having such a configuration is suitable for forming an oxide semiconductor layer, for example, as exemplified in Embodiment 2.

[0068] Alternatively, a manufacturing apparatus according to another embodiment of the present invention includes a first film formation chamber, a second film formation chamber, a first treatment chamber, and a transfer chamber.

[0069] The first film formation chamber has a function of forming a film by a PEALD method using a first precursor and a first gas containing nitrogen, the second film formation chamber has a function of forming a film by a thermal ALD method using a second precursor and an oxidizing agent, the first treatment chamber has a function of performing a heat treatment or a microwave treatment, and the first film formation chamber is connected to the second film formation chamber and the first treatment chamber via a transfer chamber.

[0070] The manufacturing apparatus preferably further includes a third deposition chamber having a function of depositing a film by a PEALD method using a third precursor and a second gas containing nitrogen, and the third deposition chamber is connected to the first deposition chamber, the second deposition chamber, and the first processing chamber via a transfer chamber.

[0071] This configuration allows the nitride film deposition process by PEALD and the oxide film deposition process by thermal ALD to be performed consecutively without exposing the substrate to the atmosphere. Furthermore, even if a heat treatment or microwave treatment is performed between the two deposition processes, it can be performed in the first processing chamber, which is preferable because it is not necessary to take the substrate out of the manufacturing apparatus.

[0072] Specifically, for example, a silicon nitride film can be formed using the PEALD method, and a silicon oxide film can be formed using the thermal ALD method. The successive deposition of an oxide film and a nitride film is suitable for, for example, the successive deposition of a gate insulating layer of a transistor and the successive deposition of an interlayer film constituting a semiconductor device or the like.

[0073] Preferably, each of the manufacturing apparatuses further includes a second treatment chamber, the first treatment chamber having a function of performing heat treatment, the second treatment chamber having a function of performing microwave treatment, and the second treatment chamber being connected to the first film formation chamber, the second film formation chamber, and the first treatment chamber via a transfer chamber.

[0074] This is preferable because, even when both a heat treatment and a microwave treatment are performed between two film formation steps, the heat treatment and the microwave treatment can be performed in the first treatment chamber and the second treatment chamber, eliminating the need to take the substrate out of the manufacturing apparatus.Furthermore, even when the heat treatment or the microwave treatment is performed before or after the film formation step, the first treatment chamber or the second treatment chamber can be used, which is preferable.

[0075] <Configuration example of manufacturing apparatus> Fig. 1 is a schematic diagram of a multi-chamber manufacturing apparatus 4000A. Fig. 2A is a schematic diagram of a multi-chamber manufacturing apparatus 4000B. Fig. 2B is a schematic diagram of a multi-chamber manufacturing apparatus 4000C. Fig. 3 is a schematic diagram of a multi-chamber manufacturing apparatus 4000D. Figs. 4A, 4B, and 5A to 5C are cross-sectional views of an ALD apparatus that can be used in the above manufacturing apparatus. Fig. 6 is a cross-sectional view of a sputtering apparatus that can be used in the above manufacturing apparatus. Note that Figs. 1 to 6 show representative configurations, and some components are omitted.

[0076] 1 , the manufacturing apparatus 4000A includes a load / unload chamber 4002, a load / unload chamber 4004, a transfer chamber 4006, a film formation chamber 4007, a film formation chamber 4008, a film formation chamber 4009, and a processing chamber 4011. The load / unload chamber 4002 and the load / unload chamber 4004 have a function of switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, and can load or unload a substrate. The transfer chamber 4006 is provided with a transfer arm 4014, and can transfer a substrate to or from each chamber in a vacuum.

[0077] Here, the loading / unloading chamber 4002, the loading / unloading chamber 4004, the film formation chamber 4007, the film formation chamber 4008, the film formation chamber 4009, and the treatment chamber 4011 are each connected to the transfer chamber 4006 via a gate valve. Therefore, the manufacturing apparatus 4000A can independently maintain a vacuum state in each chamber. This allows continuous processing in the film formation chamber 4007, the film formation chamber 4008, the film formation chamber 4009, and the treatment chamber 4011 without exposure to the atmosphere, thereby preventing impurities from being mixed into the film. Furthermore, contamination of the interface between the substrate and the film and the interface between each film is reduced, resulting in clean interfaces.

[0078] It is preferable to transport the substrate while adjusting the pressures in the film formation chamber and the transfer chamber to be approximately the same. For example, if the pressure difference between the film formation chamber and the transfer chamber is large, an air current due to the pressure difference may occur, causing foreign matter to be stirred up inside the chamber. By adjusting the pressures in the film formation chamber and the transfer chamber to be approximately the same, it is possible to prevent particles from adhering to the substrate and the substrate from being contaminated with impurities, etc., and this is preferable. Specifically, the difference in pressure between the transfer chamber and the film formation chamber is preferably 200 Pa or less, more preferably 100 Pa or less, and even more preferably 50 Pa or less. Furthermore, in order to prevent gases, impurities, etc. in the film formation chamber from flowing into the transfer chamber and contaminating the transfer chamber, it is preferable that the pressure in the film formation chamber be lower than the pressure in the transfer chamber.

[0079] The film formation chambers 4007 to 4009 each have a film formation apparatus. Examples of the film formation apparatus include an ALD apparatus, a CVD apparatus, and a sputtering apparatus. Examples of the ALD apparatus include a thermal ALD apparatus and a PEALD apparatus. Examples of the CVD apparatus include a PECVD apparatus, a thermal CVD apparatus, a photo-CVD apparatus, a metal CVD apparatus, and an MOCVD apparatus.

[0080] For example, it is preferable that the film formation chambers 4007 and 4009 have thermal ALD devices, and the film formation chamber 4008 has a PEALD device.

[0081] With this configuration, the insulating layer 250d, the insulating layer 250a, and the insulating layer 250b described in embodiment 3 ( FIG. 10C ) can be formed in the manufacturing apparatus 4000A. Specifically, the insulating layer 250d can be formed by a thermal ALD method in the film formation chamber 4007. Similarly, the insulating layer 250a can be formed by a PEALD method in the film formation chamber 4008. Furthermore, the insulating layer 250b can be formed by a thermal ALD method in the film formation chamber 4009. For example, it is preferable to use an aluminum oxide film for the insulating layer 250d, a silicon oxide film for the insulating layer 250a, and a hafnium oxide film for the insulating layer 250b.

[0082] The insulating layers 250d, 250a, and 250b preferably have low impurity concentrations because they function as gate insulating layers, which can prevent impurities from entering a channel formation region of the oxide semiconductor layer.

[0083] Alternatively, for example, it is preferable that the film formation chambers 4007 and 4009 have ALD devices, and the film formation chamber 4008 has a sputtering device.

[0084] A heating device (typically, a vacuum heating device) can be used in the processing chamber 4011. Note that the processing chamber 4011 may be configured to be provided with a processing device other than a film formation device, such as a plasma generation device (typically, a microwave processing device).

[0085] With such a structure, the oxide semiconductor 230a described in Embodiment 2 (FIG. 7A) can be formed in the deposition chamber 4007 by an ALD method. Similarly, the oxide semiconductor 230b (FIG. 7B) can be formed in the deposition chamber 4008 by a sputtering method. Furthermore, the oxide semiconductor 230c (FIG. 7C) can be formed in the deposition chamber 4009 by an ALD method. Furthermore, heat treatment (FIG. 7D) is preferably performed in the treatment chamber 4011.

[0086] 7A to 7D , the oxide semiconductors 230a to 230c can be successively formed and processed without exposure to the air. This prevents impurities from being mixed into the formed oxide semiconductor layer 230. Furthermore, since the impurities are prevented from interfering with crystal growth, the crystallinity can be improved.

[0087] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to result in a transistor suitable for high-speed operation and improved reliability.

[0088] Alternatively, for example, it is preferable that the film formation chambers 4007 and 4009 have PEALD devices, and the film formation chamber 4008 has a sputtering device.

[0089] With this structure, the insulating layers 161c, 161a, and 161d described in Embodiment 4 ( FIG. 27A ) can be formed in the manufacturing apparatus 4000A. Specifically, the insulating layer 161c can be formed by a PEALD method in the film formation chamber 4007. Similarly, the insulating layer 161a can be formed by a sputtering method in the film formation chamber 4008. Furthermore, the insulating layer 161d can be formed by a PEALD method in the film formation chamber 4009. For example, it is preferable to use silicon nitride films for the insulating layers 161c and 161d and a silicon oxide film for the insulating layer 161a.

[0090] In this manner, by using the manufacturing apparatus 4000A, the insulating layers 161c, 161a, and 161d can be successively formed without exposure to the air. Therefore, impurities can be prevented from being mixed into the insulating layers 161c, 161a, and 161d. The insulating layers 161c, 161a, and 161d are preferably low in impurity concentration because they are in contact with or near the oxide semiconductor layer. This can prevent impurities from being mixed into the channel formation region of the oxide semiconductor layer.

[0091] Using a similar structure and method, the insulating layers 280c, 280a, and 280e ( FIG. 28B ) described in Embodiment 4 can also be successively deposited without exposure to the air. Using a similar structure and method, the insulating layers 280f, 280b, and 280d ( FIG. 29A ) described in Embodiment 4 can also be successively deposited without exposure to the air. This can prevent impurities from being mixed into the insulating layers 280a to 280f. The insulating layers 280a to 280f are preferably low in impurity concentration because they are in contact with or near the oxide semiconductor layer. This can prevent impurities from being mixed into the channel formation region of the oxide semiconductor layer.

[0092] The loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, the film formation chamber 4007, the film formation chamber 4008, the film formation chamber 4009, and the treatment chamber 4011 are each connected to an exhaust unit. Examples of the exhaust unit include vacuum pumps such as dry pumps, mechanical booster pumps, cryopumps, and turbomolecular pumps. For example, the film formation chambers 4007, 4008, 4009, and the treatment chamber 4011 can be connected to a turbomolecular pump and a dry pump. Alternatively, for example, the film formation chambers 4007, 4008, 4009, and the treatment chamber 4011 may be further provided with a cryotrap. Alternatively, for example, when an ALD apparatus is used in the film formation chamber 4007 and the film formation chamber 4009, a dry pump and a powder adsorption trap may be provided. Furthermore, for example, a cryopump and a dry pump can be connected to the load / unload chamber 4002, the load / unload chamber 4004, and the transfer chamber 4006.

[0093] The film formation chambers 4007, 4008, 4009, and the processing chamber 4011 may each be connected to a gas purifier via a gas supply device. Each chamber may also be connected to the gas supply device via a gas heating mechanism. The gas heating mechanism is connected to the gas purifier via the gas supply device. The gas introduced into the processing chamber may have a dew point of −80° C. or lower, preferably −100° C. or lower, and more preferably −120° C. or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used. The gas introduced into the processing chamber can be heated to 40° C. or higher and 400° C. or lower by the gas heating mechanism. It is preferable to provide as many gas heating mechanisms, gas supply devices, and gas purifiers as there are gas types.

[0094] In addition, it is preferable that the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, the film formation chamber 4007, the film formation chamber 4008, the film formation chamber 4009, and the processing chamber 4011 are filled with an inert gas (nitrogen gas, etc.) with a controlled dew point to prevent moisture from adhering, and it is desirable to maintain a reduced pressure.

[0095] Alternatively, a substrate supply chamber may be provided outside the load / unload chamber 4002 and the load / unload chamber 4004. The substrate supply chamber has a cassette port for accommodating substrates and an alignment port for aligning the substrates. The substrate supply chamber, the load / unload chamber 4002, and the load / unload chamber 4004 may be connected by a transfer chamber having a transfer arm. With this configuration, substrates can be transferred between the substrate supply chamber and the load / unload chamber 4002 and the load / unload chamber 4004.

[0096] Furthermore, although the manufacturing apparatus 4000A is configured to include a loading / unloading chamber 4002, a loading / unloading chamber 4004, a film formation chamber 4007, a film formation chamber 4008, a film formation chamber 4009, and a processing chamber 4011, the present invention is not limited to this. The manufacturing apparatus may be configured to include two or four or more film formation chambers. The manufacturing apparatus may be configured to include two or more processing chambers. The manufacturing apparatus may be configured to include one loading / unloading chamber, or three or more. The manufacturing apparatus may be configured to include two or more transfer chambers. Furthermore, although one transfer arm 4014 is shown in FIG. 1, the present invention is not limited to this. For example, the transfer chamber 4006 may be configured to include two or more transfer arms.

[0097] For example, a manufacturing apparatus 4000B shown in FIG. 2A differs from the manufacturing apparatus 4000A in that it does not have a film formation chamber 4009.

[0098] Note that the deposition steps for multiple layers formed using the same material and the same deposition method may be performed in one deposition chamber. For example, when the same material (here, silicon nitride) is used for the insulating layer 161c and the insulating layer 161d, the steps for forming the insulating layer 161c and the insulating layer 161d may both be performed in one deposition chamber.

[0099] Furthermore, a manufacturing apparatus 4000C shown in FIG. 2B differs from the manufacturing apparatus 4000A in that it includes a film formation chamber 4010 and a processing chamber 4012.

[0100] In the manufacturing apparatus 4000C, for example, the film formation chambers 4007 and 4009 preferably have thermal ALD devices, and the film formation chambers 4008 and 4010 preferably have PEALD devices.

[0101] With this configuration, the insulating layers 250d, 250a, 250b, and 250c ( FIG. 10B ) described in Embodiment 3 can be formed in the manufacturing apparatus 4000C. Specifically, the insulating layer 250d can be formed in the film formation chamber 4007 using a thermal ALD method. Similarly, the insulating layer 250a can be formed in the film formation chamber 4008 using a PEALD method. Furthermore, the insulating layer 250b can be formed in the film formation chamber 4009 using a thermal ALD method. Furthermore, the insulating layer 250c can be formed in the film formation chamber 4010 using a PEALD method. For example, it is preferable to use an aluminum oxide film for the insulating layer 250d, a silicon oxide film for the insulating layer 250a, a hafnium oxide film for the insulating layer 250b, and a silicon nitride film for the insulating layer 250c.

[0102] The insulating layers 250d, 250a, 250b, and 250c preferably have low impurity concentrations because they function as gate insulating layers, which can prevent impurities from entering a channel formation region of the oxide semiconductor layer.

[0103] It is preferable that one of the treatment chambers 4011 and 4012 has a heating device (typically, a vacuum heating device) and the other has a plasma generating device (typically, a microwave processing device). This allows both heat treatment and microwave treatment to be performed on the film, thereby further reducing the impurity concentration in the film.

[0104] Alternatively, both the treatment chamber 4011 and the treatment chamber 4012 may have a heating device. By providing a plurality of treatment chambers that can be used for heat treatment, the amount of processing per unit time can be increased in a heat treatment process that requires a relatively long processing time. This can improve the productivity of semiconductor devices and the like. Alternatively, both the treatment chamber 4011 and the treatment chamber 4012 may have a plasma generation device.

[0105] Furthermore, the treatment performed in one or both of the treatment chambers 4011 and 4012 is not limited to heat treatment and microwave treatment. For example, substrate cleaning treatment, plasma treatment, reverse sputtering treatment, etching treatment, ashing treatment, etc. may be performed. In this case, a dry etching apparatus may be provided in one or both of the treatment chambers 4011 and 4012.

[0106] 3 includes a loading / unloading chamber 4052, a loading / unloading chamber 4054, a transfer chamber 4056a, a transfer chamber 4056b, a transfer chamber 4065, a film formation chamber 4060a, a film formation chamber 4060b, a film formation chamber 4060c, a film formation chamber 4060d, a film formation chamber 4060e, a treatment chamber 4061a, and a treatment chamber 4061b. A transfer arm 4064a is provided in the transfer chamber 4056a, and a transfer arm 4064b is provided in the transfer chamber 4056b. Here, the loading / unloading chamber 4052, the loading / unloading chamber 4054, the film formation chamber 4060a, the film formation chamber 4060b, the treatment chamber 4061a, and the treatment chamber 4061b are independently connected to the transfer chamber 4056a via gate valves. The film formation chambers 4060c, 4060d, and 4060e are independently connected to the transfer chamber 4056b via gate valves.

[0107] The load / unload chamber 4052 corresponds to the load / unload chamber 4002, the load / unload chamber 4054 corresponds to the load / unload chamber 4004, the transfer chamber 4056a and the transfer chamber 4056b correspond to the transfer chamber 4006, the film formation chambers 4060a to 4060e correspond to the film formation chambers 4007 to 4009, the treatment chamber 4061a and the treatment chamber 4061b correspond to the treatment chamber 4011, and the transfer arm 4064a and the transfer arm 4064b correspond to the transfer arm 4014. Therefore, the above description can be referred to for details.

[0108] The transfer chamber 4065 connects the transfer chamber 4056a and the transfer chamber 4056b. Substrates can be transferred between the transfer arm 4064a and the transfer arm 4064b via the transfer chamber 4065. Note that a configuration may be adopted in which multiple transfer chambers are provided between the transfer chamber 4056a and the transfer chamber 4056b. Furthermore, when the number of transfer chambers is further increased, transfer chambers can be provided as appropriate according to the number of transfer chambers.

[0109] 3 , by increasing the number of film formation chambers, for example, ALD apparatuses can be used in the film formation chambers 4060a, 4060b, 4060d, and 4060e, and a sputtering apparatus can be used in the film formation chamber 4060c. This allows for an increased amount of film formation per unit time in the ALD film formation process, which requires a relatively long processing time. Therefore, productivity of oxide semiconductor layers and semiconductor devices using oxide semiconductor layers can be improved.

[0110] Furthermore, for example, it is preferable that the film formation chambers 4060a and 4060c have a thermal ALD apparatus, the film formation chamber 4060b has a PEALD apparatus, and the film formation chambers 4060d and 4060e have a metal CVD apparatus or an MOCVD apparatus.

[0111] With this configuration, the conductive layers 265a and 265b can be formed in the manufacturing apparatus 4000D in succession to the formation of the insulating layers 250d, 250a, and 250b ( FIG. 10C ) described in Embodiment 3. Specifically, the insulating layer 250d can be formed in the deposition chamber 4060a using a thermal ALD method. Similarly, the insulating layer 250a can be formed in the deposition chamber 4060b using a PEALD method. Furthermore, the insulating layer 250b can be formed in the deposition chamber 4060c using a thermal ALD method. Furthermore, the conductive layer 265a can be formed in the deposition chamber 4060d, and the conductive layer 265b can be formed in the deposition chamber 4060e.

[0112] In this way, the gate insulating layer and the gate electrode can be formed successively without being exposed to the atmosphere, which reduces impurities at the interface between the gate insulating layer and the gate electrode, thereby improving the electrical characteristics and reliability of the transistor.

[0113] Further, the manufacturing apparatus according to one embodiment of the present invention may be of a single-wafer type or a batch type in which films are formed on a plurality of substrates at once.

[0114] [ALD Apparatus] Next, an example of the configuration of a thermal ALD apparatus that can be used in the film formation chamber will be described with reference to Fig. 4A. The thermal ALD apparatus includes a film formation chamber (chamber 4520), a raw material supply unit 4521 (raw material supply units 4521a to 4521c), a raw material supply unit 4531, high-speed valves 4522a to 4522d that are introduction amount controllers, a gas supply unit 4532, a raw material inlet 4523, a raw material outlet 4524, and an exhaust unit 4525. The raw material inlet 4523 installed in the chamber 4520 is connected to the raw material supply units 4521a, 4521b, 4521c, 4531, and 4532 via supply pipes and valves, respectively, and the raw material outlet 4524 is connected to the exhaust unit 4525 via an exhaust pipe, a valve, a pressure regulator, and a powder adsorption trap.

[0115] A substrate holder 4526 is provided inside the chamber 4520, and a substrate 4530 is placed on the substrate holder 4526. The substrate holder 4526 may have a rotation mechanism. A heater 4527 is provided on the outer wall of the chamber 4520, and is capable of controlling the temperature of the interior of the chamber 4520, the substrate holder 4526, the surface of the substrate 4530, and the like. The heater 4527 can preferably control the temperature of the surface of the substrate 4530 to 100°C or higher and 600°C or lower, preferably 100°C or higher and 350°C or lower, and more preferably 200°C or higher and lower than the decomposition temperature of the precursor, and the temperature of the heater 4527 itself can preferably be set to 100°C or higher and 600°C or lower. By performing film formation while heating the substrate within such a temperature range, impurities such as hydrogen or carbon contained in the precursor or reactant can be prevented from remaining in the film. For example, when forming a metal oxide layer, the removal of the impurities simultaneously causes rearrangement of metal atoms and oxygen atoms, allowing each oxide layer to be arranged in a highly ordered manner. Therefore, a metal oxide having a highly crystalline, layered crystal structure can be formed. Heat treatment after forming the metal oxide film may be performed using a heater 4527.

[0116] In the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, and the raw material supply unit 4531, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating means, etc. Alternatively, the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, and the raw material supply unit 4531 may be configured to supply a gaseous raw material gas.

[0117] 4A , a metal oxide can be formed by appropriately selecting raw materials (such as a volatile organometallic compound) used in the raw material supply unit 4521 and the raw material supply unit 4531 and introducing the selected raw materials into the chamber 4520. As described above, when forming an In—Ga—Zn oxide containing indium, gallium, and zinc as a metal oxide, it is preferable to use a film formation apparatus provided with at least three raw material supply units 4521 a to 4521 c and at least one raw material supply unit 4531, as shown in FIG.

[0118] For example, a precursor containing indium is supplied from the raw material supply unit 4521a, a precursor containing gallium is supplied from the raw material supply unit 4521b, and a precursor containing zinc is supplied from the raw material supply unit 4521c.

[0119] Examples of precursors containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0120] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0121] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0122] Oxidizing agents include, for example, ozone, oxygen, and water.

[0123] Furthermore, the pressure inside the raw material supply unit 4521 is preferably set to a level that allows the internal gas to flow sufficiently through the piping when the high-speed valve is opened. Therefore, it is preferable to appropriately adjust the temperature of the raw material supply unit 4521. For example, when storing triethylindium in the raw material supply unit 4521a and triethylgallium in the raw material supply unit 4521b, it is preferable to heat the raw material supply units 4521a and 4521b with a heater to keep them warm, since triethylindium and triethylgallium have low vapor pressures. Furthermore, for example, when storing diethylzinc in the raw material supply unit 4521c, it is preferable to cool the raw material supply unit 4521c with a Peltier element for storage, since diethylzinc has a high vapor pressure.

[0124] Furthermore, it is preferable that the precursor containing indium, the precursor containing gallium, and the precursor containing zinc have a high decomposition temperature. Therefore, an inorganic precursor may be used as the precursor. When a halogen-based compound or the like is used as the inorganic precursor, the gas derived from the inorganic precursor may be highly corrosive. Therefore, it is preferable to use a highly corrosion-resistant material, such as titanium, for components that come into contact with gas, such as chambers, piping, and various gas supply units.

[0125] Furthermore, a reactant is supplied from the raw material supply unit 4531. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0126] A carrier gas is supplied from the gas supply unit 4532. The carrier gas may be argon (Ar), helium (He), or nitrogen (N ２The precursor from the raw material supply part 4521 and the reactant from the raw material supply part 4531 are mixed with the carrier gas and introduced into the chamber 4520.

[0127] Furthermore, a piping heater 4534a is provided to cover piping or valves between the raw material supply unit 4521a, the raw material supply unit 4521b, the raw material supply unit 4521c, the raw material supply unit 4531, and the gas supply unit 4532 and the chamber 4520. A piping heater 4534b is provided to cover piping or valves between the exhaust device 4525 and the chamber 4520. The temperatures of the piping heaters 4534a and 4534b can be appropriately set, for example, within a range of room temperature or higher and 300°C or lower. By providing such a piping heater, it is possible to prevent precursors supplied from the raw material supply unit 4521 from solidifying on the inner walls of the piping of the gas introduction system and the gas exhaust system. In particular, precursors with high decomposition temperatures, such as inorganic precursors, tend to solidify easily. Therefore, when using such precursors, it is preferable to provide a piping heater to cover the piping of the gas introduction system and the gas exhaust system. Furthermore, it is preferable that the temperatures of the piping heater 4534a, the piping heater 4534b, and the heater 4527 can be controlled independently. By independently controlling the piping heater 4534a, the piping heater 4534b, and the heater 4527, the temperature of each heater can be controlled individually. However, this is not limiting, and the temperature controls of the piping heater 4534a, the piping heater 4534b, and the heater 4527 may be configured to be linked to each other. In this case, the temperatures can be adjusted collectively, which reduces the cost of device components, etc.

[0128] The high-speed valves 4522a to 4522d can be precisely controlled in time, thereby enabling the source gases supplied from the source supply units 4521a, 4521b, 4521c, and 4531 to be controlled and introduced into the chamber 4520.

[0129] For example, when supplying precursors contained in the raw material supply units 4521a, 4521b, and 4521c, the corresponding high-speed valves among the high-speed valves 4522a to 4522c are opened. When supplying a reactant contained in the raw material supply unit 4531, the high-speed valve 4522d is opened. When purging the chamber 4520, the high-speed valves 4522a to 4522d are closed, and only the carrier gas contained in the gas supply unit 4532 is introduced into the chamber 4520.

[0130] 4A, the raw material supply unit 4521 and the gas supply unit 4532 are connected via one high-speed valve each in the high-speed valves 4522a to 4522c, but the present invention is not limited to this. For example, the raw material supply unit 4521 and the gas supply unit 4532 may be connected via two high-speed valves each in the high-speed valves 4522a to 4522c. In this case, one high-speed valve has the function of drawing carrier gas from the gas supply unit 4532 into the raw material supply unit 4521. The other high-speed valve has the function of pushing the gas, which is a mixture of precursor and carrier gas in the raw material supply unit 4521, toward the chamber.

[0131] 4A shows an example in which three raw material supply units 4521 and one raw material supply unit 4531 are provided, but this embodiment is not limited to this. One, two, or four or more raw material supply units 4521 may be provided. Two or more raw material supply units 4531 may also be provided.

[0132] 4A , heater 4527, raw material inlet 4523, and raw material outlet 4524 are arranged in the lower part of chamber 4520, but the arrangement thereof can be appropriately set. Also, in FIG. 4A , the inlets of raw material supply unit 4521 a, raw material supply unit 4521 b, raw material supply unit 4521 c, raw material supply unit 4531, and gas supply unit 4532 are combined into raw material inlet 4523, but the arrangement is not limited to this, and a different inlet may be provided for each.

[0133] 4B , the PEALD apparatus includes a deposition chamber (chamber 4020), a source supply unit 4021 (source supply units 4021 a to 4021 c), a source supply unit 4031, high-speed valves 4022 a to 4022 d serving as introduction amount controllers, a gas supply unit 4032, a source inlet 4023, a source inlet 4033, a source outlet 4024, and an exhaust device 4025. Raw material inlet 4023 and raw material inlet 4033 installed in chamber 4020 are connected to raw material supply unit 4021a, raw material supply unit 4021b, raw material supply unit 4021c, raw material supply unit 4031, and gas supply unit 4032 via supply pipes and valves, respectively, and raw material outlet 4024 is connected to exhaust device 4025 via an exhaust pipe, valve, and pressure regulator. A substrate holder 4026 is also provided inside chamber 4020, and a substrate 4030 is placed on substrate holder 4026. A heater 4027 is also provided on the outer wall of the chamber, and piping heaters 4034a and 4034b are also provided to cover piping and the like connected to the chamber.

[0134] Here, chamber 4020 corresponds to chamber 4520, raw material supply unit 4021 corresponds to raw material supply unit 4521, raw material supply unit 4031 corresponds to raw material supply unit 4531, high-speed valves 4022a to 4022d correspond to high-speed valves 4522a to 4522d, gas supply unit 4032 corresponds to gas supply unit 4532, raw material inlet 4023 corresponds to raw material inlet 4523, raw material outlet 4024 corresponds to raw material outlet 4524, exhaust device 4025 corresponds to exhaust device 4525, substrate holder 4026 corresponds to substrate holder 4526, substrate 4030 corresponds to substrate 4530, heater 4027 corresponds to heater 4527, piping heater 4034a corresponds to piping heater 4534a, and piping heater 4034b corresponds to piping heater 4534b, and the above description can be referred to for detailed configurations.

[0135] As shown in FIG. 4B , by connecting a plasma generator 4028 to the chamber 4020, the PEALD apparatus can perform film formation by the PEALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP-type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 2 MHz to 60 MHz. For example, it can output power having a frequency of 13.56 MHz. The PEALD method allows film formation without reducing the film formation rate even at low temperatures, so it is suitable for use in a single-wafer deposition apparatus with low film formation efficiency.

[0136] The reactant discharged from the raw material supply unit 4031 passes through the plasma generator 4028 and is converted into a plasma state. The reactant in a plasma state is introduced into the chamber 4020 from the raw material inlet 4033. Although not shown in FIG. 4B , the reactant discharged from the raw material supply unit 4031 may be configured to be mixed with a carrier gas.

[0137] Furthermore, a mechanism for applying a constant potential or high frequency may be provided to the substrate holder 4526. Alternatively, the substrate holder 4526 may be floating or grounded.

[0138] In FIG. 4B , raw material inlet 4033 is located at the top of chamber 4520, heater 4027 and raw material inlet 4023 are located on the side of chamber 4520, and raw material outlet 4524 is located at the bottom of chamber 4520; however, the arrangement is not limited to this and can be set as appropriate.

[0139] 5A to 5C, different configurations of an ALD apparatus that can be used in a manufacturing apparatus according to one embodiment of the present invention will be described. Note that detailed description of configurations and functions similar to those of the ALD apparatus shown in FIG. 4B may be omitted.

[0140] 5A is a schematic diagram showing one embodiment of a PEALD apparatus. The PEALD apparatus 4100 includes a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively referred to as a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. Furthermore, a plasma generation device 4128 can apply high frequency waves such as RF or microwaves to a gas introduced into the plasma generation chamber 4111 to generate plasma 4131 within the plasma generation chamber 4111. When generating plasma 4131 using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Furthermore, such plasma generated by applying microwaves and a magnetic field is sometimes called ECR (Electron Cyclotron Resonance) plasma.

[0141] The reaction chamber 4120 also has a substrate holder 4126, on which a substrate 4130 is placed. The source gas introduced through the source gas inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. The source gas introduced through the source gas inlet 4133 is converted into a plasma state by the plasma generator 4128. The source gas in the plasma state recombines with electrons or other molecules before reaching the surface of the substrate 4130, becoming a radical state, which then reaches the substrate 4130. An ALD apparatus that uses radicals to form a film in this manner is sometimes called a radical-enhanced ALD (radical-ALD) apparatus. While the PEALD apparatus 4100 has a configuration in which the plasma generation chamber 4111 is provided above the reaction chamber 4120, this embodiment is not limited to this. The plasma generation chamber 4111 may also be provided adjacent to the side of the reaction chamber 4120.

[0142] FIG. 5B is a schematic diagram showing one embodiment of a PEALD apparatus. The PEALD apparatus 4200 includes a chamber 4220. The chamber 4220 includes an electrode 4213, a source gas outlet 4224, and a substrate holder 4226. A substrate 4230 is disposed on the substrate holder 4226. The electrode 4213 includes a source gas inlet 4223 and a shower head 4214 that supplies the introduced source gas into the chamber 4220. A power supply 4215 capable of applying high frequency power is connected to the electrode 4213 via a capacitor 4217. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode, respectively, for generating plasma 4231. The source gas introduced from the source inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the source gas introduced from the source inlet 4223 becomes plasma between the electrode 4213 and the substrate holder 4226. The source gas in plasma state is incident on the substrate 4230 due to a potential difference (also referred to as an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0143] FIG. 5C is a schematic diagram showing an embodiment of a PEALD apparatus different from that shown in FIG. 5B . The PEALD apparatus 4300 includes a chamber 4320. The chamber 4320 includes an electrode 4313, a source gas outlet 4324, and a substrate holder 4326. A substrate 4330 is disposed on the substrate holder 4326. The electrode 4313 includes a source gas inlet 4323 and a shower head 4314 that supplies the introduced source gas into the chamber 4320. A power supply 4315 capable of applying high frequency power is connected to the electrode 4313 via a capacitor 4317. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency power. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode, respectively, for generating plasma 4331. The PEALD apparatus 4300 differs from the PEALD apparatus 4200 in that it includes a mesh 4319 connected to a power supply 4321 capable of applying high-frequency waves via a capacitor 4322 between an electrode 4313 and a substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The source gas introduced from the source inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced from the source inlet 4323 becomes a plasma between the electrode 4313 and the substrate holder 4326. The charge of the plasma-state source gas is removed by the mesh 4319, and the plasma-state source gas reaches the substrate 4130 in an electrically neutral state, such as in the form of radicals. This allows film formation to be performed while suppressing ion incidence and plasma-induced damage.

[0144] 4B and 5A to 5C, plasma processing or microwave processing may be performed using the PEALD apparatus. In this case, plasma processing or microwave processing can be performed without moving to a processing chamber.

[0145] [Sputtering Apparatus] Next, an example of the configuration of a sputtering apparatus that can be used in the film formation chamber will be described with reference to FIG.

[0146] The sputtering apparatus includes a deposition chamber 4602, and includes a backing plate 4608 and a substrate holder 4612 therein. A target 4610 can be attached to the backing plate 4608. Note that the target 4610 can be, for example, a target that can be used for an oxide semiconductor layer. A substrate 4620 is disposed on the substrate holder 4612. As shown in FIG. 6 , the target 4610 and the substrate 4620 are preferably disposed facing each other. Outside the deposition chamber 4602, there are provided a magnet unit 4606, a DC power supply (direct current power supply) 4615 electrically connected to the backing plate 4608, an RF power supply (high frequency power supply) 4618 electrically connected to the backing plate 4608, and an RF power supply (high frequency power supply) 4616 electrically connected to the substrate holder 4612. Note that in this specification, a combination of multiple magnets is referred to as a magnet unit. Although not shown, the sputtering apparatus is also provided with an exhaust system having a vacuum pump that exhausts the inside of the film formation chamber 4602, and a gas supply system that introduces gas into the film formation chamber 4602. In addition, a configuration in which an adhesion prevention plate is placed inside the film formation chamber 4602 may be adopted.

[0147] Power applied from an RF power supply 4618 or a DC power supply 4615 is applied to the target 4610 via a backing plate 4608. At this time, plasma can be generated by keeping the film formation chamber 4602 in a reduced pressure state. In addition, by placing a magnet unit 4606 near the target 4610, electrons in the plasma are confined by the magnetic field of the magnet unit 4606, increasing the probability of collisions between gas molecules and electrons, and making it possible to obtain high-density plasma.

[0148] Here, the RF power supply 4618 can preferably output power at a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 2 MHz to 60 MHz. For example, it can be configured to output power with a frequency of 13.56 MHz. By applying power with a high frequency, plasma can be made denser. By applying power to the target 4610 using the RF power supply 4618 in this way, RF sputtering can be performed. When the target 4610 has high insulating properties, RF sputtering is preferably performed.

[0149] When RF sputtering is performed, the DC power supply 4615 may be configured not to apply power. In this case, the DC power supply 4615 may not be provided.

[0150] Alternatively, the power of the DC power supply 4615 may be applied superimposed on the power of the RF power supply 4618. In this case, RF superimposed DC sputtering can be performed. In the RF superimposed DC sputtering, for example, applying the power of the DC power supply 4615 can improve the ionization rate of gas molecules and increase the film formation rate.

[0151] Alternatively, a DC sputtering method may be performed by applying power from the DC power supply 4615 instead of applying power from the RF power supply 4618. When the conductivity of the target 4610 is high, it is preferable to perform the DC sputtering method. When the DC sputtering method is performed, a configuration without providing the RF power supply 4618 is also possible.

[0152] Alternatively, a configuration may be adopted in which pulsed power is output from the DC power supply 4615 to perform pulsed DC sputtering. In pulsed DC sputtering, an oxide or nitride film can be formed by reacting oxygen gas or nitrogen gas. During this process, the film can be formed while removing the charge accumulation on the target surface that accompanies improved insulation of the target surface due to oxidation or nitridation of the target surface. Therefore, by forming a film using pulsed DC sputtering, it is possible to form an oxide or nitride film with relatively high insulation properties.

[0153] Furthermore, in the above sputtering method, a configuration may be adopted in which power is applied to the substrate holder 4612 from an RF power supply 4616. That is, a bias potential can be applied to the substrate 4620. Note that a configuration may be adopted in which power is not applied from the RF power supply 4616. In this case, a configuration may be adopted in which the RF power supply 4616 is not provided.

[0154] The substrate holder 4612 preferably has a function of heating the substrate 4620. The substrate holder 4612 can preferably heat the substrate 4620 to a temperature of, for example, 100° C. to 400° C., more preferably 200° C. to 300° C.

[0155] As shown in FIG. 6, it is preferable that the film formation chamber 4602 is electrically connected to a ground potential at the wall surface or the like.

[0156] 6 is a face-up arrangement in which the substrate 4620 is placed below the deposition chamber 4602 and the target 4610 is placed above the deposition chamber 4602, but the present invention is not limited to this. For example, the target 4610 may be placed below the deposition chamber 4602 and the substrate 4620 may be placed above the deposition chamber 4602, a face-down arrangement.

[0157] [Heating Device] Next, a heating device that can be used in the processing chamber will be described. There are no particular limitations on the heating device used for heat treatment, and the heating mechanism used in the heating device may be, for example, a mechanism that uses a resistance heating element or the like to heat. Alternatively, it may be a mechanism that heats by thermal conduction or thermal radiation from a medium such as heated gas. For example, an electric furnace or an RTA device such as an LRTA device or a GRTA device can be used. In an LRTA, the workpiece is heated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. In a GRTA, heat treatment is performed using high-temperature gas.

[0158] The temperature of the heat treatment by the heating mechanism may be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). The treatment time can be 10 hours or less, or 1 minute to 5 hours or lower, or 1 minute to 2 hours or lower. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes.

[0159] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration can be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0160] In addition, the gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the formed film as much as possible.

[0161] For example, after the oxide semiconductor layer is formed, the heat treatment is performed at a temperature of 350° C. to 550° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4 slm:1 slm. This heat treatment can reduce impurities such as water and hydrogen contained in the oxide semiconductor layer. Furthermore, the crystallinity of the oxide semiconductor layer can be improved.

[0162] Before or after forming a film in a film-forming chamber of a manufacturing apparatus, a heat treatment can be performed in a treatment chamber as appropriate, which is preferable because it can reduce impurities contained in the device to be fabricated and increase the purity of the main components in the film.

[0163] [Microwave Processing Apparatus] A microwave processing apparatus refers to an apparatus having a power source that generates high-density plasma using microwaves, and microwave processing refers to processing using a microwave processing apparatus. In addition, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0164] The frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. High-density plasma can be used to generate high-density oxygen radicals. The power of the power supply that applies microwaves to the microwave processing apparatus is preferably 1,000 W to 10,000 W, more preferably 2,000 W to 5,000 W. The microwave processing apparatus may also have a power supply that applies high-frequency waves such as RF to the substrate side. By applying high-frequency waves such as RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided to the workpiece.

[0165] The microwave treatment is preferably performed under reduced pressure, preferably at a pressure of 10 to 1000 Pa, more preferably at a pressure of 300 to 700 Pa. The treatment temperature is preferably 750° C. or less, more preferably 500° C. or less, and can be, for example, about 250° C. After the microwave treatment, a heat treatment may be performed without exposure to the atmosphere. The heat treatment temperature is, for example, preferably 100 to 750° C., more preferably 300 to 500° C.

[0166] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. By performing microwave treatment in an atmosphere containing oxygen in this manner, the carrier concentration of the oxide semiconductor layer can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration of the oxide semiconductor layer can be prevented.

[0167] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0168] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that oxygen supplied to the oxide semiconductor layer can be in one or more of the above forms, and is particularly preferably in the form of an oxygen radical.

[0169] In this manner, the impurities in the oxide semiconductor layer can be reduced, which allows crystal growth in the oxide semiconductor layer with a reduced impurity concentration, thereby further improving the crystallinity.

[0170] Note that the microwave treatment may be performed after the oxide semiconductor layer is formed, or after an insulating layer (for example, at least a part of a gate insulating layer) is formed on the oxide semiconductor layer. When the insulating layer includes an insulating layer (for example, an aluminum oxide film) that has a function of capturing or fixing hydrogen, the microwave treatment is preferably performed after the insulating layer is formed. This allows hydrogen generated by the microwave treatment to be captured or fixed to the insulating layer. Therefore, the V included in the channel formation region can be more effectively reduced. Ｏ H can be reduced.

[0171] Furthermore, by performing microwave treatment in a treatment chamber after forming a film in a film formation chamber, the film quality can be improved and the diffusion of impurities such as hydrogen and water can be suppressed. For example, by performing microwave treatment after forming a gate insulating layer, the film quality of the gate insulating layer can be improved, thereby improving the reliability of the transistor. When the gate insulating layer has a stacked structure, the microwave treatment may be performed once or multiple times. For example, the microwave treatment may be performed after each layer is formed, or after at least one layer is formed. The microwave treatment may also be performed before forming the gate insulating layer. Depending on the treatment temperature, the microwave treatment may also serve as a heat treatment.

[0172] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0173] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0174] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0175] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0176] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0177] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0178] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0179] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0180] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0181] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0182] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0183] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0184] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0185] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0186] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed by two different deposition methods may be referred to as a hybrid OS.

[0187] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0188] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0189] When a metal oxide is formed using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0190] For example, when an insulating layer having silicon, such as silicon oxide, is used as a surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method, and there is a concern that the mixing of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide.

[0191] Therefore, in one embodiment of the present invention, a metal oxide is formed by a second film formation method before a metal oxide is formed by a first film formation method. That is, a metal oxide is formed as a first layer by a second film formation method, and then a metal oxide is formed as a second layer on the first layer by a first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the second film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, since the incorporation of impurities such as silicon into the second layer can be suppressed, the crystallinity of the second layer can be potentially improved. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering.

[0192] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0193] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0194] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0195] Examples of the second film formation method include an ALD method, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo-assisted CVD method, a metal organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include a spray coating method.

[0196] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method and then forming a metal oxide as a second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure.

[0197] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a deposition method that easily imparts crystallinity is not used as a deposition method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a deposition method that provides better coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the entire layer. Furthermore, for example, by forming the third layer using a deposition method that causes less damage than the second layer, damage to the second layer can be reduced, and the oxide semiconductor layer can have high crystallinity throughout the entire layer.

[0198] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0199] Note that the third layer is an uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0200] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method, forming a metal oxide as a second layer by the first deposition method, and forming a metal oxide as a third layer by the second deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method has better coverage than the sputtering method. The use of the ALD method for the first and third layers can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0201] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor layer 230 can be manufactured by, for example, forming an oxide semiconductor 230a over a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor layer 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used. The layer 229 is an insulating film, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0202] The oxide semiconductor layer 230 can be used as the oxide semiconductor layer 230 included in each transistor described in Embodiment 3. The layer 229 corresponds to one or more of the conductive layer 220, the insulating layer 235, the conductive layer 240, and the like described in Embodiment 3.

[0203] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer 230.

[0204] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS. 7A to 8D.

[0205] First, an oxide semiconductor 230a is formed on the layer 229 (FIG. 7A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a (FIG. 7B).

[0206] The oxide semiconductor 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0207] The oxide semiconductor 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 230a is formed than the deposition method for the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0208] When a metal oxide film is formed by sputtering, damage to the surface on which the film is to be formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0209] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, the oxide semiconductor 230a is formed over the layer 229, and then the oxide semiconductor 230b is formed by a sputtering method. The oxide semiconductor 230a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed. By forming the oxide semiconductor 230a between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed, alloying of components contained in the oxide semiconductor layer 230 and components contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0210] By using the above structure, the thickness of the alloyed region can be reduced, or the thickness can be reduced to such an extent that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 7A and 7B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0211] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0212] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0213] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0214] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0215] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0216] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0217] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0218] Alternatively, the CAAC structure near the surface to be formed can sometimes be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. The FFT pattern reflects reciprocal lattice space information similar to an electron diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is 70° or more and 100° or less relative to the surface to be formed can be considered to have a CAAC structure.

[0219] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 7A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0220] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 230a by an ALD method will be described.

[0221] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 229. Here, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor.

[0222] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursor and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer of indium and oxygen combined (hereinafter referred to as the first layer). Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactant and reaction products are discharged from the chamber.

[0223] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the first layer. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0224] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors, reaction products, etc. are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are combined (hereinafter referred to as the second layer). Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants, reaction products, etc. are discharged from the chamber.

[0225] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the second layer, preferably at a temperature corresponding to the decomposition temperature of the precursor.

[0226] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0227] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, leaving zinc adsorbed on the substrate while desorbing components other than zinc, thereby forming a layer of zinc and oxygen combined (hereinafter referred to as the third layer). Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0228] Next, the first layer is formed again on the third layer by the above-described method. By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 230a on the layer 229 by an ALD method.

[0229] The ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, for example, the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0230] After the oxide semiconductor 230a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 230b over the oxide semiconductor 230a by a sputtering method.

[0231] Here, when the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, when the oxide semiconductor 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0232] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0233] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0234] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0235] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0236] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 230b by a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0237] As a result, as shown in FIG. 7B, an oxide semiconductor 230a can be formed over the layer 229 and an oxide semiconductor 230b can be formed over the oxide semiconductor 230a.

[0238] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b (FIG. 7C). Here, the oxide semiconductor 230c is formed by an ALD method. For the formation of the oxide semiconductor 230c by the ALD method, the method for forming the oxide semiconductor 230a can be referred to.

[0239] When an oxide semiconductor 230c having lower crystallinity than the CAAC structure is formed on an oxide semiconductor 230b having the CAAC structure by using an ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Thus, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0240] Next, a heat treatment step may be carried out.

[0241] The heat treatment temperature is, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment temperature can be 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 230b with the oxide semiconductor 230c (in other words, the crystal molecules formed by the ALD method).

[0242] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0243] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after deposition by the ALD method, the heat treatment step may cause the region to expand upward ( FIG. 7D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0244] Furthermore, the heat treatment process may further repair the oxide semiconductor 230b by the oxide semiconductor 230c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 230b.

[0245] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 7D ). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of the oxide semiconductor 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0246] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0247] After the heat treatment, microwave treatment is preferably performed in an atmosphere containing oxygen. By performing the microwave treatment, impurities such as hydrogen and carbon in the oxide semiconductor layer 230 can be reduced.

[0248] 7A to 7D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 7A to 7D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 7A to 7D , the crystallinity of the oxide semiconductor 230a and the oxide semiconductor 230c increases with the oxide semiconductor 230b, which has high crystallinity, serving as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a may be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c may be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. Note that the heat treatment has an assisting effect of increasing the crystallinity.

[0249] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0250] 7A to 7D can be successively performed without exposure to air by using the manufacturing apparatus of one embodiment of the present invention described in Embodiment 1. This can prevent impurities from being mixed into the oxide semiconductor layer 230. Furthermore, since impurities are prevented from interfering with crystal growth, the crystallinity can be improved.

[0251] It is preferable that a region having the CAAC structure is widely present throughout the entire oxide semiconductor layer 230 including the oxide semiconductors 230a and 230c. FIG. 8A shows the crystallized states of the oxide semiconductors 230a, 230b, and 230c. The region having the CAAC structure in the oxide semiconductor 230a is crystalline and connected to the region having the CAAC structure in the oxide semiconductor 230b. The region having the CAAC structure in the oxide semiconductor 230c is crystalline and connected to the region having the CAAC structure in the oxide semiconductor 230b. As a result, the boundary between the oxide semiconductors 230a and 230b may not be observed. Furthermore, the boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor layer 230 may be expressed as a single layer with no clearly observable interface. The oxide semiconductor layer 230 may be expressed as a single layer.

[0252] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Fig. 8B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Fig. 8C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Fig. 8D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0253] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0254] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0255] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 230, the boundaries between the stacked oxide semiconductors 230a, 230b, and 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0256] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0257] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0258] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0259] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. The oxide semiconductor 230b preferably contains, in addition to zinc, the element M. The inclusion of the element M in the oxide semiconductor 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b can be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0260] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition with an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout. Furthermore, it may have a composition with an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereabout.

[0261] The oxide semiconductor 230a and the oxide semiconductor 230c can be a metal oxide having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0262] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0263] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0264] Alternatively, for example, metal oxides having a higher Ga content than the oxide semiconductor 230b can be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c are preferably made of a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof, or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereof. Increasing the Ga content can sometimes make the band gaps of the oxide semiconductors 230a and 230c larger than that of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, which reduces trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof. This makes it possible to realize a buried-channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side is reduced, which suppresses light degradation of the transistor (e.g., negative-bias light degradation) and improves the reliability of the transistor.

[0265] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0266] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0267] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0268] The oxide semiconductors 230a and 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0269] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0270] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0271] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. Furthermore, it may be difficult to quantify element M, or element M may not be detected.

[0272] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0273] When the oxide semiconductor layer 230 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and is preferably 20 nm to 15 nm, 12 nm to 10 nm.

[0274] The oxide semiconductor 230b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 230b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0275] Alternatively, if the oxide semiconductor 230b can function as a crystal nucleus, the oxide semiconductor 230b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 230b exist discretely.

[0276] The oxide semiconductor 230a and the oxide semiconductor 230c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm.

[0277] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0278] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include a discrepancy in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.

[0279] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0280] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0281] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0282] Furthermore, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0283] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0284] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0285] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0286] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0287] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0288] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10１８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0289] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0290] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0291] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0292] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0293] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0294] The c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20 degrees or less.

[0295] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated by, for example, TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0296] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0297] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0298] After the oxide semiconductor layer 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0299] The oxide semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0300] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher. The c-axis orientation rate of the second region is 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0301] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 230 .

[0302] Alternatively, the layer thickness in each region may be, for example, approximately the same.

[0303] This embodiment mode can be combined with other embodiment modes as appropriate.

[0304] Embodiment 3 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0305] A semiconductor device of one embodiment of the present invention includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers.

[0306] The oxide semiconductor layer functions as a semiconductor layer of a transistor, the first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the fourth conductive layer functions as a first gate electrode of the transistor, the fourth insulating layer functions as a first gate insulating layer of the transistor, the second conductive layer functions as a second gate electrode, and the third insulating layer functions as a second gate insulating layer.

[0307] The first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer, and the third conductive layer is located on the second insulating layer, the first conductive layer has a first recess, and the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping the first recess. The third insulating layer is in contact with the first conductive layer and in contact with at least a side surface of the first insulating layer, a side surface of the second conductive layer, and a side surface of the second insulating layer within the first opening. The oxide semiconductor layer is in contact with a top surface of the third conductive layer and a bottom surface and side surfaces of the first recess and in contact with the third insulating layer within the first opening. The fourth insulating layer is located inside the oxide semiconductor layer within the first opening. The fourth conductive layer is located inside the first opening and inside the fourth insulating layer.

[0308] In a transistor according to one embodiment of the present invention, a first recess is provided in the first conductive layer. This allows the height of the lower surface of the fourth insulating layer and the height of the lower surface of the fourth conductive layer in the first opening to be lower than in a case where the first recess is not provided. Therefore, a gate electric field can be easily applied to the oxide semiconductor layer, thereby improving the electrical characteristics of the transistor. Here, the height of each surface can be determined, for example, based on the surface on which the transistor is formed.

[0309] In addition, in a cross-sectional view, the oxide semiconductor layer included in the transistor of one embodiment of the present invention has a region that overlaps with the second conductive layer with the third insulating layer interposed therebetween and with the fourth conductive layer with the fourth insulating layer interposed therebetween. One of the second conductive layer and the fourth conductive layer functions as a gate, and the other functions as a back gate. The back gate of the transistor makes it easy to control the threshold voltage and can suppress fluctuations in the threshold voltage, thereby improving the electrical characteristics and reliability of the transistor.

[0310] Furthermore, if the parasitic capacitance generated between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may become slow, and the frequency characteristics of a circuit using the transistor may be degraded.

[0311] Therefore, the transistor of one embodiment of the present invention preferably has a structure in which parasitic capacitance generated between the third conductive layer and the gate wiring is reduced, thereby enabling the transistor to operate at high speed and providing a semiconductor device with favorable electrical characteristics.

[0312] For example, the semiconductor device of one embodiment of the present invention preferably further includes a fifth conductive layer and a fifth insulating layer. In this case, the fifth insulating layer is preferably located over the fourth insulating layer and has a second opening that reaches the fourth conductive layer at a position overlapping with the first opening, and the fifth conductive layer is preferably in contact with the fourth conductive layer in the second opening.

[0313] The fifth conductive layer functions as a gate wiring. Since the fifth conductive layer is disposed on the fifth insulating layer, the physical distance between the third conductive layer and the gate wiring can be increased. Therefore, the parasitic capacitance generated between the third conductive layer and the gate wiring can be reduced.

[0314] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0315] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0316] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thicknesses of the first insulating layer, the second conductive layer, the second insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0317] When the channel length of a transistor is shortened, the transistor tends to be normally on due to the so-called short channel effect (SCE). On the other hand, as described above, the transistor of one embodiment of the present invention has a back gate. Therefore, by controlling the threshold voltage, a normally off transistor can be easily realized. That is, the transistor of one embodiment of the present invention can be said to have a high on-state current, be normally off, and be highly reliable even when miniaturized.

[0318] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, high integration and low power consumption of the memory device can be achieved.

[0319] The semiconductor device of this embodiment is preferably manufactured using the manufacturing apparatus described in Embodiment 1. This can prevent impurities from being mixed in during the manufacturing of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0320] <Structural Example 1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 9A1 to 9E and FIGS. 10A to 10C.

[0321] [Transistor 200] FIG. 9A1 is a plan view of a semiconductor device including a transistor 200. FIG. 9A2 is a plan view showing an example of an arrangement of a plurality of transistors 200. FIGS. 9B and 10A are cross-sectional views taken along dashed lines A1-A2 in FIG. 9A1. FIG. 10A corresponds to an example of an enlarged view of FIG. 9B and shows an example of the configuration of each layer in more detail. FIG. 9C is a cross-sectional view taken along dashed lines A3-A4 in FIG. 9A1. FIG. 9D is a cross-sectional view taken along dashed lines A5-A6 in FIGS. 9B and 9C. FIG. 9D can also be considered a cross-sectional view of the XY plane including the insulating layer 280a. FIG. 9E is a cross-sectional view taken along dashed lines A7-A8 in FIGS. 9B and 9C. FIG. 9E can also be considered a cross-sectional view of the XY plane including the conductive layer 255. Note that some elements are omitted from the plan view of FIG. 9A1 for clarity. Some elements may also be omitted from the subsequent plan views.

[0322] 9A1, 9B to 9E, and 10A includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, and an insulating layer 280b over the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0323] The transistor 200 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 255 on the insulating layer 280a, a conductive layer 240a on the insulating layer 280b, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, a conductive layer 265a on the insulating layer 250, and a conductive layer 265b on the conductive layer 265a.

[0324] Note that, hereinafter, the conductive layers 220a and 220b may be collectively referred to as the conductive layers 220. Furthermore, the conductive layers 240a and 240b may be collectively referred to as the conductive layers 240. Furthermore, the conductive layers 265a and 265b may be collectively referred to as the conductive layers 265.

[0325] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 265 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer. The conductive layer 265 also functions as a gate wiring.

[0326] It is preferable that the conductive layer 265 function as a gate electrode and the conductive layer 255 function as a back gate electrode. In this case, the insulating layer 250 functions as a gate insulating layer and the insulating layer 235 functions as a back gate insulating layer. Note that the conductive layer 265 may function as a back gate electrode and the conductive layer 265 may function as a gate electrode.

[0327] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200. One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0328] As shown in FIGS. 9B and 9C, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0329] The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 includes a recess, and the side and bottom surfaces of the recess correspond to the side and bottom surfaces of the recess in the conductive layer 220b. Specifically, the conductive layer 220b includes a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. Therefore, in FIG. 9B and other figures, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the oxide semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280a and other layers facing the opening 290. Hereinafter, the first recess and the second recess may be collectively referred to as recess.

[0330] 9B and 9C , the opening 290 overlaps with the recess in the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the recess in the conductive layer 220b, and the sidewall of the opening 290 includes the side surface of the recess in the conductive layer 220b, the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0331] The opening 290 includes an opening in the insulating layer 280a, an opening in the conductive layer 255, an opening in the insulating layer 280b, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, the opening in the region where the insulating layer 280a overlaps with the conductive layer 220a is part of the opening 290, the opening in the region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the insulating layer 280b overlaps with the conductive layer 220a is another part of the opening 290, the opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and the opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the opening 290 in a plan view may differ depending on the layer. When the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0332] At least some of the components of the transistor 200 are disposed in the opening 290. Specifically, at least some of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265 are disposed in the opening 290.

[0333] The insulating layer 235 has at least a region located between the oxide semiconductor layer 230 and the conductive layer 255. The oxide semiconductor layer 230 is in contact with the insulating layer 235 in the opening 290.

[0334] 9B and other figures, the insulating layer 235 is in contact with the bottom and side surfaces of the recesses (specifically, second recesses) of the conductive layer 220, and is also in contact with the side surfaces of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b within the opening 290. The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses (specifically, first recesses) of the conductive layer 220, the insulating layer 235, and the top surface of the conductive layer 240b. The insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 265a is located inside the insulating layer 250 within the opening 290.

[0335] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. Furthermore, the portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom and sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. Then, the conductive layer 265a is provided so as to fill at least a part of the recess of the insulating layer 250 that reflects the shape of the opening 290.

[0336] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 290. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 265 in the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller. Figures 9B and 9C show an example in which the conductive layer 265 has a two-layer structure, in which only the conductive layer 265a is provided in the opening 290, and the conductive layer 265b over the conductive layer 265a is provided so as to overlap with the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, both the conductive layer 265a and the conductive layer 265b may be located in the opening 290.

[0337] By providing a recess in the conductive layer 220b at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 265a in the opening 290 can be lower than the height of the top surface of the conductive layer 220b that is in contact with the insulating layer 280a, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which the transistor or semiconductor device is provided may be used as the reference.

[0338] 10A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220b that contacts the insulating layer 280a is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the contact area between the side surface of the conductive layer 220b and the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 within the opening 290.

[0339] 10A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 265a, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200. Furthermore, the gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220b, thereby increasing the on-state current of the transistor 200. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 265a in the opening 290.

[0340] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses of the conductive layer 220b and the top surface of the conductive layer 240b. The recesses in the conductive layer 220b can increase the area in which the oxide semiconductor layer 230 is in contact with the conductive layer 220b. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced.

[0341] The conductive layer 220b is preferably formed using a conductive material containing oxygen, which can reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b.

[0342] When the conductive layer 220 and the conductive layer 240 have a stacked structure, it is preferable to use a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, because this can reduce contact resistance with the oxide semiconductor layer 230. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240b, for example.

[0343] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is used for a layer of the stacked structure that is closest to a channel formation region, and the contact resistance with the oxide semiconductor layer 230 is reduced, thereby shortening the current path between the source and the drain, and thereby increasing the on-state current of the transistor. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0344] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an oxide conductor).

[0345] 9B illustrates a structure in which the end portions of the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 are aligned outside the opening 290. As described in a manufacturing method example below, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing the semiconductor device can be reduced. Note that the present invention is not limited to this. For example, in the X direction or the Y direction, any one of the end portions of the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b may be located inside or outside the other end portions.

[0346] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. Furthermore, the conductive layer 240 is preferably not located inside the opening 290 of the insulating layer 280b or the like. That is, the conductive layer 240 preferably does not have a region in contact with the side surface of the insulating layer 280b in the opening 290. With this structure, the opening 290 can be formed simultaneously in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a. Furthermore, if the side surfaces of the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a are aligned in the opening 290, the thickness distribution of the insulating layer 235, the oxide semiconductor layer 230, and the like provided inside the opening 290 can be made uniform. Furthermore, the insulating layer 235, the oxide semiconductor layer 230, and the like can be prevented from being separated by a step or the like between the conductive layer 240 and the insulating layer 280b.

[0347] 9B and 9C show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 are flush (or may be said to be aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280b in the opening 290 may differ from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280b in the opening 290. With such a configuration, the coverage of the oxide semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 280a and insulating layer 280b each have a stacked structure, the inclination of the side surface of each layer may be different within opening 290. Similarly, when conductive layer 240 has a stacked structure, the inclination of the side surface of each layer within opening 290 may be different.

[0348] The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0349] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0350] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0351] As described above, the oxide semiconductor layer 230 is provided inside the opening 290. In addition, the transistor 200 has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located above, and thus, a current flows vertically. That is, a channel is formed along the side surface of the opening 290.

[0352] 9D and 9E , the positional relationship of each layer in the opening 290 will be described. The insulating layer 235 is in contact with the outer surface of the oxide semiconductor layer 230. The conductive layer 255 surrounds the entire periphery of the oxide semiconductor layer 230 with the insulating layer 235 interposed therebetween. The insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The oxide semiconductor layer 230 surrounds the entire periphery of the conductive layer 265a with the insulating layer 250 interposed therebetween. Thus, the channel formation region of the transistor 200 can be formed over the entire outer surface of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235). Note that FIG. 9E can also be considered a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0353] The channel length of the transistor 200 can be considered as the distance between the source region and the drain region, i.e., the channel length of the transistor 200 is determined by the thicknesses of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, and the like on the conductive layer 220.

[0354] Since the transistor 200 includes the conductive layer 255 that functions as a back gate, the threshold voltage of the transistor 200 can be controlled by the potential applied to the conductive layer 255. In this case, a portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween is most susceptible to the influence of the conductive layer 255. Therefore, in FIG. 10A , the oxide semiconductor layer 230 is shown divided into three regions: a region 230n+, a region 230n−, and a region 230i. The region 230i corresponds to the portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween.

[0355] The region 230n+ is formed in a region in contact with the conductive layer 240b or the conductive layer 220b and in the vicinity thereof in the oxide semiconductor layer 230. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0356] The region 230i is a region in the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 265a with the insulating layer 250 interposed therebetween, and can be referred to as a channel formation region. The channel formation region is preferably controlled to be i-type (intrinsic) or substantially i-type by a potential applied to the conductive layer 255.

[0357] The region 230n- is preferably a region having a higher resistance than the region 230n+ and a lower resistance than the region 230i. If a high-resistance region exists between the region 230i and the region 230n+, the on-current of the transistor 200 may decrease. By making the region 230n- a relatively low-resistance region, the on-current of the transistor 200 may be increased. Note that the region 230n- may also function as a channel formation region.

[0358] As described above, when the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be referred to as length L1. On the other hand, since the region 230n- has a lower resistance than the region 230i, the channel formation region of the transistor 200 can also be regarded as the region 230i that is controlled by the conductive layer 255 to become a high-resistance region. In this case, the channel length of the transistor 200 can be regarded as length L0 of the region 230i, which is shorter than length L1. In this case, length L0 can also be referred to as the effective channel length of the transistor 200.

[0359] When the resistance of the region 230n− is low and the effective channel length of the transistor is short, the transistor tends to be normally on. On the other hand, the transistor of one embodiment of the present invention has a back gate. By supplying a potential equal to or lower than the source potential or a potential equal to or lower than 0 V (preferably a negative potential) to the back gate, the threshold voltage of the transistor can be shifted in the positive direction, thereby making the transistor normally off. As a result, the transistor of one embodiment of the present invention can have both a large on-state current and a normally off state.

[0360] In the transistor of one embodiment of the present invention, either the conductive layer 255 or the conductive layer 265 may be used as a gate or a back gate. In particular, the transistor of one embodiment of the present invention may have a structure in which the conductive layer 265 is used as a gate and the conductive layer 255 is used as a back gate. When the conductive layer 265, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate, a gate electric field can be applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor.

[0361] In a planar transistor, the channel length is set by the exposure limit of photolithography. However, in one embodiment of the present invention, the channel length can be set by the film thicknesses of the insulating layers 280a and 280b. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0362] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0363] 9A2 shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 9A2 shows an example in which 5×5 transistors are arranged in the X and Y directions. As shown in FIG. 9A2, the transistor 200 is provided at the intersection of a conductive layer 265 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 9A2, the diameter of the opening 290 can be made smaller than the width of the short side of the conductive layer 240, the width of the short side of the conductive layer 255, and the width of the short side of the conductive layer 265. Thus, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0364] 9D , the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are arranged concentrically. Therefore, the side surface of the conductive layer 265a located in the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region in a plan view. In this case, for example, the channel width of the transistor 200 is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 9B to 9E , the width D of the opening 290 is shown, and FIG. 9E shows the channel width W of the transistor 200. Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0365] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 255 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 255, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b on the opening 290 side may be used as the width D. Furthermore, the width of the opening 290 at the highest position in the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D.

[0366] When the opening 290 is formed by photolithography, the width D of the opening 290 is set by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 has a circular shape in a plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0367] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0368] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230 and the distance between the conductive layer 265a and the oxide semiconductor layer 230 become approximately uniform, and therefore, a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0369] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 9A1 and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0370] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. FIGS. 9B and 9C show an example in which the conductive layer 220a has a single-layer structure. FIG. 10A shows an example in which the conductive layer 220a has a stacked-layer structure.

[0371] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0372] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0373] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0374] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, refer to the description in Embodiment 2. For a method for manufacturing the oxide semiconductor layer 230, refer to the descriptions in Embodiments 1 and 2. Detailed description will be omitted here.

[0375] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0376] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0377] The semiconductor layer of a transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0378] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0379] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 235, insulating layer 280a, insulating layer 280b, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0380] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, materials can be selected depending on the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0381] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0382] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0383] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0384] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0385] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0386] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal nitride oxides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0387] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0388] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0389] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0390] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0391] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0392] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0393] Specifically, examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0394] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0395] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0396] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0397] A barrier insulating layer against hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0398] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0399] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0400] For example, it is preferable to use a silicon nitride film as the insulating layer 210 .

[0401] The insulating layer 280a and the insulating layer 280b each preferably have the aforementioned barrier insulating layer against hydrogen. The insulating layer 280a and the insulating layer 280b are provided so as to surround the oxide semiconductor layer 230. The insulating layer 280a and the insulating layer 280b provided on the outer side of the oxide semiconductor layer 230 have a barrier property against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230. For example, the insulating layer 280a and the insulating layer 280b each preferably have one or both of an aluminum oxide film and a silicon nitride film.

[0402] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280 a and the insulating layer 280 b, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, which can prevent excessive oxygen vacancies from being formed in the oxide semiconductor layer 230.

[0403] Furthermore, using silicon nitride for the insulating layers 280a and 280b can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Therefore, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, which can improve the reliability of the transistor 200.

[0404] The insulating layer 280a and the insulating layer 280b preferably include the above-described oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.

[0405] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentrations in the insulating layers 280a and 280b can be reduced. By depositing at least some of the layers that constitute the insulating layers 280a and 280b in this manner, oxygen can be supplied from the insulating layers 280a and 280b to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0406] The concentrations of impurities such as water and hydrogen in the insulating layers 280a and 280b are preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0407] Since the thickness of the insulating layer 280a and the insulating layer 280b on the conductive layer 220 affects the channel length of the transistor 200A, the thickness of the insulating layer 280a and the insulating layer 280b is set appropriately according to the design value of the channel length of the transistor 200A.

[0408] For example, the insulating layers 280a and 280b preferably have a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film. Alternatively, the insulating layers 280a and 280b preferably have a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order. For example, the insulating layers 280a and 280b preferably have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order.

[0409] The insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0410] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0411] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0412] When the gate insulating layer has a stacked-layer structure, a layer in contact with the oxide semiconductor layer 230 preferably has a function of capturing and fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the oxide semiconductor layer 230. In addition, the layer preferably has an amorphous structure.

[0413] By making the layer amorphous, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 250 uniform, and it is possible to reduce portions with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer 250. It is also possible to make the film thickness distribution of the film provided on the insulating layer 250 uniform.

[0414] Furthermore, by suppressing the formation of grain boundaries in the layer, leakage current due to defect levels in the grain boundaries can be reduced, and the insulating layer 250 can function as an insulating film with low leakage current.

[0415] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0416] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0417] The above-described barrier insulating layer against hydrogen is preferably used as the insulating layer 250. By using a barrier insulating layer against hydrogen for the insulating layer 250, diffusion of impurities contained in the conductive layer 265 into the oxide semiconductor layer 230 can be suppressed. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Furthermore, the insulating layer 250 may include an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0418] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0419] Additionally, insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0420] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0421] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0422] The use of a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 that is in contact with the conductive layer 265 can suppress oxidation of the conductive layer 265. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 265, which can suppress formation of oxygen vacancies in the oxide semiconductor layer 230.

[0423] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0424] The layer of the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280b. The layer has oxygen barrier properties, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0425] Each layer constituting the insulating layer 250 is preferably a thin film. For example, by setting the thickness of each insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0426] The thickness of each layer constituting the insulating layer 250 is preferably more than 0 nm and not more than 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0427] The insulating layer 250 preferably has a three-layer structure in which, from the oxide semiconductor layer 230 side, a first insulating layer containing a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and an insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant for the first insulating layer. The first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using oxide for the first insulating layer, oxygen can be supplied from the first insulating layer to the oxide semiconductor layer 230. Furthermore, by providing a third insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 265, thereby preventing oxidation of the conductive layer 265. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230 can be prevented.

[0428] 10B and 10C show examples of enlarged views of the insulating layer 250 shown in Fig. 10A and the surrounding area P. Fig. 10B shows an example in which the insulating layer 250 has a four-layer structure, and Fig. 10C shows an example in which the insulating layer 250 has a three-layer structure.

[0429] 10B , the insulating layer 250 preferably has a four-layer structure in which, from the oxide semiconductor layer 230 side, a fourth insulating layer (insulating layer 250d) having a barrier property against oxygen, a first insulating layer (insulating layer 250a) made of a material with a low dielectric constant, a second insulating layer (insulating layer 250b) having a function of capturing or fixing hydrogen, and a third insulating layer (insulating layer 250c) having a barrier property against hydrogen and oxygen are stacked in this order. The first to third insulating layers can have a structure similar to that of the layers used in the above-described three-layer structure. The insulating layer 250d is in contact with the oxide semiconductor layer 230. The insulating layer 250d has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. For example, aluminum oxide may be used as the insulating layer 250d. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable for the insulating layer 250d in contact with the oxide semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0430] Typically, the thicknesses of the insulating layer 250d, the insulating layer 250a, the insulating layer 250b, and the insulating layer 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. Such a configuration allows the transistor to have good electrical characteristics even when miniaturized or highly integrated. The thicknesses of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d are not limited to the above. For example, the thicknesses of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d are preferably greater than 0 nm and less than or equal to 10 nm. Furthermore, any one or more of the insulating layer 250a, the insulating layer 250b, the insulating layer 250c, and the insulating layer 250d may not be provided.

[0431] 10C , it is preferable to use a three-layer structure as the insulating layer 250, in which a fourth insulating layer (insulating layer 250d) having a barrier property against oxygen, a first insulating layer (insulating layer 250a) made of a material with a low dielectric constant, and a second insulating layer (insulating layer 250b) having a function of capturing or fixing hydrogen are stacked in this order from the oxide semiconductor layer 230 side. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0432] Typically, the thicknesses of the insulating layer 250d, the insulating layer 250a, and the insulating layer 250b are 1 nm, 2 nm, and 2 nm, respectively. With such a configuration, the transistor can have good electrical characteristics even when miniaturized or highly integrated. As described above, the thicknesses of the insulating layer 250a, the insulating layer 250b, and the insulating layer 250d are not limited to the above values.

[0433] 10B or 10C is preferably manufactured using the manufacturing apparatus described in Embodiment 1. By successively forming the layers constituting the insulating layer 250 without exposure to the air, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the conductive layers 265a and 265b are preferably formed using the same manufacturing apparatus.

[0434] Note that the insulating layer 210 may be an insulating layer having the above-described function of capturing or fixing hydrogen. This allows hydrogen in the oxide semiconductor layer 230 to diffuse into the insulating layer 210 through the conductive layers 220a and 220b, and the hydrogen can be captured or fixed. This allows the hydrogen concentration in the oxide semiconductor layer 230 to be reduced. For example, the insulating layer 210 may have a two-layer structure including a silicon nitride film and a hafnium silicate film on the silicon nitride film.

[0435] The insulating layer 235 may also be referred to as a sidewall, a sidewall insulating layer, or a sidewall protective layer.

[0436] The insulating layer 235 preferably includes an insulating layer having a region containing oxygen that is released by heating, thereby enabling oxygen to be supplied from the insulating layer 235 to the oxide semiconductor layer 230. For example, the insulating layer 235 is preferably made of silicon oxide or silicon oxynitride.

[0437] The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0438] Furthermore, the insulating layer 235 may be made of the above-mentioned material that can have ferroelectricity.

[0439] For example, the insulating layer 235 can have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, for example, it is preferable to provide a silicon oxide film on the oxide semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side. This makes it possible to efficiently supply oxygen to the oxide semiconductor layer 230 and to suppress the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230. Alternatively, a silicon nitride film may be provided on the oxide semiconductor layer 230 side and a silicon oxide film may be provided on the conductive layer 255 side.

[0440] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 265, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0441] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0442] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0443] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0444] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0445] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0446] By using a conductive material containing oxygen for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0447] 10A illustrates an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. In this case, for example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 220a1, a highly conductive material as the conductive layer 220a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220b. Specifically, for example, it is preferable to use titanium nitride as the conductive layer 220a1, tungsten as the conductive layer 220a2, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) as the conductive layer 220b. In this case, the titanium nitride is in contact with the insulating layer 210, and the oxide conductor is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the oxide semiconductor layer 230, and therefore the current path between the source and drain can be shortened, thereby increasing the on-state current of the transistor. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0448] 10A shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240b and a material having higher conductivity than the conductive layer 240b for the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 240b and tungsten for the conductive layer 240a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240a.

[0449] Of the conductive layer 240, the layer that is mainly in contact with the oxide semiconductor layer 230 is the conductive layer 240b. Using an oxide conductor for the conductive layer 240b is preferable because contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, using a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240 is preferable because the conductivity of the conductive layer 240 can be increased.

[0450] Note that a conductive material containing oxygen can be used for the conductive layer 240a, and a material having higher conductivity than that of the conductive layer 240a can be used for the conductive layer 240b. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0451] The conductive layer 255 and the conductive layer 265 are preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 255 and the conductive layer 265 are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255 and the conductive layer 265.

[0452] The conductive layer 265 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0453] 10A shows an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b on the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0454] The conductive layer 265 may also have a stacked structure of three or more layers, such as a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0455] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0456] The conductive layer 255 is preferably made of, for example, tungsten or tantalum nitride.

[0457] [Substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0458] <Structural Example 2 of Semiconductor Device> A structure of a semiconductor device of another embodiment of the present invention will be described with reference to FIGS.

[0459] [Transistor 200A] FIG. 11A is a cross-sectional view of a semiconductor device having a transistor 200A.

[0460] FIG. 11A shows an example in which the sidewall of the opening 290 has a tapered shape. Tapering the sidewall of the opening 290 improves coverage of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the like, and reduces defects such as voids. When the sidewall of the opening 290 has a tapered shape, for example, the taper angle θ280 of the side surface of the insulating layer 280a in the opening 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle θ280 of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle θ280 of 45 degrees or more, or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because it improves coverage of the film formed in the opening 290.

[0461] Alternatively, for example, the sidewall of the opening 290 may have an inverse tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280a in the opening 290 may be greater than 90 degrees.

[0462] [Transistors 200B, 200C, and 200D] Fig. 11B is a cross-sectional view of a semiconductor device including transistor 200B. Fig. 12A is a cross-sectional view of a semiconductor device including transistor 200C. Fig. 12B is a cross-sectional view of a semiconductor device including transistor 200D.

[0463] The transistors 200B, 200C, and 200D differ from the transistor 200 mainly in that the insulating layer 235 has a two-layer structure and that the transistors 200B, 200C, and 200D each have an insulating layer 280c and an insulating layer 280d.

[0464] The transistors 200B, 200C, and 200D each include an insulating layer 235a and an insulating layer 235b over the insulating layer 235a. The insulating layer 235a and the insulating layer 235b function as second gate insulating layers of the transistors.

[0465] One of the insulating layer 235a and the insulating layer 235b preferably includes an insulating layer having a region containing oxygen that is released by heating. The other of the insulating layer 235a and the insulating layer 235b preferably includes a barrier insulating layer against hydrogen.

[0466] This allows oxygen to be supplied from the insulating layer 235a or the insulating layer 235b to the oxide semiconductor layer 230, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0467] For example, it is preferable to use a silicon nitride film for the insulating layer 235a and a silicon oxide film for the insulating layer 235b, or to use a silicon oxide film for the insulating layer 235a and a silicon nitride film for the insulating layer 235b.

[0468] In the transistor 200B, an insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, and an insulating layer 235b is provided on the insulating layer 235a. For example, an insulating film that will become the insulating layer 235a and an insulating film that will become the insulating layer 235b are stacked, and then the two insulating films are processed to form the insulating layer 235a and the insulating layer 235b having the structure shown in FIG. 11B. Therefore, it can be said that this structure can be manufactured relatively easily.

[0469] The insulating layers 235a and 235b are preferably manufactured using the manufacturing apparatus described in Embodiment 1. When a plurality of layers functioning as back-gate insulating layers are successively formed without exposure to air, the electrical characteristics and reliability of the transistor 200B can be improved.

[0470] In transistor 200C, an example is shown in which insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of conductive layer 220b, and insulating layer 235b is located inside insulating layer 235a within the opening and is provided in contact with the bottom of the recess of conductive layer 220b.

[0471] In the transistor 200D, the conductive layer 220b has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. The third recess is provided in the conductive layer 220b when forming the opening 290, and then the second recess is provided in the conductive layer 220b when processing the insulating layer 235a, and then the first recess is provided in the conductive layer 220b when processing the insulating layer 235b. Therefore, in FIG. 12B , the side of the first recess is aligned with the surface of insulating layer 235b facing the oxide semiconductor layer 230, the side of the second recess is aligned with the surface of insulating layer 235b of insulating layer 235a, and the side of the third recess is aligned with the side of insulating layer 280a or the like facing the opening 290.

[0472] In the transistor 200D, an example is shown in which an insulating layer 235a is provided in contact with the bottom and side surfaces of the third recess of the conductive layer 220b, and an insulating layer 235b is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220b.

[0473] 12A or 12B can be formed by providing the insulating layer 235a on the sidewall of the opening and then forming and processing an insulating film to be the insulating layer 235b. Compared to the transistor 200B, the region where the insulating layer 235a is in contact with the oxide semiconductor layer 230 is reduced, and a configuration in which the insulating layer 235b is in contact with the oxide semiconductor layer 230 can be realized.

[0474] In the transistors 200B, 200C, and 200D, the insulating layers 280a and 280b are closer to the channel formation region of the oxide semiconductor layer 230 than the insulating layers 280c and 280d. By using an insulating layer containing oxygen as the insulating layers 280a and 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0475] The insulating layer 280a and the insulating layer 280b each preferably have a region with a higher oxygen content than at least one of the insulating layer 280c and the insulating layer 280d. The higher oxygen content of the insulating layer 280a and the insulating layer 280b makes it easier to form an i-type region in the oxide semiconductor layer 230.

[0476] It is more preferable that the insulating layers 280a and 280b each be a film that releases oxygen when heated. The insulating layers 280a and 280b release oxygen due to heat applied during the manufacturing process of the transistor, and thus oxygen can be supplied to the oxide semiconductor layer 230. By supplying oxygen from the insulating layers 280a and 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V in the oxide semiconductor layer 230 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0477] To improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0478] In particular, when the channel length of a transistor is short, oxygen vacancies in the channel formation region and V Ｏ The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230 and then optimizing the amount of oxygen supplied to the oxide semiconductor layer 230, a transistor with a short channel length, favorable electrical characteristics, and high reliability can be realized.

[0479] The insulating layers 280a and 280b are preferably formed by a deposition method such as a sputtering method or a plasma-enhanced CVD (PECVD) method. In particular, when a sputtering method is used, hydrogen is not used as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the oxide semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor can be stabilized.

[0480] To increase the amount of oxygen supplied to the oxide semiconductor layer 230, for example, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed after the insulating layer 280a or the insulating layer 280b is formed. Alternatively, oxygen may be supplied by forming an oxide film on the top surface of the insulating layer 280a or the insulating layer 280b by a sputtering method in an oxygen atmosphere. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 280a or the insulating layer 280b, and the amount of oxygen supplied to the oxide semiconductor layer 230 can be increased.

[0481] An insulating layer suitable for the insulating layer 280a and the insulating layer 280b is preferably used for the insulating layer 235 (particularly the insulating layer 235b in contact with the oxide semiconductor layer 230). This allows oxygen to be supplied to the oxide semiconductor layer 230 more efficiently.

[0482] Furthermore, it is preferable to use a material with a low dielectric constant for the insulating layer 280a and the insulating layer 280b, which can reduce parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 280a and the insulating layer 280b.

[0483] The insulating layers 280c and 280d are preferably barrier insulating layers against oxygen, which can prevent oxidation of the conductive layers 220 and 240 and prevent the resistance from increasing.

[0484] The insulating layer 280c and the insulating layer 280d may each be a barrier insulating layer against hydrogen. Such a structure is preferable because it can suppress diffusion of impurities such as hydrogen into the oxide semiconductor layer 230.

[0485] In the transistors 200B, 200C, and 200D, it is preferable that the insulating layers 280a and 280b be formed using silicon oxide films, and the insulating layers 280c and 280d be formed using silicon nitride films or aluminum oxide films.

[0486] The insulating layers 280c and 280a are preferably manufactured using the manufacturing apparatus described in Embodiment 1. When the insulating layers 280c and 280a are successively formed without exposure to air, the electrical characteristics and reliability of the transistor can be improved.

[0487] Similarly, the insulating layers 280b and 280d are preferably formed using the manufacturing apparatus described in Embodiment 1. By successively forming the insulating layers 280b and 280d without exposure to the air, the electrical characteristics and reliability of the transistor can be improved.

[0488] There is no particular limitation on the number of layers that constitute the insulating layer 235. The insulating layer 235 can be a single layer, two layers, or three or more layers.

[0489] When the insulating layer 235 has three or more layers, it preferably includes at least one insulating layer having a region containing oxygen that is released by heating.When the insulating layer 235 has three or more layers, it preferably includes at least one barrier insulating layer against hydrogen.

[0490] This allows oxygen to be supplied to the oxide semiconductor layer 230 from at least one of the layers constituting the insulating layer 235, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0491] For example, the insulating layer 235 preferably has a three-layer structure in which a silicon oxide film is sandwiched between a pair of silicon nitride films, or a three-layer structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films.

[0492] [Transistor 200E] FIG. 13A is a cross-sectional view of a semiconductor device having a transistor 200E.

[0493] Transistor 200E differs from transistor 200 primarily in that only one recess is provided in conductive layer 220b.

[0494] A recess may be formed in the conductive layer 220b in one or both of the steps of forming the opening 290 and forming the insulating layer 235. The transistor 200 illustrates an example in which a recess is formed in the conductive layer 220b in both steps, whereas the transistor 200E illustrates an example in which a recess is not formed in the conductive layer 220b in the step of forming the opening 290, but is formed in the step of forming the insulating layer 235.

[0495] In the transistor 200E, the insulating layer 235 is in contact with the side surfaces of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the top surface of the conductive layer 220b in the opening 290. The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recess of the conductive layer 220b.

[0496] When a recess is formed in the conductive layer 220b in at least one of the steps of forming the opening 290 and forming the insulating layer 235, the height of the bottom surface of the conductive layer 265a in the opening 290 can be reduced, making it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200.

[0497] When a recess is formed in the conductive layer 220b in the process of forming the insulating layer 235, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess in the conductive layer 220b, the contact area between the oxide semiconductor layer 230 and the conductive layer 220b is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced, which is preferable.

[0498] [Transistor 200F] FIG. 13B is a cross-sectional view of a semiconductor device having a transistor 200F.

[0499] The transistor 200F differs from the transistor 200 mainly in that the insulating layer 235 does not cover the side surfaces of the conductive layer 240b.

[0500] 13B is in contact with the bottom and side surfaces of the recess of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280a, the conductive layer 255, and the insulating layer 280b within the opening 290. The insulating layer 235 is in contact with a portion of the side surface of the conductive layer 240a, but is not in contact with the side surface of the conductive layer 240b. The insulating layer 235 functions as a second gate insulating layer. Therefore, the insulating layer 235 covers at least the entire side surface of the conductive layer 255 within the opening 290, electrically insulating the conductive layer 255 from the oxide semiconductor layer 230. The insulating layer 235 may be in contact with one or more of the side surfaces of the insulating layer 280a, the side surfaces of the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b within the opening 290, or may cover a portion or all of each side surface.

[0501] When at least a portion of the side surface of the conductive layer 240b is not covered with the insulating layer 235, that portion is in contact with the oxide semiconductor layer 230. This makes it possible to increase the area of ​​the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable. Similarly, when the insulating layer 235 does not cover the side surface of the conductive layer 240b and also does not cover at least a portion of the side surface of the conductive layer 240a, that portion is in contact with the oxide semiconductor layer 230. This makes it possible to increase the area of ​​the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable.

[0502] [Transistor 200G, Transistor 200H] Fig. 13C is a cross-sectional view of a semiconductor device including transistor 200G. Fig. 13D is a cross-sectional view of a semiconductor device including transistor 200H.

[0503] The transistors 200G and 200H differ from the transistor 200 mainly in that they include an insulating layer 280c, an insulating layer 280d, an insulating layer 280e, and an insulating layer 280f, respectively.

[0504] In the transistors 200G and 200H, it is preferable to use silicon oxide films as the insulating layers 280a and 280b, and to use silicon nitride films or aluminum oxide films as the insulating layers 280c, 280d, 280e, and 280f. By providing a barrier insulating layer against hydrogen in the insulating layer 280c in contact with the top surface of the conductive layer 220, the insulating layer 280d in contact with the bottom surface of the conductive layer 240, the insulating layer 280e in contact with the bottom surface of the conductive layer 255, and the insulating layer 280f in contact with the top surface of the conductive layer 255, it is possible to suppress diffusion of impurities such as hydrogen into the oxide semiconductor layer 230.

[0505] Furthermore, for example, when tungsten, tantalum nitride, or the like is used for the conductive layer 255, the conductive layer 255 may be oxidized if an oxide insulating layer is used as an insulating layer in contact with the conductive layer 255. Therefore, it is preferable to use silicon nitride films as the insulating layers 280e and 280f above and below the conductive layer 255. This makes it possible to suppress oxidation of the conductive layer 255 and to provide a barrier insulating layer against hydrogen.

[0506] The transistor 200G can be manufactured by forming the insulating layer 280e after performing planarization treatment after forming the insulating layer 280a to planarize the top surface of the insulating layer 280a. The insulating layers 280c and 280a are preferably manufactured using the manufacturing apparatus described in Embodiment 1. By successively forming the insulating layers 280c and 280a without exposure to the air, the electrical characteristics and reliability of the transistor 200G can be improved.

[0507] The transistor 200H can be manufactured by performing planarization treatment after the insulating layer 280e is formed to planarize the top surface of the insulating layer 280e. The insulating layers 280c, 280a, and 280e are preferably manufactured using the manufacturing apparatus described in Embodiment 1. By successively forming the insulating layers 280c, 280a, and 280e without exposure to the air, the electrical characteristics and reliability of the transistor 200H can be improved.

[0508] In the transistors 200G and 200H, the insulating layers 280f, 280b, and 280d are preferably formed using the manufacturing apparatus described in Embodiment 1. By successively forming the insulating layers 280f, 280b, and 280d without exposure to air, the electrical characteristics and reliability of the transistors can be improved.

[0509] [Transistors 200I and 200J] Fig. 14A is a cross-sectional view of a semiconductor device including a transistor 200I. Fig. 14B is a cross-sectional view of a semiconductor device including a transistor 200J.

[0510] The transistor 200I differs from the transistor 200 mainly in that the transistor 200I does not include the conductive layer 265a and the conductive layer 265b but includes the conductive layer 265 having a single-layer structure.

[0511] Like the conductive layer 265 of the transistor 2001, a conductive layer functioning as a gate electrode may have a single-layer structure. The conductive layer 265 is preferably provided so as to fill the opening 290.

[0512] Transistor 200J differs from transistor 200 primarily in that both conductive layer 265a and conductive layer 265b are located within opening 290.

[0513] In the transistor 200J, the conductive layer 265b is located in the opening 290. As described above, depending on the diameter of the opening 290 and the thickness of the conductive layer 265a, not only the conductive layer 265a but also the conductive layer 265b may be provided in the opening 290.

[0514] [Transistors 200K and 200L] Fig. 14C is a cross-sectional view of a semiconductor device including a transistor 200K. Fig. 14D is a cross-sectional view of a semiconductor device including a transistor 200L.

[0515] The transistor 200K differs from the transistor 200 mainly in that it does not include the insulating layer 250, the conductive layer 265a, and the conductive layer 265b. The transistor 200L has a structure in which the conductive layer 255 functioning as a gate electrode surrounds the channel formation region of the oxide semiconductor layer 230, and thus can be said to be a transistor with a gate-all-around (GAA) structure. An insulating layer 283 over the oxide semiconductor layer 230 and an insulating layer 285 over the insulating layer 283 are located in the opening 290. The insulating layer 283 can be formed using any of the insulating materials described in the above [Insulating Layer] as a single layer or a stacked layer, and in particular, it is preferable to use a barrier insulating layer against hydrogen.

[0516] The transistor 200K differs mainly from the transistor 200 in that the transistor 200K does not include the conductive layer 255 and the insulating layer 235. The transistor 200L has a structure in which the oxide semiconductor layer 230 surrounds the conductive layer 265a functioning as a gate electrode, and thus can be said to be a transistor with a channel-all-around (CAA) structure.

[0517] As described above, the semiconductor device of one embodiment of the present invention may include a transistor with a single gate structure, that is, a transistor without a back gate.

[0518] [Transistor 203] FIG. 15A is a plan view of a semiconductor device including a transistor 203. FIG. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 15A. FIG. 15C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 15A. FIG. 15D is a cross-sectional view taken along dashed dotted line A5-A6 in FIGS. 15B and 15C. FIG. 15E is a cross-sectional view taken along dashed dotted line A7-A8 in FIGS. 15B and 15C. Note that FIGS. 15D and 15E have the same configuration as FIGS. 9D and 9E except that they do not have conductive layer 265a but have conductive layer 260, and therefore detailed description thereof will be omitted.

[0519] 15A to 15E includes an insulating layer 210 over a substrate (not shown), a transistor 203 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, an insulating layer 280b over the insulating layer 280a, an insulating layer 285 over the insulating layer 250, a conductive layer 265a over the insulating layer 285, and a conductive layer 265b over the conductive layer 265a. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, and the insulating layer 285 function as interlayer films.

[0520] The transistor 203 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 255 over the insulating layer 280a, a conductive layer 240a over the insulating layer 280b, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the conductive layer 265a and the conductive layer 265b may each be considered as components of the transistor 203.

[0521] The conductive layer 260 functions as a gate electrode (first gate electrode) of the transistor 203, and the conductive layers 265a and 265b function as gate wirings. The conductive layer 260 can be formed using any of the materials that can be used for the conductive layer 265.

[0522] In the transistor 203, the stacked structure from the conductive layer 220a to the insulating layer 250 is similar to that of the transistor 200, and therefore detailed description thereof will be omitted.

[0523] 15B and 15C , the transistor 203 includes a conductive layer 260 over the insulating layer 250. The conductive layer 260 is provided to fill the opening 290. The conductive layer 260 of the transistor 203 can also be considered a conductive layer obtained by modifying the shape of the conductive layer 265a of the transistor 200. The conductive layer 260 does not extend in either the X direction or the Y direction. The width of the conductive layer 260 is preferably narrow in both the X direction and the Y direction. This can reduce the area of ​​the region of the conductive layer 260 that overlaps with the top surface of the conductive layer 240, thereby reducing the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240.

[0524] 15B and 15C show an example in which the maximum width of the conductive layer 260 is smaller than the width D of the opening 290. As such, it is preferable that the maximum width of the conductive layer 260 is equal to or smaller than the width of the opening 290.

[0525] The maximum width of the conductive layer 260 may be larger than the width of the opening 290. For example, the maximum width of the conductive layer 260 is preferably equal to or smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in FIG. 15C ). Also, for example, the maximum width of the conductive layer 260 is preferably equal to or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 15E ). This allows the area of ​​the overlapping portion between the conductive layer 260 and the conductive layer 240 to be sufficiently small, thereby reducing the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240.

[0526] 15B and 15C , an opening 270 is provided in the insulating layer 285 at a position overlapping the opening 290, reaching the conductive layer 260. The conductive layer 265a is arranged so that at least a portion thereof is located within the opening 270. Furthermore, the conductive layer 265b may also be arranged so that at least a portion thereof is located within the opening 270. The conductive layer 265a contacts the conductive layer 260 within the opening 270. It can also be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other.

[0527] The conductive layer 265a is provided so as to fill at least a part of the opening 270. Alternatively, the conductive layer 265b may be provided so as to fill a part of the opening 270.

[0528] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 270. When the conductive layer 265 has a stacked-layer structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 265 in the opening 270 as the transistor is miniaturized and the diameter of the opening 270 becomes smaller. Figures 15B and 15C show an example in which the conductive layer 265 has a two-layer structure and a conductive layer 265a and a conductive layer 265b are provided in the opening 270. Note that depending on the diameter of the opening 270, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like, only the conductive layer 265a may be located in the opening 270.

[0529] The portions of the conductive layers 265a and 265b that do not overlap with the opening 290 are mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have overlapping portions without the insulating layer 285 being therebetween.

[0530] 15B and 15C show an example in which the width of the opening 270 is narrower than the width D of the opening 290. The narrower the width of the opening 270, the narrower the region where the conductive layer 240 and the conductive layer 265 overlap without the insulating layer 285 therebetween can be made, and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be reduced, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0531] The width of the opening 270 may be larger than the width of the opening 290. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layers 265a and 265b in FIG. 15C ). Furthermore, for example, the maximum width of the conductive layer 265 is preferably equal to or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 15E ). This allows the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 without the insulating layer 285 interposed therebetween to be sufficiently smaller than the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 interposed therebetween, thereby reducing the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265.

[0532] That is, the transistor 203 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0533] [Transistor 203A] FIG. 16A is a cross-sectional view of a semiconductor device having a transistor 203A.

[0534] 16A shows an example in which the sidewalls of the opening 290 are tapered. For details of the case in which the sidewalls of the opening 290 are tapered, the description of the transistor 200A (FIG. 11A) can be referred to.

[0535] [Transistor 203B] FIG. 16B is a cross-sectional view of a semiconductor device having a transistor 203B.

[0536] The transistor 203B differs from the transistor 203 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, refer to the description of the transistor 200B ( FIG. 11B ).

[0537] The transistor 203 can be modified in shape and details, similarly to the transistor 200. Specifically, the transistor 203 can have the same structure as the transistors 200C to 200L.

[0538] [Transistors 203C and 203D] Fig. 17A is a cross-sectional view of a semiconductor device including a transistor 203C. Fig. 17B is a cross-sectional view of a semiconductor device including a transistor 203D.

[0539] The transistor 203C differs from the transistor 203 mainly in that the transistor 203C does not include the insulating layer 285 but includes insulating layers 285a and 285b.

[0540] The transistors 203C and 203D are different from the transistor 203 mainly in that the top surface of the conductive layer 260 is flat.

[0541] In this way, the upper surface of the conductive layer 260 may be planarized. In addition, it is preferable that the height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 285a are aligned or approximately aligned.

[0542] [Transistor 203E] FIGS. 17C1 and 17C2 are cross-sectional views of a semiconductor device having a transistor 203E.

[0543] The transistor 203E differs from the transistor 203 mainly in that the conductive layer 260 has a portion overlapping with the top surface of the conductive layer 240b.

[0544] As described above, the conductive layer 260 may have a portion overlapping with the conductive layer 240. On the other hand, it is preferable to separately provide a conductive layer 265 that functions as a gate wiring and to provide an insulating layer 285 between the conductive layer 265 and the conductive layer 240. This increases the physical distance between the conductive layer 265 and the conductive layer 240, and reduces parasitic capacitance generated between the gate wiring and the conductive layer 240.

[0545] [Region Having a Halogen Element, Region Having a First Element] In the semiconductor device of one embodiment of the present invention, at least one of the side surface of the insulating layer 280a on the opening 290 side and its vicinity, the side surface of the insulating layer 280b on the opening 290 side and its vicinity, the insulating layer 235, and the oxide semiconductor layer 230 may have a region containing a halogen element.

[0546] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. From the viewpoint of substituting oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.

[0547] When the insulating layer 280a, the insulating layer 280b, or the insulating layer 235 contains a halogen element, the halogen element can be supplied into the oxide semiconductor layer 230. The halogen element (X) becomes a defect (VoX) in the oxide semiconductor layer 230, where the halogen element enters an oxygen vacancy (Vo), and has a function of generating electrons that serve as carriers. For example, when chlorine (Cl) is used as the halogen element, Cl exists stably in the oxide semiconductor layer 230 (particularly at and in the vicinity of the interface between the insulating layer 235 and the oxide semiconductor layer 230) in the state of VoCl. In this case, Cl can enter the state of VoCl not only by entering existing Vo but also by substituting oxygen.

[0548] On the other hand, oxygen substituted with Cl (also referred to as excess oxygen) has a function of trapping electrons. Carrier trapping by oxygen occurs preferentially over carrier generation by VoCl. Therefore, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer 235 and the oxide semiconductor layer 230 and in the vicinity thereof. The presence of negative charges in the channel formation region can shift the threshold voltage of the transistor in the positive direction. Therefore, even when the transistor has a miniaturized structure or an extremely short channel length, the transistor can be normally off.

[0549] In this manner, the transistor of one embodiment of the present invention can be normally off not only by controlling the threshold voltage with the back gate but also by using a halogen element.

[0550] In the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 preferably contain an impurity element. The impurity element is preferably the first element. Alternatively, the impurity element is preferably both the first element and hydrogen. The oxide semiconductor layer 230 preferably contains the impurity element, particularly in the region 230n+ (see FIG. 10A ).

[0551] Note that at least one of the conductive layer 240a, the conductive layer 240b, the conductive layer 220a, and the conductive layer 220b may also contain an impurity element.

[0552] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0553] The first element is not limited to the above elements, and may be one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements.

[0554] By supplying the first element to the source region and the drain region, the first element deprives these regions of oxygen, causing oxygen vacancies in these regions. The oxygen vacancies then bond with hydrogen in the film, generating carriers, thereby reducing the resistance of the source region and the drain region. This reduces the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. This increases the on-state current of the transistor. Increasing the on-state current reduces the operating voltage of the transistor. This reduces the power consumption of the semiconductor device.

[0555] When an element that easily bonds with oxygen is used as the first element, the first element exists in a state bonded to oxygen in the semiconductor layer. Furthermore, when an element that bonds with oxygen to stabilize the semiconductor layer is used as the first element, the first element in the semiconductor layer exists stably in an oxidized state, and is therefore less likely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device, thereby achieving a stable low-resistance region with low electrical resistance. For this reason, it is preferable to use an element whose oxide can exist as a solid at 25°C and 1 atmosphere as the first element. Specifically, preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals), and particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0556] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0557] Furthermore, hydrogen is suitable as an impurity element because it has the function of bonding with oxygen vacancies in addition to the function of causing the oxygen vacancies.

[0558] By using both the first element and hydrogen as the impurity elements, the electrical resistance of the source region and the drain region in the oxide semiconductor layer 230 can be easily reduced and the low electrical resistance can be stably maintained.

[0559] Furthermore, when both the first element and hydrogen are supplied, ions generated from the source gas can be added without mass separation, which is preferable because it is possible to increase productivity. ２ H ６ By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using the gas, phosphorus and hydrogen can be supplied as impurity elements. However, the method of supplying the impurity elements is not limited to this. For example, a specific element may be added by ionizing the source gas and mass-separating the ions. For example, B ２ H ６A gas may be used, and boron may be added after mass separation.

[0560] Note that the impurity element might be supplied also to a channel formation region in the oxide semiconductor layer 230. Alternatively, due to the influence of heat during the manufacturing process, part of the impurity element contained in the region 230n+ or the region 230n− might diffuse into the channel formation region (region 230i).

[0561] In manufacturing the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 are preferably doped with an impurity element more easily than the channel formation region. Therefore, the impurity element is preferably doped from a direction perpendicular or substantially perpendicular to the top surface of the substrate. In this case, the amount of the impurity element doped is smaller in a surface of the oxide semiconductor layer 230 that is inclined with respect to the top surface of the substrate than in a surface that is parallel or substantially parallel to the top surface of the substrate. That is, the amount of the impurity element doped is larger in the source region and the drain region of the oxide semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source region and the drain region can be preferentially reduced.

[0562] As described above, the semiconductor device of one embodiment of the present invention has a structure in which a gate electric field is easily applied to the oxide semiconductor, which leads to favorable electrical characteristics of the transistor.

[0563] Furthermore, the semiconductor device of one embodiment of the present invention has a structure in which parasitic capacitance between a source electrode or a drain electrode and a gate electrode and between a source electrode or a drain electrode and a gate wiring are reduced, thereby improving the frequency characteristics of a circuit using the semiconductor device.

[0564] Furthermore, the transistor of one embodiment of the present invention has a back gate. Therefore, the transistor of one embodiment of the present invention can have a structure that combines excellent on-state characteristics, normally-off operation, and high reliability even when miniaturized.

[0565] This embodiment mode can be combined with other embodiment modes as appropriate.

[0566] 18 to 35. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0567] 18A to 18C , the structure of a memory device including a transistor and a capacitor will be described. Fig. 18A is a plan view of a memory device including a transistor 203 and a capacitor 100. Fig. 18B is a cross-sectional view taken along dashed line A1-A2 in Fig. 18A . Fig. 18C is a cross-sectional view taken along dashed line A3-A4 in Fig. 18A .

[0568] 18A to 18C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280a, an insulating layer 280b, an insulating layer 285, and a conductive layer 265 over the insulating layer 285. The insulating layer 140, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, and the insulating layer 285 function as interlayer films. The conductive layer 110 and the conductive layer 265 function as wirings.

[0569] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 203 over the capacitor 100 .

[0570] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 220a on the insulating layer 130. The conductive layer 220a functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor. The conductive layer 220b can also be considered as part of the upper electrode of the capacitor 100.

[0571] As shown in FIGS. 18B and 18C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed within the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 within the opening 190, a region in contact with the side surface of the insulating layer 180 within the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located within the opening 190. The conductive layer 220a is disposed so that at least a portion of it is located within the opening 190. As shown in FIGS. 18B and 18C , the conductive layer 220a is preferably disposed so as to fill the opening 190. The films disposed within the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220a are preferably formed by an ALD method.

[0572] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0573] 18B and 18C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0574] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 220a is provided on the insulating layer 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench capacitor or a trench capacitor.

[0575] Furthermore, an insulating layer 280a is disposed on the capacitor element 100. The insulating layer 280a has a portion located on the insulating layer 130 and a portion located on the conductive layer 220b.

[0576] The transistor 203 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 255 over the insulating layer 280a, a conductive layer 240 over the insulating layer 280b, an oxide semiconductor layer 230, an insulating layer 235 between the conductive layer 255 and the oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The oxide semiconductor layer 230 functions as a semicondu...

Claims

The apparatus includes a first film formation chamber, a second film formation chamber, a third film formation chamber, a first treatment chamber, and a transfer chamber; the first film formation chamber has a function of forming a film by a thermal ALD method using a first precursor and a first oxidizing agent; the second film formation chamber has a function of forming a film by a plasma ALD method using a second precursor and a second oxidizing agent; the third film formation chamber has a function of forming a film by a thermal ALD method using a third precursor and a third oxidizing agent; the first treatment chamber has a function of performing a heat treatment or a microwave treatment, The manufacturing apparatus, wherein the first film formation chamber is connected to the second film formation chamber, the third film formation chamber, and the first processing chamber via the transfer chamber. 　 In claim 1, A fourth deposition chamber is provided, the fourth film formation chamber has a function of forming a conductive layer by a CVD method, the fourth film formation chamber is connected to the first film formation chamber, the second film formation chamber, and the first processing chamber via the transfer chamber. 　 The apparatus includes a first film formation chamber, a second film formation chamber, a first treatment chamber, and a transfer chamber; the first film formation chamber has a function of forming a film by a plasma ALD method using a first precursor and a first gas containing nitrogen; the second film formation chamber has a function of forming a film by a thermal ALD method using a second precursor and an oxidizing agent; the first treatment chamber has a function of performing a heat treatment or a microwave treatment, The first film formation chamber is connected to the second film formation chamber and the first processing chamber via the transfer chamber. 　 In claim 3, A third film forming chamber is provided, the third film formation chamber has a function of forming a film by a plasma ALD method using a third precursor and a second gas containing nitrogen; the third film formation chamber is connected to the first film formation chamber, the second film formation chamber, and the first processing chamber via the transfer chamber. 　 In claim 1 or 3, A second processing chamber is provided. the first treatment chamber has a function of performing a heat treatment, the second treatment chamber has a function of performing microwave treatment, The second treatment chamber is connected to the first film formation chamber, the second film formation chamber, and the first treatment chamber via the transfer chamber. 　 A method for manufacturing a semiconductor device including an oxide semiconductor layer, a gate insulating layer, and a gate electrode stacked in this order, using a manufacturing apparatus including a first deposition chamber, a second deposition chamber, a third deposition chamber, and a transfer chamber, the method comprising the steps of: the gate insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer; forming the first insulating layer on the oxide semiconductor layer by a thermal ALD method using a first precursor and a first oxidizing agent in the first film formation chamber; forming the second insulating layer on the first insulating layer by a plasma ALD method using a second precursor and a second oxidizing agent in the second film formation chamber; forming the third insulating layer on the second insulating layer by a thermal ALD method using a third precursor and a third oxidant in the third film formation chamber; The method for manufacturing a semiconductor device, wherein the first deposition chamber is connected to the second deposition chamber and the third deposition chamber via the transfer chamber. 　 In claim 6, The manufacturing apparatus has a fourth film formation chamber, a conductive layer which is to become the gate electrode is formed on the third insulating layer by a CVD method in the fourth film formation chamber.

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