Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device (100) is provided with: a semiconductor layer (10) having a first main surface (50) and a second main surface (51); and a diamond layer (11) having a third main surface (52) and a fourth main surface (53). The diamond layer (11) is provided with: a first recess (30) formed in the third main surface (52); and a first bonding layer (13) embedded in the first recess (30). The second main surface (51) of the semiconductor layer (10) and the third main surface (52) of the diamond layer (11) are bonded via the first bonding layer (13).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Semiconductor devices made of nitride semiconductors, such as field effect transistors (FETs), are known as semiconductor devices that operate at high power and high frequencies. However, nitride semiconductor devices have a problem in that the characteristics or reliability of the semiconductor device deteriorate due to an increase in the internal temperature of the semiconductor device during high power operation.

[0003] In order to suppress temperature rises inside semiconductor devices, it is important to provide materials or structures with high heat dissipation properties near heat-generating parts. Diamond boasts the highest thermal conductivity of any solid material, making it an ideal heat dissipation material.

[0004] A semiconductor device with a high heat dissipation effect is known to have a structure in which the entire substrate of the semiconductor device is replaced with diamond, that is, diamond is used as a heat spreader. In particular, the GaN-on-Diamond structure, which uses gallium nitride (GaN) as a nitride semiconductor, is widely known.

[0005] Since it is difficult to grow nitride semiconductor directly on diamond, the above-mentioned structure is formed by growing diamond on nitride semiconductor via an intermediate layer, or by bonding a diamond substrate separately formed on a semiconductor substrate made of nitride semiconductor.In the technology of bonding a diamond substrate to a semiconductor substrate, due to the difference in thermal expansion coefficient between them, it is desirable to bond at a relatively low temperature in order to suppress the stress change of each substrate.Therefore, in the direct bonding of a semiconductor substrate and a diamond substrate, a surface activated bonding method is used, which forms dangling bonds at the bonding interface by irradiating Ar at room temperature and in high vacuum, and then performs pressure bonding.

[0006] When directly bonding substrates, the bonding is performed at the atomic level, so the bonding surfaces of the diamond substrate and the semiconductor substrate must be flattened and smoothed to a surface roughness of 1 nm or less. While it is possible to smooth and flatten single-crystal diamond and polycrystalline diamond on diamond substrates, it is difficult to smooth and flatten large diamond substrates with a surface area of ​​2 inches or more uniformly and with high precision. In particular, when bonding a large semiconductor substrate and a diamond substrate, the influence of stress is large, and peeling is likely to occur unless the adhesion between the substrates is high.

[0007] Therefore, methods have been proposed to introduce an interface layer to enhance adhesion between substrates, with the aim of mitigating the effects of substrate surface roughness and improving the bonding strength of paired dangling bonds formed by amorphous materials (e.g., Patent Documents 1 and 2). By making the interface layer thicker, the amorphous layer expands, increasing the bonding strength and enabling uniform bonding within the substrate surface.

[0008] Japanese Patent Application Laid-Open No. 2020-109796 Japanese Patent Application Laid-Open No. 2016-509372

[0009] However, when an interface layer is introduced between the substrates, the influence of the amorphous layer with low thermal conductivity increases, and the heat dissipation effect of the diamond substrate cannot be fully achieved. Therefore, a method for forming a bonding layer that can increase the bonding strength with the semiconductor substrate while maintaining the heat dissipation effect of the diamond substrate is desired.

[0010] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a manufacturing method thereof that can increase the bonding strength between the semiconductor layer and the diamond layer while ensuring the heat dissipation effect of the diamond layer.

[0011] The semiconductor device according to the present disclosure comprises a semiconductor layer having a first main surface and a second main surface, a diamond layer having a third main surface and a fourth main surface, a first recess formed in the third main surface of the diamond layer, and a first bonding layer embedded in the first recess, wherein the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer.

[0012] In the semiconductor device according to the present disclosure, the bonding layer is thicker in the recessed portion, and the bonding strength between the semiconductor layer and the diamond layer is increased in that portion, so that the influence of stress is alleviated and high bonding strength is obtained overall. Furthermore, since the bonding layer introduced between the semiconductor layer and the diamond layer is localized, the heat dissipation effect of the diamond substrate is also sufficiently obtained.

[0013] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0014] 1 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 3 is a top view of a semiconductor device according to a first embodiment; FIG. 4 is a view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 5 is a view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 6 is a view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 7 is a view showing a second step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 8 is a view showing a second step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 9 is a view showing a second step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 10 is a view showing a second step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 11 is a view showing a third step of a method for manufacturing a semiconductor device according to a first embodiment; FIG. 12 is a cross-sectional view of a semiconductor device according to a second embodiment; FIG. 13 is a view showing a first step of a method for manufacturing a semiconductor device according to a second embodiment; 1 is a diagram showing a second step in the method for manufacturing a semiconductor device according to embodiment 2. FIG. 2 is a diagram showing a second step in the method for manufacturing a semiconductor device according to embodiment 2. FIG. 3 is a diagram showing a third step in the method for manufacturing a semiconductor device according to embodiment 2. FIG. 4 is a cross-sectional view of a semiconductor device according to embodiment 3. FIG. 5 is a cross-sectional view of a semiconductor device according to embodiment 3. FIG. 6 is a diagram showing a third step in the method for manufacturing a semiconductor device according to embodiment 3. FIG. 7 is a diagram showing a third step in the method for manufacturing a semiconductor device according to embodiment 3. FIG. 8 is a cross-sectional view of a semiconductor device according to embodiment 4. FIG. 9 is a top view of a semiconductor device according to embodiment 4. FIG. 10 is a top view of a semiconductor device according to embodiment 4.

[0015] The semiconductor device and the manufacturing method thereof according to the present disclosure will be described in detail with reference to the drawings. In the drawings, for ease of understanding, the scale of each component may differ from the actual components.

[0016] A. First Embodiment A-1. Configuration A description will be given of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 includes a semiconductor layer 10 and a diamond layer 11, as shown in FIG.

[0017] The semiconductor layer 10 has a first main surface 50 and an opposing second main surface 51. In Figure 1, the upper surface of the semiconductor layer 10 is the first main surface 50, and the lower surface is the second main surface 51. The diamond layer 11 has a third main surface 52 and an opposing fourth main surface 53. In Figure 1, the upper surface of the diamond layer 11 is the third main surface 52, and the lower surface is the fourth main surface 53. The semiconductor layer 10 is mounted on the diamond layer 11, and the third main surface 52 of the diamond layer 11 and the second main surface 51 of the semiconductor layer 10 are bonded together.

[0018] A first recess 30 is formed in third main surface 52 of diamond layer 11. A first bonding layer 13 is densely embedded in first recess 30. The surface of first bonding layer 13 forms the same plane as third main surface 52 of diamond layer 11, and first bonding layer 13 is bonded to second main surface 51 of semiconductor layer 10.

[0019] The shape of first recess 30 is preferably an inverted cone, an inverted truncated cone, an inverted pyramid, or an inverted truncated pyramid in order to obtain high coverage of first bonding layer 13 on first recess 30. The depth of first recess 30 is preferably 10 nm or more and 500 nm or less, taking into account the influence of the thickness of first bonding layer 13 formed.

[0020] The material of the first bonding layer 13 can be any one of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film, or a combination of two or more of these.

[0021] As shown in Fig. 2, a second bonding layer 14 may be provided between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 to enhance the bonding strength between the semiconductor layer 10 and the diamond layer 11. The second bonding layer 14 is provided over the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, bonding the second main surface 51 and the third main surface 52 together. A thick second bonding layer 14 may result in the generation of parasitic components and a reduction in heat dissipation performance, so its thickness is preferably 10 nm or less. As will be described later, the first bonding layer 13 enhances the bonding strength between the semiconductor layer 10 and the diamond layer 11, so sufficient bonding strength can be obtained even if the second bonding layer 14 is 10 nm or less in thickness. The second bonding layer 14 is preferably made of the same material as the first bonding layer 13 to enhance the bonding strength.

[0022] A semiconductor device is formed on the first main surface 50 of the semiconductor layer 10. As an example, FIG. 3 shows an example in which a high electron mobility transistor (HEMT) is formed on the first main surface 50. Note that FIGS. 1 and 2 correspond to a cross section taken along line A1-A2 in FIG. 3. The HEMT is composed of electrodes such as a source electrode 20, a gate electrode 21, and a drain electrode 22.

[0023] The semiconductor layer 10 may be made of, for example, GaN, AlGaN, InAlN, AlN, SiC, Si, GaAs, or Ga. ２ O ３ The semiconductor layer 10 may have a single layer structure made of one of these materials, or a laminate structure made of a plurality of materials. The thickness of the semiconductor layer 10 is preferably 10.0 μm or less, but may be more than 10.0 μm.

[0024] The diamond layer 11 may be a single crystal diamond, a mosaic diamond in which a plurality of single crystal diamonds are joined laterally, or a polycrystalline diamond. The diamond layer 11 is preferably produced by a chemical vapor deposition (CVD) method. The thickness of the diamond layer 11 is preferably 10 μm or more and 700 μm or less.

[0025] The materials of the source electrode 20, the gate electrode 21, and the drain electrode 22 may be a single metal element or an alloy. The single metal element may be one element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo. The alloy may be AlSi, AlCu, AuGe, AuGa, AuSn, or the like. The materials of the source electrode 20, the gate electrode 21, and the drain electrode 22 may be a laminate of any of the above materials.

[0026] A-2. Manufacturing Method Figures 4 to 14 are diagrams showing a manufacturing method for semiconductor device 100 according to embodiment 1. Below, a description will be given of a manufacturing method for semiconductor device 100 according to embodiment 1 with reference to Figures 4 to 14. The manufacturing method for semiconductor device 100 comprises a "first step" of processing semiconductor layer 10, a "second step" of processing diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and diamond layer 11.

[0027] The first step will be described.

[0028] First, as shown in FIG. 4, a support layer 16 made of Si, SiC, GaN, or the like is prepared, and a semiconductor layer 10 is formed on the support layer 16, thereby producing a first semiconductor substrate 1a made of the semiconductor layer 10 and the diamond layer 11.

[0029] Next, as shown in FIG. 5, the source electrode 20 , the gate electrode 21 , and the drain electrode 22 are formed on the first major surface 50 of the semiconductor layer 10 .

[0030] 6, a separately prepared support substrate 2 is bonded to the first main surface 50 of the semiconductor layer 10 via an adhesive layer 17, thereby producing a second semiconductor substrate 3a which is the first semiconductor substrate 1a bonded to the support substrate 2. The support substrate 2 may be a glass substrate, a sapphire substrate, a Si substrate, or the like.

[0031] 7, the support layer 16 is completely removed from the second semiconductor substrate 3a to expose the second main surface 51 of the semiconductor layer 10. The second main surface 51 of the semiconductor layer 10 is processed by grinding or polishing to make the surface shape flat and smooth. The smoothed second main surface 51 is processed to have a surface roughness Sa≦1.0 nm.

[0032] The second step will be described.

[0033] First, as shown in Fig. 8, a diamond substrate 4a that will become the diamond layer 11 is prepared. Then, as shown in Fig. 9, the third main surface 52 of the diamond layer 11 is ground and polished to flatten and smooth the surface shape of the third main surface 52. The smoothed third main surface 52 has been processed to have a surface roughness Sa≦1.0 nm.

[0034] 10 , a first recess 30 is formed in the ground and polished third main surface 52. The first recess 30 can be formed by selectively etching the third main surface 52 using an etching mask made of a patterned resist or a metal mask. The etching method may be, for example, etching by a thermochemical reaction with nickel, or dry etching using a reactive etching gas.

[0035] 11 , a first bonding layer 13 is formed on the third main surface 52 of the diamond substrate 4a on which the first recess 30 is formed, and the first bonding layer 13 is embedded in the first recess 30. The first bonding layer 13 is formed by a method such as plasma CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition. The first bonding layer 13 is formed to a thickness equal to or greater than the depth of the first recess 30, so that the first recess 30 is completely embedded with the first bonding layer 13.

[0036] 12, using the third main surface 52 of the diamond substrate 4a as a guide, the first bonding layer 13 is polished by CMP (Chemical Mechanical Polishing) to remove the first bonding layer 13 on the third main surface 52, and to adjust the height of the surface of the first bonding layer 13 embedded in the first recess 30 to match the height of the third main surface 52. This flattens the surface of the third main surface 52.

[0037] The third step will be described below: In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded together.

[0038] First, as shown in Fig. 13, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. When bonding the second semiconductor substrate 3a and the diamond substrate 4a, room temperature surface activated bonding or the like is used. When using the configuration of Fig. 2, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. The second bonding layer 14 is preferably made of the same material as the first bonding layer 13 in order to improve adhesion with the first bonding layer 13.

[0039] 14, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a, thus completing the semiconductor device 100 having the structure shown in FIG.

[0040] A-3. Effects In the semiconductor device 100 according to the first embodiment, the diamond layer 11 and the semiconductor layer 10 are bonded via the first bonding layer 13 embedded in the first recess 30. This increases the bonding surface area and the bonding layer thickness, and increases the bonding strength between the semiconductor layer 10 and the diamond layer 11 in the first recess 30 portion.

[0041] The first bonding layer 13 between the semiconductor layer 10 and the diamond layer 11 can correct surface roughness and assist in bonding dissimilar substrates together through the amorphous component, but the presence of the first bonding layer 13 may also lead to the generation of parasitic components and a decrease in heat dissipation performance. Therefore, it is desirable to reduce the influence of the first bonding layer 13 as much as possible. In the semiconductor device 100 according to the first embodiment, the first bonding layer 13 is formed locally, thereby suppressing the influence of the first bonding layer 13. Therefore, the generation of parasitic components is prevented and the heat dissipation effect of the diamond layer 11 is sufficiently obtained.

[0042] B. Second Embodiment B-1. Configuration A semiconductor device 100 according to a second embodiment will be described. FIG. 15 is a diagram showing the configuration of the semiconductor device 100 according to the second embodiment. In FIG. 15, elements that are the same as or correspond to those shown in FIG. 1 are given the same reference numerals. Therefore, detailed description thereof will be omitted.

[0043] In semiconductor device 100 according to the second embodiment, diamond layer 11 does not have first recessed portion 30 and first bonding layer 13 shown in the first embodiment (FIG. 1), and instead, semiconductor layer 10 has second recessed portion 31 and third bonding layer 15 as shown in FIG. 15. Second recessed portion 31 is formed in second main surface 51 of semiconductor layer 10, and third bonding layer 15 is densely embedded in second recessed portion 31. The surface of third bonding layer 15 forms the same plane as second main surface 51 of semiconductor layer 10, and third bonding layer 15 is bonded to third main surface 52 of diamond layer 11.

[0044] The shape of second recess 31 is preferably an inverted cone, an inverted truncated cone, an inverted pyramid, or an inverted truncated pyramid in order to improve the coating property of third bonding layer 15 on second recess 31. The depth of second recess 31 is preferably 10 nm or more and 500 nm or less, taking into account the influence of the thickness of third bonding layer 15 formed.

[0045] The third bonding layer 15 can be made of any one of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film, or a combination of two or more of these.

[0046] As shown in Figure 16, a second bonding layer 14 may be formed between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 to enhance bonding strength. The second bonding layer 14 is provided over the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, bonding the second main surface 51 and the third main surface 52 together. A thick second bonding layer 14 may result in the generation of parasitic components and a reduction in heat dissipation performance, so its thickness is preferably 10 nm or less. As will be described later, the third bonding layer 15 improves the bonding strength between the semiconductor layer 10 and the diamond layer 11, so sufficient bonding strength can be obtained even if the second bonding layer 14 is 10 nm or less in thickness. To enhance bonding strength, the second bonding layer 14 is preferably made of the same material as the third bonding layer 15.

[0047] B-2. Manufacturing method Figures 17 to 27 are diagrams showing a manufacturing method for semiconductor device 100 according to embodiment 2. The manufacturing method for semiconductor device 100 according to embodiment 2 will be described below with reference to Figures 17 to 27. The manufacturing method for semiconductor device 100 according to embodiment 2 also comprises a "first step" of processing semiconductor layer 10, a "second step" of processing diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and diamond layer 11.

[0048] The first step will be described.

[0049] First, as shown in FIG. 17, a support layer 16 made of Si, SiC, GaN, or the like is prepared, and a semiconductor layer 10 is formed on the support layer 16, thereby producing a first semiconductor substrate 1a made of the semiconductor layer 10 and the diamond layer 11.

[0050] Next, as shown in FIG. 18, the source electrode 20, the gate electrode 21, and the drain electrode 22 are formed on the first major surface 50 of the semiconductor layer 10.

[0051] 19 , a separately prepared support substrate 2 is bonded to the first main surface 50 of the semiconductor layer 10 via an adhesive layer 17, thereby producing a second semiconductor substrate 3a which is the first semiconductor substrate 1a bonded to the support substrate 2. The support substrate 2 may be a glass substrate, a sapphire substrate, a Si substrate, or the like.

[0052] 20, the support layer 16 is removed from the second semiconductor substrate 3a to expose the second main surface 51 of the semiconductor layer 10. Then, as shown in FIG. 21, a second recess 31 is formed in the exposed second main surface 51. The second recess 31 can be formed by selectively etching the second main surface 51 using an etching mask made of a patterned resist or a metal mask. The etching method may be, for example, etching by a thermochemical reaction with nickel, or dry etching using a reactive etching gas.

[0053] 22 , a third bonding layer 15 is formed on the second main surface 51 of the semiconductor layer 10 in which the second recess 31 is formed, and the third bonding layer 15 is embedded in the second recess 31. The third bonding layer 15 is formed by a method such as plasma CVD, sputtering, or vacuum deposition. The third bonding layer 15 is formed to a thickness equal to or greater than the depth of the second recess 31, so that the second recess 31 is completely embedded with the third bonding layer 15.

[0054] 23 , second main surface 51 of semiconductor layer 10 is processed by grinding or polishing to flatten and smooth the surface shape. Smoothed second main surface 51 is processed to have a surface roughness Sa≦1.0 nm. In addition, third bonding layer 15 on second main surface 51 is removed, and the surface height of third bonding layer 15 embedded in second recess 31 is adjusted to the height of second main surface 51.

[0055] The second step will be described.

[0056] First, as shown in Fig. 24, a diamond substrate 4a that will become the diamond layer 11 is prepared. Then, as shown in Fig. 25, the third main surface 52 of the diamond layer 11 is ground and polished to flatten and smooth the surface shape of the third main surface 52. The smoothed third main surface 52 has been processed to have a surface roughness Sa≦1.0 nm.

[0057] The third step will be described below: In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded together.

[0058] First, as shown in Fig. 26, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. When bonding the second semiconductor substrate 3a and the diamond substrate 4a, room temperature surface activated bonding or the like is used. When using the configuration of Fig. 16, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. The second bonding layer 14 is preferably made of the same material as the third bonding layer 15 in order to improve adhesion with the third bonding layer 15.

[0059] 27, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a, thus completing the semiconductor device 100 having the structure shown in FIG.

[0060] B-3. ​​Effects In semiconductor device 100 according to the second embodiment, semiconductor layer 10 and diamond layer 11 are bonded via third bonding layer 15 embedded in second recess 31. This increases the bonding surface area and bonding layer thickness, and increases the bonding strength between semiconductor layer 10 and diamond layer 11 in the second recess 31 portion.

[0061] Furthermore, in semiconductor device 100 according to the second embodiment, third bonding layer 15 is formed locally, thereby suppressing the influence of third bonding layer 15. This prevents the generation of parasitic components and ensures the sufficient heat dissipation effect of diamond layer 11.

[0062] C. Third Embodiment C-1. Configuration A semiconductor device 100 according to a third embodiment will be described. FIG. 28 is a diagram showing the configuration of the semiconductor device 100 according to the third embodiment. In FIG. 28, elements that are the same as or correspond to those shown in FIG. 1 or FIG. 15 are given the same reference numerals. Therefore, detailed description thereof will be omitted.

[0063] In semiconductor device 100 according to the third embodiment, diamond layer 11 has first recess 30 and first bonding layer 13 on second main surface 51, similar to embodiment 1 (FIG. 1), and semiconductor layer 10 has second recess 31 and third bonding layer 15 on third main surface 52, similar to embodiment 2 (FIG. 15). Furthermore, first recess 30 and second recess 31 are formed at positions where they overlap each other, and first bonding layer 13 in first recess 30 and third bonding layer 15 in second recess 31 are bonded on the same plane. First bonding layer 13 and third bonding layer 15 are preferably formed from the same material.

[0064] As shown in Figure 29, a second bonding layer 14 may be formed between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11 to enhance bonding strength. The second bonding layer 14 is provided over the entire bonding surface between the second main surface 51 of the semiconductor layer 10 and the third main surface 52 of the diamond layer 11, bonding the second main surface 51 and the third main surface 52 together. A thick second bonding layer 14 may result in the generation of parasitic components and a reduction in heat dissipation performance, so its thickness is preferably 10 nm or less. Because the first bonding layer 13 and the third bonding layer 15 improve the bonding strength between the semiconductor layer 10 and the diamond layer 11, sufficient bonding strength can be obtained even if the second bonding layer 14 is 10 nm or less in thickness. To enhance bonding strength, the second bonding layer 14 is preferably made of the same material as the first bonding layer 13 and the third bonding layer 15.

[0065] C-2. Manufacturing Method Hereinafter, a description will be given of a manufacturing method for semiconductor device 100 according to embodiment 3. The manufacturing method for semiconductor device 100 according to embodiment 3 also comprises a "first step" of processing semiconductor layer 10, a "second step" of processing diamond layer 11, and a "third step" of bonding the processed semiconductor layer 10 and diamond layer 11 together.

[0066] The first step in the third embodiment is the same as the first step in the second embodiment (FIGS. 17 to 23).

[0067] The second step in the third embodiment is similar to the second step in the first embodiment (FIGS. 8 to 12).

[0068] In the third step, the second semiconductor substrate 3a processed in the first step and the diamond substrate 4a processed in the second step are bonded together.

[0069] First, as shown in Figure 30, the second main surface 51 of the semiconductor layer 10 of the second semiconductor substrate 3a is bonded to the third main surface 52 of the diamond substrate 4a. At this time, the first recess 30 and the second recess 31 are aligned. When bonding the second semiconductor substrate 3a and the diamond substrate 4a, room-temperature surface activated bonding or the like is used. When using the configuration of Figure 29, a second bonding layer 14 is formed on the third main surface 52 of the diamond substrate 4a prior to bonding. It is preferable that the second bonding layer 14 be made of the same material as the first bonding layer 13 and the third bonding layer 15 in order to improve adhesion with the third bonding layer 15.

[0070] 31, the adhesive layer 17 and the support substrate 2 are peeled off from the first semiconductor substrate 1a, thus completing the semiconductor device 100 having the structure shown in FIG.

[0071] C-3. Effects In semiconductor device 100 according to the third embodiment, semiconductor layer 10 and diamond layer 11 are bonded via first bonding layer 13 embedded in first recess 30 and third bonding layer 15 embedded in second recess 31. First recess 30 and first bonding layer 13, and second recess 31 and third bonding layer 15 are provided in positions where they overlap each other, and first bonding layer 13 and third bonding layer 15 are bonded together. This increases the bonding surface area and bonding layer thickness, and increases the bonding strength between semiconductor layer 10 and diamond layer 11 in the areas of first recess 30 and second recess 31.

[0072] Furthermore, in semiconductor device 100 according to the second embodiment, first bonding layer 13 and third bonding layer 15 are formed locally, thereby suppressing the influence of first bonding layer 13 and third bonding layer 15. This prevents the generation of parasitic components and ensures a sufficient heat dissipation effect by diamond layer 11.

[0073] D. Fourth Embodiment D-1. Configuration Figures 32 and 33 are a cross-sectional view and a top view of a semiconductor device 100 according to a fourth embodiment. Figure 32 is a cross-section taken along line A1-A2 in Figure 33.

[0074] The basic structure of the semiconductor device 100 according to the fourth embodiment is the same as that of the first to third embodiments, but as shown in Figures 32 and 33, one or both of the first recess 30 and the second recess 31 are formed at a position away from directly below the conductive region 54 of the semiconductor layer 10 (a region that becomes a current path when a semiconductor device such as a transistor operates).

[0075] In order to reduce the effect on heat generation when the semiconductor device is energized, the positions of the first recess 30 and the second recess 31 are preferably at least 50 μm away from the energized region 54, and more preferably at least 100 μm away from the energized region 54.

[0076] Furthermore, as shown in FIG. 34 , one or both of the first recessed portion 30 and the second recessed portion 31 may extend so as to surround the current-carrying region 54 .

[0077] D-2. Manufacturing Method The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device 100 according to the first to third embodiments only in the arrangement of the first recessed portion 30 or the second recessed portion 31. Therefore, the semiconductor device 100 according to the fourth embodiment can be formed by a method similar to the manufacturing method of the semiconductor device 100 according to the first to third embodiments.

[0078] D-3. Effects In semiconductor device 100 according to the fourth embodiment, first recessed portion 30 or second recessed portion 31 is provided at a position away from directly below current-carrying region 54 of the semiconductor device, thereby reducing the effect of heat generation during current flow and suppressing the effect on the semiconductor device of parasitic components due to dissimilar materials between substrates, leak paths, and the like.

[0079] Furthermore, by arranging the first recess 30 or the second recess 31 so as to surround the current-carrying region 54, the effects of local stress can be widely alleviated, and peeling in the region necessary for device operation can be suppressed.

[0080] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0081] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0082] REFERENCE SIGNS LIST 1a First semiconductor substrate, 2 Support substrate, 3a Second semiconductor substrate, 4a Diamond substrate, 10 Semiconductor layer, 11 Diamond layer, 12 Support layer, 13 First bonding layer, 14 Second bonding layer, 15 Third bonding layer, 16 Support layer, 17 Adhesion layer, 20 Source electrode, 21 Gate electrode, 22 Drain electrode, 30 First recessed portion, 31 Second recessed portion, 50 First main surface, 51 Second main surface, 52 Third main surface, 53 Fourth main surface, 54 Current-carrying region, 100 Semiconductor device.

Claims

1. A semiconductor device comprising: a semiconductor layer having a first main surface and a second main surface; a diamond layer having a third main surface and a fourth main surface; a first recessed portion formed in the third main surface of the diamond layer; and a first bonding layer embedded in the first recessed portion, wherein the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer.

2. The semiconductor device according to claim 1, further comprising a second bonding layer provided over the entire bonding surface between the second main surface of the semiconductor layer and the third main surface of the diamond layer, bonding the second main surface and the third main surface.

3. The semiconductor device according to claim 1 or claim 2, further comprising: a second recessed portion formed on the second main surface of the semiconductor layer; and a third bonding layer embedded in the second recessed portion, wherein the second recessed portion and the third bonding layer are provided at a position overlapping the first recessed portion and the first bonding layer, and the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the first bonding layer and the third bonding layer.

4. A semiconductor device comprising: a semiconductor layer having a first main surface and a second main surface; a diamond layer having a third main surface and a fourth main surface; a second recessed portion formed in the second main surface of the semiconductor layer; and a third bonding layer embedded in the second recessed portion, wherein the second main surface of the semiconductor layer and the third main surface of the diamond layer are bonded via the third bonding layer.

5. The semiconductor device according to claim 4, further comprising a second bonding layer provided across the entire bonding surface between the second main surface of the semiconductor layer and the third main surface of the diamond layer, bonding the second main surface and the third main surface.

6. The semiconductor device according to any one of claims 1 to 3, wherein the first bonding layer is composed of one or more of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film.

7. The semiconductor device according to claim 2 or claim 5, wherein the second bonding layer is composed of one or more of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, or a Pt-based thin film.

8. The semiconductor device according to any one of claims 3 to 5, wherein the third bonding layer is composed of one or more of a silicon-based thin film, a silicon carbide-based thin film, a silicon nitride-based thin film, a silicon oxide-based thin film, a gallium oxide-based thin film, an aluminum oxide thin film, a Ti-based thin film, a Ta-based thin film, a Cu-based thin film, an Au-based thin film, and a Pt-based thin film.

9. The semiconductor device according to claim 2, claim 5 or claim 7, wherein the second bonding layer has a thickness of 10 nm or less.

10. The semiconductor device according to any one of claims 1, 2, 3 and 6, wherein the first recessed portion is formed in a shape selected from the group consisting of an inverted cone, an inverted truncated cone, an inverted pyramid and an inverted truncated pyramid.

11. The semiconductor device according to any one of claims 3, 4, 5 and 8, wherein the second recessed portion is shaped in any one of an inverted cone, an inverted truncated cone, an inverted pyramid and an inverted truncated pyramid.

12. The semiconductor device according to claim 1, 2, 3, 6 or 10, wherein the depth of the first recess is not less than 10 nm and not more than 500 nm.

13. The semiconductor device according to claim 3, 4, 5, 8 or 11, wherein the depth of the second recess is not less than 10 nm and not more than 500 nm.

14. A semiconductor device according to any one of claims 1, 2, 3, 6, 10 and 12, wherein the first recessed portion is formed at a position 50 μm or more away from the conductive region of the semiconductor layer.

15. A semiconductor device according to any one of claims 3, 4, 5, 8, 11 and 13, wherein the second recessed portion is formed at a position 50 μm or more away from the conductive region of the semiconductor layer.

16. A semiconductor device according to any one of claims 1, 2, 3, 6, 10, 12 and 14, wherein the first recessed portion extends so as to surround the periphery of the conductive region of the semiconductor layer.

17. A semiconductor device according to any one of claims 3, 4, 5, 8, 11, 13 and 15, wherein the second recessed portion extends so as to surround the periphery of the conductive region of the semiconductor layer.

18. A first step including a step of forming a semiconductor layer having a first main surface and a second main surface on a support layer such that the second main surface is connected to the support layer, thereby producing a first semiconductor substrate consisting of the support layer and the semiconductor layer, and a step of removing the support layer from the first semiconductor substrate and grinding and polishing the second main surface of the semiconductor layer; a second step including a step of preparing a diamond layer having a third main surface and a fourth main surface, and grinding and polishing the third main surface to flatten and smooth it, a step of forming a first recessed portion in the third main surface, a step of forming a first bonding layer on the third main surface and embedding the first bonding layer in the first recessed portion, and a step of polishing the first bonding layer using the second main surface as a guide to remove the first bonding layer on the third main surface and to adjust the height of the surface of the first bonding layer embedded in the first recessed portion to the height of the third main surface; and a step of bonding the third main surface of the diamond layer to the second main surface of the semiconductor layer. and a third step including the steps of:

19. The method for manufacturing a semiconductor device as described in claim 18, wherein the third step further includes a step of forming a second bonding layer on the third main surface of the diamond layer, and the third main surface of the diamond layer and the second main surface of the semiconductor layer are bonded via the second bonding layer.

20. A method for manufacturing a semiconductor device as described in claim 18 or claim 19, wherein the first step further includes the steps of: forming a second recessed portion in the second main surface; forming a third bonding layer on the second main surface and embedding the third bonding layer in the second recessed portion; and grinding and polishing the second main surface on which the third bonding layer is formed to remove the third bonding layer on the second main surface and adjust the height of the surface of the third bonding layer embedded in the second recessed portion to the height of the second main surface, wherein the second recessed portion and the third bonding layer are provided in positions that overlap the first recessed portion and the first bonding layer when the diamond layer and the semiconductor layer are bonded in the third step.

21. A method for manufacturing a semiconductor device, comprising: a first step including: a step of forming a semiconductor layer having a first main surface and a second main surface on a support layer such that the second main surface is connected to the support layer, thereby producing a first semiconductor substrate consisting of the support layer and the semiconductor layer; a step of removing the support layer from the first semiconductor substrate and forming a second recessed portion in the second main surface; a step of forming a third bonding layer on the second main surface and embedding the third bonding layer in the second recessed portion, and a step of grinding and polishing the second main surface on which the third bonding layer is formed, thereby removing the third bonding layer on the second main surface and adjusting the height of a surface of the third bonding layer embedded in the second recessed portion to match the height of the second main surface; a second step including: a step of preparing a diamond layer having a third main surface and a fourth main surface, and grinding and polishing the third main surface to flatten and smooth it; and a third step including a step of bonding the third main surface of the diamond layer to the second main surface of the semiconductor layer.

22. The method for manufacturing a semiconductor device as described in claim 21, wherein the third step further includes a step of forming a second bonding layer on the third main surface of the diamond layer, and the third main surface of the diamond layer and the second main surface of the semiconductor layer are bonded via the second bonding layer.

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