Semiconductor device, semiconductor module, and wireless communication device

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises: a substrate; a first nitride semiconductor layer that is provided on one surface side of the substrate; a second nitride semiconductor layer that is laminated on the first nitride semiconductor layer, and that has a different bandgap from the first nitride semiconductor layer; a two-dimensional electron gas layer that is formed in the vicinity of the interface with the second nitride semiconductor layer of the first nitride semiconductor layer; a gate electrode that is provided contacting the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode that are disposed facing each other in the in-surface direction of the substrate with the gate electrode therebetween, and that are each electrically connected to the two-dimensional electron gas layer; a first gate barrier film that is laminated on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode, that includes a nitride semiconductor, and that has a first film thickness; and a second gate barrier film that is laminated on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, that includes a nitride semiconductor, and that has a second film thickness smaller than the first film thickness.

Description

Semiconductor device, semiconductor module, and wireless communication device

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and a wireless communication device.

[0002] For example, Patent Document 1 discloses a semiconductor device in which two layers, a spacer layer and a barrier layer, are provided between a gate electrode and a source electrode, and a barrier layer is provided directly below the gate electrode between the gate electrode and the drain electrode.

[0003] JP 2022-61810 A

[0004] Incidentally, there is a demand for improved device characteristics in HEMTs.

[0005] Therefore, it is desirable to provide a semiconductor device, a semiconductor module, and a wireless communication device that can improve the device characteristics.

[0006] a first ohmic electrode and a second ohmic electrode disposed opposite each other in an in-plane direction of the substrate with the gate electrode interposed therebetween, the first ohmic electrode and the second ohmic electrode being electrically connected to the two-dimensional electron gas layer; a first gate barrier film, the first gate barrier film and the second ohmic electrode being disposed on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode, the first gate barrier film containing a nitride semiconductor and having a first thickness; and a second gate barrier film, the second gate barrier film containing a nitride semiconductor and having a second thickness smaller than the first thickness, the second gate barrier film being disposed on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, the second gate barrier film containing a nitride semiconductor and having a second thickness smaller than the first thickness.

[0007] A semiconductor module according to an embodiment of the present disclosure includes the semiconductor device according to the embodiment of the present disclosure.

[0008] A wireless communication device according to an embodiment of the present disclosure includes the semiconductor device according to the embodiment of the present disclosure.

[0009] In a semiconductor device according to an embodiment of the present disclosure, a semiconductor module according to an embodiment, and a wireless communication device according to an embodiment, a first nitride semiconductor layer and a second nitride semiconductor layer are stacked in this order on one surface of a substrate. A two-dimensional electron gas layer is formed near the interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A gate electrode is provided in direct contact with the second nitride semiconductor layer, and a first ohmic electrode and a second ohmic electrode electrically connected to the two-dimensional electron gas layer are disposed opposite each other across the gate electrode. A first gate barrier film and a second gate barrier film are stacked on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode and on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, respectively. The film thickness of the first gate barrier film (first film thickness) is greater than the film thickness of the second gate barrier film (second film thickness). This reduces the resistance between the gate electrode and the first ohmic electrode.

[0010] FIG. 1 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically illustrating an example of a planar configuration of the semiconductor device illustrated in FIG. 1. FIG. 3 is a characteristic diagram illustrating the relationship between the film thickness of a gate barrier layer and the sheet carrier concentration. FIG. 4A is a cross-sectional view schematically illustrating an example of a process of a method for manufacturing the semiconductor device illustrated in FIG. 1. FIG. 4B is a cross-sectional view schematically illustrating a process subsequent to FIG. 4A. FIG. 4C is a cross-sectional view schematically illustrating a process subsequent to FIG. 4B. FIG. 4D is a cross-sectional view schematically illustrating a process subsequent to FIG. 4C. FIG. 4E is a cross-sectional view schematically illustrating a process subsequent to FIG. 4D. FIG. 4F is a cross-sectional view schematically illustrating a process subsequent to FIG. 4E. FIG. 4G is a cross-sectional view schematically illustrating a process subsequent to FIG. 4F. FIG. 4H is a cross-sectional view schematically illustrating a process subsequent to FIG. 4G. FIG. 4I is a cross-sectional view schematically illustrating a process subsequent to FIG. 4H. FIG. 5 is a cross-sectional view schematically illustrating an example of a configuration of a semiconductor device as a comparative example. FIG. 6A is a cross-sectional view schematically illustrating an example of a process of a method for manufacturing the semiconductor device illustrated in FIG. 5. Fig. 6B is a schematic cross-sectional view showing a step subsequent to Fig. 6A. Fig. 6C is a schematic cross-sectional view showing a step subsequent to Fig. 6B. Fig. 6D is a schematic cross-sectional view showing a step subsequent to Fig. 6C. Fig. 7 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to a modified example of the present disclosure. Fig. 8 is a schematic perspective view showing the configuration of a semiconductor module. Fig. 9 is a block diagram showing the configuration of a wireless communication device.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following embodiment. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing.

[0012] The description will be given in the following order: 1. Embodiment (Example of a semiconductor device in which the thickness of the gate barrier layer between the gate and source is different from that between the gate and drain) 1-1. Configuration of the semiconductor device 1-2. Manufacturing method of the semiconductor device 1-3. Actions and effects 2. Modifications (Other examples of the configuration of the semiconductor device) 3. Application examples 3-1. Application example to a semiconductor module 3-2. Application example to a wireless communication device

[0013] 1. Embodiments> [1-1. Configuration of Semiconductor Device] Fig. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present disclosure. Fig. 2 is a schematic diagram illustrating an example of a planar configuration of the semiconductor device 1 illustrated in Fig. 1.

[0014] The semiconductor device 1 has a laminated structure in which a substrate 11, a buffer layer 12, a channel layer 13, a spacer layer 14, a barrier layer 15, and a gate barrier layer 16 are laminated in this order. The semiconductor device 1 further includes a gate electrode G provided on the barrier layer 15, a pair of contact layers 17 arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G interposed therebetween, and a source electrode S and a drain electrode D provided on the pair of contact layers 17. In this embodiment, the gate electrode G is in direct contact with the barrier layer 15. The gate barrier layers 16 are provided between the gate electrode G and the pair of contact layers 17, respectively. The gate barrier layer 16A provided between the gate electrode G and the contact layer 17 (contact layer 17S) on which the source electrode S is laminated has a thickness greater than the gate barrier layer 16B provided between the gate electrode G and the contact layer 17 (contact layer 17D) on which the drain electrode D is laminated. The semiconductor device 1 has, for example, a Schottky gate structure.

[0015] Here, the substrate 11 corresponds to a specific example of a "substrate" in an embodiment of the present disclosure. The channel layer 13 corresponds to a specific example of a "first nitride semiconductor layer" in an embodiment of the present disclosure, and the barrier layer 15 corresponds to a specific example of a "second nitride semiconductor layer" in an embodiment of the present disclosure. Of the pair of contact layers 17, the contact layer 17 on which the source electrode S is stacked corresponds to a specific example of a "first ohmic electrode" in an embodiment of the present disclosure, and the contact layer 17 on which the drain electrode D is stacked corresponds to a specific example of a "second ohmic electrode" in an embodiment of the present disclosure. The gate barrier layer 16A corresponds to a specific example of a "first gate barrier film" in an embodiment of the present disclosure, and the gate barrier layer 16B corresponds to a specific example of a "second gate barrier film" in an embodiment of the present disclosure.

[0016] The semiconductor device 1 according to this embodiment is a high electron mobility transistor (HEMT) having a two-dimensional electron gas layer 2DEG as a channel. The two-dimensional electron gas layer 2DEG is generated due to the difference in the magnitude of polarization between the channel layer 13 and the barrier layer 15. The two-dimensional electron gas layer 2DEG is generated in the channel layer 13, for example, near the interface K34 between the channel layer 13 and the spacer layer 14.

[0017] The substrate 11 is a support for the semiconductor device 1. The substrate 11 is, for example, a Si (silicon) substrate, a SiC (silicon carbide) substrate, a sapphire substrate, a GaN (gallium nitride) substrate, or an AlN (aluminum nitride) substrate. As the Si substrate, for example, a single-crystal Si (111) substrate having a (111) plane as its main surface is suitable. As described above, the semiconductor device 1 is provided with a buffer layer 12. The buffer layer 12 can reduce the mismatch between the lattice constant of the substrate 11 and the lattice constant of the channel layer 13. Therefore, the substrate 11 may be made of a material having a lattice constant different from that of the channel layer 13.

[0018] The substrate 11 made of the above materials can provide the effects of the semiconductor device of the present disclosure described below. The semiconductor device 1 using a substrate made of SiC or GaN, which has better single crystallinity than Si(111) and a lower threading dislocation density, can be expected to further reduce off-leak current and increase breakdown voltage. Therefore, the substrate 11 can be constructed by selecting a suitable material depending on the application, etc.

[0019] The buffer layer 12 is made of an epitaxially grown nitride semiconductor. The buffer layer 12 can alleviate the lattice mismatch between the substrate 11 and the channel layer 13 by controlling the lattice constant of the surface on which the channel layer 13 is provided. Therefore, the buffer layer 12 can improve the crystalline state of the channel layer 13 and suppress warpage of the substrate 11.

[0020] Depending on the configuration of the substrate 11 and the channel layer 13, the buffer layer 12 may be omitted.

[0021] The channel layer 13 is made of a nitride semiconductor having a band gap smaller than the band gaps of the spacer layer 14 and the barrier layer 15. The channel layer 13 is provided on the buffer layer 12. The channel layer 13 can accumulate carriers at the interface on the barrier layer 15 side due to the difference in the magnitude of polarization between the channel layer 13 and the barrier layer 15.

[0022] The channel layer 13 is an epitaxially grown nitride semiconductor, Al ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） N (0≦x1≦1, 0≦y1≦1, 0≦x1+y1≦1). For example, the channel layer 13 is made of epitaxially grown GaN (gallium nitride). The channel layer 13 may be made of undoped u-GaN to which no impurities are added. The channel layer 13 may also be made of at least one of InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), and AlInGaN (aluminum indium gallium nitride). Furthermore, the channel layer 13 may have a stacked structure made of multiple layers with different compositions. In such cases, the channel layer 13 can suppress impurity scattering of carriers. Therefore, the channel layer 13 can further increase carrier mobility.

[0023] The spacer layer 14 is made of a nitride semiconductor having a band gap larger than that of the channel layer 13. The spacer layer 14 is provided on the channel layer 13. The spacer layer 14 reduces alloy scattering between the barrier layer 15 and the channel layer 13, and suppresses a decrease in carrier mobility in the two-dimensional electron gas layer 2DEG due to the alloy scattering.

[0024] The spacer layer 14 is an epitaxially grown Al ｘ２ In ｙ２ Ga （１－ｘ２－ｙ２） N (0<x2≦1, 0≦y2<1, 0≦x2+y2≦1). For example, the spacer layer 141 may be made of AlN, AlGaN, or AlInGaN.

[0025] The thickness of the spacer layer 14 is preferably, for example, 0.26 nm or more and 3.0 nm or less, and particularly preferably 0.5 nm or more and 1.5 nm or less. When the thickness of the spacer layer 14 is 0.26 nm or more, the spacer layer 14 is expected to be more effective in suppressing alloy scattering. On the other hand, when the thickness of the spacer layer 14 is 3.0 nm or less, the spacer layer 14 can more appropriately control the band gap profile of the semiconductor device 1. This allows for a further increase in the carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 13.

[0026] The barrier layer 15 is made of a nitride semiconductor having a band gap larger than that of the channel layer 13. The barrier layer 15 is provided on the spacer layer 14. The barrier layer 15 can accumulate carriers in a region of the channel layer 13 near the barrier layer 15 by spontaneous polarization or piezoelectric polarization. As a result, in the semiconductor device 1, a two-dimensional electron gas layer 2DEG with high mobility and high carrier concentration can be formed in a region of the channel layer 13 near the interface K34.

[0027] The barrier layer 15 is an epitaxially grown nitride semiconductor, Al ｘ３ In ｙ３ Ga （１－ｘ３－ｙ３） N (0<x3<1, 0<y3<1). Here, x3 may be greater than 0.7 and y3 may be less than 0.3. For example, the barrier layer 15 may be undoped u-Al ｘ３ In （１－ｘ３） In this case, the barrier layer 15 can have a small lattice mismatch with GaN, and therefore, a crystal with excellent single crystallinity can be obtained.

[0028] The carrier density of the two-dimensional electron gas layer 2DEG can be controlled, for example, by the band gap profile of each layer from the barrier layer 15 to the channel layer 13. One factor that determines the carrier density of the two-dimensional electron gas layer 2DEG is the height of the conduction band minimum of the barrier layer 15.

[0029] For example, the higher the Al composition of each layer, the greater the polarization of each layer. Therefore, the slope of the conduction band minimum becomes steeper. Furthermore, the thicker each layer becomes, the higher the height of the conduction band minimum becomes. Therefore, by appropriately controlling the thickness and composition of each layer from the barrier layer 15 to the channel layer 13 and controlling the height of the conduction band minimum of the barrier layer 15, the carrier density of the two-dimensional electron gas layer 2DEG can be increased.

[0030] For example, the barrier layer 15 is made of Al, which constitutes the spacer layer 14. ｘ２ In ｙ２ Ga （１－ｘ２－ｙ２） Al with a higher Al composition ratio than N ｘ３ In （１－ｘ３） N (0 < x3 < 1, 0 < y3 < 1). That is, by forming the barrier layer 15 from a nitride semiconductor such that x2 < x3 relative to the spacer layer 14, a larger polarization can be obtained. This allows for a higher carrier concentration in the two-dimensional electron gas layer 2DEG. For example, by forming the barrier layer 15 from a nitride semiconductor such that x3 exceeds 0.7, a larger polarization can be obtained. This allows for a higher carrier concentration in the two-dimensional electron gas layer 2DEG. The barrier layer 15 is formed from, for example, AlInN. The barrier layer 15 may also be formed from AlInGaN, AlGaN, or AlN. When the barrier layer 15 is formed from AlInGaN, a certain design margin can be obtained for the band gap and the amount of strain. Furthermore, when the barrier layer 15 contains Ga, the single crystallinity of the barrier layer 15 is improved.

[0031] The thickness of the barrier layer 15 is preferably 2.0 nm or more and 20 nm or less. In such a case, the barrier layer 15 can more appropriately control the band gap profile of the semiconductor device 1. This can further increase the carrier density of the two-dimensional electron gas layer 2DEG generated in the channel layer 13. Note that the thickness of the barrier layer 15 here does not include the thickness of the intermediate layer 18. Furthermore, the thickness of the barrier layer 15 is more preferably 3.0 nm or more and 10 nm or less.

[0032] The gate barrier layer 16 is a regrown film made of an epitaxially grown nitride semiconductor. Here, a "regrowth film" refers to a film that is grown on a substrate, temporarily removed from the growth furnace, processed as necessary, and then returned to the growth furnace for crystal growth. The gate barrier layer 16 includes a gate barrier layer 16A and a gate barrier layer 16B. The gate barrier layer 16A is provided on the barrier layer 15 between the gate electrode G and the contact layer 17S. The gate barrier layer 16B is provided on the barrier layer 15 between the gate electrode G and the contact layer 17D. The gate barrier layer 16A has a two-layer structure, for example, in which a first layer 16A1 and a second layer 16A2 are stacked in this order. As will be described in detail later, the second layer 16A2 is a regrown film formed in the same process as the gate barrier layer 16B, and the second layer 16A2 and the gate barrier layer 16B have the same composition.

[0033] The side surfaces of gate barrier layer 16A and gate barrier layer 16B each have an inclination angle of 50° or more and 60° or less in absolute value with respect to the XY plane of barrier layer 15. In particular, the side surfaces of first layer 16A1 and second layer 16A2 constituting gate barrier layer 16A each form a continuous inclined surface having an inclination angle of 50° or more and 60° or less in absolute value with respect to the XY plane of barrier layer 15.

[0034] The gate barrier layer 16 (gate barrier layers 16A and 16B), like the barrier layer 15, is made of an epitaxially grown nitride semiconductor, Al. ｘ４ In ｙ４ Ga （１－ｘ４－ｙ４） N (0<x4<1, 0<y4<1). For example, the gate barrier layers 16A and 16B are each made of undoped u-Al ｘ４ In （１－ｘ４）The gate barrier layers 16A and 16B may be made of AlInN, for example. The gate barrier layers 16A and 16B may be made of AlInGaN, AlGaN, or AlN, for example. When the gate barrier layers 16A and 16B are made of AlInGaN, a certain design margin can be obtained for the band gap and strain amount. Furthermore, the gate barrier layer 16 contains Ga, which improves the single crystallinity of the gate barrier layer 16.

[0035] 3 shows the relationship between the film thickness of the gate barrier layer 16 and the sheet carrier concentration. It can be seen from FIG. 3 that if the thickness of the gate barrier layer 16 in the stacking direction (Z-axis direction) is 1 nm or more, the sheet carrier concentration increases by 10% or more. That is, if the thicknesses in the Z-axis direction of the gate barrier layer 16A between the gate electrode G and the source electrode S (contact layer 17S) and the gate barrier layer 16B between the gate electrode G and the drain electrode D (contact layer 17D) are each 1 nm or more, two-dimensional electron gas layers 2DEG having sufficient carrier concentrations are formed between the gate electrode G and the contact layer 17S and between the gate electrode G and the contact layer 17D.

[0036] The layer structures of the gate barrier layers 16A and 16B are not limited to these. For example, the gate barrier layer 16A may have a single layer structure or a stacked structure of three or more layers, and the gate barrier layer 16B may also have a single layer structure or a stacked structure of two or more layers.

[0037] The contact layer 17 constitutes a part of the current path between the source electrode S and the drain electrode D, which are arranged with the gate electrode G therebetween. As shown in Fig. 1, the contact layer 17 includes a contact layer 17S provided below the source electrode S, which is arranged with the gate electrode G therebetween, and a contact layer 17D provided below the drain electrode. The contact layers 17S and 17D are each electrically connected to the two-dimensional electron gas layer 2DEG.

[0038] The contact layers 17S and 17D each have a bottom surface within the buffer layer 12, for example, and an upper surface above the gate barrier layer 16. The contact layers 17S and 17D are made of, for example, GaN (gallium nitride). １８ cm －３ 10 above ２１ cm －３ The contact layers 17S and 17D have carrier concentrations in the following ranges and contain, for example, silicon (Si) as a dopant: The contact layers 17S and 17D are each formed by, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), or sputtering.

[0039] The gate electrode G, the source electrode S, and the drain electrode D are all made of a conductive material. The gate electrode G, the source electrode S, and the drain electrode D are all provided on a semiconductor layer. The gate electrode G is disposed between the source electrode S and the drain electrode D.

[0040] The gate electrode G is a Schottky gate that forms a Schottky junction by making contact with the nitride semiconductor that constitutes the barrier layer 15 without an insulating film therebetween. The gate electrode G has an asymmetric cross-sectional shape. Specifically, as shown in FIG. 1 , a portion of the gate electrode G is in contact with the barrier layer 15. The gate electrode G has a bottom portion that is in contact with the barrier layer 15, and one end portion extends along the side surface of the gate barrier layer 16A and protrudes up to a portion of the upper surface of the gate barrier layer 16A. The other end portion extends along the side surface of the gate barrier layer 16B and protrudes up to a portion of the upper surface of the gate barrier layer 16B. This results in an asymmetric, approximately V-shaped configuration.

[0041] As described above, the gate barrier layer 16A provided between the gate electrode G and the contact layer 17S has a thickness greater than that of the gate barrier layer 16B provided between the gate electrode G and the contact layer 17D. This makes the capacitance between the gate electrode G and the source electrode S (contact layer 17S) smaller than the capacitance between the gate electrode G and the drain electrode D (contact layer 17D). That is, the resistance between the gate electrode G and the source electrode S (contact layer 17S) is reduced compared to the resistance between the gate electrode G and the drain electrode D (contact layer 17D). This makes it possible to improve the alternating conductance (gm) while ensuring the breakdown voltage between the gate electrode G and the drain electrode D (contact layer 17D), to which a high voltage is applied.

[0042] The gate electrode G may have a two-layer structure in which, for example, a Ni (nickel) layer and an Au (gold) layer are laminated in this order.

[0043] As described above, the source electrode S and the drain electrode D are provided on a pair of contact layers 17 that are arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G interposed therebetween. The source electrode S and the drain electrode D may have a structure in which a Ti (titanium) layer, an Al (aluminum) layer, a Ni (nickel) layer, and an Au (gold) layer are sequentially stacked.

[0044] The gate barrier layer 16 between the gate electrode G and the source electrode S and between the gate electrode G and the drain electrode D may be covered with an insulating film. The insulating film may be, for example, Al ２ O ３ (aluminum oxide), SiO ２ (silicon dioxide), Si ３ N ４ (silicon nitride) or HfO ２ The insulating film may be a single layer film made of the above-mentioned constituent material, or a multilayer film in which multiple layers made of the above-mentioned constituent material are stacked.

[0045] 4A to 4I, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described. 4A to 4I are cross-sectional views showing the steps of the method for manufacturing the semiconductor device 1.

[0046] 4A, for example, a buffer layer 12, a channel layer 13, a spacer layer 14, and a barrier layer 15 are epitaxially grown in sequence on a substrate 11. At this time, by growing the barrier layer 15 thick enough to generate a two-dimensional electron gas layer 2DEG at the heterointerface (interface K34), a transistor operating in depletion mode (D-mode) can be realized. Although the substrate 11 can be a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, or a ScAlMgO substrate, the following description will be given using a Si substrate as an example.

[0047] For example, first, a Si substrate having a (111) plane as its main surface is placed in a MOCVD (metal organic chemical vapor deposition) apparatus and thermally cleaned for about 10 minutes at 1000° C. After that, AlN is epitaxially grown at about 700° C. to 1100° C. to a thickness of about 100 nm to 300 nm, thereby forming the buffer layer 12.

[0048] Next, a channel layer 13 is formed on the buffer layer 12 by epitaxially growing, for example, GaN at approximately 900°C to 1100°C to a thickness of 500 nm to 2000 nm. Thereafter, a spacer layer 14 is formed on the channel layer 13 by epitaxially growing, for example, AlN at approximately 900°C to 1100°C to a thickness of approximately 0.5 nm to 1.5 nm. Subsequently, a barrier layer 15 is formed on the spacer layer 14 by epitaxially growing, for example, AlInN at 700°C to 900°C to a thickness of approximately 1 nm to 10 nm.

[0049] 4B, a mask (regrowth mask 21) for regrowing the first layer 16A1 of the gate barrier layer 16A is deposited and patterned. The regrowth mask 21 is made of, for example, silicon nitride (Si３ N ４ ) and silicon oxide (SiO ２ ) can be formed using

[0050] 4C, a first layer 16A1 is regrown on the barrier layer 15 exposed from the regrowth mask 21, and then the regrowth mask 21 is removed as shown in FIG. 4D. By removing the regrowth mask 21 using wet etching, damage to the crystals constituting the barrier layer 15 can be prevented.

[0051] 4E, a mask (regrowth mask 22) for regrowing the second layer 16A2 of the gate barrier layer 16A and the gate barrier layer 16B is formed so as to uniformly cover the surfaces of the barrier layer 15 and the first layer 16A1 of the gate barrier layer 16A.

[0052] Next, anisotropic etching is performed on the entire surface of the regrowth mask 22. For example, fluorine (F)-based or chlorine (Cl)-based dry etching is used. The thickness of the regrowth mask 22 in the stacking direction on the side surfaces of the first layer 16A1 is thicker than in other regions. Therefore, after the etching, as shown in FIG. 4F, the regrowth mask 22 remains only on the side surfaces of the first layer 16A1.

[0053] 4G, the second layer 16A2 and the gate barrier layer 16B are regrown using a regrowth mask 22. Specifically, the second layer 16A2 is regrown on the first layer 16A1 exposed by the regrowth mask 22, and the gate barrier layer 16B is regrown on the barrier layer 15 exposed by the regrowth mask 22. At this time, the thicknesses of the second layer 16A2 and the gate barrier layer 16B can be determined by the breakdown voltage and resistance between the gate electrode G and the drain electrode D, which are in a trade-off relationship. For example, if the gate barrier layer 16B is too thick, the breakdown voltage will be low, and if it is too thin, the resistance will be high.

[0054] 4H, a continuous regrowth mask 23 is formed on the second layer 16A2 and the gate barrier layer 16B to regrow the contact layer 17. Note that this step can be omitted if the source electrode S and the drain electrode D are formed directly on the gate barrier layers 16A and 16B, respectively, to obtain ohmic characteristics.

[0055] Next, the regrowth mask 23 is patterned, and using the regrowth mask 23 as a mask, grooves are formed by, for example, dry etching, reaching the buffer layer 12. Thereafter, as shown in FIG. 4I, contact layers 17S and 17D having n-type conductivity are grown by, for example, MOCVD or sputtering, and further, a source electrode S and a drain electrode D are formed.

[0056] Thereafter, the regrowth mask 23 is removed by wet etching, and a lift-off process is performed to form the gate electrode G. Through the above steps, the semiconductor device 1 shown in FIG.

[0057] [1-3. Actions and Effects] In recent years, research and development of HEMTs using nitride semiconductors has been actively conducted. Nitride semiconductors have a larger band gap than Si, GaAs, etc., and have polarization specific to hexagonal crystals. Therefore, HEMTs using nitride semiconductors are expected to be transistors that can achieve low resistance, high breakdown voltage, and high-speed operation.

[0058] Specifically, HEMTs are expected to be applied to power devices, radio frequency (RF) devices, etc. For example, HEMTs using AlGaN for the barrier layer have been put to practical use in base stations for satellite communications or wireless communications. HEMTs using AlInN for the barrier layer can obtain a higher two-dimensional electron gas concentration than HEMTs using AlGaN for the barrier layer, and are therefore expected to enable even higher output.

[0059] In power amplifiers for fifth-generation mobile communications (5G), which use radio waves in higher frequency bands, it is desirable to reduce the current flowing through the gate driver due to space limitations within the communications device, and to improve gain in order to reduce power consumption through higher efficiency.

[0060] To reduce the driver current, it is necessary to reduce the leakage current of the transistors used inside the device. This can be achieved by reducing damage to the crystal layer directly below the gate. Also, to improve gain, it is necessary to improve gm. This can be achieved by reducing the source resistance.

[0061] 5 is a schematic diagram illustrating an example of a cross-sectional configuration of a typical semiconductor device 100 as a comparative example. The semiconductor device 100 includes a buffer layer 112, a channel layer 1113, a spacer layer 114, and a barrier layer 115 stacked in this order on a substrate 111, and a pair of contact layers 117 are provided on both ends of the channel layer 1113, the spacer layer 114, and the barrier layer 115. In the semiconductor device 100, a T-shaped gate electrode G, for example, is provided on the barrier layer 115, and a source electrode S and a drain electrode D are provided on the pair of contact layers 117, respectively.

[0062] The gate electrode G of the semiconductor device 100 can be manufactured, for example, as follows. First, as shown in FIG. 6A, a buffer layer 112, a channel layer 113, a spacer layer 114, and a barrier layer 115 are epitaxially grown in this order on the substrate 11. Next, as shown in FIG. 6B, three resist films (resist films 121, 122, and 123) are patterned on the barrier layer 115 using electron beam lithography. Subsequently, as shown in FIG. 6C, the gate electrode G is formed, and then the resist films 121, 122, and 123 are removed as shown in FIG. 6D.

[0063] In the semiconductor device 100 manufactured in this manner, the thickness between the barrier layer 115 and the portion of the gate electrode G that protrudes in the XY plane direction is uniform on both the source electrode S side and the drain electrode D side. Therefore, it is not possible to arbitrarily adjust the thickness of the gate barrier layer between the gate electrode G and the source electrode S and between the gate electrode and the drain electrode D, and it is not possible to reduce the source resistance.

[0064] In contrast, in the semiconductor device 1 of this embodiment, in a laminated structure in which a buffer layer 12, a channel layer 13, a spacer layer 14, and a barrier layer 15 are laminated in this order on a substrate 11, gate barrier layers 16A and 16B are provided between a gate electrode G provided in contact with the barrier layer 15 and a pair of contact layers 17 (a contact layer 17S on which a source electrode S is laminated and a contact layer 17D on which a drain electrode D is laminated) arranged opposite each other in the in-plane direction of the substrate 11, with the gate electrode G sandwiched therebetween. The gate barrier layer 16A provided between the gate electrode G and the contact layer 17S has a thickness larger than that of the gate barrier layer 16B provided between the gate electrode G and the contact layer 17D.

[0065] This increases the carrier concentration of the two-dimensional electron gas layer 2DEG between the gate electrode G and the contact layer 17S, thereby reducing the source resistance and improving gm.

[0066] As described above, the semiconductor device 1 of this embodiment can improve the device characteristics. For example, improved efficiency of the power amplifier can reduce power consumption, thereby extending the operating time of a communication device or the like equipped with the device.

[0067] Furthermore, in the semiconductor device 1 of this embodiment, the regrowth masks 21, 22, and 23 formed on the barrier layer 15 are removed using wet etching, which reduces damage to the barrier layer 15 compared to when dry etching is performed directly below the gate electrode G. This reduces leakage current, which in turn makes it possible to further improve device characteristics, such as extending operating time through reduced power consumption.

[0068] Next, modifications, examples, and application examples of the present disclosure will be described. Note that components corresponding to those in the semiconductor device of the above embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0069] 2. Modification FIG. 7 is a schematic diagram illustrating an example of a cross-sectional configuration of a semiconductor device (semiconductor device 1A) according to a modification of the present disclosure.

[0070] In the above embodiment, the configuration of a semiconductor device operating in D-mode is shown, but by omitting the barrier layer 15 or thinning it to about 2 nm to prevent the generation of a two-dimensional electron gas layer 2DEG below the gate electrode G, a transistor operating in enhancement mode (E-mode) can be realized.

[0071] The semiconductor device 1A has a layered structure in which a substrate 11, a buffer layer 12, a channel layer 13, a spacer layer 14, and a gate barrier layer 16 are stacked in this order. The semiconductor device 1A further includes a gate electrode G, a pair of contact layers 17 arranged opposite each other in the in-plane direction (XY plane direction) of the substrate 11 with the gate electrode G interposed therebetween, and a source electrode S and a drain electrode D provided on the pair of contact layers 17. In this modification, the gate electrode G is provided in contact with the spacer layer 4. The gate barrier layers 16 are respectively provided between the gate electrode G and the pair of contact layers 17. The gate barrier layer 16A provided between the gate electrode G and the contact layer 17 (contact layer 17S) on which the source electrode S is stacked has a thickness greater than the gate barrier layer 16B provided between the gate electrode G and the contact layer 17 (contact layer 17D) on which the drain electrode D is stacked. The semiconductor device 1A has, for example, a Schottky gate structure.

[0072] Here, the substrate 11 corresponds to a specific example of a "substrate" in the modified example of the present disclosure. The channel layer 13 corresponds to a specific example of a "first nitride semiconductor layer" in the modified example of the present disclosure, and the spacer layer 14 corresponds to a specific example of a "second nitride semiconductor layer" in the modified example of the present disclosure. Of the pair of contact layers 17, the contact layer 17 on which the source electrode S is stacked corresponds to a specific example of a "first ohmic electrode" in the modified example of the present disclosure, and the contact layer 17 on which the drain electrode D is stacked corresponds to a specific example of a "second ohmic electrode" in the modified example of the present disclosure. The gate barrier layer 16A corresponds to a specific example of a "first gate barrier film" in the modified example of the present disclosure, and the gate barrier layer 16B corresponds to a specific example of a "second gate barrier film" in the modified example of the present disclosure.

[0073] The semiconductor device 1A according to this modification is a HEMT having a two-dimensional electron gas layer 2DEG as a channel. In the semiconductor device 1A, the two-dimensional electron gas layer 2DEG is formed in the channel layer 13 near the interface K34 between the channel layer 13 and the spacer layer 14, except for a portion below the gate electrode G.

[0074] Even with this configuration, the same effects as those of the above embodiment can be obtained.

[0075] 3. Application Examples (3-1. Semiconductor Module) Next, a semiconductor module, which is a first application example of the technology according to the present disclosure, will be described with reference to Fig. 8. Fig. 8 is a schematic perspective view showing the configuration of a semiconductor module 1000.

[0076] 8 , the semiconductor module 1000 is, for example, an antenna-integrated module in which an edge antenna 1020 and multiple front-end components are mounted as a module on a single chip 1050. For example, multiple edge antennas 1020 are formed in an array on the chip 1050. The front-end components include, for example, a switch 1010, a low-noise amplifier 1041, a band-pass filter 1042, and a power amplifier 1043. The semiconductor module 1000 can be used, for example, as a transceiver for wireless communication.

[0077] The semiconductor module 1000 includes a semiconductor device (e.g., semiconductor device 1) according to the above-described embodiments as a transistor constituting, for example, a switch 1010, a low-noise amplifier 1041, or a power amplifier 1043. For example, in fifth-generation mobile communications (5G), which use radio waves in a higher frequency band, radio wave propagation loss increases. Therefore, a semiconductor module 1000 compatible with 5G is desired to transmit radio waves at higher power. The semiconductor module 1000 including the semiconductor device 10 can improve device characteristics, enabling high-output, low-power, and highly reliable wireless communications. In other words, the semiconductor module 1000 can be more suitably used for fifth-generation mobile communications (5G).

[0078] (3-2. Wireless Communication Device) Next, a wireless communication device that is a second application example of the technology according to the present disclosure will be described with reference to Fig. 9. Fig. 9 is a block diagram showing the configuration of a wireless communication device 2000.

[0079] 9 , wireless communication device 2000 includes an antenna ANT, an antenna switch circuit 2003, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F (e.g., a wireless local area network (W-LAN) or Bluetooth (registered trademark)). Wireless communication device 2000 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0080] In the wireless communication device 2000, during transmission, a transmission signal is output from the baseband unit BB to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the antenna switch circuit 203. Furthermore, during reception in the wireless communication device 2000, a received signal is input from the antenna ANT to the baseband unit BB via the antenna switch circuit 2003 and the radio frequency integrated circuit RFIC. The received signal processed by the baseband unit BB is output to the outside of the wireless communication device 2000, for example, from the audio output unit MIC, the data output unit DT, or the interface unit I / F.

[0081] The wireless communication device 2000 includes a semiconductor device (e.g., semiconductor device 1) according to the above-described embodiment as a transistor constituting the antenna switch circuit 2003, the high-power amplifier HPA, the radio-frequency integrated circuit RFIC, the baseband unit BB, etc. This allows the wireless communication device 2000 to further improve device characteristics, thereby enabling wireless communication with high output, low power consumption, and high reliability.

[0082] The technology according to the present disclosure has been described above by giving embodiments, modifications, examples, and application examples. However, the technology according to the present disclosure is not limited to the above embodiments, etc., and various modifications are possible.

[0083] Furthermore, not all of the configurations and operations described in the embodiments are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any component not recited in an independent claim showing the highest concept of the present disclosure should be understood as an optional component.

[0084] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0085] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to terms similar to these and terms of a similar meaning.

[0086] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0087] The present technology can also be configured as follows: According to the present technology configured as follows, the resistance between the gate electrode and the first ohmic electrode can be reduced, thereby improving device characteristics. a first nitride semiconductor layer provided on one surface of the substrate; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of the interface of the first nitride semiconductor layer with the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode arranged opposite each other in an in-plane direction of the substrate with the gate electrode interposed therebetween and electrically connected to the two-dimensional electron gas layer; a first gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode, the first gate barrier film containing a nitride semiconductor and having a first thickness; and a second gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, the second gate barrier film containing a nitride semiconductor and having a second thickness smaller than the first thickness. (2) The semiconductor device according to (1), wherein the gate electrode extends along each side surface of the first gate barrier film and the second gate barrier film and extends up to the upper surfaces of the first gate barrier film and the second gate barrier film. (3) The semiconductor device according to (1) or (2), wherein the gate electrode has an asymmetric cross-sectional shape. (4) The semiconductor device according to (3), wherein the gate electrode has a substantially V-shaped cross-sectional shape. (5) The semiconductor device according to any one of (1) to (4), wherein a capacitance between the gate electrode and the first ohmic electrode is smaller than a capacitance between the gate electrode and the second ohmic electrode. (6) The semiconductor device according to any one of (1) to (5), wherein the first gate barrier film has a thickness of 1 nm or more. (7) The semiconductor device according to any one of (1) to (6), wherein the first gate barrier film is a stacked film including a first layer and a second layer.(8) The semiconductor device according to any one of (1) to (6), wherein the first gate barrier film is composed of a single layer or multiple layers. (9) The semiconductor device according to (7), wherein the first layer and the second layer are stacked in this order from the second nitride semiconductor layer side, and the second layer and the second gate barrier film have the same composition. (10) The semiconductor device according to any one of (1) to (9), wherein the second gate barrier film has a film thickness of 1 nm or more. (11) The semiconductor device according to any one of (1) to (10), wherein the second gate barrier film is composed of a single layer or multiple layers. (12) The semiconductor device according to any one of (1) to (11), wherein the first gate barrier film and the second gate barrier film are composed of any one of AlInN (aluminum indium nitride), AlGaN (aluminum gallium nitride), and AlInGaN (aluminum indium gallium nitride). (13) The semiconductor device according to any one of (1) to (12), wherein the second nitride semiconductor layer is made of any one of AlInN (aluminum indium nitride), AlGaN (aluminum gallium nitride), and AlInGaN (aluminum indium gallium nitride). (14) The semiconductor device according to any one of (1) to (13), wherein the first nitride semiconductor layer contains at least one of GaN (gallium nitride), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), and AlInGaN (aluminum indium gallium nitride). (15) The semiconductor device according to any one of (1) to (14), wherein the substrate contains at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), and AlN (aluminum nitride).a first nitride semiconductor layer provided on one surface of the substrate; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode arranged opposite each other in an in-plane direction of the substrate with the gate electrode therebetween and electrically connected to the two-dimensional electron gas layer; a first gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode, the first gate barrier film containing a nitride semiconductor and having a first thickness; and a second gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, the second gate barrier film containing a nitride semiconductor and having a second thickness smaller than the first thickness. a first nitride semiconductor layer provided on one surface of the substrate; a second nitride semiconductor layer stacked on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode arranged opposite each other in an in-plane direction of the substrate with the gate electrode therebetween and electrically connected to the two-dimensional electron gas layer; a first gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode, the first gate barrier film containing a nitride semiconductor and having a first film thickness; and a second gate barrier film stacked on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode, the second gate barrier film containing a nitride semiconductor and having a second film thickness smaller than the first film thickness.

[0088] This application claims priority based on Japanese Patent Application No. 2023-118660, filed on July 20, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0089] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

a first nitride semiconductor layer provided on one surface of the substrate; a second nitride semiconductor layer laminated on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of an interface of the first nitride semiconductor layer with the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode disposed opposite each other in an in-plane direction of the substrate with the gate electrode therebetween and electrically connected to the two-dimensional electron gas layer; a first gate barrier film comprising a nitride semiconductor and having a first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode; and a second gate barrier film comprising a nitride semiconductor and having a second thickness smaller than the first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode.

2. The semiconductor device of claim 1, wherein the gate electrode extends along each side of the first gate barrier film and the second gate barrier film and projects up to the upper surfaces of the first gate barrier film and the second gate barrier film.

3. The semiconductor device according to claim 1, wherein said gate electrode has an asymmetric cross-sectional shape.

4. The semiconductor device according to claim 3, wherein said gate electrode has a substantially V-shaped cross section.

5. The semiconductor device of claim 1, wherein a capacitance between said gate electrode and said first ohmic electrode is less than a capacitance between said gate electrode and said second ohmic electrode.

6. The semiconductor device according to claim 1, wherein the first gate barrier film has a thickness of 1 nm or more.

7. The semiconductor device according to claim 1, wherein the first gate barrier film is made of a laminated film including a first layer and a second layer.

8. The semiconductor device according to claim 1, wherein the first gate barrier film consists of a single layer or multiple layers.

9. The semiconductor device according to claim 7, wherein the first layer and the second layer are stacked in this order from the second nitride semiconductor layer side, and the second layer and the second gate barrier film have the same composition.

10. The semiconductor device according to claim 1, wherein the second gate barrier film has a thickness of 1 nm or more.

11. The semiconductor device according to claim 1, wherein the second gate barrier film consists of a single layer or multiple layers.

12. The semiconductor device of claim 1, wherein the first gate barrier film and the second gate barrier film are made of any one of AlInN (aluminum indium nitride), AlGaN (aluminum gallium nitride) and AlInGaN (aluminum indium gallium nitride).

13. The semiconductor device of claim 1, wherein the second nitride semiconductor layer is made of any one of AlInN (aluminum indium nitride), AlGaN (aluminum gallium nitride) and AlInGaN (aluminum indium gallium nitride).

14. The semiconductor device of claim 1, wherein the first nitride semiconductor layer comprises at least one of GaN (gallium nitride), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride) and AlInGaN (aluminum indium gallium nitride).

15. The semiconductor device of claim 1, wherein the substrate comprises at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), and AlN (aluminum nitride).

16. A semiconductor module comprising: a substrate; a first nitride semiconductor layer provided on one surface side of the substrate; a second nitride semiconductor layer laminated on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of an interface of the first nitride semiconductor layer with the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode arranged to face each other in an in-plane direction of the substrate with the gate electrode between them and electrically connected to the two-dimensional electron gas layer; a first gate barrier film comprising a nitride semiconductor and having a first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode; and a second gate barrier film comprising a nitride semiconductor and having a second thickness smaller than the first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode.

17. A communication device comprising: a substrate; a first nitride semiconductor layer provided on one surface of the substrate; a second nitride semiconductor layer laminated on the first nitride semiconductor layer and having a band gap different from that of the first nitride semiconductor layer; a two-dimensional electron gas layer formed in the vicinity of an interface of the first nitride semiconductor layer with the second nitride semiconductor layer; a gate electrode provided in contact with the second nitride semiconductor layer; a first ohmic electrode and a second ohmic electrode arranged to face each other in an in-plane direction of the substrate with the gate electrode between them and electrically connected to the two-dimensional electron gas layer; a first gate barrier film comprising a nitride semiconductor and having a first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the first ohmic electrode; and a second gate barrier film comprising a nitride semiconductor and having a second thickness smaller than the first thickness, laminated on the second nitride semiconductor layer between the gate electrode and the second ohmic electrode.

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