Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device comprising an active part provided to a semiconductor substrate, and a temperature-sensitive part provided above the semiconductor substrate. The temperature-sensitive part has: a temperature-sensitive diode provided above the semiconductor substrate; a first interlayer insulation film provided above the temperature-sensitive diode; a temperature-sensitive contact portion provided extending from the upper surface to the lower surface of the first interlayer insulation film; and a housing portion provided below the temperature-sensitive contact portion. A bottom-surface corner section of the temperature-sensitive contact portion is in contact with the temperature-sensitive diode, and the bottom surface of the temperature-sensitive contact portion is in contact with the housing portion.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 describes a "semiconductor device with an integrated PN diode temperature sensor and a method for manufacturing the same." [Prior art documents] [Patent documents] [Patent document 1] U.S. Patent Application Publication No. 2019 / 0172770 General disclosure

[0003] In a first aspect of the present invention, there is provided a semiconductor device comprising an active portion provided on a semiconductor substrate and a temperature-sensing portion provided above the semiconductor substrate, wherein the temperature-sensing portion has a temperature-sensing diode provided above the semiconductor substrate, a first interlayer insulating film provided above the temperature-sensing diode, a temperature-sensing contact portion extending from the upper surface to the lower surface of the first interlayer insulating film, and a housing portion provided below the temperature-sensing contact portion, wherein a bottom corner portion of the temperature-sensing contact portion contacts the temperature-sensing diode and the bottom surface of the temperature-sensing contact portion contacts the housing portion.

[0004] In the semiconductor device, a side surface of the temperature sensitive diode may be in contact with a side surface of the housing portion.

[0005] Any of the above semiconductor devices may further include a second interlayer insulating film provided between the temperature sensitive diode and the semiconductor substrate in the depth direction of the semiconductor substrate.

[0006] In any of the above semiconductor devices, the upper surface of the second interlayer insulating film may be in contact with the lower surface of the temperature sensitive diode and the lower surface of the housing portion.

[0007] In any of the above semiconductor devices, the housing portion may be a region of the first interlayer insulating film that is provided below the temperature-sensitive contact portion.

[0008] In any of the above semiconductor devices, the housing portion may be the second interlayer insulating film provided above the semiconductor substrate.

[0009] In any of the above semiconductor devices, the second interlayer insulating film may have a recess on its upper surface, and the temperature-sensitive diode may be provided in the recess of the second interlayer insulating film.

[0010] In any of the above semiconductor devices, the housing portion may have polysilicon of a different conductivity type from that of the contact region of the temperature sensitive diode.

[0011] In any of the above semiconductor devices, the housing portion may have polysilicon of the same conductivity type as the contact region of the temperature sensitive diode and having a lower doping concentration than the contact region.

[0012] In any of the above semiconductor devices, the temperature-sensitive diode may have a temperature-sensitive anode region provided above the semiconductor substrate, and a temperature-sensitive cathode region provided above the semiconductor substrate and in contact with the temperature-sensitive anode region.

[0013] In any of the above semiconductor devices, the temperature-sensitive contact portion may have a barrier metal film provided at the corners of the bottom surface of the temperature-sensitive contact portion, and a plug portion provided in contact with the inner side of the barrier metal film.

[0014] In any of the above semiconductor devices, the active portion may have a plurality of active contact portions provided on the front surface of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the bottom surface of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the housing portion.

[0016] In any of the above semiconductor devices, the temperature sensitive diode may contact the bottom surface of the temperature sensitive contact portion over an area from the bottom corner to 10% to 40% of the bottom surface of the temperature sensitive contact portion.

[0017] In any of the above semiconductor devices, the sidewall of the temperature-sensitive contact portion may have a trench contact structure in contact with a side surface of the temperature-sensitive diode.

[0018] In any of the above semiconductor devices, the sidewall of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the first interlayer insulating film, and the temperature-sensitive diode may be in contact with the sidewall of the temperature-sensitive contact portion over an area from the bottom corner to 10% to 90% of the sidewall of the temperature-sensitive contact portion.

[0019] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming an active portion in a semiconductor substrate and forming a temperature-sensing portion above the semiconductor substrate, wherein the step of forming the temperature-sensing portion comprises the steps of forming a temperature-sensing diode above the semiconductor substrate, forming a first interlayer insulating film above the temperature-sensing diode, forming a temperature-sensing contact portion extending from the upper surface to the lower surface of the first interlayer insulating film, and forming a housing portion below the temperature-sensing contact portion, wherein a bottom corner portion of the temperature-sensing contact portion contacts the temperature-sensing diode and the bottom surface of the temperature-sensing contact portion contacts the housing portion.

[0020] In a third aspect of the present invention, there is provided a semiconductor device having an active portion and an inactive portion, wherein the inactive portion has a polycrystalline portion provided above a semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, a first inactive contact portion extending from the upper surface to the lower surface of the interlayer insulating film, and a housing portion provided below the first inactive contact portion, wherein a bottom corner portion of the first inactive contact portion contacts the polycrystalline portion and the bottom surface of the first inactive contact portion contacts the housing portion.

[0021] In the semiconductor device, a side surface of the polycrystalline portion may be in contact with a side surface of the housing portion.

[0022] In any of the above semiconductor devices, the housing portion may be a region of the interlayer insulating film that is provided below the first inactive contact portion.

[0023] In any of the above semiconductor devices, the first inactive contact portion may have a barrier metal film provided at a corner portion of the bottom surface of the first inactive contact portion, and a plug portion provided in contact with the inner side of the barrier metal film.

[0024] In any of the above semiconductor devices, the active portion may have a plurality of active contact portions provided on the front surface of the semiconductor substrate.

[0025] In any of the above semiconductor devices, the bottom surface of the first inactive contact portion may be in contact with the polycrystalline portion and the housing portion.

[0026] In any of the above semiconductor devices, the polycrystalline portion may contact the bottom surface of the first non-active contact portion from the bottom corner to an area of ​​10% to 40% of the bottom surface of the first non-active contact portion.

[0027] In any of the above semiconductor devices, the sidewall of the first inactive contact portion may have a trench contact structure in contact with a side surface of the polycrystalline portion.

[0028] In any of the above semiconductor devices, a sidewall of the first inactive contact portion may be in contact with the polycrystalline portion and the interlayer insulating film. The polycrystalline portion may be in contact with the sidewall of the first inactive contact portion over an area from the bottom corner to 10% to 90% of the sidewall of the first inactive contact portion.

[0029] The semiconductor device may further include a gate trench portion provided on a front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, wherein the polycrystalline portion may be connected to the gate metal layer through the first inactive contact portion.

[0030] The semiconductor device may further include a dummy trench portion provided on a front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the polycrystalline portion may be connected to the emitter electrode via the first inactive contact portion and to the dummy conductive portion.

[0031] The semiconductor device may further include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, and the polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion.

[0032] Any of the above semiconductor devices may further include a field insulating film provided below the interlayer insulating film, and the first inactive contact portion may be provided above the polycrystalline portion above the field insulating film.

[0033] Any of the above semiconductor devices may include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate, an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, and a field insulating film provided below the interlayer insulating film. The polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion. The housing portion may be a region of the field insulating film provided below the first inactive contact portion.

[0034] Any of the above semiconductor devices may include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring. The polycrystalline portion may be connected to the edge metal layer via the first inactive contact portion. The polycrystalline portion may include a contact region in contact with the housing portion. The housing portion may include polysilicon having a lower impurity concentration than the contact region of the polycrystalline portion.

[0035] Any of the above semiconductor devices may include a pad electrode provided above the semiconductor substrate, and the polycrystalline portion may be connected to the pad electrode via the first inactive contact portion.

[0036] In a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of forming an active portion and forming an inactive portion, wherein the step of forming the inactive portion comprises the steps of forming a polycrystalline portion above a semiconductor substrate, forming an interlayer insulating film above the polycrystalline portion, forming a first inactive contact portion extending from the upper surface to the lower surface of the interlayer insulating film, and forming a housing portion below the first inactive contact portion, wherein a bottom corner portion of the first inactive contact portion contacts the polycrystalline portion and the bottom surface of the first inactive contact portion contacts the housing portion.

[0037] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0038] 1A shows an example of an enlarged view of the top surface of the semiconductor device 100. 1B shows an example of a cross section taken along a-a' in FIG. 1A. 1C shows an enlarged view of the top surface of a modified example of the semiconductor device 100. 2D shows an example of a cross section taken along a-b-b' in FIG. 2A. 2E shows an example of a top view of the semiconductor device 100. 2F shows an example of a cross section of the semiconductor device 100 including a temperature sensitive portion 180. 2G shows an example of an enlarged view of the cross section of the semiconductor device 100. 2G shows an enlarged view of a cross section of a modified example of the semiconductor device 100. 2G shows an example of an enlarged view of the cross section ... when a void 302 occurs in the temperature sensitive contact portion 188. 2G shows another example of an enlarged view of the cross section of the semiconductor device 100 when a void 302 occurs in the temperature sensitive contact portion 188. 2G shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive portion 180. 2G shows an enlarged view of the cross section of the modified example of the semiconductor device 100. 2G shows an enlarged view of the cross section of the modified example of the semiconductor device 100. 9 shows an example of an enlarged cross-section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. Another example of an enlarged cross-section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188 is shown. A flowchart showing an example of a manufacturing process for the semiconductor device 100. An example of electrical connections between the components of the semiconductor device 100 shown in FIG. 3 is shown. An example of an enlarged top view of the semiconductor device 100 is shown. An example of a c-c' cross-section in FIG. 9 is shown. An example of a d-d' cross-section in FIG. 9 is shown. An example of an enlarged d-d' cross-section in FIG. 9 is shown. An example of an enlarged d-d' cross-section in FIG. 9 is shown when a void 302 occurs in the first inactive contact portion 134. Another example of an enlarged d-d' cross-section in FIG. 9 is shown when a void 302 occurs in the first inactive contact portion 134. An example of a d-d' cross-section in FIG. 9 is shown. An example of an enlarged d-d' cross-section in FIG. 9 is shown. 9 shows an example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. FIG. 10 shows another example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. FIG. 11 shows an example of an e-e' cross section in FIG. 9. FIG. 12 shows an example of an enlarged view of the e-e' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134.Another example of an enlarged view of the e-e' cross-section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134 is shown. An example of the e-e' cross-section in FIG. 9 is shown. An example of an enlarged view of the e-e' cross-section in FIG. 9 is shown. An example of an enlarged view of the e-e' cross-section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134 is shown. Another example of an enlarged view of the e-e' cross-section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134 is shown. An example of a top view of the semiconductor device 100 is shown. An example of the region R in FIG. 19A is shown. An example of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. Another example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. An example of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. Another example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. An example of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. Another example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. An example of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B is shown. An example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown. Another example of an enlarged view of the f-f' cross-section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134 is shown.19A. FIG. 19B shows an example of a cross section taken along line gg' in FIG. 19A. FIG. 19C shows an example of a region P in FIG. 19A. FIG. 19D shows another example of a region P in FIG. 19A. FIG. 19E shows another example of a cross section taken along line gg' in FIG. 19A. FIG. 19F shows a flowchart illustrating an example of a manufacturing process for the semiconductor device 100.

[0039] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0040] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0041] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0042] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0043] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0044] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0045] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is ND and the acceptor concentration is NA, the net doping concentration at any position is ND-NA. In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0046] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects in semiconductors, where vacancies (V), oxygen (O), and hydrogen (H) are bonded, Si-i-H defects in which interstitial silicon (Si-i) and hydrogen are bonded, and CiOi-H defects in which interstitial carbon (Ci) and interstitial oxygen (Oi) and hydrogen are bonded, function as donors that supply electrons. In this specification, these VOH defects may be referred to as hydrogen donors.

[0047] In this specification, the terms P+ type and N+ type refer to a doping concentration higher than that of P type or N type, and the terms P- type and N- type refer to a doping concentration lower than that of P type or N type. In addition, in this specification, the terms P++ type and N++ type refer to a doping concentration higher than that of P+ type or N+ type.

[0048] In this specification, chemical concentration refers to the concentration atomic density of impurities measured regardless of the state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be referred to as the net doping concentration. Carriers refer to charge carriers of electrons or holes. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. Furthermore, in an N-type region, the donor concentration is sufficiently greater than the acceptor concentration, so the carrier concentration in that region may also be referred to as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be referred to as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0049] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0050] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility occurs when carriers are scattered due to a disorder in the crystalline structure caused by lattice defects or the like. The reason for the decrease in carrier concentration is as follows. In the SR method, spreading resistance is measured and the carrier concentration is calculated from the measured spreading resistance. At this time, the carrier mobility is calculated using the carrier mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, the carrier mobility is decreased, but the carrier concentration is calculated using the carrier mobility in the crystalline state. Therefore, the value obtained is lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0051] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is adopted. In this specification, distance and length units may be expressed in cm (centimeter). In this case, various calculations may be performed by converting them to m (meter). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 １６ , and the display of 1E-16 is 1×10 －１６ Shows.

[0052] 1A shows an example of an enlarged view of the top surface of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10. The configuration of this figure may be repeatedly provided in the positive and negative directions of the X-axis.

[0053] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may be another transistor such as a MOSFET.

[0054] In this figure, the area around the active section 120 of the semiconductor device 100 is shown, and other areas are omitted. The active section 120 is the portion between the front surface 21 and the back surface 23 of the semiconductor substrate 10 through which the main current flows. The active section 120 will be described later. For example, an edge termination structure may be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side of the Y-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

[0055] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, another compound semiconductor substrate, or a diamond semiconductor substrate. The semiconductor substrate 10 in this example is a silicon substrate. Note that, in this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.

[0056] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of a front surface side metal layer. The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that although the semiconductor device 100 of this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0057] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0058] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal film made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0059] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0060] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. Inside the contact hole 55, a barrier metal film made of titanium or a titanium compound or the like and / or a plug portion made of tungsten or the like may be formed.

[0061] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a barrier metal film made of titanium or a titanium compound or the like and / or a plug portion made of tungsten or the like may be formed.

[0062] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 is provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0063] The gate trench portion 40 is an example of an active trench portion 122 provided in the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0064] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0065] The dummy trench portion 30 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may also have a U-shape on the front surface 21 of the semiconductor substrate 10, like the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0066] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0067] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and may not have dummy trench portions 30.

[0068] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0069] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0070] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0071] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0072] The base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0073] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0074] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0075] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is P+ type, for example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0076] 1B shows an example of the aa' cross section in FIG. 1A. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and an active contact section 124. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0077] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0078] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0079] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0080] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0081] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0082] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0083] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0084] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1.0E+12 cm －２ Above, 1.0E+13cm －２ The ion implantation dose of the accumulation region 16 may be 3.0E+12 cm －２ Above, 6.0E + 12cm －２ By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0085] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion may be an active trench portion 122 included in the active portion 120. Each trench portion is provided from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region does not necessarily mean that the trench portion is formed in the order of forming the doped region and then the trench portion. The trench portion penetrating the doped region also includes a trench portion formed after the trench portion is formed.

[0086] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0087] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0089] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided penetrating the interlayer insulating film 38. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, a phosphosilicate glass (PSG) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0090] The active contact portion 124 is provided on the front surface 21 of the semiconductor substrate 10. The active contact portion 124 may have a contact hole 54 and a metal layer filled inside the contact hole 54. The contact hole 54 may be filled with the same material as the emitter electrode 52, or a material different from that of the emitter electrode 52. The active contact portion 124 may include a barrier metal film 1242 provided in the contact hole 54 and in contact with the semiconductor substrate 10. The active contact portion 124 may include a plug portion 1244 provided in contact with the barrier metal film 1242 and filling the contact hole 54. The barrier metal film 1242 of the active contact portion 124 may contain titanium or a titanium compound, etc. The plug portion 1244 of the active contact portion 124 may contain a plug metal such as tungsten. The contact holes 55 and 56, and the metal layers filled inside the contact holes 55 and 56 may also have a similar configuration. The active portion 120 may have a plurality of active contact portions 124 provided on the front surface 21 of the semiconductor substrate 10. An alloy layer may be formed in contact with the barrier metal film 1242, and the alloy layer may be formed from a metal contained in the barrier metal film 1242 and a layer of the semiconductor substrate 10 or the like below the contact holes 54, 55, and 56. A region with a high impurity concentration may be formed in the layer of the semiconductor substrate 10 or the like below the contact holes 54, 55, and 56 at a location in contact with the alloy layer. The active contact portions 124 in this example have a planar contact structure, but may also have a trench contact structure as described below.

[0091] The back side lifetime control region 151 may be provided in the transistor portion 70. However, the back side lifetime control region 151 may be omitted. The back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons. By providing the back side lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0092] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams or protons may be used to form the lattice defects.

[0093] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0094] The back surface-side lifetime control region 151 may be formed by implantation from the back surface 23 side. This makes it easier to avoid any influence on the front surface 21 side of the semiconductor device 100. For example, the back surface-side lifetime control region 151 is formed by irradiating helium or protons from the back surface 23 side. Here, whether the back surface-side lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by acquiring the state of the front surface 21 side by the SR method or by measuring leakage current.

[0095] 2A shows an enlarged view of the top surface of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. The configuration of this figure may be repeatedly provided in both the positive and negative directions of the X axis.

[0096] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, which are provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of an active trench portion 122.

[0097] The dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0098] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0099] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion in the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0100] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0101] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0102] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0103] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0104] 2B shows an example of the b-b' cross section in FIG. 2A. The semiconductor device 100 of this example includes a back surface-side lifetime control region 151 and a front surface-side lifetime control region 152. However, the semiconductor device 100 does not necessarily have to include either the back surface-side lifetime control region 151 or the front surface-side lifetime control region 152. The semiconductor device 100 of this example includes a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20.

[0105] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0106] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0107] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0108] The back side lifetime control region 151 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the transistor portion 70, or may be provided only in the diode portion 80. This enables the semiconductor device 100 of this example to speed up the turn-off operation of the transistor portion 70 or the reverse recovery operation in the diode portion 80, thereby further improving switching loss. The back side lifetime control region 151 may be formed by a method similar to that used for the back side lifetime control region 151 of the other embodiments.

[0109] The front surface side lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. The front surface side lifetime control region 152 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the diode portion 80. The front surface side lifetime control region 152 is provided in the diode portion 80 and the boundary portion 90, and may not be provided in part of the transistor portion 70. The front surface side lifetime control region 152 can suppress hole injection from the transistor portion 70 and the diode portion 80, thereby reducing reverse recovery loss.

[0110] The front surface side lifetime control region 152 may be formed by any method among the methods for forming the back surface side lifetime control region 151. The elements, doses, etc. for forming the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.

[0111] The front surface side lifetime control region 152 is provided extending from the diode section 80 to the transistor section 70. The front surface side lifetime control region 152 may be formed by introducing a lifetime killer from the front surface 21 of the semiconductor substrate 10. The front surface side lifetime control region 152 may also be formed by irradiation from the back surface 23 side of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided below the gate trench section 40. When a particle beam or the like for forming the front surface side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0112] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure including a backside metal layer on the backside 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a lateral semiconductor structure that does not include a metal layer on the backside 23 side.

[0113] In this example, an RC-IGBT with a trench gate structure is described as an example of the semiconductor device 100. However, the semiconductor device 100 may be a semiconductor device with a planar gate structure, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0114] 3 shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a temperature-sensing unit 180. In this example, only some of the components of the semiconductor device 100 are shown, and some other components are omitted.

[0115] The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In this example, the X-axis and the Y-axis are parallel to either of the edges 102.

[0116] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is not shown in the figure.

[0117] The active section 120 may be provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 3 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In another example, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80. That is, the active section 120 may be provided with only the transistor section 70 as shown in FIG. 1A , or may be provided with both the transistor section 70 and the diode section 80 as shown in FIG. 2A , or may be provided with only the diode section 80.

[0118] In this example, the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the gate trench section 40 and the dummy trench section 30.

[0119] The diode section 80 may be a region obtained by projecting a cathode region 82 provided on the rear surface 23 of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10 may be located inside the diode section 80. A P+ type collector region 22 may be provided in a region of the rear surface 23 of the semiconductor substrate 10 other than the cathode region 82.

[0120] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. When viewed from above, the edge termination structure 140 is provided between the active section 120 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active section 120.

[0121] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. Each pad may be located near an edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0122] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 in the active portion 120. The semiconductor device 100 may include a gate wiring that connects the gate pad 112 and the gate trench portion 40. The gate wiring may be configured by either the gate metal layer 50 or the connection portion 25, or by combining both appropriately.

[0123] The sense electrode 114 is electrically connected to a current sense unit 115 provided below the sense electrode 114. The sense electrode 114 detects the current flowing in the current sense unit 115. The current sense unit 115 detects the current flowing in the transistor unit 70. The current sense unit 115 has a structure corresponding to the transistor unit 70. The current flowing in the current sense unit 115 is smaller than the current flowing in the transistor unit 70. A current proportional to the current flowing in the transistor unit 70 may flow in the current sense unit 115, simulating the operation of the transistor unit 70. The ratio of the current flowing in the current sense unit 115 to the current flowing in the transistor unit 70 is appropriately set. The current flowing in the transistor unit 70 can be monitored by using the current sense unit 115.

[0124] The temperature sensing unit 180 is provided on or inside the semiconductor substrate 10. In this example, the temperature sensing unit 180 is provided between the transistor units 70 in the center of the semiconductor device 100. The temperature sensing unit 180 detects the temperature of the active unit 120. The temperature sensing unit 180 may include a diode formed of monocrystalline or polycrystalline silicon. The temperature sensing unit 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip (semiconductor substrate 10) from overheating. The temperature sensing unit 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sensing unit 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature sensing unit 180.

[0125] The anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive unit 180. The anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive unit 180 by an anode wiring part 117 that is electrically connected to the temperature-sensitive anode region 182. The temperature-sensitive anode region 182 will be described later.

[0126] The cathode pad 118 is electrically connected to a temperature-sensitive cathode region 181 of the temperature-sensitive unit 180. The cathode pad 118 is electrically connected to the temperature-sensitive cathode region 181 of the temperature-sensitive unit 180 by a cathode wiring part 119 that is electrically connected to the temperature-sensitive cathode region 181. The temperature-sensitive cathode region 181 will be described later.

[0127] 4 shows an example of a cross section of a semiconductor device 100 including a temperature sensing portion 180. The temperature sensing portion 180 includes a temperature sensing diode 183, a first interlayer insulating film 36, a temperature sensing contact portion 188, and a housing portion 198. The temperature sensing portion 180 may include a second interlayer insulating film 37.

[0128] The temperature-sensitive diode 183 is provided above the semiconductor substrate 10. The temperature-sensitive diode 183 may be a PN diode including a temperature-sensitive anode region 182 provided above the semiconductor substrate 10 and a temperature-sensitive cathode region 181 provided above the semiconductor substrate 10 and in contact with the temperature-sensitive anode region 182. The temperature-sensitive cathode region 181 may be formed of an N-type semiconductor and function as the cathode of the PN diode. The temperature-sensitive anode region 182 may be formed of a P-type semiconductor and function as the anode of the PN diode. The material of the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 may be a polycrystalline semiconductor, for example, polysilicon.

[0129] A well region 17 may be provided in the semiconductor substrate 10 below the temperature-sensitive diode 183. The well region 17 provided below the temperature-sensitive diode 183 may be the same as the well region 17 provided on the peripheral side of the active portion 120 in FIG. 1A and may be formed in the same process.

[0130] The first interlayer insulating film 36 is provided above the temperature sensitive diode 183. "Above" may refer to the positive direction in the Z-axis direction with respect to the front surface 21 of the semiconductor substrate 10. The first interlayer insulating film 36 may be the interlayer insulating film 38. That is, the interlayer insulating film 38 may be a concept that includes both the first interlayer insulating film 36 and a second interlayer insulating film 37, which will be described later. The first interlayer insulating film 36 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0131] The temperature-sensitive contact portion 188 is provided to extend from the upper surface to the lower surface of the first interlayer insulating film 36. The contact hole 58 may be provided to penetrate the first interlayer insulating film 36. The temperature-sensitive contact portion 188 may include the contact hole 58 and a metal layer filled inside the contact hole 58. The detailed configuration of the temperature-sensitive contact portion 188 will be described later.

[0132] The cathode wiring portion 119 is electrically connected to the temperature-sensitive cathode region 181 via the contact hole 58. The cathode wiring portion 119 may be formed of a metal material. The cathode wiring portion 119 may be formed of the same material as the emitter electrode 52. The temperature-sensitive cathode region 181 may be electrically connected to the cathode pad 118 by the cathode wiring portion 119.

[0133] The anode wiring portion 117 is electrically connected to the temperature-sensitive anode region 182 via the contact hole 58. The anode wiring portion 117 may be made of a metal material. The anode wiring portion 117 may be made of the same material as the emitter electrode 52. The temperature-sensitive anode region 182 may be electrically connected to the anode pad 116 via the anode wiring portion 117.

[0134] The housing portion 198 is provided below the temperature-sensitive contact portion 188. The material of the housing portion 198 may be the same as the material of the first interlayer insulating film 36, the same as the material of the second interlayer insulating film 37, or the same as the material of the temperature-sensitive diode 183. The detailed configuration of the housing portion 198 will be described later.

[0135] The second interlayer insulating film 37 may be provided between the temperature sensing diode 183 and the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second interlayer insulating film 37 may be the interlayer insulating film 38. That is, the interlayer insulating film 38 may be a concept that includes both the first interlayer insulating film 36 and the second interlayer insulating film 37. The second interlayer insulating film 37 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0136] 5A shows an example of an enlarged cross-sectional view of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.

[0137] A bottom corner 1880 of the temperature sensitive contact portion 188 may be in contact with the temperature sensitive diode 183. The bottom corner 1880 of the temperature sensitive contact portion 188 may be the intersection of the bottom surface of the temperature sensitive contact portion 188 and the side surface of the temperature sensitive contact portion 188. The bottom corner 1880 being in contact with the temperature sensitive diode 183 may be in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183, on the side surface of the temperature sensitive diode 183, or in an internal region of the temperature sensitive diode 183. In this example, the bottom corner 1880 is in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183.

[0138] The temperature-sensitive contact portion 188 in this example has two bottom corners 1880. One of the two bottom corners 1880 may be in contact with the temperature-sensitive diode 183. The other of the two bottom corners 1880 may or may not be in contact with the housing portion 198. The temperature-sensitive contact portion 188a in this example has one bottom corner 1880a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner 1880b in contact with the housing portion 198.

[0139] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the housing portion 198. The bottom surface of the temperature-sensitive contact portion 188 may be the surface between two bottom corner portions 1880 of the temperature-sensitive contact portion 188. The bottom surface of the temperature-sensitive contact portion 188 in contact with the housing portion 198 may be in contact with the housing portion 198 at the top surface of the housing portion 198, or may be in contact with the housing portion 198 in an internal region of the housing portion 198. In this example, the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0140] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the housing portion 198. In the present example, one bottom corner portion 1880a of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198, so that the bottom surface of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive diode 183 and the housing portion 198.

[0141] The temperature-sensitive diode 183 may contact the bottom surface of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188. That is, the ratio of the area of ​​the surface of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 to the area of ​​the bottom surface of the temperature-sensitive contact portion 188 may be 10% to 40%. Referring to FIG. 5A , length L1 is the length of the bottom surface of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the temperature sensitive diode 183 contacts the bottom surface of the temperature sensitive contact portion 188a from the bottom corner 1880a to an area that is 25% of the bottom surface of the temperature sensitive contact portion 188. In other words, in this example, the ratio of length L2 to length L1 is 25%.

[0142] In the above explanation, the bottom surface, bottom corners 1880a, and bottom corners 1880b of the temperature-sensitive contact portion 188a that contact the temperature-sensitive cathode region 181 have been given as examples, but the same may be true for the temperature-sensitive contact portion 188b that contacts the temperature-sensitive anode region 182. That is, the bottom corners 1880 of the temperature-sensitive contact portion 188b may contact the temperature-sensitive diode 183, the bottom surface of the temperature-sensitive contact portion 188b may contact the housing portion 198, the bottom surface of the temperature-sensitive contact portion 188b may contact the temperature-sensitive diode 183 and the housing portion 198, and the temperature-sensitive diode 183 may contact the bottom surface of the temperature-sensitive contact portion 188b from the bottom corners 1880 over an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188b. Furthermore, the lengths L1 and L2 of the temperature sensitive contact portion 188b may be the same as those of the temperature sensitive contact portion 188a.

[0143] In this example, the temperature-sensitive contact portion 188 is provided such that the bottom corners 1880 contact the temperature-sensitive diode 183 and the bottom surface contacts the housing portion 198. This ensures reliable electrical connection between the anode pad 116, the cathode pad 118, and the temperature-sensitive diode 183. If the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are over-etched during the etch-back process of the plug portion 1884, voids may be generated inside the temperature-sensitive contact portion 188. Even in this case, the electrical connection can be ensured by the barrier metal film 1882 and / or the plug portion 1884 remaining at the bottom corners 1880 of the temperature-sensitive contact portion 188. The barrier metal film 1882 and the plug portion 1884 will be described later.

[0144] The temperature-sensitive contact portion 188 of this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the temperature-sensitive contact portion near the center of its bottom surface, the effect on the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 at the bottom corners 1880 is suppressed. This improves the yield of semiconductor devices 100 with desired characteristics. The temperature-sensitive portion 180 of this example ensures electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corners 1880 rather than the bottom center of the temperature-sensitive contact portion 188. This ensures stable quality and improved yield, even if a void forms in the region near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.

[0145] The temperature-sensitive contact portion 188 may have a barrier metal film 1882 and a plug portion 1884. In this example, the barrier metal film 1882 and the plug portion 1884 are formed of different materials, but they may also be formed of the same material.

[0146] The barrier metal film 1882 may be provided at the bottom corners 1880 of the temperature-sensitive contact portion 188. In this example, the barrier metal film 1882 is provided over the entire side and bottom surfaces of the temperature-sensitive contact portion 188, but this is not limiting. The barrier metal film 1882 may be provided so as to cover at least the bottom corners 1880, or may be provided so as not to cover the center portion of the bottom surface of the temperature-sensitive contact portion 188. The barrier metal film 1882 may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36. The material of the barrier metal film 1882 may be titanium, a titanium compound, or the like.

[0147] The plug portion 1884 may be provided in contact with the inner side of the barrier metal film 1882. In this example, the plug portion 1884 is provided by filling the temperature-sensitive contact portion 188, but this is not limiting. The plug portion 1884 may be provided in a portion of the temperature-sensitive contact portion 188, or may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36. When the plug portion 1884 is provided in a portion of the temperature-sensitive contact portion 188, the remaining region of the temperature-sensitive contact portion 188 may be filled with the same material as the anode wiring portion 117 or the cathode wiring portion 119. The material of the plug portion 1884 may be a plug metal such as tungsten.

[0148] The side surfaces of the temperature sensitive diode 183 may contact the side surfaces of the housing portion 198. In the temperature sensitive diode 183 of this example, the side surfaces of the temperature sensitive cathode region 181 and the temperature sensitive anode region 182 contact the side surfaces of the housing portion 198.

[0149] The upper surface of the second interlayer insulating film 37 may be in contact with the lower surface of the temperature-sensitive diode 183 and the lower surface of the housing portion 198. In this example, the upper surface of the second interlayer insulating film 37 is in contact with the lower surface of the housing portion 198 provided in contact with the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive anode region 182, and the lower surface of the housing portion 198 provided in contact with the temperature-sensitive anode region 182.

[0150] The housing portion 198 may be a region of the first interlayer insulating film 36 that is provided below the temperature-sensitive contact portion 188. The housing portion 198 may be formed in the process of providing the first interlayer insulating film 36, and may be formed from the same material as the first interlayer insulating film 36. When the housing portion 198 is formed as a region of the first interlayer insulating film 36 that is provided below the temperature-sensitive contact portion 188, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 5A . In other words, the housing portion 198 may be formed integrally as part of the first interlayer insulating film 36.

[0151] 5B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the example of FIG. 5A in that the shapes of the first interlayer insulating film 36 and the second interlayer insulating film 37 are different. In this example, differences from the example of FIG. 5A will be particularly described, and the rest may be the same as the example of FIG. 5A.

[0152] The second interlayer insulating film 37 may have a recess 200 on its upper surface. The temperature-sensitive diode 183 may be provided in the recess 200 in the second interlayer insulating film 37. The recess 200 may be formed by etching the upper surface of the second interlayer insulating film 37. The upper surface of the temperature-sensitive diode 183 in this example may be flush with the upper surface of the recess 200, or may be lower than the upper surface of the recess 200.

[0153] The housing portion 198 may be the second interlayer insulating film 37 provided above the semiconductor substrate 10. The housing portion 198 may be formed during the process of providing the second interlayer insulating film 37 and may be formed from the same material as the second interlayer insulating film 37. When the housing portion 198 is formed as the second interlayer insulating film 37, the housing portion 198 is a virtual region, as indicated by the dotted line in FIG. 5B . That is, the housing portion 198 may be formed integrally with the second interlayer insulating film 37. Note that if the upper surface of the temperature sensitive diode 183 is higher than the upper surface of the recess 200, the lower end of the temperature sensitive contact portion 188 does not reach the second interlayer insulating film 37 but is located in the first interlayer insulating film 36. The housing portion 198 may be considered to be part of the first interlayer insulating film 36, or may be considered to be made up of both the first interlayer insulating film 36 and the second interlayer insulating film 37. Furthermore, even if the portion of the second interlayer insulating film 37 that does not have the recess 200 is narrow and the lower end of the temperature-sensitive contact portion 188 is located at the boundary between the first interlayer insulating film 36 and the second interlayer insulating film 37, the housing portion 198 may be considered to be part of the second interlayer insulating film 37, or may be considered to be made up of both the first interlayer insulating film 36 and the second interlayer insulating film 37.

[0154] FIG. 5C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIGS. 5A and 5B in that a housing portion 198 is provided separately from the first interlayer insulating film 36 and the second interlayer insulating film 37. In this example, differences from the embodiment of FIGS. 5A and 5B will be particularly described, and the rest may be the same as the embodiment of FIGS. 5A and / or 5B. The housing portion 198 of this example is provided in the region of the first interlayer insulating film 36 corresponding to the housing portion 198 in FIG. 5A, but may also be provided in the region of the second interlayer insulating film 37 corresponding to the housing portion 198 in FIG. 5B.

[0155] The housing portion 198 may have polysilicon of a different conductivity type from the contact region 300 of the temperature sensitive diode 183. The contact region 300 of the temperature sensitive diode 183 may be the temperature sensitive cathode region 181 or the temperature sensitive anode region 182 of the temperature sensitive diode 183 that the housing portion 198 contacts.

[0156] The housing portion 198a in this example is in contact with the temperature-sensitive cathode region 181. Therefore, the housing portion 198a may have polysilicon of a different conductivity type from that of the temperature-sensitive cathode region 181, which is the contact region 300 of the temperature-sensitive diode 183. In other words, the housing portion 198a may have P-type polysilicon or undoped polysilicon.

[0157] The housing portion 198b in this example is in contact with the temperature-sensitive anode region 182. Therefore, the housing portion 198b may have polysilicon of a different conductivity type from that of the temperature-sensitive anode region 182, which is the contact region 300 of the temperature-sensitive diode 183. In other words, the housing portion 198b may have N-type polysilicon or undoped polysilicon.

[0158] In the present example, the temperature sensitive contact portion 188 is in contact with the temperature sensitive diode 183 at a bottom corner 1880 of the temperature sensitive contact portion 188. In the present example, the temperature sensitive contact portion 188 is provided such that the bottom surface of the temperature sensitive contact portion 188 is in contact with the housing portion 198. The housing portion 198 and a contact region 300 of the temperature sensitive diode 183 with the housing portion 198 may have the same potential.

[0159] When the housing portion 198 and the contact region 300 of the temperature-sensitive diode 183 have the same potential, no current flows between the housing portion 198 and the temperature-sensitive diode 183, and the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. As an example, when the housing portion 198a has P-type polysilicon, which is a different conductivity type from the temperature-sensitive cathode region 181, the housing portion 198a and the temperature-sensitive cathode region 181 have the same potential, so substantially no current flows through the PN junction at the contact interface. Therefore, the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. Similarly, even when the housing portion 198b has N-type polysilicon, which is a different conductivity type from the temperature-sensitive anode region 182, the housing portion 198b and the temperature-sensitive anode region 182 have the same potential, so the PN junction at the contact interface does not function and does not impede the operation of the temperature-sensitive diode 183.

[0160] The housing portion 198 may have the same conductivity type as the contact region 300 of the temperature sensitive diode 183 and may include polysilicon with a lower doping concentration than the contact region 300. The housing portion 198a in this example is in contact with the temperature sensitive cathode region 181. Therefore, the housing portion 198a may have the same conductivity type as the temperature sensitive cathode region 181, which is the contact region 300 of the temperature sensitive diode 183, and may include polysilicon with a lower doping concentration than the temperature sensitive cathode region 181. In other words, the housing portion 198a may include N-type polysilicon. The housing portion 198b in this example is in contact with the temperature sensitive anode region 182. Therefore, the housing portion 198b may have the same conductivity type as the temperature sensitive anode region 182, which is the contact region 300 of the temperature sensitive diode 183, and may include polysilicon with a lower doping concentration than the temperature sensitive anode region 182. In other words, the housing portion 198b may include P-type polysilicon.

[0161] Even if the housing part 198 has the same conductivity type as the contact region 300 of the temperature sensitive diode 183, the doping concentration of the housing part 198 is lower than the doping concentration of the contact region 300, so the housing part 198 has little effect on the operation of the temperature sensitive diode 183. Therefore, the housing part 198 is unlikely to interfere with the operation of the temperature sensitive diode 183.

[0162] As described above, the housing portion 198a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183 may have P-type, non-doped, or N-type polysilicon, and the housing portion 198b in contact with the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 may have N-type, non-doped, or P-type polysilicon. If the width of the polysilicon is narrow, a portion of the lower end of the temperature-sensitive contact portion 188 may overlap the interlayer insulating film 38. In this case, the housing portion 198 can be considered to be made of a mixture of polysilicon and the first interlayer insulating film 36 and / or the second interlayer insulating film 37.

[0163] 5D shows an example of an enlarged cross section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where the plug portion 1884 near the center of the bottom surface of the temperature-sensitive contact portion 188 is removed by over-etching during the etch-back process of the plug portion 1884. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or the cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0164] In this example, the temperature-sensitive contact portion 188 is provided such that the bottom corners 1880 contact the temperature-sensitive diode 183 and the bottom surface contacts the housing portion 198. Therefore, even if a void 302 occurs inside the temperature-sensitive contact portion near the center of the bottom surface, the influence on the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 at the bottom corners 1880 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. In this example, the temperature-sensitive portion 180 ensures electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corners 1880 rather than the center of the bottom surface of the temperature-sensitive contact portion 188. This ensures stable quality and improved yield, even if a void 302 forms in the region near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.

[0165] 5E shows another example of an enlarged cross section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. In this example, the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are over-etched and removed during the etch-back process of the plug portion 1884, and the housing portion 198 is also over-etched. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or the cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0166] In the temperature-sensing part 180 of this example, the electrical connection between the temperature-sensing contact part 188 and the temperature-sensing diode 183 is ensured not at the center of the bottom surface of the temperature-sensing contact part 188 but at the bottom corner part 1880. As a result, even if a void 302 is formed in the region near the center of the temperature-sensing contact part 188 that contacts the housing part 198, as in the example of Fig. 5D, stable quality can be obtained and yield can be improved.

[0167] FIG. 6 shows a cross section of a modified example of the semiconductor device 100 including the temperature-sensitive portion 180. The semiconductor device 100 of this example differs from the embodiment of FIG. 4 in that the temperature-sensitive contact portion 188 and the active contact portion 124 have a trench contact structure. The rest of the semiconductor device 100 may be the same as the embodiment of FIG. 4. When the temperature-sensitive contact portion 188 has a trench contact structure, the temperature-sensitive contact portion 188 may extend from the upper surface of the temperature-sensitive diode 183 in the depth direction of the semiconductor substrate 10. When the active contact portion 124 has a trench contact structure, the active contact portion 124 may extend from the front surface 21 in the depth direction of the semiconductor substrate 10. The bottom surface of the active contact portion 124 may be shallower or deeper than the lower end of the emitter region in the depth direction of the semiconductor substrate 10.

[0168] 7A shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region of the temperature-sensitive portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 5A in that the structure of the temperature-sensitive contact portion 188 is different. In this example, differences from the embodiment of FIG. 5A will be particularly described, and the rest may be the same as the embodiment of FIG. 5A.

[0169] The sidewalls of the temperature sensitive contact portion 188 may have a trench contact structure that contacts the side surfaces of the temperature sensitive diode 183. In this example, the bottom corners 1880 of the temperature sensitive contact portion 188 contact the temperature sensitive diode 183 on the side surfaces of the temperature sensitive diode 183.

[0170] The sidewall of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the first interlayer insulating film 36. The temperature-sensitive diode 183 may be in contact with the sidewall of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of ​​10% to 90% of the sidewall of the temperature-sensitive contact portion. That is, the ratio of the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 to the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 may be 10% to 90%. Referring to FIG. 7A , length L3 is the length of the sidewall of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, the temperature sensitive diode 183 contacts the sidewall of the temperature sensitive contact portion 188 from the bottom corner 1880 to 36% of the area of ​​the sidewall of the temperature sensitive contact portion 188. In other words, in this example, the ratio of length L4 to length L3 is 36%.

[0171] 7B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 7A in that the housing portion 198 is the second interlayer insulating film 37 provided above the semiconductor substrate 10. Other aspects may be the same as the embodiment of FIG. 7A.

[0172] 7C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This view shows the region of the temperature-sensitive portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIGS. 7A and 7B in that the housing portion 198 includes polysilicon. Other aspects may be the same as the embodiment of FIGS. 7A and / or 7B.

[0173] 7D shows an example of an enlarged cross section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. This example shows a case where the plug portion 1884 near the center of the bottom surface of the temperature-sensitive contact portion 188 is removed by over-etching during the etch-back process of the plug portion 1884. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or the cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0174] In this example, the temperature-sensitive contact portion 188 is provided such that the bottom corners 1880 contact the temperature-sensitive diode 183 and the bottom surface contacts the housing portion 198. Therefore, even if a void 302 occurs inside the temperature-sensitive contact portion near the center of the bottom surface, the influence on the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 at the bottom corners 1880 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. In this example, the temperature-sensitive portion 180 ensures electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corners 1880 rather than the center of the bottom surface of the temperature-sensitive contact portion 188. This ensures stable quality and improved yield, even if a void 302 forms in the region near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.

[0175] 7E shows another example of an enlarged cross section of the semiconductor device 100 when a void 302 occurs in the temperature-sensitive contact portion 188. In this example, the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are over-etched and removed during the etch-back process of the plug portion 1884, and the housing portion 198 is also over-etched. In this case, it is difficult to fill the temperature-sensitive contact portion 188 with the metal material of the anode wiring portion 117 or the cathode wiring portion 119, and a void 302 may occur near the center of the bottom surface of the temperature-sensitive contact portion 188.

[0176] In the temperature-sensing part 180 of this example, the electrical connection between the temperature-sensing contact part 188 and the temperature-sensing diode 183 is ensured not at the center of the bottom surface of the temperature-sensing contact part 188 but at the bottom corner part 1880. As a result, even if a void 302 is formed in the region near the center of the temperature-sensing contact part 188 that contacts the housing part 198, as in the example of Fig. 7D, stable quality can be obtained and yield can be improved.

[0177] 8 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. The manufacturing process in this example includes step S100 of forming the active portion 120 on the semiconductor substrate 10, and step S110 of forming the temperature-sensing portion 180 above the semiconductor substrate 10. The order of step S100 of forming the active portion 120 and step S110 of forming the temperature-sensing portion 180 is not limited to this. The active portion 120 may be formed after the temperature-sensing portion 180 is formed, or part of the process of forming the active portion 120 and part of the process of forming the temperature-sensing portion 180 may be the same process.

[0178] Step S110 of forming the temperature sensing portion 180 includes step S114 of forming the temperature sensing diode 183, step S116 of forming the first interlayer insulating film 36, step S118 of forming the temperature sensing contact portion 188, and step S120 of forming the housing portion 198. Step S110 of forming the temperature sensing portion 180 may include step S112 of forming the second interlayer insulating film 37.

[0179] In step S112, a second interlayer insulating film 37 is formed above the semiconductor substrate 10. The second interlayer insulating film 37 may be formed by stacking a plurality of insulating films. If the second interlayer insulating film 37 is not provided in the semiconductor device 100, step S112 may be omitted. If the insulating film (thermal oxide film, HTO, etc.) formed in step S100 is used as the second interlayer insulating film 37, step S112 may be omitted.

[0180] In step S114, the temperature sensing diode 183 is formed above the semiconductor substrate 10. The temperature sensing diode 183 may be formed by a method known to those skilled in the art. For example, the temperature sensing diode 183 may be formed by depositing undoped polysilicon above the semiconductor substrate 10, implanting impurity ions, and performing an annealing process.

[0181] The step S114 of forming the temperature sensing diode 183 may include a step of forming a recess by etching the second interlayer insulating film 37. In this case, as shown in the embodiment of FIG. 5B or 7B, the temperature sensing diode 183 may be provided in the recess of the second interlayer insulating film 37.

[0182] In step S116, a first interlayer insulating film 36 is formed above the temperature sensitive diode. The first interlayer insulating film 36 may be formed by stacking a plurality of insulating films. Step S116 of forming the first interlayer insulating film 36 may be a step of forming the interlayer insulating film 38 in the active section 120. However, the first interlayer insulating film 36 and the interlayer insulating film 38 in the active section 120 may be formed in different processes.

[0183] In step S118, a temperature-sensitive contact portion 188 is formed, extending from the upper surface to the lower surface of the first interlayer insulating film 36. Step S118 of forming the temperature-sensitive contact portion 188 may be a step of forming an active contact portion 124 in the active portion 120, extending from the upper surface to the lower surface of the interlayer insulating film 38. However, the temperature-sensitive contact portion 188 and the active contact portion 124 may be formed in different processes.

[0184] Step S118 of forming the temperature-sensitive contact portion 188 may include a step of forming the contact hole 58 by etching the first interlayer insulating film 36. In this step, the contact holes 54, 55, and 56 may be formed in the interlayer insulating film 38. However, the contact hole 58 of the temperature-sensitive contact portion 188 and the contact holes 54, 55, and 56 may be formed in different steps. Furthermore, in step S116 of forming the first interlayer insulating film 36, the first interlayer insulating film 36 may be formed to have the contact hole 58.

[0185] Step S118 of forming the temperature-sensitive contact portion 188 may include a step of forming a barrier metal film 1882. The barrier metal film 1882 may be formed by forming a metal film inside the contact hole 58 and then annealing the metal film in a nitrogen atmosphere. As an example, the barrier metal film 1882 may be formed by forming a Ti film inside the contact hole 58 and then annealing the Ti film in a nitrogen atmosphere. In this case, a TiN film may be formed by annealing the Ti film. In this process, a barrier metal film may be formed in the active contact portion 124.

[0186] The step S118 of forming the temperature-sensitive contact portion 188 may include a step of forming a plug portion 1884. As an example, the plug portion 1884 may be formed by forming tungsten to fill the inside of the contact hole 58 using a chemical vapor deposition (CVD) method. In this process, the plug portion may be formed in the active contact portion 124.

[0187] Step S118 of forming the temperature-sensitive contact portion 188 may include a step of etching back the plug portion 1884. This may remove unnecessary tungsten film outside the contact hole 58. However, the plug portion 1884 may be provided in a portion of the temperature-sensitive contact portion 188, or may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36. The etch-back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film is removed, the barrier metal film 1882 may also be removed. The barrier metal film 1882 may be removed in a separate process from the etching back of the plug portion 1884. In this process, the plug portion of the active contact portion 124 may be etched back.

[0188] The above steps may be omitted if the barrier metal film 1882 and the plug portion 1884 are not provided in the temperature-sensitive contact portion 188. In this case, the inside of the contact hole 58 may be filled and the temperature-sensitive contact portion 188 may be formed at the same time as the step of providing the anode wiring portion 117 and the cathode wiring portion 119.

[0189] In step S118 of forming the temperature-sensitive contact portion 188, the temperature-sensitive contact portion 188 may be formed such that a bottom corner 1880 of the temperature-sensitive contact portion 188 contacts the temperature-sensitive diode 183. In step S118 of forming the temperature-sensitive contact portion 188, the temperature-sensitive contact portion 188 may be formed such that a bottom surface of the temperature-sensitive contact portion 188 contacts the housing portion 198.

[0190] In this example, the bottom corners 1880 of the temperature-sensitive contact portion 188 are in contact with the temperature-sensitive diode 183, and the bottom surface is in contact with the housing portion 198, thereby reliably ensuring electrical connection between the anode pad 116 and the cathode pad 118 and the temperature-sensitive diode 183. Because the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198, even if the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are over-etched and removed during the etch-back process of the plug portion 1884, causing voids inside the temperature-sensitive contact portion 188, this suppresses the effect on the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 at the bottom corners 1880, thereby improving the yield of semiconductor devices 100 with desired characteristics. In other words, by ensuring the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corner 1880 rather than the center of the bottom of the temperature-sensitive contact portion 188, stable quality can be obtained and yield can be improved even if a void is formed in the area near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.

[0191] In step S120, the housing portion 198 is formed below the temperature-sensitive contact portion 188. The order of step S120 of forming the housing portion 198 is not limited thereto. Step S120 of forming the housing portion 198 may be included in step S112 of forming the second interlayer insulating film 37, step S114 of forming the temperature-sensitive diode 183, or step S116 of forming the first interlayer insulating film 36.

[0192] 5A or 7A, the housing portion 198 is a region of the first interlayer insulating film 36 that is disposed below the temperature-sensitive contact portion 188. In this case, step S120 of forming the housing portion 198 may be included in step S116 of forming the first interlayer insulating film 36.

[0193] 5B or 7B, the housing portion 198 is the second interlayer insulating film 37 disposed above the semiconductor substrate 10. In this case, step S120 of forming the housing portion 198 may be included in step S112 of forming the second interlayer insulating film 37.

[0194] 5C or 7C , the housing portion 198b includes polysilicon. In this case, step S120 of forming the housing portion 198 may be included in step S114 of forming the temperature-sensitive diode 183. The temperature-sensitive diode 183 and the housing portion 198 may be formed by stacking undoped polysilicon in the regions that will become the housing portion 198 and the temperature-sensitive diode 183, implanting impurity ions of the corresponding conductivity type into each region, and performing an annealing process. Alternatively, the temperature-sensitive diode 183 and the housing portion 198 may be formed by stacking heavily doped N-type or P-type polysilicon in the regions that will become the housing portion 198 and the temperature-sensitive diode 183, and implanting impurity ions into the regions having the other conductivity type to invert the conductivity type.

[0195] In the above explanation, the connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 has been taken as an example, but the same may be true for contact portions provided in other contact holes. As an example, the bottom corners of the contact portion that electrically connects the polysilicon of the connection portion 25 and the gate metal layer 50 may be provided so as to come into contact with the polysilicon. In these cases, too, the electrical connection at each contact portion can be ensured. These cases will be described later.

[0196] FIG. 9 shows an example of electrical connections between the components of the semiconductor device 100 shown in FIG. 3 . In this example, a Zener diode section 170 is provided in anti-parallel between the cathode pad 118 and the anode pad 116 to protect against voltage breakdown. The Zener diode section 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the forward voltage of the Zener diode section 170 may be different from that of the temperature-sensitive diode 183. When the temperature-sensitive diode 183 is formed by connecting a plurality of temperature-sensitive cathode regions 181 and a temperature-sensitive anode regions 182 in series, the Zener diode section 170 may be provided between the temperature-sensitive cathode regions 181 and the temperature-sensitive anode regions 182. Furthermore, when the Zener diode section 170 is provided between the temperature-sensitive section 180 and the active section 120 for field protection, the Zener diode section 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the breakdown voltage of the Zener diode section 170 may be different from that of the temperature-sensitive diode 183. A plurality of Zener diode sections 170 may be connected in series. In other examples, the Zener diode sections 170 may be connected at different positions, or the Zener diode section 170 may not be provided.

[0197] 10A shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1A in that a connection portion 25 is provided between the emitter electrode 52 and the dummy conductive portion 34. In this example, differences from the embodiment of FIG. 1A will be particularly described, and the rest may be the same as the embodiment of FIG. 1A. As with the embodiment of FIG. 1A, the configuration of this figure may be repeatedly provided in both the positive and negative directions of the X-axis.

[0198] The semiconductor device 100 includes an active portion 120, which is a portion through which a main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10, and an inactive portion 130, which is the other portion. For example, the boundary between the active portion 120 and the inactive portion 130 is the boundary between the base region 14 and the well region 17.

[0199] An interlayer insulating film 38 is provided above the active portion 120 and the inactive portion 130, but the interlayer insulating film 38 is omitted in Fig. 10A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0200] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion 44 in the transistor portion 70 via the connection portion 25. The contact hole 56 electrically connects the emitter electrode 52 and the dummy conductive portion 34 in the dummy trench portion 30 via the connection portion 25. The connection portion 25 is a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. Polysilicon is an example of a polycrystalline semiconductor. The connection portion 25 is an example of a polycrystalline portion 132 provided above the semiconductor substrate 10. The connection portion 25 is an example of the polycrystalline portion 132 that the inactive portion 130 has.

[0201] Figure 10B shows an example of a cross section taken along the line cc' in Figure 9. The semiconductor device 100 of this example differs from the embodiment of Figure 1B in that the active contact portion 124 has a trench shape. Other aspects may be the same as the embodiment of Figure 1B.

[0202] 11 shows an example of the dd' cross section in FIG. 9. The dd' cross section is a YZ plane passing through the contact hole 56 in the inactive portion 130. In the dd' cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, and the first inactive contact portion 134. Note that although this example is described using the contact hole 56 having its longitudinal direction in the X-axis direction, the longitudinal direction of the contact hole 56 may be along the Y-axis direction or another direction.

[0203] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is the connection portion 25. The polycrystalline portion 132 may be provided above a third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as the dummy insulating film 32, for example. The third interlayer insulating film 138 may be a thermal oxide film. In another example, the third interlayer insulating film 138 may be made of a different material from the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0204] The first inactive contact portion 134 is provided to extend from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 56 may be provided to penetrate the interlayer insulating film 38. The first inactive contact portion 134 may have the contact hole 56 and a metal layer filled inside the contact hole 56. A detailed configuration of the first inactive contact portion 134 will be described later. The housing portion 198 is provided below the first inactive contact portion 134.

[0205] The polycrystalline portion 132 may be connected to the emitter electrode 52 via the first inactive contact portion 134. The polycrystalline portion 132 may be connected to the dummy conductive portion 34. The connection portion 25 in this example is connected to the emitter electrode 52 via the first inactive contact portion 134, and is also connected to the dummy conductive portion 34.

[0206] Fig. 12A shows an example of an enlarged view of the dd' cross section in Fig. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the non-active portion 130.

[0207] A bottom corner 1340 of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132. The bottom corner 1340 of the first inactive contact portion 134 may be the intersection of the bottom surface of the first inactive contact portion 134 and the side surface of the first inactive contact portion 134. The bottom corner 1340 being in contact with the polycrystalline portion 132 may be in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132, may be in contact with the polycrystalline portion 132 on the side surface of the polycrystalline portion 132, or may be in contact with the polycrystalline portion 132 in an internal region of the polycrystalline portion 132. In this example, the bottom corner 1340 is in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132.

[0208] The first inactive contact portion 134 of this example has two bottom corners 1340. One of the two bottom corners 1340 may contact the polycrystalline portion 132. The other of the two bottom corners 1340 may or may not contact the housing portion 198. The first inactive contact portion 134 of this example has one bottom corner 1340a in contact with the polycrystalline portion 132 and the other bottom corner 1340b in contact with the housing portion 198.

[0209] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. The bottom surface of the first inactive contact portion 134 may be the surface between two bottom corner portions 1340 of the first inactive contact portion 134. The bottom surface of the first inactive contact portion 134 in contact with the housing portion 198 may be in contact with the housing portion 198 at the top surface of the housing portion 198, or may be in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0210] In this example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the emitter electrode 52 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched during the etch-back process of the plug portion 1344, voids may be generated inside the first inactive contact portion 134. Even in this case, the electrical connection can be ensured by the barrier metal film 1342 and / or the plug portion 1344 remaining at the bottom corners 1340 of the first inactive contact portion 134. The barrier metal film 1342 and the plug portion 1344 will be described later.

[0211] The first inactive contact portion 134 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in this example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corners 1340 rather than the bottom center of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0212] The bottom surface of first inactive contact portion 134 may be in contact with polycrystalline portion 132 and housing portion 198. In this example, first inactive contact portion 134 has one bottom corner 1340 a in contact with polycrystalline portion 132 and the other bottom corner 1340 b in contact with housing portion 198, so that the bottom surface of first inactive contact portion 134 is in contact with polycrystalline portion 132 and housing portion 198.

[0213] The polycrystalline portion 132 may contact the bottom surface of the first inactive contact portion 134 from the bottom corner 1340 to an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. That is, the area ratio of the surface of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the bottom surface of the first inactive contact portion 134 may be 10% to 40%. Referring to FIG. 12A , length L1 is the length of the bottom surface of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in the cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 132 contacts the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to an area that is 20% of the bottom surface of the first inactive contact portion 134. That is, in this example, the ratio of the length L2 to the length L1 is 20%.

[0214] The first inactive contact portion 134 may have a barrier metal film 1342 and a plug portion 1344. In this example, the barrier metal film 1342 and the plug portion 1344 are formed of different materials, but they may also be formed of the same material.

[0215] The barrier metal film 1342 may be provided at the bottom corners 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surfaces of the first inactive contact portion 134, but this is not limiting. The barrier metal film 1342 may be provided so as to cover at least the bottom corners 1340, or may be provided without covering the center portion of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 56 and extend above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium, a titanium compound, or the like.

[0216] The plug portion 1344 may be provided in contact with the inner side of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but this is not limiting. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, or may extend beyond the contact hole 56 and extend above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining region of the first inactive contact portion 134 may be filled with the same material as the emitter electrode 52. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0217] The side surface of the polycrystalline portion 132 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 12A . That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be the third interlayer insulating film 138 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed of the same material as the third interlayer insulating film 138. That is, the housing portion 198 may be formed integrally as part of the third interlayer insulating film 138. In this case, the polycrystalline portion 132 may be provided in a recess formed by etching the upper surface of the thick third interlayer insulating film 138. In still another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 132 or undoped polysilicon.

[0218] 12B shows an example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0219] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0220] 12C shows another example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and the housing portion 198 is also over-etched. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0221] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured not at the center of the bottom surface of the first inactive contact portion 134 but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of FIG. 12B , stable quality can be obtained and yield can be improved.

[0222] 13 shows an example of a dd' cross section in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 11 in that the first inactive contact portion 134 has a trench contact structure. The rest may be the same as the embodiment of FIG. 11. When the first inactive contact portion 134 has a trench contact structure, the first inactive contact portion 134 may extend from the upper surface of the polycrystalline portion 132 in the depth direction of the semiconductor substrate 10. The active contact portion 124 may have the planar contact structure of FIG. 1B or the trench contact structure of FIG. 10B.

[0223] 14A shows an example of an enlarged view of the dd' cross section in FIG. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 12A in that the structure of the first inactive contact portion 134 is different. In this example, differences from the embodiment of FIG. 12A will be particularly described, and the rest may be the same as the embodiment of FIG. 12A.

[0224] The sidewalls of the first non-active contact portions 134 may have a trench contact structure in contact with the side surfaces of the polycrystalline portions 132. In this example, the bottom corners 1340 of the first non-active contact portions 134 contact the side surfaces of the polycrystalline portions 132.

[0225] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. In other words, the ratio of the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 may be 10% to 90%. 14A , length L3 is the length of the sidewall of first inactive contact portion 134 in a cross section perpendicular to front surface 21 of semiconductor substrate 10, and length L4 is the length of the sidewall of first inactive contact portion 134 that contacts polycrystalline portion 132 in a cross section perpendicular to front surface 21 of semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, polycrystalline portion 132 contacts the sidewall of first inactive contact portion 134 from bottom corner 1340 to 35% of the sidewall of first inactive contact portion 134. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0226] 14B shows an example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching during the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0227] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0228] 14C shows another example of an enlarged view of the dd' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and the housing portion 198 is also over-etched. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the emitter electrode 52, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0229] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured not at the center of the bottom surface of the first inactive contact portion 134 but at the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of FIG. 14B , stable quality can be obtained and yield can be improved.

[0230] 15 shows an example of the ee' cross section in Fig. 9. The ee' cross section is a YZ plane passing through the contact hole 55 in the inactive portion 130. In the ee' cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the gate metal layer 50, the collector electrode 24, and the first inactive contact portion 134.

[0231] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is the connection portion 25. The polycrystalline portion 132 may be provided above a third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as the gate insulating film 42, for example. The third interlayer insulating film 138 may be a thermal oxide film. In another example, the third interlayer insulating film 138 may be made of a different material from the gate insulating film 42. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0232] The first inactive contact portion 134 is provided to extend from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 55 may be provided to penetrate the interlayer insulating film 38. The first inactive contact portion 134 may have the contact hole 55 and a metal layer filled inside the contact hole 55. The housing portion 198 is provided below the first inactive contact portion 134.

[0233] The polycrystalline portion 132 may be connected to the gate metal layer 50 via the first inactive contact portion 134. The polycrystalline portion 132 may be connected to the gate conductive portion 44. The connection portion 25 in this example is connected to the gate metal layer 50 via the first inactive contact portion 134, and is connected to the gate conductive portion 44.

[0234] Fig. 16A shows an example of an enlarged view of the ee' cross section in Fig. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the non-active portion 130.

[0235] The bottom corners 1340 of the first inactive contact portions 134 may be in contact with the polycrystalline portion 132. In this example, the bottom corners 1340 are in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132.

[0236] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0237] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the gate metal layer 50 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched during the etch-back process of the plug portion 1344, voids may be generated inside the first inactive contact portion 134. Even in this case, the electrical connection can be ensured by the barrier metal film 1342 and / or the plug portion 1344 remaining at the bottom corners 1340 of the first inactive contact portion 134.

[0238] The first inactive contact portion 134 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the temperature-sensitive contact portion near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 with desired characteristics. The inactive portion 130 in this example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corners 1340 rather than the bottom center of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0239] The bottom surface of first inactive contact portion 134 may be in contact with polycrystalline portion 132 and housing portion 198. In this example, first inactive contact portion 134 has one bottom corner 1340 a in contact with polycrystalline portion 132 and the other bottom corner 1340 b in contact with housing portion 198, so that the bottom surface of first inactive contact portion 134 is in contact with polycrystalline portion 132 and housing portion 198.

[0240] The polycrystalline portion 132 may contact the bottom surface of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. In this example, the polycrystalline portion 132 contacts the bottom surface of the first inactive contact portion 134 over an area of ​​20% of the bottom surface of the first inactive contact portion 134 from the bottom corner 1340a. That is, in this example, the ratio of length L2 to length L1 is 20%.

[0241] The barrier metal film 1342 may be provided at the bottom corners 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surfaces of the first inactive contact portion 134, but this is not limiting. The barrier metal film 1342 may be provided so as to cover at least the bottom corners 1340, or may be provided without covering the center portion of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 55 and extend above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium, a titanium compound, or the like.

[0242] The plug portion 1344 may be provided in contact with the inner side of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but this is not limiting. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, or may extend beyond the contact hole 55 and extend above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining region of the first inactive contact portion 134 may be filled with the same material as the gate metal layer 50. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0243] The side surface of the polycrystalline portion 132 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 16A . In other words, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be the third interlayer insulating film 138 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed of the same material as the third interlayer insulating film 138. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138. In yet another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 132 or undoped polysilicon.

[0244] 16B shows an example of an enlarged view of the e-e' cross section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0245] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0246] 16C shows another example of an enlarged view of the e-e' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etching occurs up to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0247] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured by the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of FIG. 16B , stable quality can be obtained and yield can be improved.

[0248] Fig. 17 shows an example of the e-e' cross section in Fig. 9. The semiconductor device 100 of this example differs from the embodiment of Fig. 15 in that the first inactive contact portion 134 has a trench contact structure. Other aspects may be the same as the embodiment of Fig. 15.

[0249] 18A shows an example of an enlarged view of the ee' cross section in FIG. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 16A in that the structure of the first inactive contact portion 134 is different. In this example, differences from the embodiment of FIG. 16A will be particularly described, and the rest may be the same as the embodiment of FIG. 16A.

[0250] The sidewalls of the first non-active contact portions 134 may have a trench contact structure in contact with the side surfaces of the polycrystalline portions 132. In this example, the bottom corners 1340 of the first non-active contact portions 134 contact the side surfaces of the polycrystalline portions 132.

[0251] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. In this example, the polycrystalline portion 132 is in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​35% of the sidewall of the first inactive contact portion 134. That is, the ratio of length L4 to length L3 in this example is 35%.

[0252] 18B shows an example of an enlarged view of the e-e' cross section in FIG. 9 when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0253] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0254] 18C shows another example of an enlarged view of the e-e' cross section in FIG. 9 when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etching occurs up to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the gate metal layer 50, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0255] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured by the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of FIG. 18B , stable quality can be obtained and yield can be improved.

[0256] 19A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a guard ring 142 in the edge termination structure 140. The semiconductor device 100 may include multiple guard rings 142.

[0257] The guard ring 142 is a second conductivity type region provided on the front surface 21 of the semiconductor substrate 10 between the active portion 120 and the edge 102 of the semiconductor substrate 10. The guard ring 142 is, for example, a P+ type. The guard ring 142 may surround the active portion 120 in a top view. In this example, the well region 17 adjacent to the active portion 120 may also be included in the guard ring 142. Furthermore, multiple guard rings 142 may be provided. The guard ring 142 disposed on the outer side may surround the guard ring 142 disposed on the inner side. The outer side refers to the side closer to the edge 102, and the inner side refers to the side closer to the center of the semiconductor substrate 10 in a top view. By providing the guard ring 142, the depletion layer on the front surface 21 side of the active portion 120 can be extended toward the edge 102, thereby improving the breakdown voltage of the semiconductor device 100. The guard ring 142, which is spaced apart from the well region 17 adjacent to the active portion 120, may also be formed by the same diffusion process as the well region 17, and the inner and outer diffusion shapes may be substantially the same. In another example, the guard ring 142 may be a VLD whose depth becomes shallower toward the outer side. In yet another example, the guard ring 142 may be formed by the same diffusion process as the base region 14. The semiconductor device 100 may further include at least one of a field plate or a resurf provided in the edge termination structure 140 surrounding the active portion 120.

[0258] 19B shows an example of region R in FIG. 19A . In this example, semiconductor device 100 includes guard ring 142 and field plate 144 in edge termination structure 140. Edge termination structure 140 is an example of inactive portion 130. In edge termination structure 140, semiconductor device 100 may include interlayer insulating film 38, edge metal layer 146, and field insulating film 148. Interlayer insulating film 38 and field insulating film 148 are omitted in FIG. 19B . Contact holes 57 and 59 are provided penetrating interlayer insulating film 38.

[0259] The field plate 144 is a conductive member provided above the semiconductor substrate 10. In this example, the field plate 144 is formed of polysilicon to which impurities are added. The field plate 144 is an example of the polycrystalline portion 132. The field plate 144 is provided above the guard ring 142. The field plate 144 may be electrically connected to the corresponding guard ring 142.

[0260] The guard ring 142 has a non-corner region 1420 and a corner region 1422. The non-corner region 1420 is, for example, a region of the guard ring 142 that extends along the edge 102 of the semiconductor substrate 10, and the corner region 1422 is, for example, a portion of the guard ring 142 that connects the regions that extend along the edge 102 of the semiconductor substrate 10.

[0261] Contact hole 57 connects edge metal layer 146 and field plate 144. Inside contact hole 57, a barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed.

[0262] Contact hole 59 connects edge metal layer 146 and guard ring 142. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside contact hole 59. Field plate 144 does not need to be provided around contact hole 59.

[0263] Contact holes 57 and 59 may be provided above corner regions 1422 of guard ring 142. However, at least one of contact holes 57 and 59 may be provided above non-corner regions 1420 of guard ring 142, or both contact holes 57 and 59 may be provided above non-corner regions 1420 of guard ring 142. In this example, contact holes 57 and 59 have their longitudinal direction in the direction in which guard ring 142 and field plate 144 extend, and are provided side by side from the center toward edge 102. In another example, contact holes 57 and 59 may be arranged in the direction in which guard ring 142 and field plate 144 extend, and the longitudinal direction of each contact hole may be from the center toward edge 102, and each contact hole may consist of multiple holes.

[0264] The width d2 of the corner region 1422 may be wider than the width d1 of the non-corner region 1420. That is, the radius of curvature r1 on the side of the edge 102 (outside) may be smaller than the sum of the radii of curvature r2 and d1 on the central side (inside). In this example, r1 is smaller than r2. The edge metal layer 146 may be provided at or near the widest point of the corner region 1422. In another example, the width d2 of the corner region 1422 may be equal to the width d1 of the non-corner region 1420. In still another example, the edge metal layer 146 may be provided in the non-corner region 1420, or may be provided across the non-corner region 1420 and the corner region 1422.

[0265] 20 shows an example of the ff' cross section in FIG. 19B. The ff' cross section is a plane parallel to the Z-axis direction that passes through contact holes 57 and 59 in inactive portion 130. In the ff' cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, field insulating film 148, edge metal layer 146, collector electrode 24, first inactive contact portion 134, and second inactive contact portion 135.

[0266] The field insulating film 148 is provided above the semiconductor substrate 10. The field insulating film 148 may be provided between the well region 17 adjacent to the active portion 120 and the guard ring 142, and between the guard rings 142, so as to cover the drift region 18 exposed on the front surface 21 of the semiconductor substrate 10. The field insulating film 148 may be provided along the guard ring 142 so as to surround the active portion 120.

[0267] The field insulating film 148 may include an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, an insulating film deposited by CVD or the like, or another insulating film. The field insulating film 148 may be a single-layer insulating film, or may be an insulating film in which multiple films formed by different methods are stacked.

[0268] The edge metal layer 146 is provided above the semiconductor substrate 10 and is electrically connected to the guard ring 142. The edge metal layer 146 is provided above the semiconductor substrate 10 with the interlayer insulating film 38 sandwiched therebetween. The edge metal layer 146 may be electrically connected to the field plate 144. The edge metal layer 146 may be electrically floating. For example, when a voltage V is applied to the collector electrode 24 with the gate of the semiconductor device 100 in an off state, the edge metal layer 146 has a predetermined voltage lower than the voltage V. If the guard ring 142 is a well region 17 adjacent to the active portion 120, the edge metal layer 146 may be at the same potential as the emitter electrode 52.

[0269] The edge metal layer 146 is formed of a material containing metal, and at least a portion of the edge metal layer 146 may be formed of a metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0270] The polycrystalline portion 132 is provided above the semiconductor substrate. In this example, the polycrystalline portion 132 is a field plate 144. The polycrystalline portion 132 may be provided above a third interlayer insulating film 138. The third interlayer insulating film 138 may be made of the same material as the gate insulating film 42 and / or the dummy insulating film 32, for example. The third interlayer insulating film 138 may be a thermal oxide film. In another example, the third interlayer insulating film 138 may be made of a different material from the gate insulating film 42 and / or the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 132.

[0271] The first inactive contact portion 134 extends from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 57 may be formed to penetrate the interlayer insulating film 38. The first inactive contact portion 134 may have the contact hole 57 and a metal layer filled inside the contact hole 57. The housing portion 198 is formed below the first inactive contact portion 134. The field insulating film 148 may be formed below the interlayer insulating film 38. The polycrystalline portion 132 may be connected to the edge metal layer 146 via the first inactive contact portion 134. The field plate 144 of this example is connected to the edge metal layer 146 via the first inactive contact portion 134.

[0272] The second inactive contact portion 135 is provided to extend from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 59 may be provided to penetrate the interlayer insulating film 38. The second inactive contact portion 135 may have the contact hole 59 and a metal layer filled inside the contact hole 59. The guard ring 142 may be connected to the edge metal layer 146 via the second inactive contact portion 135. The guard ring 142 of this example is connected to the edge metal layer 146 via the second inactive contact portion 135. The second inactive contact portion 135 may have the same configuration as the active contact portion 124. That is, the second inactive contact portion 135 may include a barrier metal film 1352 and a plug portion 1354.

[0273] 21A shows an example of an enlarged view of the ff' cross section in FIG. 19B. This view shows a region above the front surface 21 of the semiconductor substrate 10 in the non-active portion 130.

[0274] The bottom corners 1340 of the first inactive contact portions 134 may be in contact with the polycrystalline portion 132. In this example, the bottom corners 1340 are in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132.

[0275] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0276] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the edge metal layer 146 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched during the etch-back process of the plug portion 1344, voids may be generated inside the first inactive contact portion 134. Even in this case, the electrical connection can be ensured by the barrier metal film 1342 and / or the plug portion 1344 remaining at the bottom corners 1340 of the first inactive contact portion 134.

[0277] The first inactive contact portion 134 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the temperature-sensitive contact portion near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 with desired characteristics. The inactive portion 130 in this example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corners 1340 rather than the bottom center of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0278] The bottom surface of first inactive contact portion 134 may be in contact with polycrystalline portion 132 and housing portion 198. In this example, first inactive contact portion 134 has one bottom corner 1340 a in contact with polycrystalline portion 132 and the other bottom corner 1340 b in contact with housing portion 198, so that the bottom surface of first inactive contact portion 134 is in contact with polycrystalline portion 132 and housing portion 198.

[0279] The polycrystalline portion 132 may contact the bottom surface of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. In this example, the polycrystalline portion 132 contacts the bottom surface of the first inactive contact portion 134 over an area of ​​20% of the bottom surface of the first inactive contact portion 134 from the bottom corner 1340a. That is, in this example, the ratio of length L2 to length L1 is 20%.

[0280] The barrier metal film 1342 may be provided at the bottom corners 1340 of the first inactive contact portion 134. In this example, the barrier metal film 1342 is provided over the entire side and bottom surfaces of the first inactive contact portion 134, but this is not limiting. The barrier metal film 1342 may be provided so as to cover at least the bottom corners 1340, or may be provided without covering the center portion of the bottom surface of the first inactive contact portion 134. The barrier metal film 1342 may extend beyond the contact hole 57 and extend above the interlayer insulating film 38. The material of the barrier metal film 1342 may be titanium, a titanium compound, or the like.

[0281] The plug portion 1344 may be provided in contact with the inner side of the barrier metal film 1342. In this example, the plug portion 1344 is provided by filling the first inactive contact portion 134, but this is not limiting. The plug portion 1344 may be provided in a part of the first inactive contact portion 134, or may extend beyond the contact hole 57 and extend above the interlayer insulating film 38. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining region of the first inactive contact portion 134 may be filled with the same material as the edge metal layer 146. The material of the plug portion 1344 may be a plug metal such as tungsten.

[0282] The side surface of the polycrystalline portion 132 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 21A . That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be the third interlayer insulating film 138 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 138 and may be formed of the same material as the third interlayer insulating film 138. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 138 .

[0283] 21B shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 21A in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first inactive contact portion 134. Other aspects may be the same as the embodiment of FIG. 21A.

[0284] 21C shows an example of an enlarged view of the ff' cross section in FIG. 19B. This view shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIGS. 21A and 21B in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. In this example, differences from the embodiment of FIGS. 21A and 21B will be particularly described, and the rest may be the same as the embodiment of FIGS. 21A and / or 21B.

[0285] The housing portion 198 may have polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. The contact region 300 of the polycrystalline portion 132 may be a region of the polycrystalline portion 132 that is in contact with the housing portion 198. For example, the housing portion 198 has polysilicon with a lower impurity concentration than the polycrystalline portion 132 or undoped polysilicon.

[0286] 21D shows an example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0287] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0288] 21E shows another example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etched down to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0289] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured by the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of Fig. 21D, stable quality can be obtained and yield can be improved.

[0290] Fig. 22 shows an example of the ff' cross section in Fig. 19B. The semiconductor device 100 of this example differs from the embodiment of Fig. 20 in that the first inactive contact portion 134 has a trench contact structure. Other aspects may be the same as the embodiment of Fig. 20.

[0291] 23A shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the example of FIG. 21A in that the structure of the first inactive contact portion 134 is different. In this example, differences from the example of FIG. 21A will be particularly described, and the rest may be the same as the example of FIG. 21A.

[0292] The sidewalls of the first non-active contact portions 134 may have a trench contact structure in contact with the side surfaces of the polycrystalline portions 132. In this example, the bottom corners 1340 of the first non-active contact portions 134 contact the side surfaces of the polycrystalline portions 132.

[0293] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. In this example, the polycrystalline portion 132 is in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​35% of the sidewall of the first inactive contact portion 134. That is, the ratio of length L4 to length L3 in this example is 35%.

[0294] 23B shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 23A in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first inactive contact portion 134. Other aspects may be the same as the embodiment of FIG. 23A.

[0295] 23C shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region in the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIGS. 23A and 23B in that a housing portion 198 is provided in addition to the interlayer insulating film 38 and the field insulating film 148, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Other aspects may be the same as the embodiment of FIGS. 23A and / or 23B.

[0296] 23D shows an example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0297] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0298] 23E shows another example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etched down to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0299] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured not by the center portion of the bottom surface of the first inactive contact portion 134 but by the bottom corner portion 1340. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of Fig. 23D, stable quality can be obtained and yield can be improved.

[0300] Fig. 24 shows an example of the ff' cross section in Fig. 19B. The semiconductor device 100 of this example differs from the embodiment of Fig. 20 in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Other aspects may be the same as the embodiment of Fig. 20.

[0301] 20 and the first inactive contact portion 134 of FIG. 24 may be provided separately or in combination. For example, as the first inactive contact portion 134 connecting the edge metal layer 146 and the polycrystalline portion 132, the first inactive contact portion 134 may be provided only at the end of the field plate 144 facing the guard ring 142 as shown in FIG. 20 , or the first inactive contact portion 134 may be provided only at the end of the field plate 144 facing away from the guard ring 142 as shown in FIG. 24 , or the first inactive contact portion 134 may be provided at both the end of the field plate 144 facing the guard ring 142 and the end of the field plate 144 facing away from the guard ring 142. The first inactive contact portion 134 may be provided only at the end of one field plate 144 facing away from the guard ring 142 as seen from the contact hole 59. The edge metal layer 146 and the guard ring 142 are electrically connected via the contact hole 59 in which the second inactive contact portion 135 is buried.

[0302] 25A shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 21A in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Other aspects may be the same as the embodiment of FIG. 21A.

[0303] 25B shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region in the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 25A in that a housing portion 198 is provided separately from the interlayer insulating film 38, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Other aspects may be the same as the embodiment of FIG. 25A.

[0304] 25C shows an example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0305] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0306] 25D shows another example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etched down to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0307] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured by the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of Fig. 25C, stable quality can be obtained and yield can be improved.

[0308] Fig. 26 shows an example of the ff' cross section in Fig. 19B. The semiconductor device 100 of this example differs from the embodiment of Fig. 22 in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Other aspects may be the same as the embodiment of Fig. 22.

[0309] 22 and the first inactive contact portion 134 of FIG. 26 may be provided separately or in combination. For example, as the first inactive contact portion 134 connecting the edge metal layer 146 and the polycrystalline portion 132, the first inactive contact portion 134 may be provided only at the end of the field plate 144 facing the guard ring 142 as shown in FIG. 22 , or the first inactive contact portion 134 may be provided only at the end of the field plate 144 facing away from the guard ring 142 as shown in FIG. 26 , or the first inactive contact portion 134 may be provided at both the end of the field plate 144 facing the guard ring 142 and the end of the field plate 144 facing away from the guard ring 142. The first inactive contact portion 134 may be provided only at the end of one field plate 144 facing away from the guard ring 142 as seen from the contact hole 59. The edge metal layer 146 and the guard ring 142 are electrically connected via the contact hole 59 in which the second inactive contact portion 135 is buried.

[0310] 27A shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the inactive portion 130. The semiconductor device 100 of this example differs from the embodiment of FIG. 23A in that the first inactive contact portion 134 is provided above the polycrystalline portion 132 above the field insulating film 148. Other aspects may be the same as the embodiment of FIG. 23A.

[0311] 27B shows an example of an enlarged view of the ff' cross section in FIG. 19B. This figure shows a region in the inactive portion 130 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 27A in that a housing portion 198 is provided separately from the interlayer insulating film 38, and the housing portion 198 has polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 132. Other aspects may be the same as the embodiment of FIG. 27A.

[0312] 27C shows an example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first non-active contact portion 134. This example shows a case where the plug portion 1344 near the center of the bottom surface of the first non-active contact portion 134 is removed by over-etching in the etch-back process of the plug portion 1344. In this case, it is difficult to fill the first non-active contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first non-active contact portion 134.

[0313] In the present example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. Therefore, even if a void 302 occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in the present example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 via the bottom corners 1340 rather than the center of the bottom surface of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0314] 27D shows another example of an enlarged view of the ff' cross section in FIG. 19B when a void 302 occurs in the first inactive contact portion 134. This example shows a case where, in the etch-back process of the plug portion 1344, the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed, and further over-etched down to the housing portion 198. In this case, it is difficult to fill the first inactive contact portion 134 with the metal material of the edge metal layer 146, and a void 302 may occur near the center of the bottom surface of the first inactive contact portion 134.

[0315] In the inactive portion 130 of this example, the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 is ensured by the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. As a result, even if a void 302 is formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198, as in the example of Fig. 27C, stable quality can be obtained and yield can be improved.

[0316] 28 shows an example of the gg' cross section of FIG. 19A. The gg' cross section is an XZ plane that passes through the gate pad 112 in the inactive portion 130. In the gg' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a pad electrode 51, a collector electrode 24, and a first inactive contact portion 134. The gate pad 112 is an example of the pad electrode 51.

[0317] The pad electrode 51 is provided above the semiconductor substrate 10. The pad electrode 51 may be provided above the interlayer insulating film 38. The gate pad 112 of this example is provided above the interlayer insulating film 38. The material of the pad electrode 51 may be the same metal as the material of the emitter electrode 52.

[0318] The inactive portion 130 has a polycrystalline portion 132 provided above the semiconductor substrate 10. In this example, the polycrystalline portion 132 is a pad connection portion 125.

[0319] The inactive portion 130 may have a third interlayer insulating film 138 on the upper surface of the semiconductor substrate 10. The third interlayer insulating film 138 may be made of the same material as the gate insulating film 42 and / or the dummy insulating film 32, for example. As an example, the third interlayer insulating film 138 may be a thermal oxide film. The polycrystalline portion 132 may be provided above the third interlayer insulating film 138. As another example, the third interlayer insulating film 138 may be made of a different material from the gate insulating film 42 and / or the dummy insulating film 32. The pad connection portion 125 of this example is provided above the third interlayer insulating film 138.

[0320] The first inactive contact portion 134 is electrically connected to the polycrystalline portion 132. In this example, the first inactive contact portion 134 is electrically connected to the pad connection portion 125. The first inactive contact portion 134 may electrically connect the pad electrode 51 and the pad connection portion 125.

[0321] The first inactive contact portion 134 is provided to extend from the upper surface to the lower surface of the interlayer insulating film 38. The contact hole 53 may be provided to penetrate the interlayer insulating film 38. The first inactive contact portion 134 may have the contact hole 53 and a metal layer filled inside the contact hole 53. The housing portion 198 is provided below the first inactive contact portion 134.

[0322] The polycrystalline portion 132 may be connected to the pad electrode 51 via the first inactive contact portion 134. The pad connection portion 125 of this example is connected to the pad electrode 51 via the first inactive contact portion 134.

[0323] A bottom corner 1340 of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132. The bottom corner 1340 of the first inactive contact portion 134 may be the intersection of the bottom surface of the first inactive contact portion 134 and the side surface of the first inactive contact portion 134. The bottom corner 1340 being in contact with the polycrystalline portion 132 may be in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132, may be in contact with the polycrystalline portion 132 on the side surface of the polycrystalline portion 132, or may be in contact with the polycrystalline portion 132 in an internal region of the polycrystalline portion 132. In this example, the bottom corner 1340 is in contact with the polycrystalline portion 132 on the top surface of the polycrystalline portion 132.

[0324] The first inactive contact portion 134 of this example has two bottom corners 1340. One of the two bottom corners 1340 may contact the polycrystalline portion 132. The other of the two bottom corners 1340 may or may not contact the housing portion 198. The first inactive contact portion 134 of this example has one bottom corner 1340a in contact with the polycrystalline portion 132 and the other bottom corner 1340b in contact with the housing portion 198.

[0325] The bottom surface of the first inactive contact portion 134 may be in contact with the housing portion 198. The bottom surface of the first inactive contact portion 134 may be the surface between two bottom corner portions 1340 of the first inactive contact portion 134. The bottom surface of the first inactive contact portion 134 in contact with the housing portion 198 may be in contact with the housing portion 198 at the top surface of the housing portion 198, or may be in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0326] In this example, the first inactive contact portion 134 is provided such that the bottom corners 1340 are in contact with the polycrystalline portion 132 and the bottom surface is in contact with the housing portion 198. This reliably ensures electrical connection between the pad electrode 51 and the polycrystalline portion 132. If the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched during the etch-back process of the plug portion 1344, voids may be generated inside the first inactive contact portion 134. Even in this case, the electrical connection can be ensured by the barrier metal film 1342 and / or the plug portion 1344 remaining at the bottom corners 1340 of the first inactive contact portion 134.

[0327] The first inactive contact portion 134 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corners 1340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The inactive portion 130 in this example ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corners 1340 rather than the bottom center of the first inactive contact portion 134. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0328] The bottom surface of first inactive contact portion 134 may be in contact with polycrystalline portion 132 and housing portion 198. In this example, first inactive contact portion 134 has one bottom corner 1340 a in contact with polycrystalline portion 132 and the other bottom corner 1340 b in contact with housing portion 198, so that the bottom surface of first inactive contact portion 134 is in contact with polycrystalline portion 132 and housing portion 198.

[0329] The polycrystalline portion 132 may contact the bottom surface of the first inactive contact portion 134 from the bottom corner 1340 to an area of ​​10% to 40% of the bottom surface of the first inactive contact portion 134. That is, the area ratio of the surface of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the bottom surface of the first inactive contact portion 134 may be 10% to 40%. Referring to FIG. 28 , length L1 is the length of the bottom surface of the first inactive contact portion 134 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 in the cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 132 contacts the bottom surface of the first inactive contact portion 134 from the bottom surface corner 1340a to an area that is 20% of the bottom surface of the first inactive contact portion 134. That is, in this example, the ratio of the length L2 to the length L1 is 20%.

[0330] The side surface of the polycrystalline portion 132 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134, the housing portion 198 may be a virtual region. In other words, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 132 or undoped polysilicon. In another example, the housing portion 198 may be the third interlayer insulating film 138 that is provided above the semiconductor substrate 10. In this case, the housing portion 198 may be formed in the process of providing the third interlayer insulating film 138, and may be formed from the same material as the third interlayer insulating film 138. In other words, the housing portion 198 may be formed integrally as part of the third interlayer insulating film 138.

[0331] The first inactive contact portion 134 may include a barrier metal film 1342 and a plug portion 1344 provided in the contact hole 53. The barrier metal film 1342 of the first inactive contact portion 134 may include titanium, a titanium compound, or the like. The plug portion 1344 of the first inactive contact portion 134 may include a plug metal such as tungsten. In this example, the barrier metal film 1342 is provided above the interlayer insulating film 38 and is in contact with the pad electrode 51. In the active portion 120 or other inactive portions 130 such as the edge termination structure 140 or the temperature sensing portion 180, a barrier metal film 1242, a barrier metal film 1342, and / or a barrier metal film 1882 may also be provided above the interlayer insulating film 38. In this example, the plug portion 1344 is provided inside the contact hole 53. When the plug portion 1344 is provided in a part of the first inactive contact portion 134, the remaining region of the first inactive contact portion 134 may be filled with the same material as the pad electrode 51. In another example, the plug portion 1344 may be provided above the barrier metal film 1342 outside the contact hole 53 and in contact with the pad electrode 51. Also in the active portion 120 or another inactive portion 130, the plug portion 1244, the plug portion 1344, and / or the plug portion 1884 may be provided above the barrier metal film 1242, the barrier metal film 1342, and / or the barrier metal film 1882 outside the contact hole 54, the contact hole 55, the contact hole 56, the contact hole 57, the contact hole 58, and / or the contact hole 59. In yet another example, the barrier metal film 1342 may not be provided above the interlayer insulating film 38 but may be provided only inside the contact hole 53.

[0332] The polycrystalline portion 132 may be connected to the pad electrode 51 through a contact hole 53 provided in the interlayer insulating film 38. The pad connection portion 125 of this example is connected to the pad electrode 51 through the contact hole 53 provided in the interlayer insulating film 38.

[0333] The polycrystalline portion 132 in this example may be formed below the gate pad 112. Although the pad connection portions 125 are provided discretely in the cross section of Figure 28, the pad connection portions 125 may be connected to each other in different cross sections as will be described later.

[0334] The pad connection portion 125 may be made of the same polycrystalline material as the gate conductive portion 44 and the dummy conductive portion 34. In another example, the pad connection portion 125 may be made of polycrystalline material formed simultaneously with the polycrystalline material constituting the temperature-sensitive diode 183 and made conductive by ion implantation or the like as necessary. The insulating film below the polycrystalline portion 132 may not be made of the same material as the gate insulating film 42 or the like, but may have the same structure as the second interlayer insulating film 37 of the temperature-sensitive portion 180. The pad connection portion 125 may not be electrically connected to anything other than the pad electrode 51. In this case, the pad electrode 51 may be directly connected to the gate metal layer 50. Alternatively, the pad connection portion 125 may not be conductive. In another example, the pad connection portion 125 may be electrically connected to anything other than the pad electrode 51. For example, the pad connection portion 125 may be connected to the connection portion 25. Alternatively, the pad electrode 51 may not be directly connected to the gate metal layer 50, but may be connected via the pad connection portion 125. In this case, the pad connection portion 125 is conductive and may be connected to the gate metal layer 50 outside the gate pad 112 when viewed from above, and may be connected to the gate metal layer 50 in a manner similar to the connection to the pad electrode 51.

[0335] The barrier metal film 1342 may be provided up to the edge of the pad electrode 51. The pad electrode 51 may be provided wider than the edge of the pad connection portion 125. In another example, the pad electrode 51 does not have to be provided up to the edge of the pad connection portion 125.

[0336] FIG. 29A shows an example of region P including a portion of the gg' cross section in FIG. 19A and its periphery. In this figure, polycrystalline portions 132 and housing portion 198 are repeatedly arranged in the X-axis direction on the gg' cross section and its periphery. Each polycrystalline portion 132 is connected to another at a location spaced apart from the gg' cross section in the Y-axis direction. As described above, polycrystalline portions 132 may be arranged in a comb-like pattern. By providing multiple contact holes 53 across housing portion 198 and polycrystalline portions 132, it is possible to connect polycrystalline portions 132 repeatedly arranged in the X-axis direction to pad electrodes 51. Furthermore, the arrangement shown in this example may be repeatedly arranged by translating or inverting the arrangement along the X-axis or Y-axis.

[0337] FIG. 29B shows another example of region P, including a portion of the gg' cross section in FIG. 19A and its periphery. In this figure, polycrystalline portions 132 and housing portions 198 are repeatedly arranged in the X-axis direction on the gg' cross section and its periphery. The polycrystalline portions 132 are connected to each other at locations spaced apart from the gg' cross section in the Y-axis direction. As described above, polycrystalline portions 132 may be arranged to have multiple housing portions 198 dispersed therein. By providing multiple contact holes 53 across the housing portions 198 and polycrystalline portions 132, the polycrystalline portions 132 repeatedly arranged in the X-axis direction can be connected to pad electrodes 51. Furthermore, the arrangement shown in this example may be repeatedly arranged by translating or inverting the arrangement along the X-axis or Y-axis. The arrangement of the polycrystalline portion 132 shown in Figures 29A and 29B may be applied not only to the arrangement of the pad connection portion 125 and contact hole 53, but also to the arrangement of the connection portion 25, contact hole 55, and contact hole 56 in other inactive portions 130, the arrangement of the field plate 144 and contact hole 57, and the arrangement of the temperature-sensitive anode region 182, temperature-sensitive cathode region 181, and contact hole 58 in the temperature-sensitive portion 180.

[0338] FIG. 29C shows another example of region P, including a portion of the gg' cross section in FIG. 19A and its periphery. In this figure, polycrystalline portions 132 and housing portions 198 are repeatedly arranged in the X-axis direction on the gg' cross section and its periphery. The polycrystalline portions 132 are not connected to each other. As described above, the polycrystalline portions 132 may be arranged discretely. By providing multiple contact holes 53 across the housing portions 198 and the polycrystalline portions 132, the polycrystalline portions 132 repeatedly arranged in the X-axis direction can be connected to the pad electrodes 51. If the pad connection portion 125 is not connected to other components of the semiconductor device 100, the polycrystalline portions 132 may not be connected to each other. The polycrystalline portions 132 may also be arranged discretely in the Y-axis direction.

[0339] 30 shows another example of the gg' cross section in FIG. 19A. The semiconductor device 100 of this example differs from the embodiment of FIG. 28 in that the first inactive contact portion 134 has a trench contact structure. Other aspects may be the same as the embodiment of FIG. 28. When the first inactive contact portion 134 has a trench contact structure, the first inactive contact portion 134 may extend from the upper surface of the polycrystalline portion 132 in the depth direction of the semiconductor substrate 10. The active contact portion 124 may have the planar contact structure of FIG. 1B or the trench contact structure of FIG. 10B.

[0340] The semiconductor device 100 of this example differs from the embodiment of Fig. 28 in that the structure of the first inactive contact portion 134 is different. In this example, differences from the embodiment of Fig. 28 will be particularly described, and the rest may be the same as the embodiment of Fig. 28.

[0341] The sidewalls of the first non-active contact portions 134 may have a trench contact structure in contact with the side surfaces of the polycrystalline portions 132. In this example, the bottom corners 1340 of the first non-active contact portions 134 contact the side surfaces of the polycrystalline portions 132.

[0342] The sidewall of the first inactive contact portion 134 may be in contact with the polycrystalline portion 132 and the interlayer insulating film 38. The polycrystalline portion 132 may be in contact with the sidewall of the first inactive contact portion 134 from the bottom corner 1340 over an area of ​​10% to 90% of the sidewall of the first inactive contact portion 134. In other words, the ratio of the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 to the area of ​​the sidewall of the first inactive contact portion 134 that is in contact with the polycrystalline portion 132 may be 10% to 90%. 30 , length L3 is the length of the sidewall of first inactive contact portion 134 in a cross section perpendicular to front surface 21 of semiconductor substrate 10, and length L4 is the length of the sidewall of first inactive contact portion 134 that contacts polycrystalline portion 132 in a cross section perpendicular to front surface 21 of semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, polycrystalline portion 132 contacts the sidewall of first inactive contact portion 134 from bottom corner 1340 to 35% of the sidewall of first inactive contact portion 134. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0343] If the plug portion 1344 near the center of the bottom surface of the first inactive contact portion 134 is over-etched during the etch-back process of the plug portion 1344, it may be difficult to fill the first inactive contact portion 134 with the metal material of the pad electrode 51, and a void may occur near the center of the bottom surface of the first inactive contact portion 134. In this example, the first inactive contact portion 134 is provided such that the bottom corner portion 1340 contacts the polycrystalline portion 132 and the bottom surface contacts the housing portion 198. Therefore, even if a void occurs inside the first inactive contact portion 134 near the center of the bottom surface, the influence on the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 at the bottom corner portion 1340 is suppressed. This makes it possible to improve the yield of semiconductor devices 100 having desired characteristics. In the present example, the inactive portion 130 ensures electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corner portion 1340 rather than the bottom center portion of the first inactive contact portion 134. This ensures stable quality and improved yield even when voids are formed in the region near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0344] Although the gate pad 112 has been described in FIGS. 28 to 30 , the configuration described with respect to the gate pad 112 may also be applied to other pads. For example, it may be used for the anode pad 116, cathode pad 118, sense electrode 114, and / or any pad not shown in FIG. 19A . The pad electrode 51 may be in direct contact with the anode wiring portion 117 or the cathode wiring portion 119, or may be indirectly connected via the polycrystalline portion 132. Note that, although the example of the X-Z cross section has been described using FIG. 28 , the longitudinal direction of the contact hole 53 does not have to be the Y-axis direction. For example, the longitudinal direction of the contact hole 53 may be the X-axis direction or any other direction, and contact holes 53 oriented in different directions may be used in combination.

[0345] 31 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. The manufacturing process of this example includes step S200 of forming the active portion 120 and step S210 of forming the inactive portion 130. The order of step S200 of forming the active portion 120 and step S210 of forming the inactive portion 130 is not limited to this. The active portion 120 may be formed after the inactive portion 130 is formed, and some or all of the steps of forming the active portion 120 and some of the steps of forming the inactive portion 130 may be the same step.

[0346] Step S210 of forming the inactive portion 130 includes step S212 of forming the third interlayer insulating film 138, step S214 of forming the polycrystalline portion 132, step S216 of forming the interlayer insulating film 38, step S218 of forming the first inactive contact portion 134, and step S220 of forming the housing portion 198.

[0347] In step S212, a third interlayer insulating film 138 is formed above the semiconductor substrate 10. The third interlayer insulating film 138 may be an insulating film that insulates the semiconductor substrate 10 from the connection portion 25, an insulating film that insulates the semiconductor substrate 10 from the field plate 144, or an insulating film that insulates the semiconductor substrate 10 from the pad connection portion 125. The third interlayer insulating film 138 may be formed by a method known to those skilled in the art. For example, step S212 may be a step of forming the gate insulating film 42 in the active portion 120, and the third interlayer insulating film 138 may be a thermal oxide film formed by heating the semiconductor substrate 10. For another example, step S212 may be step S112 of forming the second interlayer insulating film 37 in the temperature-sensing portion 180.

[0348] In step S214, a polycrystalline portion 132 is formed above the semiconductor substrate 10. The polycrystalline portion 132 may be formed above the third interlayer insulating film 138. The polycrystalline portion 132 may be the connection portion 25 electrically connecting the emitter electrode 52 and the dummy conductive portion 34, the connection portion 25 electrically connecting the gate metal layer 50 and the gate conductive portion 44, the field plate 144, or the pad connection portion 125 provided below the pad electrode 51. The polycrystalline portion 132 may be formed by a method conventional to those skilled in the art. As an example, step S214 may be a step of forming the gate conductive portion 44 in the active portion 120, and the polycrystalline portion 132 may be formed by depositing polysilicon doped with impurities above the semiconductor substrate 10. As another example, step S212 may be step S114, in which non-doped polysilicon is deposited above the semiconductor substrate 10 in the temperature-sensing portion 180, followed by implanting impurity ions and performing annealing.

[0349] In step S216, an interlayer insulating film 38 is formed above the polycrystalline portion 132. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films. Step S216 of forming the interlayer insulating film 38 may be a stage of forming the interlayer insulating film 38 on the active portion 120.

[0350] In step S218, first inactive contact portions 134 are formed, extending from the upper surface to the lower surface of the interlayer insulating film 38. Step S218 for forming the first inactive contact portions 134 may be a step of forming active contact portions 124, extending from the upper surface to the lower surface of the interlayer insulating film 38, in the active portion 120. However, the first inactive contact portions 134 and the active contact portions 124 may be formed in different processes.

[0351] Step S218 of forming the first inactive contact portion 134 may include a step of forming contact holes 53, 55, 56, and / or 57 by etching the interlayer insulating film 38. In this step, contact hole 59 may also be formed. In addition, contact hole 54 may also be formed in the interlayer insulating film 38 of the active portion 120. In addition, contact hole 58 may also be formed in the interlayer insulating film 38 of the temperature sensing portion 180. However, these contact holes may be formed in different steps.

[0352] Step S218 of forming the first inactive contact portion 134 may include forming a barrier metal film 1342. The barrier metal film 1342 may be formed by forming a metal film inside the contact hole 53, the contact hole 55, the contact hole 56, and / or the contact hole 57, and then annealing the metal film in a nitrogen atmosphere. As an example, the barrier metal film 1342 may be formed by forming a Ti film inside the contact hole 53, the contact hole 55, the contact hole 56, and / or the contact hole 57, and then annealing the Ti film in a nitrogen atmosphere. In this case, a TiN film may be formed by annealing the Ti film. In this process, a barrier metal film may be formed in the active contact portion 124 and / or the second inactive contact portion 135.

[0353] The step S218 of forming the first inactive contact portion 134 may include a step of forming a plug portion 1344. As an example, the plug portion 1344 may be formed by forming tungsten to fill the contact holes 53, 55, 56, and / or 57 using a chemical vapor deposition (CVD) method. In this process, the plug portion may be formed in the active contact portion 124 and / or the second inactive contact portion 135.

[0354] The step S218 of forming the first inactive contact portion 134 may include a step of etching back the plug portion 1344. This may remove unnecessary tungsten film outside the contact hole 53, the contact hole 55, the contact hole 56, and / or the contact hole 57. However, the plug portion 1344 may be provided in a portion of the first inactive contact portion 134, or may extend beyond the contact hole 53, the contact hole 55, the contact hole 56, and / or the contact hole 57 and extend above the interlayer insulating film 38. The etch-back may be performed by dry etching or chemical mechanical polishing (CMP). When the tungsten film outside the contact holes is removed, the barrier metal film 1342 outside the contact holes may also be removed. The barrier metal film 1342 may be removed in a process separate from the etching back of the plug portion 1344. The barrier metal film 1342 may not be removed. In this step, the plug portions of the active contact portion 124 and / or the second non-active contact portion 135 may be etched back.

[0355] The above-described steps may be omitted if the barrier metal film 1342 and / or the plug portion 1344 are not provided in the first inactive contact portion 134. In this case, the contact holes 53, 55, 56, and / or 57 may be filled to form the first inactive contact portion 134 simultaneously with the step of providing the pad electrode 51, the emitter electrode 52, the gate metal layer 50, and / or the edge metal layer 146.

[0356] In the step S218 of forming the first inactive contact portion 134, the first inactive contact portion 134 may be formed such that the bottom corner portion 1340 of the first inactive contact portion 134 contacts the polycrystalline portion 132. In the step S218 of forming the first inactive contact portion 134, the first inactive contact portion 134 may be formed such that the bottom surface of the first inactive contact portion 134 contacts the housing portion 198.

[0357] In this example, the bottom corners 1340 of the first inactive contact portion 134 are in contact with the polycrystalline portion 132, and the bottom surface is in contact with the housing portion 198, thereby reliably ensuring electrical connection between the pad electrode 51, the emitter electrode 52, the gate metal layer 50, and / or the edge metal layer 146 and the polycrystalline portion 132. Since the bottom surface of the first inactive contact portion 134 is in contact with the housing portion 198, even if the plug portion 1344 and the barrier metal film 1342 near the center of the bottom surface of the first inactive contact portion 134 are over-etched and removed in the etch-back process of the plug portion 1344, causing a void inside the first inactive contact portion 134, this suppresses the influence on the electrical connection at the bottom corners 1340 between the first inactive contact portion 134 and the polycrystalline portion 132, thereby improving the yield of semiconductor devices 100 having desired characteristics. That is, by ensuring the electrical connection between the first inactive contact portion 134 and the polycrystalline portion 132 through the bottom corner portion 1340 rather than the center portion of the bottom surface of the first inactive contact portion 134, stable quality can be obtained and yield can be improved even if a void is formed in the area near the center of the first inactive contact portion 134 that contacts the housing portion 198.

[0358] In step S220, the housing portion 198 is formed below the first inactive contact portion 134. The order of step S220 of forming the housing portion 198 is not limited thereto. Step S220 of forming the housing portion 198 may be included in step S214 of forming the polycrystalline portion 132 or step S216 of forming the interlayer insulating film 38.

[0359] 12A, 14A, 16A, 18A, 21A, 23A, 25A, 27A, or 28 to 30, the housing portion 198 is a region of the interlayer insulating film 38 that is provided below the first inactive contact portion 134. In this case, step S220 of forming the housing portion 198 may be included in step S216 of forming the interlayer insulating film 38.

[0360] 21C, 23C, 25B, 27B, or 28-30, housing portion 198 comprises polysilicon. In this case, step S220 of forming housing portion 198 may be included in step S214 of forming polycrystalline portion 132. Polycrystalline portion 132 and housing portion 198 may be formed by stacking undoped polysilicon in the regions that will become housing portion 198 and polycrystalline portion 132, implanting impurity ions into each region, and performing an annealing process.

[0361] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0362] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0363] 10: Semiconductor substrate, 12: Emitter region, 14: Base region, 15: Contact region, 16: Accumulation region, 17: Well region, 18: Drift region, 20: Buffer region, 21: Front surface, 22: Collector region, 23: Back surface, 24: Collector electrode, 25: Connection portion, 30: Dummy trench portion, 31: Extension portion, 32: Dummy insulating film, 33: Connection portion, 34: Dummy conductive portion, 36: First interlayer insulating film, 37: Second interlayer insulating film, 38: Interlayer insulating film, 40: Gate trench 3. Transistor portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 50...gate metal layer, 51...pad electrode, 52...emitter electrode, 53...contact hole, 54...contact hole, 55...contact hole, 56...contact hole, 57...contact hole, 58...contact hole, 59...contact hole, 70...transistor portion, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91... Mesa portion, 100... semiconductor device, 102... edge, 112... gate pad, 114... sense electrode, 115... current sense portion, 116... anode pad, 117... anode wiring portion, 118... cathode pad, 119... cathode wiring portion, 120... active portion, 122... active trench portion, 124... active contact portion, 125... pad connection portion, 130... inactive portion, 132... polycrystalline portion, 134... first inactive contact portion, 135... second inactive contact portion, 138... third interlayer insulating film, 140... Edge termination structure portion, 142...guard ring, 144...field plate, 146...edge metal layer, 148...field insulating film, 151...back surface side lifetime control region, 152...front surface side lifetime control region, 170...zener diode portion, 180...temperature sensing portion, 181...temperature sensing cathode region, 182...temperature sensing anode region, 183...temperature sensing diode, 188...temperature sensing contact portion, 198...housing portion, 200...recess, 300...contact region, 302...void, 1340...bottom corner portion,1242...barrier metal film, 1244...plug portion, 1342...barrier metal film, 1344...plug portion, 1352...barrier metal film, 1354...plug portion, 1420...non-corner region, 1422...corner region, 1880...bottom corner portion, 1882...barrier metal film, 1884...plug portion,

Claims

1. A semiconductor device comprising: an active portion provided on a semiconductor substrate; and a temperature-sensing portion provided above the semiconductor substrate, wherein the temperature-sensing portion has: a temperature-sensing diode provided above the semiconductor substrate; a first interlayer insulating film provided above the temperature-sensing diode; a temperature-sensing contact portion extending from an upper surface to a lower surface of the first interlayer insulating film; and a housing portion provided below the temperature-sensing contact portion, wherein a bottom corner portion of the temperature-sensing contact portion contacts the temperature-sensing diode, and the bottom surface of the temperature-sensing contact portion contacts the housing portion.

2. The semiconductor device according to claim 1, wherein a side surface of the temperature sensing diode contacts a side surface of the housing portion.

3. The semiconductor device according to claim 1, further comprising a second interlayer insulating film provided between said temperature sensing diode and said semiconductor substrate in the depth direction of said semiconductor substrate.

4. The semiconductor device according to claim 3, wherein an upper surface of the second interlayer insulating film contacts a lower surface of the temperature sensing diode and a lower surface of the housing portion.

5. The semiconductor device according to claim 1, wherein the housing portion is a region of the first interlayer insulating film provided below the temperature-sensitive contact portion.

6. The semiconductor device according to claim 3, wherein the housing portion is the second interlayer insulating film provided above the semiconductor substrate.

7. The semiconductor device according to claim 3, wherein the second interlayer insulating film has a recess on an upper surface side, and the temperature sensing diode is provided in the recess of the second interlayer insulating film.

8. The semiconductor device according to claim 1, wherein the temperature sensitive diode has a contact region in contact with the housing portion, and the housing portion has a polycrystalline semiconductor having a conductivity type different from that of the contact region of the temperature sensitive diode.

9. The semiconductor device according to claim 1, wherein the temperature sensitive diode has a contact region in contact with the housing portion, and the housing portion has the same conductivity type as the contact region of the temperature sensitive diode and comprises a polycrystalline semiconductor having a lower doping concentration than the contact region.

10. The semiconductor device according to claim 1, wherein the temperature sensitive diode comprises: a temperature sensitive anode region provided above the semiconductor substrate; and a temperature sensitive cathode region provided above the semiconductor substrate and in contact with the temperature sensitive anode region.

11. The semiconductor device according to claim 1, wherein the temperature-sensitive contact portion comprises: a barrier metal film provided at a corner portion of the bottom surface of the temperature-sensitive contact portion; and a plug portion provided in contact with an inner side of the barrier metal film.

12. The semiconductor device according to claim 1, wherein the active portion has a plurality of active contact portions provided on the front surface of the semiconductor substrate.

13. The semiconductor device according to any one of claims 1 to 12, wherein a bottom surface of the temperature-sensitive contact portion contacts the temperature-sensitive diode and the housing portion.

14. The semiconductor device according to claim 13, wherein the temperature sensitive diode contacts the bottom surface of the temperature sensitive contact portion over an area ranging from the bottom surface corner to 10% to 40% of the bottom surface of the temperature sensitive contact portion.

15. The semiconductor device according to any one of claims 1 to 12, wherein the sidewall of the temperature-sensitive contact portion has a trench contact structure in contact with a side surface of the temperature-sensitive diode.

16. The semiconductor device according to claim 15, wherein a sidewall of the temperature-sensitive contact portion is in contact with the temperature-sensitive diode and the first interlayer insulating film, and the temperature-sensitive diode is in contact with the sidewall of the temperature-sensitive contact portion over an area from the bottom corner to 10% or more and 90% or less of the sidewall of the temperature-sensitive contact portion.

17. A method for manufacturing a semiconductor device comprising the steps of: forming an active portion in a semiconductor substrate; and forming a temperature-sensing portion above the semiconductor substrate, wherein the step of forming the temperature-sensing portion comprises the steps of: forming a temperature-sensing diode above the semiconductor substrate; forming a first interlayer insulating film above the temperature-sensing diode; forming a temperature-sensing contact portion extending from an upper surface to a lower surface of the first interlayer insulating film; and forming a housing portion below the temperature-sensing contact portion, wherein a bottom corner portion of the temperature-sensing contact portion contacts the temperature-sensing diode, and a bottom surface of the temperature-sensing contact portion contacts the housing portion.

18. A semiconductor device having an active portion and a non-active portion, the non-active portion having: a polycrystalline portion provided above a semiconductor substrate; an interlayer insulating film provided above the polycrystalline portion; a first non-active contact portion extending from an upper surface to a lower surface of the interlayer insulating film; and a housing portion provided below the first non-active contact portion, wherein a bottom corner portion of the first non-active contact portion contacts the polycrystalline portion, and a bottom surface of the first non-active contact portion contacts the housing portion.

19. The semiconductor device according to claim 18, wherein a side surface of the polycrystalline portion contacts a side surface of the housing portion.

20. The semiconductor device according to claim 18, wherein the housing portion is a region of the interlayer insulating film provided below the first inactive contact portion.

21. The semiconductor device according to claim 18, wherein the first inactive contact portion has: a barrier metal film provided at a corner portion of the bottom surface of the first inactive contact portion; and a plug portion provided in contact with an inner side of the barrier metal film.

22. The semiconductor device according to claim 18, wherein the active portion has a plurality of active contact portions provided on the front surface of the semiconductor substrate.

23. The semiconductor device according to claim 18, wherein a bottom surface of the first inactive contact portion contacts the polycrystalline portion and the housing portion.

24. The semiconductor device according to claim 23, wherein the polycrystalline portion contacts the bottom surface of the first non-active contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the first non-active contact portion.

25. The semiconductor device according to claim 18, wherein the sidewall of the first inactive contact portion has a trench contact structure in contact with a side surface of the polycrystalline portion.

26. The semiconductor device described in claim 25, wherein a sidewall of the first non-active contact portion is in contact with the polycrystalline portion and the interlayer insulating film, and the polycrystalline portion is in contact with an area of ​​the sidewall of the first non-active contact portion from the bottom corner portion to 10% or more and 90% or less of the sidewall of the first non-active contact portion.

27. A semiconductor device as claimed in any one of claims 18 to 26, comprising: a gate trench portion provided on a front surface of the semiconductor substrate and having a gate conductive portion; and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, wherein the polycrystalline portion is connected to the gate metal layer via the first inactive contact portion and is connected to the gate conductive portion.

28. A semiconductor device as claimed in any one of claims 18 to 26, comprising: a dummy trench portion provided on a front surface of the semiconductor substrate and having a dummy conductive portion; and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the polycrystalline portion is connected to the emitter electrode via the first inactive contact portion and is connected to the dummy conductive portion.

29. A semiconductor device as claimed in any one of claims 18 to 26, comprising: a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate; and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, wherein the polycrystalline portion is connected to the edge metal layer via the first inactive contact portion.

30. The semiconductor device according to claim 29, further comprising a field insulating film provided below said interlayer insulating film, said first inactive contact portion being provided above said polycrystalline portion above said field insulating film.

31. A semiconductor device as described in any one of claims 18, 19, 21 to 26, comprising: a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate; an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring; and a field insulating film provided below the interlayer insulating film, wherein the polycrystalline portion is connected to the edge metal layer via the first inactive contact portion, and the housing portion is a region of the field insulating film provided below the first inactive contact portion.

32. A semiconductor device as claimed in any one of claims 18, 19, 21 to 26, comprising: a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the active portion and an edge of the semiconductor substrate; and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, wherein the polycrystalline portion is connected to the edge metal layer via the first inactive contact portion, the polycrystalline portion has a contact region in contact with the housing portion, and the housing portion has a polycrystalline semiconductor having a lower impurity concentration than the contact region of the polycrystalline portion.

33. The semiconductor device according to any one of claims 18 to 26, further comprising a pad electrode provided above the semiconductor substrate, the polycrystalline portion being connected to the pad electrode via the first inactive contact portion.

34. A method for manufacturing a semiconductor device comprising: a step of forming an active portion; and a step of forming an inactive portion, wherein the step of forming the inactive portion comprises the steps of: forming a polycrystalline portion above a semiconductor substrate; forming an interlayer insulating film above the polycrystalline portion; forming a first inactive contact portion extending from an upper surface to a lower surface of the interlayer insulating film; and forming a housing portion below the first inactive contact portion, wherein a bottom corner portion of the first inactive contact portion contacts the polycrystalline portion, and a bottom surface of the first inactive contact portion contacts the housing portion.

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