Memristor-based array device for performing three-dimensional convolutional neural network (3D cnn) operation and 3D cnn operation method using same

Abstract

A memristor array device according to one embodiment may comprise a vertical memristor-based inference element which comprises: a first stacked structure in which each of a plurality of insulating layers and each of a plurality of lower electrode layers are alternately stacked; and a second stacked structure in which a resistive switching element material layer, an intermediate electrode layer, a selection element material layer, and an upper electrode are stacked in a hole formed in the first stacked structure, and which comprises a plurality of memristor elements formed in electrical paths from the plurality of lower electrode layers to the upper electrode.

Description

A memristor-based array device for performing 3D convolutional neural network (3D CNN) operations and a 3D CNN operation method using the same.

[0001] The present disclosure relates to a device for performing a 3D convolutional neural network (3D CNN) operation and a 3D CNN operation method using the same.

[0002] A 3D convolutional neural network (3D CNN) performs convolution operations using 3D weights, rather than the 2D weights used in a 2D convolutional neural network (2D CNN). Therefore, a 3D CNN performs a convolution operation by sliding a kernel containing 3D weights in three directions with respect to input data, thereby producing a single output value. Video data containing 3D object or time-domain information can be used for 3D CNN training.

[0003] In neuromorphic-based learning using general artificial neural networks (e.g., 2D CNN, Artificial neural network (ANN), Deep neural network (DNN), etc.), it is okay to divide the input data into one-dimensional subsets and proceed with learning, so it is easy to implement elements with a conventional two-dimensional memristor array structure and perform operations using them.

[0004] However, since 3D CNN learning ultimately requires processing 3D data, the number of input data divided into one-dimensional subsets during learning becomes very large. As a specific example, if the size of the input data is N 3In this case, 1 is a subset on a one-dimensional plane. If you divide the data into N size and operate it, the data processing (operation) is N 2 Therefore, since the existing two-dimensional memristor array structure is not suitable for this learning, we propose a new concept of inference element structure and a computational method utilizing it to solve this problem.

[0005] A memristor array device according to one embodiment may include a vertical memristor-based inference element having a first laminated structure in which each of a plurality of insulating layers and each of a plurality of lower electrode layers is alternately laminated, and a second laminated structure in which a resistance change element material layer, an intermediate electrode layer, a selection element material layer, and an upper electrode are laminated in a hole formed in the first laminated structure, and a plurality of memristor elements formed in electrical paths from the plurality of lower electrode layers to the upper electrode.

[0006] According to one embodiment, a memristor array device further includes a plurality of memristor-based inference elements arranged in an array structure along an input line and an output line, an operation electrode layer connected to second stacked structures of at least one memristor-based inference element connected to the same output line among the plurality of memristor-based inference elements, and an output electrode layer that outputs an output operation result based on a column operation result transmitted from the operation electrode layer and a column operation result transmitted from another operation electrode layer of a different output line, wherein one of the plurality of memristor-based inference elements is the vertical memristor-based inference element, and the operation electrode layer receives individual operation results between inputs received through a plurality of lower electrode layers from each of the at least one memristor-based inference elements and weights stored in the plurality of memristor elements, and transmits a column operation result generated by merging the individual operation results received from the at least one memristor-based inference element to the output electrode layer.

[0007] A memristor array device according to one embodiment may be a memristor array device in which a second stacked structure of at least one memristor-based inference element connected to the same input line among the plurality of memristor-based inference elements is connected to the same lower electrode layer.

[0008] A memristor array device according to one embodiment further includes a first buffer for storing an output based on a first operation of the operation electrode layer, and a second buffer for storing an output based on a second operation of the other operation electrode layer, wherein the output electrode layer may be a memristor array device that outputs a result of integrating an output based on the first operation received from the first buffer and an output based on the second operation received from the second buffer when the first operation and the second operation are individually performed.

[0009] In a memristor array device according to one embodiment, each memristor-based inference element among the plurality of memristor-based inference elements may receive, in parallel with respect to other memristor-based inference elements, corresponding values ​​among three-dimensional partial data acquired in correspondence to a three-dimensional kernel of a predetermined size from input data through a plurality of lower electrode layers, and may generate, in parallel with respect to the other memristor-based inference elements, an operation result between the corresponding values ​​and weights of the plurality of memristor elements formed in the corresponding memristor-based inference element.

[0010] In a memristor array device according to one embodiment, the resistance change element material layer may include at least one of a metal oxide or a chalcogenide-based material, and the selection element material layer may include a chalcogenide-based material.

[0011] A memristor array device according to one embodiment can be stacked for peripheral circuits that input input data to the plurality of lower electrode layers.

[0012] A 3D convolutional neural network operation method based on a memristor array device according to one embodiment may include the steps of: obtaining 3D partial data corresponding to a 3D kernel of a predetermined size from input data; inputting values ​​of the obtained partial data to a plurality of lower electrode layers individually connected to a plurality of memristor elements formed to be vertically spaced apart; generating a column operation result corresponding to a sum of individual operation results between values ​​input to the plurality of lower electrode layers and weights stored in the plurality of memristor elements; transmitting the generated column operation result and column operation results of a plurality of memristor-based inference elements connected to another output line to an output electrode layer; and merging the transmitted column operation results to output an output operation result.

[0013] In a three-dimensional convolutional neural network operation method according to one embodiment, the memristor array device may include a plurality of memristor-based inference elements arranged in an array structure along an input line and an output line, and the inputting step may include a step of inputting the three-dimensional partial data in parallel to a plurality of lower electrode layers included in each of the plurality of memristor elements.

[0014] In a three-dimensional convolutional neural network operation method according to one embodiment, the memristor array device includes a plurality of memristor-based inference elements arranged in an array structure along an input line and an output line, and a second stacked structure of at least one memristor-based inference element connected to the same input line among the plurality of memristor-based inference elements is connected to the same lower electrode layer, and the inputting step may include a step of forming a plurality of two-dimensional data by slicing the three-dimensional partial data, and a step of inputting a value corresponding to one data among the formed plurality of two-dimensional data to a plurality of lower electrode layers of the plurality of memristor-based inference elements connected to the corresponding output line among the output lines.

[0015] A three-dimensional convolutional neural network operation method according to one embodiment may further include a step of storing the generated column operation result in a buffer.

[0016] In a three-dimensional convolutional neural network operation method according to one embodiment, the memristor array device may be stacked on a peripheral circuit that inputs input data to the plurality of lower electrode layers, and the inputting step may include a step in which the peripheral circuit inputs data to the plurality of lower electrode layers.

[0017] FIG. 1a illustrates a cross-sectional view of a vertical memristor-based inference element according to one embodiment.

[0018] Figures 1b and 1c show pulse response characteristics and resistance change characteristics over time of a memristor element when an electrical pulse is applied.

[0019] FIG. 2 illustrates a memristor array device according to one embodiment.

[0020] FIG. 3 illustrates a memristor array device according to one embodiment.

[0021] FIG. 4 illustrates a memristor array device according to one embodiment.

[0022] FIG. 5 illustrates a memristor array device according to one embodiment.

[0023] Fig. 6 is a drawing comparing the positional relationship between the peripheral circuit and the memristor array device with a comparative example.

[0024] FIGS. 7A and 7B illustrate a flowchart and schematic diagram for a three-dimensional convolutional neural network operation method based on a memristor array device according to the present disclosure.

[0025] Figures 8a to 8c show n in a memristor array device. 2 A method of operating a memristor array device for 3D CNN operation is illustrated when two-dimensional data are sequentially input.

[0026] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Therefore, the actual implementation is not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or alternatives within the technical concepts described in the embodiments.

[0027] Although terms such as "first" or "second" may be used to describe various components, these terms should be interpreted solely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

[0028] When it is said that a component is "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0029] Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "has" should be understood to indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0030] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0031] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted.

[0032] FIG. 1a illustrates a cross-sectional view of a vertical memristor-based inference element (100) according to one embodiment.

[0033] A vertical memristor-based inference element (100) may be one of the single elements constituting a memristor array device according to the present disclosure. The vertical memristor-based inference element (100) may include a first stacked structure (110) and a second stacked structure (114) formed in a hole (113) of the first stacked structure (110).

[0034] The first laminated structure (110) may have a structure in which each of a plurality of insulating layers (111) and each of a plurality of lower electrode layers (112) are alternately laminated. The plurality of lower electrode layers (112) may have a structure in which a portion of the plurality of lower electrode layers (112) is exposed to the outside of the first laminated structure (110) so that input data values ​​can be received from the outside. For example, the plurality of lower electrode layers (112) may have a structure in which they are spaced apart and exposed toward the upper surface of the first laminated structure (110), but the structure of the plurality of lower electrode layers (112) is not limited thereto. The plurality of insulating layers (111) may prevent electrical interference, interaction, or charge leakage between each of the plurality of lower electrode layers (112).

[0035] The second laminated structure (114) may be a structure in which a resistance change element material layer (115), an intermediate electrode layer, a selection element material layer (116), and an upper electrode (117) are laminated in a hole (113) formed in the first laminated structure (112). The hole (113) formed in the first laminated structure (112) may be formed through an etching process. For example, the etching process may be a dry etching process or a wet etching process. Specifically, the dry etching process may be performed using an inductively coupled plasma reactive ion etching (ICP-RIE) or a capacitively coupled plasma reactive ion etching (CCP-RIE). In the etching process, Ar gas and / or CF4, CHF3, O2, SF6, Cl2 or HBr gas for chemical reaction may be utilized to form plasma. The above specific example of the etching process is only an example, and the etching process for hole formation is not limited thereto. According to one embodiment, the resistance change element material layer (115) may be deposited or applied in the form of a thin film on the inner surface of the hole (113), but the manufacturing process is not limited thereto. The resistance change element material layer (115) may include at least one of a metal oxide or a chalcogenide-based material. For example, the resistance change element material layer (115) may include at least one of a group of materials of an oxide-based resistance random access memory (ReRAM) and a chalcogenide-based phase-change random access memory (PCRAM).

[0036] After the resistance change element material layer (115) is formed inside the hole (113), an intermediate electrode layer and a selection element material layer (116) may be laminated and formed. The selection element material layer (116) may include a chalcogenide-based material. For example, the selection element material layer (116) may include a group of materials of an ovonic-threshold switching selector (OTS) based on a chalcogenide-based material. When an input higher than a preset threshold value is applied to the selection element material layer (116), a plurality of memristor elements (118) included in the second laminated structure (114) may be operated. For example, when a voltage higher than the threshold value is applied to the selection element material layer (116), the memristor elements (118) included in the second laminated structure (114) may be operated. More specifically, by applying a specific voltage higher than a threshold value to the selection element material layer (116), the operation of the memristor elements (118) can be selectively activated or deactivated. In addition, by applying a voltage higher than a threshold value to the selection element material layer (116), different resistance values ​​corresponding to weights stored in each of the memristor elements (118) can be easily read.

[0037] As illustrated in FIG. 1a, the selection element material layer (116) may be included in the memristor element (118), but may be connected to the memristor element (118) as a separate element.

[0038] The second laminated structure (114) may include a plurality of memristor elements (118) formed in electrical paths from a plurality of lower electrode layers (111) to an upper electrode (117). For example, a resistance change element material layer (115), an intermediate electrode layer, and a selection element material layer (116) may be sequentially formed between each of the plurality of lower electrode layers (111) and the upper electrode (117), and a plurality of memristor elements (118) may be formed on electrical paths from the plurality of lower electrode layers (111) to the upper electrode (117) through the resistance change element material layer (115), the intermediate electrode layer, and the selection element material layer (116). More specifically, between each of the plurality of lower electrode layers (111) and the upper electrode (117), 4F 2 A plurality of memristor elements (118) of an area can be formed. The plurality of memristor elements (118) can form a resistance value or an impedance value by causing a phase change of a resistance change element material layer (115) by an electrical pulse or by causing the creation of an electrical path. The resistance value or impedance value of the plurality of memristor elements (118) can be a value corresponding to a weight set for 3D CNN operation. A specific method of setting the weight by the memristor element (118) is described in detail in the electrical pulse response characteristic (101) and the resistance change characteristic (102) of FIGS. 1b and 1c below.

[0039] A vertical memristor-based inference element (100) can receive input data values ​​through a plurality of lower electrode layers (112). The input data values ​​can be calculated based on weights set in a plurality of memristor elements (118), and the result values ​​calculated by the plurality of memristor elements (118) can be merged in an upper electrode (117).

[0040] Figures 1b and 1c illustrate pulse response characteristics (101) and resistance change characteristics (102) over time of a memristor element when an electrical pulse is applied.

[0041] According to the electrical pulse response characteristics (101), as the number of electrical pulses increases, the normalized conductance value may exhibit a decreasing characteristic. However, the direction of the change characteristic of the normalized conductance value according to the change in the conditions of the electrical pulse is not limited to this, and may exhibit an increasing or other gradual change characteristic.

[0042] According to the resistance change characteristic (102), the memristor element can exhibit different resistance values ​​(R) depending on the intensity of the electrical pulse. For example, in the resistance change characteristic (102), different resistance values ​​can correspond to eight different y values ​​on the resistance axis (y-axis) when the x value is 0 on the time axis (x-axis). According to the resistance change characteristic (102), the memristor element (118) can maintain the resistance value formed according to the electrical pulse within a certain critical range over time. For example, can correspond to a constant value representing the degree of change in resistance over time. The degree of change in resistance over time ( ) is 10 4 Since the maximum resistance value is only 0.0890 over a period of time, the different resistance values ​​can be maintained within a range that does not overlap with each other over time. Since the resistance values ​​are maintained within different critical ranges over time, the resistance values ​​between the memristor elements (118) can be distinguished into different ranges. The plurality of resistance values ​​that are distinguished from each other can correspond to different weight values ​​of each memristor element (118). Therefore, by applying electrical pulses of different intensities to the plurality of memristor elements (118), the resistance value corresponding to the weight value designated for each element can be individually set.

[0043] FIG. 2 illustrates a memristor array device (200) according to one embodiment.

[0044] A memristor array device (200) may include a plurality of memristor-based inference elements (201) arranged in an array structure along an input line (210) and an output line (211). One of the plurality of memristor-based inference elements (201) included in the memristor array device (200) may be a vertical memristor-based inference element as illustrated in FIG. 1. The memristor array device (200) may have the same number of input lines (210) and the same number of output lines (211), and the number of the plurality of memristor-based inference elements (201) arranged along the input line (210) and the output line (211) may be the same. For another example, the number of input lines (210) and the number of output lines (211) may be different from each other, and the number of a plurality of memristor-based inference elements arranged along the input line (210) and the number of a plurality of memristor-based inference elements arranged along the output line (211) may be different from each other. For example, the memristor array device illustrated in FIG. 2 shows that n memristor-based inference elements are arranged along the input line (210) and n memristor-based inference elements are arranged along the output line (211). For example, when the number of lower electrode layers included in each of the memristor-based inference elements (201) is n, the memristor array device (200) may have n 3 A plurality of memristor elements (240) can be formed. n 3 n due to multiple memristor elements (240) 3 The weights of the dog can be defined. For convenience of explanation, the following description is based on the case where the number of memristor-based inference elements (201) arranged along the input line (210) and the output line (211) is the same.

[0045] The memristor array device (200) may further include an operation electrode layer (220) connected to second stacked structures of at least one memristor-based inference element connected to the same output line (211) among the plurality of memristor-based inference elements (201). The operation electrode layer (220) may receive individual operation results between inputs received through the plurality of lower electrode layers from each of the at least one memristor-based inference elements and weights stored in the plurality of memristor elements, and may transmit a column operation result generated by merging the individual operation results received from the at least one memristor-based inference element to the output electrode layer. For example, one of the plurality of memristor-based inference elements included in the memristor array device (200) may receive an input through the plurality of lower electrode layers (230). Individual operations may be performed on each of the received inputs and each of the weights stored in the plurality of memristor elements (240). For example, when a voltage is input through multiple lower electrode layers (230), a current value can be output based on the resistance value of each memristor element (240). The sum result of the current values ​​output by multiple memristor-based inference elements arranged on the same output line can correspond to the column operation result.

[0046] The memristor array device (200) may further include an output electrode layer (221) that outputs an output operation result based on a column operation result transmitted from an operation electrode layer (220) and a column operation result transmitted from another operation electrode layer of a different output line. The output electrode layer (221) may output an output operation result corresponding to a sum result of a plurality of column operation results. For example, when the column operation result corresponds to a current value, the output operation result may correspond to a current value obtained by merging current values ​​corresponding to all column operation results.

[0047] FIG. 3 illustrates a memristor array device (300) according to one embodiment.

[0048] The memristor array device (300) may have second stacked structures (320) of one or more memristor-based inference elements connected to the same input line (310) among a plurality of memristor-based inference elements connected to the same lower electrode layer (321). For example, the memristor array device (300) may have a structure in which a lower electrode layer (321) extends along an input line (310), and second stacked structures (320) spaced apart from each other along the input line (310) share the extended lower electrode layer (321). More specifically, the memristor array device (300) represents n first stacked structures each including n lower electrode layers (321) arranged for each input line (310). In addition, n second stacked structures are respectively arranged along an input line (310) and along an output line (311). Since the number of lower electrode layers included in each of the first laminated structures is n, the memristor array device (300) has n 2 Data of size n can be input. For example, if the size of input data is n 3 In this case, n in the memristor array device (300) 2 The size data can be sequentially input by repeating n times. In addition, n is input by each of the second laminated structures (320) and n lower electrode layers. 3 Multiple memristor elements can be formed. n 3 n due to multiple memristor elements 3 The weights of the dog can be defined. n in the memristor array device (300) 2 The operation method of the memristor array device when data of a size is sequentially input by repeating n times will be described in detail later in FIGS. 8a to 8c.

[0049] FIG. 4 illustrates a memristor array device (400) according to one embodiment.

[0050] The memristor array device (400) is n2 may include a lower electrode layer of n included in the memristor array device (400). 2 n on the lower electrode layer of the dog 2 A two-dimensional array of data of size n can be input. The size of the input data is n. 3 In this case, n in the memristor array device (400) 2 Data of size can be sequentially input by repeating n times. The memristor array device (400) is n 2 An output line on which an operation is to be performed can be selected to generate a column operation result corresponding to the sum of individual operation results between each input data of size n and the weights stored in the memristor elements. 2 When data of size is sequentially input to the memristor array device (400) by repeating n times, a difference in operation execution time may occur depending on the input order. The memristor array device (400) is n 3 In generating one output operation result for input data of size n, 2 To offset the difference in computational execution time due to sequential input of data of different sizes, a buffer may be included on each output line. Specifically, the memristor array device (400) may store column computation results in the buffer to offset the difference in computational execution time. The column computation results stored in the buffer may be transmitted from the buffer to the output computation layer when all other column computation results are completed.

[0051] For example, the memristor array device (400) may further include a first buffer (410) that stores an output based on a first operation of an operational electrode layer and a second buffer (411) that stores an output based on a second operation of another operational electrode layer.

[0052] The first buffer (410) can store an output based on a first operation of an operation electrode layer arranged on a single output line. The first operation of the operation electrode layer can correspond to a weighted sum operation based on input values ​​received through a plurality of lower electrode layers of each of the memristor-based inference elements arranged on the same output line and weights defined in the memristor elements.

[0053] The second buffer (411) can store an output based on a second operation of an operation electrode layer disposed on an output line different from the output line on which the first buffer (410) is disposed. The second operation can be performed on an operation electrode layer different from the operation electrode layer that outputs the first operation.

[0054] As illustrated in Fig. 4, when the memristor array device (400) has n output lines and a memristor-based inference element is arranged on each output line, the memristor array device (400) may include a total of n buffers. The n-th buffer (412) may store an output based on the n-th operation of the operation electrode layer.

[0055] The output electrode layer (413) of the memristor array device (400) can output a result that integrates an output based on a first operation received from a first buffer (410) and an output based on a second operation received from a second buffer (411) when the first operation and the second operation are individually performed. More specifically, the output electrode layer (413) of the memristor array device (400) can output a result that integrates outputs based on a total of n operations from the first operation, the second operation, to the n-th operation when a total of n operations from the first operation, the second operation, to the n-th operation are individually performed, and the integrated result can correspond to a current value.

[0056] FIG. 5 illustrates a memristor array device (500) according to one embodiment.

[0057] Among the plurality of memristor-based inference elements included in the memristor array device (500), each memristor-based inference element can receive, in parallel with respect to other memristor-based inference elements, corresponding values ​​among the three-dimensional partial data acquired in response to a three-dimensional kernel of a predetermined size from the input data through the plurality of lower electrode layers (501, 502, 503). For example, the size of the three-dimensional kernel of a predetermined size is the number of output lines as the horizontal length, the number of input lines as the vertical length, and the number of the plurality of lower electrode layers as the height, length It can be the size of the height. The 3D partial data can correspond to data segmented or extracted from the input data corresponding to the 3D kernel. For example, the 3D partial data can be n n It can be of size n. For another example, 3D partial data with different width, height, and height n l It can be of size k. The number of multiple lower electrode layers included in each of the memristor-based inference elements is n, and the total number of multiple lower electrode layers (501, 502, 503) is n. 3 In the case of an individual, n in the memristor array device (200) 3 Data from dogs can be entered in parallel.

[0058] The memristor array device (500) can generate, based on data input in parallel, a calculation result between the corresponding values ​​and the weights of the plurality of memristor elements (510, 511, 512) formed in the corresponding memristor-based inference elements in parallel with respect to each other memristor-based inference elements.

[0059] Fig. 6 is a drawing comparing the positional relationship between the peripheral circuit and the memristor array device with a comparative example.

[0060] A peripheral circuit may be included in the memristor array device, and may be a separate circuit from the memristor array device, and may supply values ​​corresponding to input data to the memristor array device.

[0061] Comparative example (601) includes a separate peripheral circuit (611) for supplying values ​​corresponding to input data to the memristor array device (610). For example, if the memristor array device (610) corresponds to the memristor array device (200) illustrated in FIG. 2, the memristor array device (610) has a total of n 3 It may include a plurality of lower electrode layers. The lower electrode layers may be n in total. 3 To apply a voltage corresponding to the input data to the individual memristor array device (610), a total of n 3 A peripheral circuit (611) including a dog electrode may be required. Including the peripheral circuit (611) as a separate configuration from the memristor array device (610) has the disadvantage of increasing the volume occupied by the peripheral circuit.

[0062] The peripheral circuit stack structure (602) illustrates a structure in which a memristor array device (620) is stacked on a peripheral circuit (621) that inputs input data to a plurality of lower electrode layers. For example, if the memristor array device (620) corresponds to the memristor array device (200) illustrated in FIG. 2, the memristor array device (610) has a total of n 3 may include multiple lower electrode layers, totaling n 3 In order to apply a voltage corresponding to input data to a memristor array device (610) including a plurality of lower electrode layers, a peripheral circuit (621) may be stacked with the memristor array device (610) so that the volume occupied by the peripheral circuit (621) can be reduced.

[0063] FIGS. 7a and 7b illustrate a flowchart (701) and a schematic diagram (700) for a three-dimensional convolutional neural network operation method based on a memristor array device according to the present disclosure.

[0064] In step (720), the memristor array device (713) can obtain three-dimensional partial data (712) corresponding to a three-dimensional kernel (711) of a predetermined size from the input data (710). For example, the size of the input data (710) is m 3 , the size of the 3D kernel (711) is n 3 It can be defined as m>n. In addition, the size of the three-dimensional kernel (711) can correspond to the number of memristor elements included in the memristor array device (713).

[0065] In step (721), the memristor array device (713) can input the values ​​of the acquired partial data (712) into a plurality of lower electrode layers individually connected to a plurality of memristor elements formed vertically spaced apart, which are included in the memristor array device (713). The input method of the partial data (712) is specifically described below with reference to FIGS. 8A to 8C.

[0066] In step (722), the memristor array device (713) can generate a column operation result corresponding to the sum of individual operation results between values ​​input to the plurality of lower electrode layers and weights stored in the plurality of memristor elements. For example, when the values ​​input to the plurality of lower electrode layers are voltages, the weights stored in the plurality of memristor elements may correspond to resistance values ​​of the memristor elements. Accordingly, the individual operation results and the column operation result corresponding to the sum of the individual operation results may correspond to a current value based on the resistance values ​​of the plurality of memristor elements and the voltage values ​​input to the plurality of lower electrode layers.

[0067] In step (723), the memristor array device (713) can transmit the generated column operation results and the column operation results of a plurality of memristor-based inference elements connected to other output lines to the output electrode layer. The column operation results and the column operation results obtained from other output lines can be transmitted to the output electrode layer simultaneously or in a time series manner.

[0068] In step (724), the memristor array device (713) can merge the transmitted column operation results and output an output operation result (714). The output operation result (714) is n 3 It may correspond to a single current value corresponding to the operation result for the partial data (712) of the size.

[0069] For input data (710), a 3D kernel (711) is swept, and the 3D partial data (712) acquired by the 3D kernel (711) is input to the memristor array device (713), and steps (720) to (724) can be repeated. In addition, the memristor array device (713) repeats steps (720) to (740), thereby obtaining (m-n+1) 3 Output the output operation result (714) of the dog, and (m-n+1) 3 It is possible to generate output operation results (715) of size.

[0070]

[0071] Figures 8a to 8c show n in a memristor array device. 2 A method of operating a memristor array device for 3D CNN operation is illustrated when two-dimensional data are sequentially input.

[0072] For example, a memristor array device may include a plurality of memristor-based inference elements arranged in an array structure along an input line and an output line, and a second stacked structure of at least one memristor-based inference element connected to the same input line among the plurality of memristor-based inference elements may be connected to the same lower electrode layer. At this time, the memristor array device may form a plurality of two-dimensional data by slicing three-dimensional partial data (800). For example, the formed plurality of two-dimensional data may be n 2 It can be of size and can be defined as a total of n slices from the first two-dimensional data to the n-th two-dimensional data.

[0073] The memristor array device can input a value corresponding to one of the formed plurality of two-dimensional data into the corresponding plurality of lower electrode layers of the plurality of memristor-based inference elements connected to the corresponding output line among the output lines.

[0074] For example, FIG. 8A illustrates an operation method of a memristor array device when first two-dimensional data (801a) among partial data (800) is input to the memristor array device. The first two-dimensional data (801a) may be input to a plurality of lower electrode layers (810). The memristor array device may select a first operation electrode layer (812a) (or upper electrode) arranged on a first output line (811a). The selected first operation electrode layer (812a) may be n between the first two-dimensional data (801a) and the weights stored in the plurality of memristor elements. 2The individual operation results of the dog can be merged to generate a first column operation result. The first column operation result can be transmitted to the output electrode layer (820). Although not shown in FIG. 8A, a buffer may be included between the first operation electrode layer (812a) arranged on the first output line (811a) and the output electrode layer (820). The first operation electrode layer (812a) can store the first column operation result in the buffer until the column operation result is generated in another operation electrode layer.

[0075] FIG. 8b illustrates an operation method of a memristor array device when second two-dimensional data (801b) is input to the memristor array device after first two-dimensional data among partial data (800) is input. The second two-dimensional data (801b) may be input to a plurality of lower electrode layers (810). The memristor array device may select a second operation electrode layer (812b) (or upper electrode) arranged on a second output line (811b). The selected second operation electrode layer (812b) may be n between the second two-dimensional data (801b) and the weights stored in the plurality of memristor elements. 2 The individual operation results of the dog can be merged to generate a second column operation result. The second column operation result can be transmitted to the output electrode layer (820). Although not shown in FIG. 8b, a buffer may be included between the second operation electrode layer (812b) arranged on the second output line (811b) and the output electrode layer (820). The second operation electrode layer (812b) can store the second column operation result in the buffer until the column operation result is generated in another operation electrode layer.

[0076] Fig. 8c illustrates an operation method of a memristor array device when n-th two-dimensional data (801c) is input to the memristor array device after first and second two-dimensional data among partial data (800) are input. The n-th two-dimensional data (801c) can be input to a plurality of lower electrode layers (810). The memristor array device can select an n-th operation electrode layer (812c) (or upper electrode) arranged on an n-th output line (811c). The selected n-th operation electrode layer (812c) is an n-th two-dimensional data (801c) and weights stored in a plurality of memristor elements. 2 The individual operation results of the nth column can be merged to generate the nth column operation result. The nth column operation result can be transmitted to the output electrode layer (820). Although not shown in Fig. 8c, a buffer may be included between the nth operation electrode layer (812c) arranged on the nth output line (811c) and the output electrode layer (820). The nth operation electrode layer (812c) can store the nth column operation result in the buffer.

[0077] The memristor array device can simultaneously transmit the column operation results stored in the buffers to the output electrode layer (820) when the first to nth column operation results are stored in each buffer (not shown). The output electrode layer (820) can merge the received multiple column operation results and output the output operation result.

[0078] In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any one of the items listed together in that phrase, or all possible combinations thereof.

[0079] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the described embodiments. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0080] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In a memristor array device, A first laminated structure in which each of a plurality of insulating layers and each of a plurality of lower electrode layers are alternately laminated; and A second laminated structure in which a resistance change element material layer, an intermediate electrode layer, a selection element material layer, and an upper electrode are laminated in a hole formed in the first laminated structure, and which includes a plurality of memristor elements formed in electrical paths from the plurality of lower electrode layers to the upper electrode. Vertical memristor-based inference device with A memristor array device comprising:

2. In paragraph 1, The above memristor array device, A plurality of memristor-based inference elements arranged in an array structure along input lines and output lines; An operational electrode layer connected to second stacked structures of at least one memristor-based inference element connected to the same output line among the plurality of memristor-based inference elements; An output electrode layer that outputs an output operation result based on the column operation result transmitted from the above operation electrode layer and the column operation result transmitted from another operation electrode layer of a different output line. Including more, One of the plurality of memristor-based inference elements is the vertical memristor-based inference element, The above operation electrode layer is, Receiving individual operation results between inputs received through a plurality of lower electrode layers and weights stored in a plurality of memristor elements in each of the at least one memristor-based inference elements, and transmitting a column operation result generated by merging the individual operation results received from the at least one memristor-based inference element to the output electrode layer. Memristor array device.

3. In paragraph 2, The above memristor array device, A second stacked structure of at least one memristor-based inference element connected to the same input line among the plurality of memristor-based inference elements is connected to the same lower electrode layer. Memristor array device.

4. In paragraph 2, The above memristor array device, A first buffer for storing an output based on a first operation of the above operation electrode layer; and A second buffer storing the output based on the second operation of the other operation electrode layer Including more, The above output electrode layer, When the first operation and the second operation are performed individually, a result is output by integrating the output based on the first operation received from the first buffer and the output based on the second operation received from the second buffer. Memristor array device.

5. In paragraph 2, Among the above multiple memristor-based inference elements, each memristor-based inference element comprises: In parallel with other memristor-based inference elements, corresponding values ​​among the 3D partial data acquired in correspondence to a 3D kernel of a predetermined size from the input data are received through multiple lower electrode layers, In parallel with the other memristor-based inference elements, generating an operation result between the corresponding values ​​and the weights of a plurality of memristor elements formed in the corresponding memristor-based inference element. Memristor array device.

6. In paragraph 1, The above resistance change element material layer is, Containing at least one metal oxide or chalcogenide material, The above selection element material layer is, Containing a chalcogenide substance, Memristor array device.

7. In paragraph 1, The above memristor array device, Stacked for peripheral circuits that input data to the plurality of lower electrode layers, Memristor array device.

8. In a 3D convolutional neural network operation method based on a memristor array device, A step of obtaining three-dimensional partial data corresponding to a three-dimensional kernel of a predetermined size from input data; A step of inputting the values ​​of the acquired partial data into a plurality of lower electrode layers individually connected to a plurality of memristor elements formed vertically apart; A step of generating a column operation result corresponding to the sum of individual operation results between values ​​input to the plurality of lower electrode layers and weights stored in the plurality of memristor elements; A step of transmitting the generated column operation result and the column operation result of a plurality of memristor-based inference elements connected to other output lines to the output electrode layer; and A step of merging the above-transmitted column operation results and outputting the output operation results. Including 3D convolutional neural network computation method.

9. In paragraph 8, The above memristor array device comprises a plurality of memristor-based inference elements arranged in an array structure along input lines and output lines, The above input steps are: A step of inputting the above three-dimensional partial data in parallel to a plurality of lower electrode layers included in each of a plurality of memristor elements. Including 3D convolutional neural network computation method.

10. In paragraph 8, The memristor array device includes a plurality of memristor-based inference elements arranged in an array structure along an input line and an output line, and a second stacked structure of at least one memristor-based inference element connected to the same input line among the plurality of memristor-based inference elements is connected to the same lower electrode layer. The above input steps are: A step of forming a plurality of two-dimensional data by slicing the three-dimensional partial data; and A step of inputting a value corresponding to one of the plurality of two-dimensional data formed above into the corresponding plurality of lower electrode layers of the plurality of memristor-based inference elements connected to the corresponding output line among the output lines; Including 3D convolutional neural network computation method.

11. In paragraph 8, A step of storing the above generated column operation results in a buffer. Including more 3D convolutional neural network computation method.

12. In paragraph 8, The above memristor array device is stacked for a peripheral circuit that inputs input data to the plurality of lower electrode layers, The above input steps are: A step in which the peripheral circuit inputs data to the plurality of lower electrode layers Including 3D convolutional neural network computation method.

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